From: Yanhong Wang <yanhong.wang@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <netdev@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Cc: "David S . Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, Richard Cochran <richardcochran@gmail.com>, Andrew Lunn <andrew@lunn.ch>, Heiner Kallweit <hkallweit1@gmail.com>, Peter Geis <pgwipeout@gmail.com>, Yanhong Wang <yanhong.wang@starfivetech.com> Subject: [PATCH v2 6/9] net: phy: motorcomm: Add YT8531 phy support Date: Fri, 16 Dec 2022 15:06:29 +0800 [thread overview] Message-ID: <20221216070632.11444-7-yanhong.wang@starfivetech.com> (raw) In-Reply-To: <20221216070632.11444-1-yanhong.wang@starfivetech.com> This adds basic support for the Motorcomm YT8531 Gigabit Ethernet PHY. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> --- drivers/net/phy/Kconfig | 3 +- drivers/net/phy/motorcomm.c | 202 ++++++++++++++++++++++++++++++++++++ 2 files changed, 204 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index c57a0262fb64..86399254d9ff 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -258,9 +258,10 @@ config MICROSEMI_PHY config MOTORCOMM_PHY tristate "Motorcomm PHYs" + default SOC_STARFIVE help Enables support for Motorcomm network PHYs. - Currently supports the YT8511 gigabit PHY. + Currently supports the YT8511 and YT8531 gigabit PHYs. config NATIONAL_PHY tristate "National Semiconductor PHYs" diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 7e6ac2c5e27e..bca03185b338 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -3,13 +3,17 @@ * Driver for Motorcomm PHYs * * Author: Peter Geis <pgwipeout@gmail.com> + * */ +#include <linux/bitops.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/phy.h> #define PHY_ID_YT8511 0x0000010a +#define PHY_ID_YT8531 0x4f51e91b #define YT8511_PAGE_SELECT 0x1e #define YT8511_PAGE 0x1f @@ -17,6 +21,10 @@ #define YT8511_EXT_DELAY_DRIVE 0x0d #define YT8511_EXT_SLEEP_CTRL 0x27 +#define YTPHY_EXT_SMI_SDS_PHY 0xa000 +#define YTPHY_EXT_CHIP_CONFIG 0xa001 +#define YTPHY_EXT_RGMII_CONFIG1 0xa003 + /* 2b00 25m from pll * 2b01 25m from xtl *default* * 2b10 62.m from pll @@ -38,6 +46,51 @@ #define YT8511_DELAY_FE_TX_EN (0xf << 12) #define YT8511_DELAY_FE_TX_DIS (0x2 << 12) +struct ytphy_reg_field { + char *name; + u32 mask; + u8 dflt; /* Default value */ +}; + +struct ytphy_priv_t { + u32 tx_inverted_1000; + u32 tx_inverted_100; + u32 tx_inverted_10; +}; + +/* rx_delay_sel: RGMII rx clock delay train configuration, about 150ps per + * step. Delay = 150ps * N + * + * tx_delay_sel_fe: RGMII tx clock delay train configuration when speed is + * 100Mbps or 10Mbps, it's 150ps per step. Delay = 150ps * N + * + * tx_delay_sel: RGMII tx clock delay train configuration when speed is + * 1000Mbps, it's 150ps per step. Delay = 150ps * N + */ +static const struct ytphy_reg_field ytphy_rxtxd_grp[] = { + { "rx_delay_sel", GENMASK(13, 10), 0x0 }, + { "tx_delay_sel_fe", GENMASK(7, 4), 0xf }, + { "tx_delay_sel", GENMASK(3, 0), 0x1 } +}; + +/* tx_inverted_x: Use original or inverted RGMII TX_CLK to drive the RGMII + * TX_CLK delay train configuration when speed is + * xMbps(10/100/1000Mbps). + * 0: original, 1: inverted + */ +static const struct ytphy_reg_field ytphy_txinver_grp[] = { + { "tx_inverted_1000", BIT(14), 0x0 }, + { "tx_inverted_100", BIT(14), 0x0 }, + { "tx_inverted_10", BIT(14), 0x0 } +}; + +/* rxc_dly_en: RGMII clk 2ns delay control bit. + * 0: disable 1: enable + */ +static const struct ytphy_reg_field ytphy_rxden_grp[] = { + { "rxc_dly_en", BIT(8), 0x1 } +}; + static int yt8511_read_page(struct phy_device *phydev) { return __phy_read(phydev, YT8511_PAGE_SELECT); @@ -48,6 +101,33 @@ static int yt8511_write_page(struct phy_device *phydev, int page) return __phy_write(phydev, YT8511_PAGE_SELECT, page); }; +static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) +{ + int ret; + int val; + + ret = __phy_write(phydev, YT8511_PAGE_SELECT, regnum); + if (ret < 0) + return ret; + + val = __phy_read(phydev, YT8511_PAGE); + + return val; +} + +static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val) +{ + int ret; + + ret = __phy_write(phydev, YT8511_PAGE_SELECT, regnum); + if (ret < 0) + return ret; + + ret = __phy_write(phydev, YT8511_PAGE, val); + + return ret; +} + static int yt8511_config_init(struct phy_device *phydev) { int oldpage, ret = 0; @@ -111,6 +191,116 @@ static int yt8511_config_init(struct phy_device *phydev) return phy_restore_page(phydev, oldpage, ret); } +static int ytphy_config_init(struct phy_device *phydev) +{ + struct device_node *of_node; + u32 val; + u32 mask; + u32 cfg; + int ret; + int i = 0; + + of_node = phydev->mdio.dev.of_node; + if (of_node) { + ret = of_property_read_u32(of_node, ytphy_rxden_grp[0].name, &cfg); + if (!ret) { + mask = ytphy_rxden_grp[0].mask; + val = ytphy_read_ext(phydev, YTPHY_EXT_CHIP_CONFIG); + + /* check the cfg overflow or not */ + cfg = cfg > mask >> (ffs(mask) - 1) ? mask : cfg; + + val &= ~mask; + val |= FIELD_PREP(mask, cfg); + ytphy_write_ext(phydev, YTPHY_EXT_CHIP_CONFIG, val); + } + + val = ytphy_read_ext(phydev, YTPHY_EXT_RGMII_CONFIG1); + for (i = 0; i < ARRAY_SIZE(ytphy_rxtxd_grp); i++) { + ret = of_property_read_u32(of_node, ytphy_rxtxd_grp[i].name, &cfg); + if (!ret) { + mask = ytphy_rxtxd_grp[i].mask; + + /* check the cfg overflow or not */ + cfg = cfg > mask >> (ffs(mask) - 1) ? mask : cfg; + + val &= ~mask; + val |= cfg << (ffs(mask) - 1); + } + } + return ytphy_write_ext(phydev, YTPHY_EXT_RGMII_CONFIG1, val); + } + + phydev_err(phydev, "Get of node fail\n"); + + return -EINVAL; +} + +static void ytphy_link_change_notify(struct phy_device *phydev) +{ + u32 val; + struct ytphy_priv_t *ytphy_priv = phydev->priv; + + if (phydev->speed < 0) + return; + + val = ytphy_read_ext(phydev, YTPHY_EXT_RGMII_CONFIG1); + switch (phydev->speed) { + case SPEED_1000: + val &= ~ytphy_txinver_grp[0].mask; + val |= FIELD_PREP(ytphy_txinver_grp[0].mask, + ytphy_priv->tx_inverted_1000); + break; + + case SPEED_100: + val &= ~ytphy_txinver_grp[1].mask; + val |= FIELD_PREP(ytphy_txinver_grp[1].mask, + ytphy_priv->tx_inverted_100); + break; + + case SPEED_10: + val &= ~ytphy_txinver_grp[2].mask; + val |= FIELD_PREP(ytphy_txinver_grp[2].mask, + ytphy_priv->tx_inverted_10); + break; + + default: + break; + } + + ytphy_write_ext(phydev, YTPHY_EXT_RGMII_CONFIG1, val); +} + +static int yt8531_probe(struct phy_device *phydev) +{ + struct ytphy_priv_t *priv; + const struct device_node *of_node; + u32 val; + int ret; + + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + of_node = phydev->mdio.dev.of_node; + if (of_node) { + ret = of_property_read_u32(of_node, ytphy_txinver_grp[0].name, &val); + if (!ret) + priv->tx_inverted_1000 = val; + + ret = of_property_read_u32(of_node, ytphy_txinver_grp[1].name, &val); + if (!ret) + priv->tx_inverted_100 = val; + + ret = of_property_read_u32(of_node, ytphy_txinver_grp[2].name, &val); + if (!ret) + priv->tx_inverted_10 = val; + } + phydev->priv = priv; + + return 0; +} + static struct phy_driver motorcomm_phy_drvs[] = { { PHY_ID_MATCH_EXACT(PHY_ID_YT8511), @@ -120,6 +310,17 @@ static struct phy_driver motorcomm_phy_drvs[] = { .resume = genphy_resume, .read_page = yt8511_read_page, .write_page = yt8511_write_page, + }, { + PHY_ID_MATCH_EXACT(PHY_ID_YT8531), + .name = "YT8531 Gigabit Ethernet", + .probe = yt8531_probe, + .config_init = ytphy_config_init, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = yt8511_read_page, + .write_page = yt8511_write_page, + .link_change_notify = ytphy_link_change_notify, }, }; @@ -131,6 +332,7 @@ MODULE_LICENSE("GPL"); static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, + { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) }, { /* sentinal */ } }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Yanhong Wang <yanhong.wang@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <netdev@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Cc: "David S . Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, Richard Cochran <richardcochran@gmail.com>, Andrew Lunn <andrew@lunn.ch>, Heiner Kallweit <hkallweit1@gmail.com>, Peter Geis <pgwipeout@gmail.com>, Yanhong Wang <yanhong.wang@starfivetech.com> Subject: [PATCH v2 6/9] net: phy: motorcomm: Add YT8531 phy support Date: Fri, 16 Dec 2022 15:06:29 +0800 [thread overview] Message-ID: <20221216070632.11444-7-yanhong.wang@starfivetech.com> (raw) In-Reply-To: <20221216070632.11444-1-yanhong.wang@starfivetech.com> This adds basic support for the Motorcomm YT8531 Gigabit Ethernet PHY. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> --- drivers/net/phy/Kconfig | 3 +- drivers/net/phy/motorcomm.c | 202 ++++++++++++++++++++++++++++++++++++ 2 files changed, 204 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index c57a0262fb64..86399254d9ff 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -258,9 +258,10 @@ config MICROSEMI_PHY config MOTORCOMM_PHY tristate "Motorcomm PHYs" + default SOC_STARFIVE help Enables support for Motorcomm network PHYs. - Currently supports the YT8511 gigabit PHY. + Currently supports the YT8511 and YT8531 gigabit PHYs. config NATIONAL_PHY tristate "National Semiconductor PHYs" diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 7e6ac2c5e27e..bca03185b338 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -3,13 +3,17 @@ * Driver for Motorcomm PHYs * * Author: Peter Geis <pgwipeout@gmail.com> + * */ +#include <linux/bitops.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/phy.h> #define PHY_ID_YT8511 0x0000010a +#define PHY_ID_YT8531 0x4f51e91b #define YT8511_PAGE_SELECT 0x1e #define YT8511_PAGE 0x1f @@ -17,6 +21,10 @@ #define YT8511_EXT_DELAY_DRIVE 0x0d #define YT8511_EXT_SLEEP_CTRL 0x27 +#define YTPHY_EXT_SMI_SDS_PHY 0xa000 +#define YTPHY_EXT_CHIP_CONFIG 0xa001 +#define YTPHY_EXT_RGMII_CONFIG1 0xa003 + /* 2b00 25m from pll * 2b01 25m from xtl *default* * 2b10 62.m from pll @@ -38,6 +46,51 @@ #define YT8511_DELAY_FE_TX_EN (0xf << 12) #define YT8511_DELAY_FE_TX_DIS (0x2 << 12) +struct ytphy_reg_field { + char *name; + u32 mask; + u8 dflt; /* Default value */ +}; + +struct ytphy_priv_t { + u32 tx_inverted_1000; + u32 tx_inverted_100; + u32 tx_inverted_10; +}; + +/* rx_delay_sel: RGMII rx clock delay train configuration, about 150ps per + * step. Delay = 150ps * N + * + * tx_delay_sel_fe: RGMII tx clock delay train configuration when speed is + * 100Mbps or 10Mbps, it's 150ps per step. Delay = 150ps * N + * + * tx_delay_sel: RGMII tx clock delay train configuration when speed is + * 1000Mbps, it's 150ps per step. Delay = 150ps * N + */ +static const struct ytphy_reg_field ytphy_rxtxd_grp[] = { + { "rx_delay_sel", GENMASK(13, 10), 0x0 }, + { "tx_delay_sel_fe", GENMASK(7, 4), 0xf }, + { "tx_delay_sel", GENMASK(3, 0), 0x1 } +}; + +/* tx_inverted_x: Use original or inverted RGMII TX_CLK to drive the RGMII + * TX_CLK delay train configuration when speed is + * xMbps(10/100/1000Mbps). + * 0: original, 1: inverted + */ +static const struct ytphy_reg_field ytphy_txinver_grp[] = { + { "tx_inverted_1000", BIT(14), 0x0 }, + { "tx_inverted_100", BIT(14), 0x0 }, + { "tx_inverted_10", BIT(14), 0x0 } +}; + +/* rxc_dly_en: RGMII clk 2ns delay control bit. + * 0: disable 1: enable + */ +static const struct ytphy_reg_field ytphy_rxden_grp[] = { + { "rxc_dly_en", BIT(8), 0x1 } +}; + static int yt8511_read_page(struct phy_device *phydev) { return __phy_read(phydev, YT8511_PAGE_SELECT); @@ -48,6 +101,33 @@ static int yt8511_write_page(struct phy_device *phydev, int page) return __phy_write(phydev, YT8511_PAGE_SELECT, page); }; +static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) +{ + int ret; + int val; + + ret = __phy_write(phydev, YT8511_PAGE_SELECT, regnum); + if (ret < 0) + return ret; + + val = __phy_read(phydev, YT8511_PAGE); + + return val; +} + +static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val) +{ + int ret; + + ret = __phy_write(phydev, YT8511_PAGE_SELECT, regnum); + if (ret < 0) + return ret; + + ret = __phy_write(phydev, YT8511_PAGE, val); + + return ret; +} + static int yt8511_config_init(struct phy_device *phydev) { int oldpage, ret = 0; @@ -111,6 +191,116 @@ static int yt8511_config_init(struct phy_device *phydev) return phy_restore_page(phydev, oldpage, ret); } +static int ytphy_config_init(struct phy_device *phydev) +{ + struct device_node *of_node; + u32 val; + u32 mask; + u32 cfg; + int ret; + int i = 0; + + of_node = phydev->mdio.dev.of_node; + if (of_node) { + ret = of_property_read_u32(of_node, ytphy_rxden_grp[0].name, &cfg); + if (!ret) { + mask = ytphy_rxden_grp[0].mask; + val = ytphy_read_ext(phydev, YTPHY_EXT_CHIP_CONFIG); + + /* check the cfg overflow or not */ + cfg = cfg > mask >> (ffs(mask) - 1) ? mask : cfg; + + val &= ~mask; + val |= FIELD_PREP(mask, cfg); + ytphy_write_ext(phydev, YTPHY_EXT_CHIP_CONFIG, val); + } + + val = ytphy_read_ext(phydev, YTPHY_EXT_RGMII_CONFIG1); + for (i = 0; i < ARRAY_SIZE(ytphy_rxtxd_grp); i++) { + ret = of_property_read_u32(of_node, ytphy_rxtxd_grp[i].name, &cfg); + if (!ret) { + mask = ytphy_rxtxd_grp[i].mask; + + /* check the cfg overflow or not */ + cfg = cfg > mask >> (ffs(mask) - 1) ? mask : cfg; + + val &= ~mask; + val |= cfg << (ffs(mask) - 1); + } + } + return ytphy_write_ext(phydev, YTPHY_EXT_RGMII_CONFIG1, val); + } + + phydev_err(phydev, "Get of node fail\n"); + + return -EINVAL; +} + +static void ytphy_link_change_notify(struct phy_device *phydev) +{ + u32 val; + struct ytphy_priv_t *ytphy_priv = phydev->priv; + + if (phydev->speed < 0) + return; + + val = ytphy_read_ext(phydev, YTPHY_EXT_RGMII_CONFIG1); + switch (phydev->speed) { + case SPEED_1000: + val &= ~ytphy_txinver_grp[0].mask; + val |= FIELD_PREP(ytphy_txinver_grp[0].mask, + ytphy_priv->tx_inverted_1000); + break; + + case SPEED_100: + val &= ~ytphy_txinver_grp[1].mask; + val |= FIELD_PREP(ytphy_txinver_grp[1].mask, + ytphy_priv->tx_inverted_100); + break; + + case SPEED_10: + val &= ~ytphy_txinver_grp[2].mask; + val |= FIELD_PREP(ytphy_txinver_grp[2].mask, + ytphy_priv->tx_inverted_10); + break; + + default: + break; + } + + ytphy_write_ext(phydev, YTPHY_EXT_RGMII_CONFIG1, val); +} + +static int yt8531_probe(struct phy_device *phydev) +{ + struct ytphy_priv_t *priv; + const struct device_node *of_node; + u32 val; + int ret; + + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + of_node = phydev->mdio.dev.of_node; + if (of_node) { + ret = of_property_read_u32(of_node, ytphy_txinver_grp[0].name, &val); + if (!ret) + priv->tx_inverted_1000 = val; + + ret = of_property_read_u32(of_node, ytphy_txinver_grp[1].name, &val); + if (!ret) + priv->tx_inverted_100 = val; + + ret = of_property_read_u32(of_node, ytphy_txinver_grp[2].name, &val); + if (!ret) + priv->tx_inverted_10 = val; + } + phydev->priv = priv; + + return 0; +} + static struct phy_driver motorcomm_phy_drvs[] = { { PHY_ID_MATCH_EXACT(PHY_ID_YT8511), @@ -120,6 +310,17 @@ static struct phy_driver motorcomm_phy_drvs[] = { .resume = genphy_resume, .read_page = yt8511_read_page, .write_page = yt8511_write_page, + }, { + PHY_ID_MATCH_EXACT(PHY_ID_YT8531), + .name = "YT8531 Gigabit Ethernet", + .probe = yt8531_probe, + .config_init = ytphy_config_init, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = yt8511_read_page, + .write_page = yt8511_write_page, + .link_change_notify = ytphy_link_change_notify, }, }; @@ -131,6 +332,7 @@ MODULE_LICENSE("GPL"); static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, + { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) }, { /* sentinal */ } }; -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-12-16 7:06 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-16 7:06 [PATCH v2 0/9] Add Ethernet driver for StarFive JH7110 SoC Yanhong Wang 2022-12-16 7:06 ` Yanhong Wang 2022-12-16 7:06 ` [PATCH v2 1/9] dt-bindings: net: snps,dwmac: Add dwmac-5.20 version Yanhong Wang 2022-12-16 7:06 ` Yanhong Wang 2022-12-16 7:06 ` [PATCH v2 2/9] dt-bindings: net: snps,dwmac: Update the maxitems number of resets and reset-names Yanhong Wang 2022-12-16 7:06 ` Yanhong Wang 2022-12-16 11:03 ` Krzysztof Kozlowski 2022-12-16 11:03 ` Krzysztof Kozlowski 2022-12-20 6:48 ` yanhong wang 2022-12-20 6:48 ` yanhong wang 2022-12-20 9:21 ` Krzysztof Kozlowski 2022-12-20 9:21 ` Krzysztof Kozlowski 2022-12-27 7:48 ` yanhong wang 2022-12-27 7:48 ` yanhong wang 2022-12-27 8:18 ` Krzysztof Kozlowski 2022-12-27 8:18 ` Krzysztof Kozlowski 2022-12-16 7:06 ` [PATCH v2 3/9] net: stmmac: platform: Add snps,dwmac-5.20 IP compatible string Yanhong Wang 2022-12-16 7:06 ` Yanhong Wang 2022-12-16 7:06 ` [PATCH v2 4/9] dt-bindings: net: Add bindings for StarFive dwmac Yanhong Wang 2022-12-16 7:06 ` Yanhong Wang 2022-12-16 11:05 ` Krzysztof Kozlowski 2022-12-16 11:05 ` Krzysztof Kozlowski 2022-12-20 6:53 ` yanhong wang 2022-12-20 6:53 ` yanhong wang 2022-12-16 11:06 ` Krzysztof Kozlowski 2022-12-16 11:06 ` Krzysztof Kozlowski 2022-12-20 6:57 ` yanhong wang 2022-12-20 6:57 ` yanhong wang 2022-12-20 18:03 ` Rob Herring 2022-12-20 18:03 ` Rob Herring 2022-12-16 7:06 ` [PATCH v2 5/9] dt-bindings: net: motorcomm: add support for Motorcomm YT8531 Yanhong Wang 2022-12-16 7:06 ` Yanhong Wang 2022-12-16 11:15 ` Krzysztof Kozlowski 2022-12-16 11:15 ` Krzysztof Kozlowski 2022-12-27 9:38 ` yanhong wang 2022-12-27 9:38 ` yanhong wang 2022-12-27 9:52 ` Krzysztof Kozlowski 2022-12-27 9:52 ` Krzysztof Kozlowski 2022-12-28 3:23 ` yanhong wang 2022-12-28 3:23 ` yanhong wang 2022-12-28 9:11 ` Krzysztof Kozlowski 2022-12-28 9:11 ` Krzysztof Kozlowski 2022-12-28 9:24 ` yanhong wang 2022-12-28 9:24 ` yanhong wang 2022-12-16 7:06 ` Yanhong Wang [this message] 2022-12-16 7:06 ` [PATCH v2 6/9] net: phy: motorcomm: Add YT8531 phy support Yanhong Wang 2022-12-16 8:41 ` Arun.Ramadoss 2022-12-16 8:41 ` Arun.Ramadoss 2022-12-16 11:58 ` Heiner Kallweit 2022-12-16 11:58 ` Heiner Kallweit 2022-12-21 1:16 ` yanhong wang 2022-12-21 1:16 ` yanhong wang 2022-12-20 14:20 ` Andrew Lunn 2022-12-20 14:20 ` Andrew Lunn 2022-12-16 7:06 ` [PATCH v2 7/9] net: stmmac: Add glue layer for StarFive JH71x0 SoCs Yanhong Wang 2022-12-16 7:06 ` Yanhong Wang 2022-12-16 11:19 ` Krzysztof Kozlowski 2022-12-16 11:19 ` Krzysztof Kozlowski 2022-12-16 7:06 ` [PATCH v2 8/9] riscv: dts: starfive: jh7110: Add ethernet device node Yanhong Wang 2022-12-16 7:06 ` Yanhong Wang 2022-12-16 7:06 ` [PATCH v2 9/9] riscv: dts: starfive: visionfive-v2: Add phy clock delay train configuration Yanhong Wang 2022-12-16 7:06 ` Yanhong Wang
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