* [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws
@ 2022-12-27 1:32 Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names Dmitry Baryshkov
` (11 more replies)
0 siblings, 12 replies; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Rework apq8084 gcc and mmcc drivers to use parent_data and parent_hws
instead of parent_names. The series is sent as an RFC, since some of the
parents are not fully clear to me.
Dmitry Baryshkov (12):
dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names
dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084
clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying
num_parents
clk: qcom: gcc-apq8084: move PLL clocks up
clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names
clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying
num_parents
clk: qcom: mmcc-apq8084: move clock parent tables down
clk: qcom: mmcc-apq8084: remove spdm clocks
clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names
ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device
.../bindings/clock/qcom,gcc-apq8084.yaml | 43 +
.../devicetree/bindings/clock/qcom,mmcc.yaml | 40 +
arch/arm/boot/dts/qcom-apq8084.dtsi | 18 +
drivers/clk/qcom/gcc-apq8084.c | 1024 +++++++-------
drivers/clk/qcom/mmcc-apq8084.c | 1189 +++++++----------
include/dt-bindings/clock/qcom,gcc-apq8084.h | 1 +
6 files changed, 1095 insertions(+), 1220 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-28 10:30 ` Krzysztof Kozlowski
2022-12-27 1:32 ` [RFC PATCH 02/12] dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
` (10 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Define clock/clock-names properties of the GCC device node to be used
on APQ8084 platform.
Note: the driver uses a single pcie_pipe clock, however most probably
there are two pipe clocks, one from each of PCIe QMP PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/clock/qcom,gcc-apq8084.yaml | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
index 8ade176c24f4..02a856f14fbe 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
@@ -25,6 +25,30 @@ properties:
compatible:
const: qcom,gcc-apq8084
+ clocks:
+ items:
+ - description: XO source
+ - description: Sleep clock source
+ - description: UFS RX symbol 0 clock
+ - description: UFS RX symbol 1 clock
+ - description: UFS TX symbol 0 clock
+ - description: UFS TX symbol 1 clock
+ - description: SATA ASIC0 clock
+ - description: SATA RX clock
+ - description: PCIe PIPE clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: sleep_clk
+ - const: ufs_rx_symbol_0_clk_src
+ - const: ufs_rx_symbol_1_clk_src
+ - const: ufs_tx_symbol_0_clk_src
+ - const: ufs_tx_symbol_1_clk_src
+ - const: sata_asic0_clk
+ - const: sata_rx_clk
+ - const: pcie_pipe
+
required:
- compatible
@@ -38,5 +62,24 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <&ufsphy 0>,
+ <&ufsphy 1>,
+ <&ufsphy 2>,
+ <&ufsphy 3>,
+ <&sata 0>,
+ <&sata 1>,
+ <&pcie_phy>;
+ clock-names = "xo",
+ "sleep_clk",
+ "ufs_rx_symbol_0_clk_src",
+ "ufs_rx_symbol_1_clk_src",
+ "ufs_tx_symbol_0_clk_src",
+ "ufs_tx_symbol_1_clk_src",
+ "sata_asic0_clk",
+ "sata_rx_clk",
+ "pcie_pipe";
};
...
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 02/12] dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-28 10:30 ` Krzysztof Kozlowski
2022-12-27 1:32 ` [RFC PATCH 03/12] dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084 Dmitry Baryshkov
` (9 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Add GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the
multimedia subsystem.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
include/dt-bindings/clock/qcom,gcc-apq8084.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h
index 7f657cf8cc8a..a985248d6332 100644
--- a/include/dt-bindings/clock/qcom,gcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -339,6 +339,7 @@
#define GCC_PCIE_1_MSTR_AXI_CLK 330
#define GCC_PCIE_1_PIPE_CLK 331
#define GCC_PCIE_1_SLV_AXI_CLK 332
+#define GCC_MMSS_GPLL0_CLK_SRC 333
/* gdscs */
#define USB_HS_HSIC_GDSC 0
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 03/12] dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 02/12] dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-28 10:31 ` Krzysztof Kozlowski
2022-12-27 1:32 ` [RFC PATCH 04/12] clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
` (8 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Define clock/clock-names properties of the MMCC device node to be used
on APQ8084 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/clock/qcom,mmcc.yaml | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
index e6d17426e903..fd926df80c64 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
@@ -137,6 +137,46 @@ allOf:
- const: edp_link_clk
- const: edp_vco_div
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,mmcc-apq8084
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board sleep source
+ - description: MMSS GPLL0 voted clock
+ - description: GPLL0 clock
+ - description: GPLL0 voted clock
+ - description: GPLL1 clock
+ - description: DSI phy instance 0 dsi clock
+ - description: DSI phy instance 0 byte clock
+ - description: DSI phy instance 1 dsi clock
+ - description: DSI phy instance 1 byte clock
+ - description: HDMI phy PLL clock
+ - description: eDP phy PLL link clock
+ - description: eDP phy PLL vco clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: sleep_clk
+ - const: mmss_gpll0_vote
+ - const: gpll0
+ - const: gpll0_vote
+ - const: gpll1
+ - const: dsi0pll
+ - const: dsi0pllbyte
+ - const: dsi1pll
+ - const: dsi1pllbyte
+ - const: hdmipll
+ - const: edp_link_clk
+ - const: edp_vco_div
+
- if:
properties:
compatible:
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 04/12] clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
` (2 preceding siblings ...)
2022-12-27 1:32 ` [RFC PATCH 03/12] dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084 Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-27 11:48 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 05/12] clk: qcom: gcc-apq8084: move PLL clocks up Dmitry Baryshkov
` (7 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-apq8084.c | 136 ++++++++++++++++-----------------
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index ab088d702d7c..b41f55b289ae 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -132,7 +132,7 @@ static struct clk_rcg2 config_noc_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "config_noc_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -144,7 +144,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "periph_noc_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -156,7 +156,7 @@ static struct clk_rcg2 system_noc_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -231,7 +231,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_axi_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -250,7 +250,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -269,7 +269,7 @@ static struct clk_rcg2 usb30_sec_master_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_sec_master_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -322,7 +322,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -347,7 +347,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -360,7 +360,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -374,7 +374,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -387,7 +387,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -401,7 +401,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -414,7 +414,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -428,7 +428,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -441,7 +441,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -455,7 +455,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -468,7 +468,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -482,7 +482,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -515,7 +515,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -529,7 +529,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -543,7 +543,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -557,7 +557,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -571,7 +571,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -585,7 +585,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -598,7 +598,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -612,7 +612,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -625,7 +625,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -639,7 +639,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -652,7 +652,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -666,7 +666,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -679,7 +679,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -693,7 +693,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -706,7 +706,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -720,7 +720,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -733,7 +733,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -747,7 +747,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -761,7 +761,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -775,7 +775,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -789,7 +789,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart3_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -803,7 +803,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart4_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -817,7 +817,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart5_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -831,7 +831,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart6_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -852,7 +852,7 @@ static struct clk_rcg2 ce1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ce1_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -873,7 +873,7 @@ static struct clk_rcg2 ce2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ce2_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -894,7 +894,7 @@ static struct clk_rcg2 ce3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ce3_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -915,7 +915,7 @@ static struct clk_rcg2 gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -929,7 +929,7 @@ static struct clk_rcg2 gp2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -943,7 +943,7 @@ static struct clk_rcg2 gp3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -962,7 +962,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
.parent_names = gcc_xo_pcie_sleep,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -976,7 +976,7 @@ static struct clk_rcg2 pcie_1_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_aux_clk_src",
.parent_names = gcc_xo_pcie_sleep,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -995,7 +995,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
.parent_names = gcc_xo_pcie,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_pcie),
.ops = &clk_rcg2_ops,
},
};
@@ -1008,7 +1008,7 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_pipe_clk_src",
.parent_names = gcc_xo_pcie,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_pcie),
.ops = &clk_rcg2_ops,
},
};
@@ -1026,7 +1026,7 @@ static struct clk_rcg2 pdm2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1046,7 +1046,7 @@ static struct clk_rcg2 sata_asic0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_asic0_clk_src",
.parent_names = gcc_xo_sata_asic0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_sata_asic0),
.ops = &clk_rcg2_ops,
},
};
@@ -1066,7 +1066,7 @@ static struct clk_rcg2 sata_pmalive_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_pmalive_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1086,7 +1086,7 @@ static struct clk_rcg2 sata_rx_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_rx_clk_src",
.parent_names = gcc_xo_sata_rx,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_sata_rx),
.ops = &clk_rcg2_ops,
},
};
@@ -1104,7 +1104,7 @@ static struct clk_rcg2 sata_rx_oob_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_rx_oob_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1131,7 +1131,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_xo_gpll0_gpll4,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1145,7 +1145,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1159,7 +1159,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc3_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1173,7 +1173,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc4_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1192,7 +1192,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1210,7 +1210,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1228,7 +1228,7 @@ static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_sec_mock_utmi_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1246,7 +1246,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1312,7 +1312,7 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_io_cal_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1347,7 +1347,7 @@ static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_mock_utmi_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1365,7 +1365,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_system_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 05/12] clk: qcom: gcc-apq8084: move PLL clocks up
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
` (3 preceding siblings ...)
2022-12-27 1:32 ` [RFC PATCH 04/12] clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-27 11:49 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 06/12] clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
` (6 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Move PLL clock declarations up, before clock parent tables, so that we
can use pll hw clock fields in the next commit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-apq8084.c | 162 ++++++++++++++++-----------------
1 file changed, 81 insertions(+), 81 deletions(-)
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index b41f55b289ae..05a68f645115 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -36,6 +36,87 @@ enum {
P_SLEEP_CLK,
};
+static struct clk_pll gpll0 = {
+ .l_reg = 0x0004,
+ .m_reg = 0x0008,
+ .n_reg = 0x000c,
+ .config_reg = 0x0014,
+ .mode_reg = 0x0000,
+ .status_reg = 0x001c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll0_vote = {
+ .enable_reg = 0x1480,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_vote",
+ .parent_names = (const char *[]){ "gpll0" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll gpll1 = {
+ .l_reg = 0x0044,
+ .m_reg = 0x0048,
+ .n_reg = 0x004c,
+ .config_reg = 0x0054,
+ .mode_reg = 0x0040,
+ .status_reg = 0x005c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll1",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll1_vote = {
+ .enable_reg = 0x1480,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_vote",
+ .parent_names = (const char *[]){ "gpll1" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll gpll4 = {
+ .l_reg = 0x1dc4,
+ .m_reg = 0x1dc8,
+ .n_reg = 0x1dcc,
+ .config_reg = 0x1dd4,
+ .mode_reg = 0x1dc0,
+ .status_reg = 0x1ddc,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll4",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll4_vote = {
+ .enable_reg = 0x1480,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_vote",
+ .parent_names = (const char *[]){ "gpll4" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 }
@@ -98,33 +179,6 @@ static const char * const gcc_xo_pcie_sleep[] = {
"sleep_clk_src",
};
-static struct clk_pll gpll0 = {
- .l_reg = 0x0004,
- .m_reg = 0x0008,
- .n_reg = 0x000c,
- .config_reg = 0x0014,
- .mode_reg = 0x0000,
- .status_reg = 0x001c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll0_vote = {
- .enable_reg = 0x1480,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_vote",
- .parent_names = (const char *[]){ "gpll0" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
static struct clk_rcg2 config_noc_clk_src = {
.cmd_rcgr = 0x0150,
.hid_width = 5,
@@ -161,60 +215,6 @@ static struct clk_rcg2 system_noc_clk_src = {
},
};
-static struct clk_pll gpll1 = {
- .l_reg = 0x0044,
- .m_reg = 0x0048,
- .n_reg = 0x004c,
- .config_reg = 0x0054,
- .mode_reg = 0x0040,
- .status_reg = 0x005c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll1",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll1_vote = {
- .enable_reg = 0x1480,
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gpll1_vote",
- .parent_names = (const char *[]){ "gpll1" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
-static struct clk_pll gpll4 = {
- .l_reg = 0x1dc4,
- .m_reg = 0x1dc8,
- .n_reg = 0x1dcc,
- .config_reg = 0x1dd4,
- .mode_reg = 0x1dc0,
- .status_reg = 0x1ddc,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll4_vote = {
- .enable_reg = 0x1480,
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_vote",
- .parent_names = (const char *[]){ "gpll4" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 06/12] clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
` (4 preceding siblings ...)
2022-12-27 1:32 ` [RFC PATCH 05/12] clk: qcom: gcc-apq8084: move PLL clocks up Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-27 11:55 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
` (5 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Note, the system names for xo clocks were changed from "xo" to
"xo_board" to follow the example of other platforms. This switches the
clocks to use DT-provided "xo_board" clock instead of manually
registered "xo" clock and allows us to drop qcom_cc_register_board_clk()
call from the driver at some point.
In the same way change the looked up system "sleep_clk_src" clock to
"sleep_clk", which is registered from DT.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-apq8084.c | 730 +++++++++++++++++----------------
1 file changed, 371 insertions(+), 359 deletions(-)
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index 05a68f645115..c26e222c78d4 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -46,7 +46,9 @@ static struct clk_pll gpll0 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo", .name = "xo_board",
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -57,7 +59,9 @@ static struct clk_regmap gpll0_vote = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_vote",
- .parent_names = (const char *[]){ "gpll0" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gpll0.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -73,7 +77,9 @@ static struct clk_pll gpll1 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo", .name = "xo_board",
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -84,7 +90,9 @@ static struct clk_regmap gpll1_vote = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_vote",
- .parent_names = (const char *[]){ "gpll1" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gpll1.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -100,7 +108,9 @@ static struct clk_pll gpll4 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo", .name = "xo_board",
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -111,7 +121,9 @@ static struct clk_regmap gpll4_vote = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4_vote",
- .parent_names = (const char *[]){ "gpll4" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gpll4.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -122,9 +134,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_GPLL0, 1 }
};
-static const char * const gcc_xo_gpll0[] = {
- "xo",
- "gpll0_vote",
+static const struct clk_parent_data gcc_xo_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
@@ -133,10 +145,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_GPLL4, 5 }
};
-static const char * const gcc_xo_gpll0_gpll4[] = {
- "xo",
- "gpll0_vote",
- "gpll4_vote",
+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .hw = &gpll4_vote.hw },
};
static const struct parent_map gcc_xo_sata_asic0_map[] = {
@@ -144,9 +156,9 @@ static const struct parent_map gcc_xo_sata_asic0_map[] = {
{ P_SATA_ASIC0_CLK, 2 }
};
-static const char * const gcc_xo_sata_asic0[] = {
- "xo",
- "sata_asic0_clk",
+static const struct clk_parent_data gcc_xo_sata_asic0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "sata_asic0_clk", .name = "sata_asic0_clk" },
};
static const struct parent_map gcc_xo_sata_rx_map[] = {
@@ -154,9 +166,9 @@ static const struct parent_map gcc_xo_sata_rx_map[] = {
{ P_SATA_RX_CLK, 2}
};
-static const char * const gcc_xo_sata_rx[] = {
- "xo",
- "sata_rx_clk",
+static const struct clk_parent_data gcc_xo_sata_rx[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "sata_rx_clk", .name = "sata_rx_clk" },
};
static const struct parent_map gcc_xo_pcie_map[] = {
@@ -164,9 +176,9 @@ static const struct parent_map gcc_xo_pcie_map[] = {
{ P_PCIE_0_1_PIPE_CLK, 2 }
};
-static const char * const gcc_xo_pcie[] = {
- "xo",
- "pcie_pipe",
+static const struct clk_parent_data gcc_xo_pcie[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "pcie_pipe", .name = "pcie_pipe" },
};
static const struct parent_map gcc_xo_pcie_sleep_map[] = {
@@ -174,9 +186,9 @@ static const struct parent_map gcc_xo_pcie_sleep_map[] = {
{ P_SLEEP_CLK, 6 }
};
-static const char * const gcc_xo_pcie_sleep[] = {
- "xo",
- "sleep_clk_src",
+static const struct clk_parent_data gcc_xo_pcie_sleep[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static struct clk_rcg2 config_noc_clk_src = {
@@ -185,7 +197,7 @@ static struct clk_rcg2 config_noc_clk_src = {
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "config_noc_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -197,7 +209,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "periph_noc_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -209,7 +221,7 @@ static struct clk_rcg2 system_noc_clk_src = {
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -230,7 +242,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
.freq_tbl = ftbl_gcc_ufs_axi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_axi_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -249,7 +261,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
.freq_tbl = ftbl_gcc_usb30_master_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -268,7 +280,25 @@ static struct clk_rcg2 usb30_sec_master_clk_src = {
.freq_tbl = ftbl_gcc_usb30_sec_master_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_sec_master_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
+ F(125000000, P_GPLL0, 1, 5, 24),
+ { }
+};
+
+static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x1be8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_sec_mock_utmi_clk_src",
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -281,8 +311,8 @@ static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk",
- .parent_names = (const char *[]){
- "usb30_sec_mock_utmi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_sec_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -298,8 +328,8 @@ static struct clk_branch gcc_usb30_sec_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -321,7 +351,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -346,7 +376,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -359,7 +389,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -373,7 +403,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -386,7 +416,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -400,7 +430,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -413,7 +443,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -427,7 +457,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -440,7 +470,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -454,7 +484,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -467,7 +497,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -481,7 +511,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -514,7 +544,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -528,7 +558,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -542,7 +572,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -556,7 +586,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -570,7 +600,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -584,7 +614,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -597,7 +627,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -611,7 +641,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -624,7 +654,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -638,7 +668,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -651,7 +681,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -665,7 +695,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -678,7 +708,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -692,7 +722,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -705,7 +735,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -719,7 +749,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -732,7 +762,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -746,7 +776,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -760,7 +790,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -774,7 +804,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -788,7 +818,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -802,7 +832,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -816,7 +846,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -830,7 +860,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -851,7 +881,7 @@ static struct clk_rcg2 ce1_clk_src = {
.freq_tbl = ftbl_gcc_ce1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ce1_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -872,7 +902,7 @@ static struct clk_rcg2 ce2_clk_src = {
.freq_tbl = ftbl_gcc_ce2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ce2_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -893,7 +923,7 @@ static struct clk_rcg2 ce3_clk_src = {
.freq_tbl = ftbl_gcc_ce3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ce3_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -914,7 +944,7 @@ static struct clk_rcg2 gp1_clk_src = {
.freq_tbl = ftbl_gcc_gp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -928,7 +958,7 @@ static struct clk_rcg2 gp2_clk_src = {
.freq_tbl = ftbl_gcc_gp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -942,7 +972,7 @@ static struct clk_rcg2 gp3_clk_src = {
.freq_tbl = ftbl_gcc_gp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -961,7 +991,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
.freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
- .parent_names = gcc_xo_pcie_sleep,
+ .parent_data = gcc_xo_pcie_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
.ops = &clk_rcg2_ops,
},
@@ -975,7 +1005,7 @@ static struct clk_rcg2 pcie_1_aux_clk_src = {
.freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_aux_clk_src",
- .parent_names = gcc_xo_pcie_sleep,
+ .parent_data = gcc_xo_pcie_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
.ops = &clk_rcg2_ops,
},
@@ -994,7 +1024,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
.freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
- .parent_names = gcc_xo_pcie,
+ .parent_data = gcc_xo_pcie,
.num_parents = ARRAY_SIZE(gcc_xo_pcie),
.ops = &clk_rcg2_ops,
},
@@ -1007,7 +1037,7 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = {
.freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_pipe_clk_src",
- .parent_names = gcc_xo_pcie,
+ .parent_data = gcc_xo_pcie,
.num_parents = ARRAY_SIZE(gcc_xo_pcie),
.ops = &clk_rcg2_ops,
},
@@ -1025,7 +1055,7 @@ static struct clk_rcg2 pdm2_clk_src = {
.freq_tbl = ftbl_gcc_pdm2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1045,7 +1075,7 @@ static struct clk_rcg2 sata_asic0_clk_src = {
.freq_tbl = ftbl_gcc_sata_asic0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_asic0_clk_src",
- .parent_names = gcc_xo_sata_asic0,
+ .parent_data = gcc_xo_sata_asic0,
.num_parents = ARRAY_SIZE(gcc_xo_sata_asic0),
.ops = &clk_rcg2_ops,
},
@@ -1065,7 +1095,7 @@ static struct clk_rcg2 sata_pmalive_clk_src = {
.freq_tbl = ftbl_gcc_sata_pmalive_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_pmalive_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1085,7 +1115,7 @@ static struct clk_rcg2 sata_rx_clk_src = {
.freq_tbl = ftbl_gcc_sata_rx_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_rx_clk_src",
- .parent_names = gcc_xo_sata_rx,
+ .parent_data = gcc_xo_sata_rx,
.num_parents = ARRAY_SIZE(gcc_xo_sata_rx),
.ops = &clk_rcg2_ops,
},
@@ -1103,7 +1133,7 @@ static struct clk_rcg2 sata_rx_oob_clk_src = {
.freq_tbl = ftbl_gcc_sata_rx_oob_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_rx_oob_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1130,7 +1160,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
+ .parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_floor_ops,
},
@@ -1144,7 +1174,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
@@ -1158,7 +1188,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
@@ -1172,7 +1202,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
@@ -1191,7 +1221,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
.freq_tbl = ftbl_gcc_tsif_ref_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1209,25 +1239,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
-};
-
-static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
- F(125000000, P_GPLL0, 1, 5, 24),
- { }
-};
-
-static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
- .cmd_rcgr = 0x1be8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_sec_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1245,7 +1257,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
.freq_tbl = ftbl_gcc_usb_hs_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1268,9 +1280,9 @@ static struct clk_rcg2 usb_hsic_clk_src = {
.freq_tbl = ftbl_gcc_usb_hsic_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_clk_src",
- .parent_names = (const char *[]){
- "xo",
- "gpll1_vote",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll1_vote.hw },
},
.num_parents = 2,
.ops = &clk_rcg2_ops,
@@ -1290,9 +1302,9 @@ static struct clk_rcg2 usb_hsic_ahb_clk_src = {
.freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_ahb_clk_src",
- .parent_names = (const char *[]){
- "xo",
- "gpll1_vote",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll1_vote.hw },
},
.num_parents = 2,
.ops = &clk_rcg2_ops,
@@ -1311,29 +1323,12 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
.freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_io_cal_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
- .halt_reg = 0x1f14,
- .clkr = {
- .enable_reg = 0x1f14,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_hsic_mock_utmi_clk",
- .parent_names = (const char *[]){
- "usb_hsic_mock_utmi_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
@@ -1346,12 +1341,29 @@ static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
.freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
+static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
+ .halt_reg = 0x1f14,
+ .clkr = {
+ .enable_reg = 0x1f14,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb_hsic_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hsic_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
F(75000000, P_GPLL0, 8, 0, 0),
{ }
@@ -1364,7 +1376,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
.freq_tbl = ftbl_gcc_usb_hsic_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_system_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1378,8 +1390,8 @@ static struct clk_branch gcc_bam_dma_ahb_clk = {
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_bam_dma_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1395,8 +1407,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1411,8 +1423,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup1_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1428,8 +1440,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup1_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1445,8 +1457,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup2_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1462,8 +1474,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup2_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1479,8 +1491,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup3_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1496,8 +1508,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup3_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1513,8 +1525,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup4_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1530,8 +1542,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup4_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1547,8 +1559,8 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup5_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1564,8 +1576,8 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup5_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1581,8 +1593,8 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup6_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1598,8 +1610,8 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup6_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1615,8 +1627,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart1_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1632,8 +1644,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart2_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1649,8 +1661,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart3_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1666,8 +1678,8 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart4_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1683,8 +1695,8 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart5_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart5_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1700,8 +1712,8 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart6_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart6_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1718,8 +1730,8 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1734,8 +1746,8 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup1_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1751,8 +1763,8 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup1_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1768,8 +1780,8 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup2_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1785,8 +1797,8 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup2_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1802,8 +1814,8 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup3_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1819,8 +1831,8 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup3_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1836,8 +1848,8 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup4_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1853,8 +1865,8 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup4_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1870,8 +1882,8 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup5_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1887,8 +1899,8 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup5_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1904,8 +1916,8 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup6_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1921,8 +1933,8 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup6_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1938,8 +1950,8 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart1_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_uart1_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1955,8 +1967,8 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart2_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_uart2_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1972,8 +1984,8 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart3_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_uart3_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1989,8 +2001,8 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart4_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_uart4_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2006,8 +2018,8 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart5_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_uart5_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_uart5_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2023,8 +2035,8 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart6_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_uart6_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp2_uart6_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2041,8 +2053,8 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2058,8 +2070,8 @@ static struct clk_branch gcc_ce1_ahb_clk = {
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2075,8 +2087,8 @@ static struct clk_branch gcc_ce1_axi_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_clk",
- .parent_names = (const char *[]){
- "system_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2092,8 +2104,8 @@ static struct clk_branch gcc_ce1_clk = {
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_clk",
- .parent_names = (const char *[]){
- "ce1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ce1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2110,8 +2122,8 @@ static struct clk_branch gcc_ce2_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce2_ahb_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2127,8 +2139,8 @@ static struct clk_branch gcc_ce2_axi_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce2_axi_clk",
- .parent_names = (const char *[]){
- "system_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2144,8 +2156,8 @@ static struct clk_branch gcc_ce2_clk = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce2_clk",
- .parent_names = (const char *[]){
- "ce2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ce2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2162,8 +2174,8 @@ static struct clk_branch gcc_ce3_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce3_ahb_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2179,8 +2191,8 @@ static struct clk_branch gcc_ce3_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce3_axi_clk",
- .parent_names = (const char *[]){
- "system_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2196,8 +2208,8 @@ static struct clk_branch gcc_ce3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce3_clk",
- .parent_names = (const char *[]){
- "ce3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ce3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2213,8 +2225,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
- .parent_names = (const char *[]){
- "gp1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2230,8 +2242,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
- .parent_names = (const char *[]){
- "gp2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2247,8 +2259,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
- .parent_names = (const char *[]){
- "gp3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2264,8 +2276,8 @@ static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ocmem_noc_cfg_ahb_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2280,8 +2292,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
- .parent_names = (const char *[]){
- "pcie_0_aux_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2297,8 +2309,8 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2314,8 +2326,8 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2331,8 +2343,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
- .parent_names = (const char *[]){
- "pcie_0_pipe_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2348,8 +2360,8 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2365,8 +2377,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
- .parent_names = (const char *[]){
- "pcie_1_aux_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2382,8 +2394,8 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2399,8 +2411,8 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2416,8 +2428,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
- .parent_names = (const char *[]){
- "pcie_1_pipe_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2433,8 +2445,8 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2450,8 +2462,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
- .parent_names = (const char *[]){
- "pdm2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2467,8 +2479,8 @@ static struct clk_branch gcc_pdm_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2483,8 +2495,8 @@ static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_periph_noc_usb_hsic_ahb_clk",
- .parent_names = (const char *[]){
- "usb_hsic_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hsic_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2501,8 +2513,8 @@ static struct clk_branch gcc_prng_ahb_clk = {
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2517,8 +2529,8 @@ static struct clk_branch gcc_sata_asic0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_asic0_clk",
- .parent_names = (const char *[]){
- "sata_asic0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sata_asic0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2534,8 +2546,8 @@ static struct clk_branch gcc_sata_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_axi_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2551,8 +2563,8 @@ static struct clk_branch gcc_sata_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_cfg_ahb_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2568,8 +2580,8 @@ static struct clk_branch gcc_sata_pmalive_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_pmalive_clk",
- .parent_names = (const char *[]){
- "sata_pmalive_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sata_pmalive_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2585,8 +2597,8 @@ static struct clk_branch gcc_sata_rx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_rx_clk",
- .parent_names = (const char *[]){
- "sata_rx_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sata_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2602,8 +2614,8 @@ static struct clk_branch gcc_sata_rx_oob_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_rx_oob_clk",
- .parent_names = (const char *[]){
- "sata_rx_oob_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sata_rx_oob_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2619,8 +2631,8 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2635,8 +2647,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
- .parent_names = (const char *[]){
- "sdcc1_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2652,8 +2664,8 @@ static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_cdccal_ff_clk",
- .parent_names = (const char *[]){
- "xo"
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" }
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2668,8 +2680,8 @@ static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_cdccal_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src"
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "sleep_clk", .name = "sleep_clk" }
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2684,8 +2696,8 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2700,8 +2712,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
- .parent_names = (const char *[]){
- "sdcc2_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2717,8 +2729,8 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2733,8 +2745,8 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_apps_clk",
- .parent_names = (const char *[]){
- "sdcc3_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sdcc3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2750,8 +2762,8 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2766,8 +2778,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
- .parent_names = (const char *[]){
- "sdcc4_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2783,8 +2795,8 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_axi_clk",
- .parent_names = (const char *[]){
- "ufs_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2800,8 +2812,8 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_axi_clk",
- .parent_names = (const char *[]){
- "usb30_master_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2817,8 +2829,8 @@ static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_sec_axi_clk",
- .parent_names = (const char *[]){
- "usb30_sec_master_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2834,8 +2846,8 @@ static struct clk_branch gcc_tsif_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2850,8 +2862,8 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_inactivity_timers_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2867,8 +2879,8 @@ static struct clk_branch gcc_tsif_ref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
- .parent_names = (const char *[]){
- "tsif_ref_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &tsif_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2884,8 +2896,8 @@ static struct clk_branch gcc_ufs_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
- .parent_names = (const char *[]){
- "config_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2901,8 +2913,8 @@ static struct clk_branch gcc_ufs_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_axi_clk",
- .parent_names = (const char *[]){
- "ufs_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2918,8 +2930,8 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_cfg_clk",
- .parent_names = (const char *[]){
- "ufs_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2935,8 +2947,8 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_0_clk",
- .parent_names = (const char *[]){
- "ufs_rx_symbol_0_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2952,8 +2964,8 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_1_clk",
- .parent_names = (const char *[]){
- "ufs_rx_symbol_1_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2969,8 +2981,8 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_cfg_clk",
- .parent_names = (const char *[]){
- "ufs_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2986,8 +2998,8 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_0_clk",
- .parent_names = (const char *[]){
- "ufs_tx_symbol_0_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3003,8 +3015,8 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_1_clk",
- .parent_names = (const char *[]){
- "ufs_tx_symbol_1_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "ufs_tx_symbol_1_clk_src", .name = "ufs_tx_symbol_1_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3020,8 +3032,8 @@ static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2a_phy_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3036,8 +3048,8 @@ static struct clk_branch gcc_usb2b_phy_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2b_phy_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3052,8 +3064,8 @@ static struct clk_branch gcc_usb30_master_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
- .parent_names = (const char *[]){
- "usb30_master_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3069,8 +3081,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk",
- .parent_names = (const char *[]){
- "usb30_sec_master_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3086,8 +3098,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
- .parent_names = (const char *[]){
- "usb30_mock_utmi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3103,8 +3115,8 @@ static struct clk_branch gcc_usb30_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3119,8 +3131,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3135,8 +3147,8 @@ static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_inactivity_timers_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3152,8 +3164,8 @@ static struct clk_branch gcc_usb_hs_system_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
- .parent_names = (const char *[]){
- "usb_hs_system_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3169,8 +3181,8 @@ static struct clk_branch gcc_usb_hsic_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3185,8 +3197,8 @@ static struct clk_branch gcc_usb_hsic_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_clk",
- .parent_names = (const char *[]){
- "usb_hsic_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hsic_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3202,8 +3214,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_io_cal_clk",
- .parent_names = (const char *[]){
- "usb_hsic_io_cal_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hsic_io_cal_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3219,8 +3231,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_io_cal_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3235,8 +3247,8 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_system_clk",
- .parent_names = (const char *[]){
- "usb_hsic_system_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hsic_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
` (5 preceding siblings ...)
2022-12-27 1:32 ` [RFC PATCH 06/12] clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-27 11:58 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 08/12] clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
` (4 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Add the GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for
the multimedia subsystem.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-apq8084.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index c26e222c78d4..7085d2ccae49 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -1382,6 +1382,19 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
},
};
+static struct clk_regmap gcc_mmss_gpll0_clk_src = {
+ .enable_reg = 0x1484,
+ .enable_mask = BIT(26),
+ .hw.init = &(struct clk_init_data){
+ .name = "mmss_gpll0_vote",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpll0_vote.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_simple_ops,
+ },
+};
+
static struct clk_branch gcc_bam_dma_ahb_clk = {
.halt_reg = 0x0d44,
.halt_check = BRANCH_HALT_VOTED,
@@ -3480,6 +3493,7 @@ static struct clk_regmap *gcc_apq8084_clocks[] = {
[GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
[GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
+ [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
};
static struct gdsc *gcc_apq8084_gdscs[] = {
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 08/12] clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parents
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
` (6 preceding siblings ...)
2022-12-27 1:32 ` [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-27 12:00 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 09/12] clk: qcom: mmcc-apq8084: move clock parent tables down Dmitry Baryshkov
` (3 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/mmcc-apq8084.c | 88 ++++++++++++++++-----------------
1 file changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index e9f971359155..4acbcb43927f 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -319,7 +319,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_ahb_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -344,7 +344,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_axi_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -368,7 +368,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ocmemnoc_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -387,7 +387,7 @@ static struct clk_rcg2 csi0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -400,7 +400,7 @@ static struct clk_rcg2 csi1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -413,7 +413,7 @@ static struct clk_rcg2 csi2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -426,7 +426,7 @@ static struct clk_rcg2 csi3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi3_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -456,7 +456,7 @@ static struct clk_rcg2 vfe0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -469,7 +469,7 @@ static struct clk_rcg2 vfe1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -497,7 +497,7 @@ static struct clk_rcg2 mdp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -509,7 +509,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_names = mmcc_xo_mmpll0_1_2_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -532,7 +532,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -545,7 +545,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg1_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -558,7 +558,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg2_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -571,7 +571,7 @@ static struct clk_rcg2 pclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -585,7 +585,7 @@ static struct clk_rcg2 pclk1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -610,7 +610,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
.parent_names = mmcc_xo_mmpll0_1_3_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -629,7 +629,7 @@ static struct clk_rcg2 vp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vp_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -648,7 +648,7 @@ static struct clk_rcg2 cci_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
@@ -672,7 +672,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
- .num_parents = 7,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -686,7 +686,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
- .num_parents = 7,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -714,7 +714,7 @@ static struct clk_rcg2 mclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
@@ -728,7 +728,7 @@ static struct clk_rcg2 mclk1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
@@ -742,7 +742,7 @@ static struct clk_rcg2 mclk2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
@@ -756,7 +756,7 @@ static struct clk_rcg2 mclk3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk3_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
@@ -775,7 +775,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -788,7 +788,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -801,7 +801,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2phytimer_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -824,7 +824,7 @@ static struct clk_rcg2 cpp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -836,7 +836,7 @@ static struct clk_rcg2 byte0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -849,7 +849,7 @@ static struct clk_rcg2 byte1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -868,7 +868,7 @@ static struct clk_rcg2 edpaux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "edpaux_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -887,7 +887,7 @@ static struct clk_rcg2 edplink_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "edplink_clk_src",
.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -907,7 +907,7 @@ static struct clk_rcg2 edppixel_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "edppixel_clk_src",
.parent_names = mmcc_xo_dsi_hdmi_edp,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
.ops = &clk_edp_pixel_ops,
},
};
@@ -925,7 +925,7 @@ static struct clk_rcg2 esc0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -938,7 +938,7 @@ static struct clk_rcg2 esc1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -956,7 +956,7 @@ static struct clk_rcg2 extpclk_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "extpclk_clk_src",
.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_byte_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -975,7 +975,7 @@ static struct clk_rcg2 hdmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -993,7 +993,7 @@ static struct clk_rcg2 vsync_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1011,7 +1011,7 @@ static struct clk_rcg2 rbcpr_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1029,7 +1029,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1052,7 +1052,7 @@ static struct clk_rcg2 maple_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "maple_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1074,7 +1074,7 @@ static struct clk_rcg2 vdp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vdp_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1093,7 +1093,7 @@ static struct clk_rcg2 vpu_bus_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vpu_bus_clk_src",
.parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 09/12] clk: qcom: mmcc-apq8084: move clock parent tables down
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
` (7 preceding siblings ...)
2022-12-27 1:32 ` [RFC PATCH 08/12] clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-27 12:00 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 10/12] clk: qcom: mmcc-apq8084: remove spdm clocks Dmitry Baryshkov
` (2 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Move clock parent tables down, after the PLL declrataions, so that we
can use pll hw clock fields in the next commit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/mmcc-apq8084.c | 200 ++++++++++++++++----------------
1 file changed, 100 insertions(+), 100 deletions(-)
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 4acbcb43927f..fee7c767132d 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -40,6 +40,106 @@ enum {
P_MMSLEEP,
};
+static struct clk_pll mmpll0 = {
+ .l_reg = 0x0004,
+ .m_reg = 0x0008,
+ .n_reg = 0x000c,
+ .config_reg = 0x0014,
+ .mode_reg = 0x0000,
+ .status_reg = 0x001c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll0",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap mmpll0_vote = {
+ .enable_reg = 0x0100,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "mmpll0_vote",
+ .parent_names = (const char *[]){ "mmpll0" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll mmpll1 = {
+ .l_reg = 0x0044,
+ .m_reg = 0x0048,
+ .n_reg = 0x004c,
+ .config_reg = 0x0050,
+ .mode_reg = 0x0040,
+ .status_reg = 0x005c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll1",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap mmpll1_vote = {
+ .enable_reg = 0x0100,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "mmpll1_vote",
+ .parent_names = (const char *[]){ "mmpll1" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll mmpll2 = {
+ .l_reg = 0x4104,
+ .m_reg = 0x4108,
+ .n_reg = 0x410c,
+ .config_reg = 0x4110,
+ .mode_reg = 0x4100,
+ .status_reg = 0x411c,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll2",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_pll mmpll3 = {
+ .l_reg = 0x0084,
+ .m_reg = 0x0088,
+ .n_reg = 0x008c,
+ .config_reg = 0x0090,
+ .mode_reg = 0x0080,
+ .status_reg = 0x009c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll3",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_pll mmpll4 = {
+ .l_reg = 0x00a4,
+ .m_reg = 0x00a8,
+ .n_reg = 0x00ac,
+ .config_reg = 0x00b0,
+ .mode_reg = 0x0080,
+ .status_reg = 0x00bc,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll4",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
@@ -212,106 +312,6 @@ static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
"sleep_clk_src",
};
-static struct clk_pll mmpll0 = {
- .l_reg = 0x0004,
- .m_reg = 0x0008,
- .n_reg = 0x000c,
- .config_reg = 0x0014,
- .mode_reg = 0x0000,
- .status_reg = 0x001c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll0",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap mmpll0_vote = {
- .enable_reg = 0x0100,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmpll0_vote",
- .parent_names = (const char *[]){ "mmpll0" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
-static struct clk_pll mmpll1 = {
- .l_reg = 0x0044,
- .m_reg = 0x0048,
- .n_reg = 0x004c,
- .config_reg = 0x0050,
- .mode_reg = 0x0040,
- .status_reg = 0x005c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll1",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap mmpll1_vote = {
- .enable_reg = 0x0100,
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "mmpll1_vote",
- .parent_names = (const char *[]){ "mmpll1" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
-static struct clk_pll mmpll2 = {
- .l_reg = 0x4104,
- .m_reg = 0x4108,
- .n_reg = 0x410c,
- .config_reg = 0x4110,
- .mode_reg = 0x4100,
- .status_reg = 0x411c,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll2",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_pll mmpll3 = {
- .l_reg = 0x0084,
- .m_reg = 0x0088,
- .n_reg = 0x008c,
- .config_reg = 0x0090,
- .mode_reg = 0x0080,
- .status_reg = 0x009c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll3",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_pll mmpll4 = {
- .l_reg = 0x00a4,
- .m_reg = 0x00a8,
- .n_reg = 0x00ac,
- .config_reg = 0x00b0,
- .mode_reg = 0x0080,
- .status_reg = 0x00bc,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll4",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
static struct clk_rcg2 mmss_ahb_clk_src = {
.cmd_rcgr = 0x5000,
.hid_width = 5,
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 10/12] clk: qcom: mmcc-apq8084: remove spdm clocks
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
` (8 preceding siblings ...)
2022-12-27 1:32 ` [RFC PATCH 09/12] clk: qcom: mmcc-apq8084: move clock parent tables down Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-27 12:01 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 11/12] clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device Dmitry Baryshkov
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Georgi Djakov
SPDM is used for debug/profiling and does not have any other
functionality. These clocks can safely be removed.
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Suggested-by: Georgi Djakov <djakov@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
1 file changed, 271 deletions(-)
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index fee7c767132d..631b1ff8cf01 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -2364,262 +2364,6 @@ static struct clk_branch mmss_rbcpr_clk = {
},
};
-static struct clk_branch mmss_spdm_ahb_clk = {
- .halt_reg = 0x0230,
- .clkr = {
- .enable_reg = 0x0230,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_ahb_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_axi_clk = {
- .halt_reg = 0x0210,
- .clkr = {
- .enable_reg = 0x0210,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_axi_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_axi_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_csi0_clk = {
- .halt_reg = 0x023c,
- .clkr = {
- .enable_reg = 0x023c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_csi0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_csi0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_gfx3d_clk = {
- .halt_reg = 0x022c,
- .clkr = {
- .enable_reg = 0x022c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_gfx3d_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_gfx3d_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_jpeg0_clk = {
- .halt_reg = 0x0204,
- .clkr = {
- .enable_reg = 0x0204,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_jpeg0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_jpeg0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_jpeg1_clk = {
- .halt_reg = 0x0208,
- .clkr = {
- .enable_reg = 0x0208,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_jpeg1_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_jpeg1_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_jpeg2_clk = {
- .halt_reg = 0x0224,
- .clkr = {
- .enable_reg = 0x0224,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_jpeg2_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_jpeg2_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_mdp_clk = {
- .halt_reg = 0x020c,
- .clkr = {
- .enable_reg = 0x020c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_mdp_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_mdp_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_pclk0_clk = {
- .halt_reg = 0x0234,
- .clkr = {
- .enable_reg = 0x0234,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_pclk0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_pclk0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_pclk1_clk = {
- .halt_reg = 0x0228,
- .clkr = {
- .enable_reg = 0x0228,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_pclk1_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_pclk1_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_vcodec0_clk = {
- .halt_reg = 0x0214,
- .clkr = {
- .enable_reg = 0x0214,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_vcodec0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_vcodec0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_vfe0_clk = {
- .halt_reg = 0x0218,
- .clkr = {
- .enable_reg = 0x0218,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_vfe0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_vfe0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_vfe1_clk = {
- .halt_reg = 0x021c,
- .clkr = {
- .enable_reg = 0x021c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_vfe1_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_vfe1_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_rm_axi_clk = {
- .halt_reg = 0x0304,
- .clkr = {
- .enable_reg = 0x0304,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_rm_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
- .halt_reg = 0x0308,
- .clkr = {
- .enable_reg = 0x0308,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_rm_ocmemnoc_clk",
- .parent_names = (const char *[]){
- "ocmemnoc_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-
static struct clk_branch mmss_misc_ahb_clk = {
.halt_reg = 0x502c,
.clkr = {
@@ -3252,21 +2996,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
[MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
[MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
[MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 11/12] clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
` (9 preceding siblings ...)
2022-12-27 1:32 ` [RFC PATCH 10/12] clk: qcom: mmcc-apq8084: remove spdm clocks Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-27 12:07 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device Dmitry Baryshkov
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Note, the system names for xo clocks were changed from "xo" to
"xo_board" to follow the example of other platforms. This switches the
clocks to use DT-provided "xo_board" clock instead of manually
registered "xo" clock and allows us to drop qcom_cc_register_board_clk()
call from the driver at some point.
In the same way change the looked up system "sleep_clk_src" clock to
"sleep_clk", which is registered from DT.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/mmcc-apq8084.c | 644 ++++++++++++++++----------------
1 file changed, 331 insertions(+), 313 deletions(-)
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 631b1ff8cf01..02fc21208dd1 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -50,7 +50,9 @@ static struct clk_pll mmpll0 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll0",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -61,7 +63,9 @@ static struct clk_regmap mmpll0_vote = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmpll0_vote",
- .parent_names = (const char *[]){ "mmpll0" },
+ .parent_hws = (const struct clk_hw*[]){
+ &mmpll0.clkr.hw
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -77,7 +81,9 @@ static struct clk_pll mmpll1 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll1",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -88,7 +94,9 @@ static struct clk_regmap mmpll1_vote = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "mmpll1_vote",
- .parent_names = (const char *[]){ "mmpll1" },
+ .parent_hws = (const struct clk_hw*[]){
+ &mmpll1.clkr.hw
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -103,7 +111,9 @@ static struct clk_pll mmpll2 = {
.status_reg = 0x411c,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll2",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -119,7 +129,9 @@ static struct clk_pll mmpll3 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -134,7 +146,9 @@ static struct clk_pll mmpll4 = {
.status_reg = 0x00bc,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -147,11 +161,11 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
{ P_GPLL0, 5 }
};
-static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
- "xo",
- "mmpll0_vote",
- "mmpll1_vote",
- "mmss_gpll0_vote",
+static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0_vote.hw },
+ { .hw = &mmpll1_vote.hw },
+ { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
};
static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
@@ -163,13 +177,13 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
{ P_DSI1PLL, 3 }
};
-static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
- "xo",
- "mmpll0_vote",
- "hdmipll",
- "mmss_gpll0_vote",
- "dsi0pll",
- "dsi1pll",
+static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0_vote.hw },
+ { .fw_name = "hdmipll", .name = "hdmipll" },
+ { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
+ { .fw_name = "dsi0pll", .name = "dsi0pll" },
+ { .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
@@ -180,12 +194,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
{ P_MMPLL2, 3 }
};
-static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
- "xo",
- "mmpll0_vote",
- "mmpll1_vote",
- "mmss_gpll0_vote",
- "mmpll2",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_2_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0_vote.hw },
+ { .hw = &mmpll1_vote.hw },
+ { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
+ { .hw = &mmpll2.clkr.hw },
};
static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
@@ -196,12 +210,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
{ P_MMPLL3, 3 }
};
-static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
- "xo",
- "mmpll0_vote",
- "mmpll1_vote",
- "mmss_gpll0_vote",
- "mmpll3",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0_vote.hw },
+ { .hw = &mmpll1_vote.hw },
+ { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
+ { .hw = &mmpll3.clkr.hw },
};
static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
@@ -213,13 +227,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
{ P_DSI1PLL, 2 }
};
-static const char * const mmcc_xo_dsi_hdmi_edp[] = {
- "xo",
- "edp_link_clk",
- "hdmipll",
- "edp_vco_div",
- "dsi0pll",
- "dsi1pll",
+static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
+ { .fw_name = "hdmipll", .name = "hdmipll" },
+ { .fw_name = "edp_vco_div", .name = "edp_vco_div" },
+ { .fw_name = "dsi0pll", .name = "dsi0pll" },
+ { .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
@@ -231,13 +245,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
{ P_DSI1PLL, 2 }
};
-static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
- "xo",
- "edp_link_clk",
- "hdmipll",
- "gpll0_vote",
- "dsi0pll",
- "dsi1pll",
+static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
+ { .fw_name = "hdmipll", .name = "hdmipll" },
+ { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
+ { .fw_name = "dsi0pll", .name = "dsi0pll" },
+ { .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
@@ -249,13 +263,13 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
{ P_DSI1PLL_BYTE, 2 }
};
-static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
- "xo",
- "edp_link_clk",
- "hdmipll",
- "gpll0_vote",
- "dsi0pllbyte",
- "dsi1pllbyte",
+static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
+ { .fw_name = "hdmipll", .name = "hdmipll" },
+ { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
+ { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
+ { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
};
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
@@ -266,12 +280,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
{ P_MMPLL4, 3 }
};
-static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
- "xo",
- "mmpll0",
- "mmpll1",
- "mmpll4",
- "gpll0",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0.clkr.hw },
+ { .hw = &mmpll1.clkr.hw },
+ { .hw = &mmpll4.clkr.hw },
+ { .fw_name = "gpll0", .name = "gpll0" },
};
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
@@ -283,13 +297,13 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
{ P_GPLL1, 4 }
};
-static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
- "xo",
- "mmpll0",
- "mmpll1",
- "mmpll4",
- "gpll1",
- "gpll0",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0.clkr.hw },
+ { .hw = &mmpll1.clkr.hw },
+ { .hw = &mmpll4.clkr.hw },
+ { .fw_name = "gpll1", .name = "gpll1" },
+ { .fw_name = "gpll0", .name = "gpll0" },
};
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
@@ -302,14 +316,14 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
{ P_MMSLEEP, 6 }
};
-static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
- "xo",
- "mmpll0",
- "mmpll1",
- "mmpll4",
- "gpll1",
- "gpll0",
- "sleep_clk_src",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0.clkr.hw },
+ { .hw = &mmpll1.clkr.hw },
+ { .hw = &mmpll4.clkr.hw },
+ { .fw_name = "gpll1", .name = "gpll1" },
+ { .fw_name = "gpll0", .name = "gpll0" },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static struct clk_rcg2 mmss_ahb_clk_src = {
@@ -318,7 +332,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_ahb_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -343,7 +357,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
.freq_tbl = ftbl_mmss_axi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_axi_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -367,7 +381,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
.freq_tbl = ftbl_ocmemnoc_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ocmemnoc_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -386,7 +400,7 @@ static struct clk_rcg2 csi0_clk_src = {
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -399,7 +413,7 @@ static struct clk_rcg2 csi1_clk_src = {
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -412,7 +426,7 @@ static struct clk_rcg2 csi2_clk_src = {
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -425,7 +439,7 @@ static struct clk_rcg2 csi3_clk_src = {
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi3_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -455,7 +469,7 @@ static struct clk_rcg2 vfe0_clk_src = {
.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -468,7 +482,7 @@ static struct clk_rcg2 vfe1_clk_src = {
.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -496,7 +510,7 @@ static struct clk_rcg2 mdp_clk_src = {
.freq_tbl = ftbl_mdss_mdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
- .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
+ .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -508,7 +522,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
.parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_2_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -531,7 +545,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -544,7 +558,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -557,7 +571,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg2_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -570,7 +584,7 @@ static struct clk_rcg2 pclk0_clk_src = {
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+ .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -584,7 +598,7 @@ static struct clk_rcg2 pclk1_clk_src = {
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+ .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -609,7 +623,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
.freq_tbl = ftbl_venus0_vcodec0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_3_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -628,7 +642,7 @@ static struct clk_rcg2 vp_clk_src = {
.freq_tbl = ftbl_avsync_vp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vp_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -647,7 +661,7 @@ static struct clk_rcg2 cci_clk_src = {
.freq_tbl = ftbl_camss_cci_cci_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
@@ -671,7 +685,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
.freq_tbl = ftbl_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
.ops = &clk_rcg2_ops,
},
@@ -685,7 +699,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
.freq_tbl = ftbl_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
.ops = &clk_rcg2_ops,
},
@@ -713,7 +727,7 @@ static struct clk_rcg2 mclk0_clk_src = {
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
@@ -727,7 +741,7 @@ static struct clk_rcg2 mclk1_clk_src = {
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
@@ -741,7 +755,7 @@ static struct clk_rcg2 mclk2_clk_src = {
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
@@ -755,7 +769,7 @@ static struct clk_rcg2 mclk3_clk_src = {
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk3_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
@@ -774,7 +788,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -787,7 +801,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -800,7 +814,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2phytimer_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -823,7 +837,7 @@ static struct clk_rcg2 cpp_clk_src = {
.freq_tbl = ftbl_camss_vfe_cpp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -835,7 +849,7 @@ static struct clk_rcg2 byte0_clk_src = {
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
- .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+ .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -848,7 +862,7 @@ static struct clk_rcg2 byte1_clk_src = {
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
- .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+ .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -867,7 +881,7 @@ static struct clk_rcg2 edpaux_clk_src = {
.freq_tbl = ftbl_mdss_edpaux_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "edpaux_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -886,7 +900,7 @@ static struct clk_rcg2 edplink_clk_src = {
.freq_tbl = ftbl_mdss_edplink_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "edplink_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+ .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -906,7 +920,7 @@ static struct clk_rcg2 edppixel_clk_src = {
.freq_tbl = edp_pixel_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "edppixel_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp,
+ .parent_data = mmcc_xo_dsi_hdmi_edp,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
.ops = &clk_edp_pixel_ops,
},
@@ -924,7 +938,7 @@ static struct clk_rcg2 esc0_clk_src = {
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
- .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+ .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -937,7 +951,7 @@ static struct clk_rcg2 esc1_clk_src = {
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
- .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+ .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -955,7 +969,7 @@ static struct clk_rcg2 extpclk_clk_src = {
.freq_tbl = extpclk_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "extpclk_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+ .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_byte_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -974,7 +988,7 @@ static struct clk_rcg2 hdmi_clk_src = {
.freq_tbl = ftbl_mdss_hdmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -992,7 +1006,7 @@ static struct clk_rcg2 vsync_clk_src = {
.freq_tbl = ftbl_mdss_vsync_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1010,7 +1024,7 @@ static struct clk_rcg2 rbcpr_clk_src = {
.freq_tbl = ftbl_mmss_rbcpr_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1028,7 +1042,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = {
.freq_tbl = ftbl_oxili_rbbmtimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1051,7 +1065,7 @@ static struct clk_rcg2 maple_clk_src = {
.freq_tbl = ftbl_vpu_maple_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "maple_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1073,7 +1087,7 @@ static struct clk_rcg2 vdp_clk_src = {
.freq_tbl = ftbl_vpu_vdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vdp_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1092,7 +1106,7 @@ static struct clk_rcg2 vpu_bus_clk_src = {
.freq_tbl = ftbl_vpu_bus_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vpu_bus_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1105,7 +1119,9 @@ static struct clk_branch mmss_cxo_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_cxo_clk",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1120,8 +1136,8 @@ static struct clk_branch mmss_sleepclk_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_sleepclk_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1137,8 +1153,8 @@ static struct clk_branch avsync_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1154,8 +1170,8 @@ static struct clk_branch avsync_edppixel_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_edppixel_clk",
- .parent_names = (const char *[]){
- "edppixel_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &edppixel_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1171,8 +1187,8 @@ static struct clk_branch avsync_extpclk_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_extpclk_clk",
- .parent_names = (const char *[]){
- "extpclk_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &extpclk_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1188,8 +1204,8 @@ static struct clk_branch avsync_pclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_pclk0_clk",
- .parent_names = (const char *[]){
- "pclk0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1205,8 +1221,8 @@ static struct clk_branch avsync_pclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_pclk1_clk",
- .parent_names = (const char *[]){
- "pclk1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1222,8 +1238,8 @@ static struct clk_branch avsync_vp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_vp_clk",
- .parent_names = (const char *[]){
- "vp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1239,8 +1255,8 @@ static struct clk_branch camss_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1256,8 +1272,8 @@ static struct clk_branch camss_cci_cci_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1272,8 +1288,8 @@ static struct clk_branch camss_cci_cci_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_clk",
- .parent_names = (const char *[]){
- "cci_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &cci_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1289,8 +1305,8 @@ static struct clk_branch camss_csi0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1305,8 +1321,8 @@ static struct clk_branch camss_csi0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1322,8 +1338,8 @@ static struct clk_branch camss_csi0phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0phy_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1339,8 +1355,8 @@ static struct clk_branch camss_csi0pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0pix_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1356,8 +1372,8 @@ static struct clk_branch camss_csi0rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0rdi_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1373,8 +1389,8 @@ static struct clk_branch camss_csi1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1390,8 +1406,8 @@ static struct clk_branch camss_csi1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1407,8 +1423,8 @@ static struct clk_branch camss_csi1phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1phy_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1424,8 +1440,8 @@ static struct clk_branch camss_csi1pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1pix_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1441,8 +1457,8 @@ static struct clk_branch camss_csi1rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1rdi_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1458,8 +1474,8 @@ static struct clk_branch camss_csi2_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1474,8 +1490,8 @@ static struct clk_branch camss_csi2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_clk",
- .parent_names = (const char *[]){
- "csi2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1491,8 +1507,8 @@ static struct clk_branch camss_csi2phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2phy_clk",
- .parent_names = (const char *[]){
- "csi2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1508,8 +1524,8 @@ static struct clk_branch camss_csi2pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2pix_clk",
- .parent_names = (const char *[]){
- "csi2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1525,8 +1541,8 @@ static struct clk_branch camss_csi2rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2rdi_clk",
- .parent_names = (const char *[]){
- "csi2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1542,8 +1558,8 @@ static struct clk_branch camss_csi3_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1558,8 +1574,8 @@ static struct clk_branch camss_csi3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_clk",
- .parent_names = (const char *[]){
- "csi3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1575,8 +1591,8 @@ static struct clk_branch camss_csi3phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3phy_clk",
- .parent_names = (const char *[]){
- "csi3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1592,8 +1608,8 @@ static struct clk_branch camss_csi3pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3pix_clk",
- .parent_names = (const char *[]){
- "csi3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1609,8 +1625,8 @@ static struct clk_branch camss_csi3rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3rdi_clk",
- .parent_names = (const char *[]){
- "csi3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1626,8 +1642,8 @@ static struct clk_branch camss_csi_vfe0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe0_clk",
- .parent_names = (const char *[]){
- "vfe0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1643,8 +1659,8 @@ static struct clk_branch camss_csi_vfe1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe1_clk",
- .parent_names = (const char *[]){
- "vfe1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1660,8 +1676,8 @@ static struct clk_branch camss_gp0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk",
- .parent_names = (const char *[]){
- "camss_gp0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_gp0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1677,8 +1693,8 @@ static struct clk_branch camss_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk",
- .parent_names = (const char *[]){
- "camss_gp1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_gp1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1694,8 +1710,8 @@ static struct clk_branch camss_ispif_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ispif_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1711,8 +1727,8 @@ static struct clk_branch camss_jpeg_jpeg0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg0_clk",
- .parent_names = (const char *[]){
- "jpeg0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &jpeg0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1728,8 +1744,8 @@ static struct clk_branch camss_jpeg_jpeg1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg1_clk",
- .parent_names = (const char *[]){
- "jpeg1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &jpeg1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1745,8 +1761,8 @@ static struct clk_branch camss_jpeg_jpeg2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg2_clk",
- .parent_names = (const char *[]){
- "jpeg2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &jpeg2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1762,8 +1778,8 @@ static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1778,8 +1794,8 @@ static struct clk_branch camss_jpeg_jpeg_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1794,8 +1810,8 @@ static struct clk_branch camss_mclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk0_clk",
- .parent_names = (const char *[]){
- "mclk0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1811,8 +1827,8 @@ static struct clk_branch camss_mclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk1_clk",
- .parent_names = (const char *[]){
- "mclk1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1828,8 +1844,8 @@ static struct clk_branch camss_mclk2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk2_clk",
- .parent_names = (const char *[]){
- "mclk2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1845,8 +1861,8 @@ static struct clk_branch camss_mclk3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk3_clk",
- .parent_names = (const char *[]){
- "mclk3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1862,8 +1878,8 @@ static struct clk_branch camss_micro_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_micro_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1878,8 +1894,8 @@ static struct clk_branch camss_phy0_csi0phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy0_csi0phytimer_clk",
- .parent_names = (const char *[]){
- "csi0phytimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1895,8 +1911,8 @@ static struct clk_branch camss_phy1_csi1phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy1_csi1phytimer_clk",
- .parent_names = (const char *[]){
- "csi1phytimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1912,8 +1928,8 @@ static struct clk_branch camss_phy2_csi2phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy2_csi2phytimer_clk",
- .parent_names = (const char *[]){
- "csi2phytimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1929,8 +1945,8 @@ static struct clk_branch camss_top_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_top_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1946,8 +1962,8 @@ static struct clk_branch camss_vfe_cpp_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1963,8 +1979,8 @@ static struct clk_branch camss_vfe_cpp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_clk",
- .parent_names = (const char *[]){
- "cpp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &cpp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1980,8 +1996,8 @@ static struct clk_branch camss_vfe_vfe0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe0_clk",
- .parent_names = (const char *[]){
- "vfe0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1997,8 +2013,8 @@ static struct clk_branch camss_vfe_vfe1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe1_clk",
- .parent_names = (const char *[]){
- "vfe1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2014,8 +2030,8 @@ static struct clk_branch camss_vfe_vfe_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2031,8 +2047,8 @@ static struct clk_branch camss_vfe_vfe_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2048,8 +2064,8 @@ static struct clk_branch mdss_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2065,8 +2081,8 @@ static struct clk_branch mdss_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2082,8 +2098,8 @@ static struct clk_branch mdss_byte0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_clk",
- .parent_names = (const char *[]){
- "byte0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &byte0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2099,8 +2115,8 @@ static struct clk_branch mdss_byte1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_clk",
- .parent_names = (const char *[]){
- "byte1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &byte1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2116,8 +2132,8 @@ static struct clk_branch mdss_edpaux_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edpaux_clk",
- .parent_names = (const char *[]){
- "edpaux_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &edpaux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2133,8 +2149,8 @@ static struct clk_branch mdss_edplink_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edplink_clk",
- .parent_names = (const char *[]){
- "edplink_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &edplink_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2150,8 +2166,8 @@ static struct clk_branch mdss_edppixel_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edppixel_clk",
- .parent_names = (const char *[]){
- "edppixel_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &edppixel_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2167,8 +2183,8 @@ static struct clk_branch mdss_esc0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc0_clk",
- .parent_names = (const char *[]){
- "esc0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &esc0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2184,8 +2200,8 @@ static struct clk_branch mdss_esc1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc1_clk",
- .parent_names = (const char *[]){
- "esc1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &esc1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2201,8 +2217,8 @@ static struct clk_branch mdss_extpclk_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_extpclk_clk",
- .parent_names = (const char *[]){
- "extpclk_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &extpclk_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2218,8 +2234,8 @@ static struct clk_branch mdss_hdmi_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2235,8 +2251,8 @@ static struct clk_branch mdss_hdmi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_clk",
- .parent_names = (const char *[]){
- "hdmi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &hdmi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2252,8 +2268,8 @@ static struct clk_branch mdss_mdp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_clk",
- .parent_names = (const char *[]){
- "mdp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2269,8 +2285,8 @@ static struct clk_branch mdss_mdp_lut_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_lut_clk",
- .parent_names = (const char *[]){
- "mdp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2286,8 +2302,8 @@ static struct clk_branch mdss_pclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk0_clk",
- .parent_names = (const char *[]){
- "pclk0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2303,8 +2319,8 @@ static struct clk_branch mdss_pclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk1_clk",
- .parent_names = (const char *[]){
- "pclk1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2320,8 +2336,8 @@ static struct clk_branch mdss_vsync_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_vsync_clk",
- .parent_names = (const char *[]){
- "vsync_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vsync_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2337,8 +2353,8 @@ static struct clk_branch mmss_rbcpr_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_rbcpr_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2354,8 +2370,8 @@ static struct clk_branch mmss_rbcpr_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_rbcpr_clk",
- .parent_names = (const char *[]){
- "rbcpr_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &rbcpr_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2371,8 +2387,8 @@ static struct clk_branch mmss_misc_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_misc_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2388,8 +2404,8 @@ static struct clk_branch mmss_mmssnoc_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2405,8 +2421,8 @@ static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_bto_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2422,8 +2438,8 @@ static struct clk_branch mmss_mmssnoc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
@@ -2439,8 +2455,8 @@ static struct clk_branch mmss_s0_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_s0_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2456,8 +2472,8 @@ static struct clk_branch ocmemcx_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2473,8 +2489,8 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ocmemnoc_clk",
- .parent_names = (const char *[]){
- "ocmemnoc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2490,8 +2506,8 @@ static struct clk_branch oxili_ocmemgx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_ocmemgx_clk",
- .parent_names = (const char *[]){
- "gfx3d_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gfx3d_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2507,8 +2523,8 @@ static struct clk_branch oxili_gfx3d_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_gfx3d_clk",
- .parent_names = (const char *[]){
- "gfx3d_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gfx3d_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2524,8 +2540,8 @@ static struct clk_branch oxili_rbbmtimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_rbbmtimer_clk",
- .parent_names = (const char *[]){
- "rbbmtimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &rbbmtimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2541,8 +2557,8 @@ static struct clk_branch oxilicx_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxilicx_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2558,8 +2574,8 @@ static struct clk_branch venus0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2575,8 +2591,8 @@ static struct clk_branch venus0_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2592,8 +2608,8 @@ static struct clk_branch venus0_core0_vcodec_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_core0_vcodec_clk",
- .parent_names = (const char *[]){
- "vcodec0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2609,8 +2625,8 @@ static struct clk_branch venus0_core1_vcodec_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_core1_vcodec_clk",
- .parent_names = (const char *[]){
- "vcodec0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2626,8 +2642,8 @@ static struct clk_branch venus0_ocmemnoc_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ocmemnoc_clk",
- .parent_names = (const char *[]){
- "ocmemnoc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2643,8 +2659,8 @@ static struct clk_branch venus0_vcodec0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_vcodec0_clk",
- .parent_names = (const char *[]){
- "vcodec0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2660,8 +2676,8 @@ static struct clk_branch vpu_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2677,8 +2693,8 @@ static struct clk_branch vpu_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2694,8 +2710,8 @@ static struct clk_branch vpu_bus_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_bus_clk",
- .parent_names = (const char *[]){
- "vpu_bus_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vpu_bus_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2711,7 +2727,9 @@ static struct clk_branch vpu_cxo_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_cxo_clk",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2726,8 +2744,8 @@ static struct clk_branch vpu_maple_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_maple_clk",
- .parent_names = (const char *[]){
- "maple_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &maple_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2743,8 +2761,8 @@ static struct clk_branch vpu_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2760,8 +2778,8 @@ static struct clk_branch vpu_vdp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_vdp_clk",
- .parent_names = (const char *[]){
- "vdp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
` (10 preceding siblings ...)
2022-12-27 1:32 ` [RFC PATCH 11/12] clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
@ 2022-12-27 1:32 ` Dmitry Baryshkov
2022-12-27 12:08 ` Konrad Dybcio
11 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 1:32 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Add clocks and clock-names nodes to the gcc device to bind clocks using
the DT links.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index fe30abfff90a..815b6c53f7b8 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -388,6 +388,24 @@ gcc: clock-controller@fc400000 {
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <0>, /* ufs */
+ <0>,
+ <0>,
+ <0>,
+ <0>, /* sata */
+ <0>,
+ <0>; /* pcie */
+ clock-names = "xo",
+ "sleep_clk",
+ "ufs_rx_symbol_0_clk_src",
+ "ufs_rx_symbol_1_clk_src",
+ "ufs_tx_symbol_0_clk_src",
+ "ufs_tx_symbol_1_clk_src",
+ "sata_asic0_clk",
+ "sata_rx_clk",
+ "pcie_pipe";
};
tcsr_mutex: hwlock@fd484000 {
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 04/12] clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents
2022-12-27 1:32 ` [RFC PATCH 04/12] clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2022-12-27 11:48 ` Konrad Dybcio
0 siblings, 0 replies; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 11:48 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/clk/qcom/gcc-apq8084.c | 136 ++++++++++++++++-----------------
> 1 file changed, 68 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
> index ab088d702d7c..b41f55b289ae 100644
> --- a/drivers/clk/qcom/gcc-apq8084.c
> +++ b/drivers/clk/qcom/gcc-apq8084.c
> @@ -132,7 +132,7 @@ static struct clk_rcg2 config_noc_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "config_noc_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -144,7 +144,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "periph_noc_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -156,7 +156,7 @@ static struct clk_rcg2 system_noc_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "system_noc_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -231,7 +231,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ufs_axi_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -250,7 +250,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb30_master_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -269,7 +269,7 @@ static struct clk_rcg2 usb30_sec_master_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb30_sec_master_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -322,7 +322,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -347,7 +347,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -360,7 +360,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -374,7 +374,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -387,7 +387,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -401,7 +401,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -414,7 +414,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -428,7 +428,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -441,7 +441,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -455,7 +455,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -468,7 +468,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -482,7 +482,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -515,7 +515,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart1_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -529,7 +529,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart2_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -543,7 +543,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart3_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -557,7 +557,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart4_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -571,7 +571,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart5_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -585,7 +585,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart6_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -598,7 +598,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup1_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -612,7 +612,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup1_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -625,7 +625,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup2_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -639,7 +639,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup2_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -652,7 +652,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup3_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -666,7 +666,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup3_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -679,7 +679,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup4_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -693,7 +693,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup4_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -706,7 +706,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup5_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -720,7 +720,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup5_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -733,7 +733,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup6_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -747,7 +747,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup6_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -761,7 +761,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart1_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -775,7 +775,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart2_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -789,7 +789,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart3_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -803,7 +803,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart4_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -817,7 +817,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart5_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -831,7 +831,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart6_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -852,7 +852,7 @@ static struct clk_rcg2 ce1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ce1_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -873,7 +873,7 @@ static struct clk_rcg2 ce2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ce2_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -894,7 +894,7 @@ static struct clk_rcg2 ce3_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ce3_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -915,7 +915,7 @@ static struct clk_rcg2 gp1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp1_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -929,7 +929,7 @@ static struct clk_rcg2 gp2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp2_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -943,7 +943,7 @@ static struct clk_rcg2 gp3_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp3_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -962,7 +962,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_0_aux_clk_src",
> .parent_names = gcc_xo_pcie_sleep,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -976,7 +976,7 @@ static struct clk_rcg2 pcie_1_aux_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_1_aux_clk_src",
> .parent_names = gcc_xo_pcie_sleep,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -995,7 +995,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_0_pipe_clk_src",
> .parent_names = gcc_xo_pcie,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_pcie),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1008,7 +1008,7 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_1_pipe_clk_src",
> .parent_names = gcc_xo_pcie,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_pcie),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1026,7 +1026,7 @@ static struct clk_rcg2 pdm2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pdm2_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1046,7 +1046,7 @@ static struct clk_rcg2 sata_asic0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sata_asic0_clk_src",
> .parent_names = gcc_xo_sata_asic0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_sata_asic0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1066,7 +1066,7 @@ static struct clk_rcg2 sata_pmalive_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sata_pmalive_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1086,7 +1086,7 @@ static struct clk_rcg2 sata_rx_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sata_rx_clk_src",
> .parent_names = gcc_xo_sata_rx,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_sata_rx),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1104,7 +1104,7 @@ static struct clk_rcg2 sata_rx_oob_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sata_rx_oob_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1131,7 +1131,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc1_apps_clk_src",
> .parent_names = gcc_xo_gpll0_gpll4,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
> .ops = &clk_rcg2_floor_ops,
> },
> };
> @@ -1145,7 +1145,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc2_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> };
> @@ -1159,7 +1159,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc3_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> };
> @@ -1173,7 +1173,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc4_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> };
> @@ -1192,7 +1192,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "tsif_ref_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1210,7 +1210,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb30_mock_utmi_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1228,7 +1228,7 @@ static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb30_sec_mock_utmi_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1246,7 +1246,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hs_system_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1312,7 +1312,7 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hsic_io_cal_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 1,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1347,7 +1347,7 @@ static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hsic_mock_utmi_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 1,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1365,7 +1365,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hsic_system_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 05/12] clk: qcom: gcc-apq8084: move PLL clocks up
2022-12-27 1:32 ` [RFC PATCH 05/12] clk: qcom: gcc-apq8084: move PLL clocks up Dmitry Baryshkov
@ 2022-12-27 11:49 ` Konrad Dybcio
0 siblings, 0 replies; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 11:49 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Move PLL clock declarations up, before clock parent tables, so that we
> can use pll hw clock fields in the next commit.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/clk/qcom/gcc-apq8084.c | 162 ++++++++++++++++-----------------
> 1 file changed, 81 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
> index b41f55b289ae..05a68f645115 100644
> --- a/drivers/clk/qcom/gcc-apq8084.c
> +++ b/drivers/clk/qcom/gcc-apq8084.c
> @@ -36,6 +36,87 @@ enum {
> P_SLEEP_CLK,
> };
>
> +static struct clk_pll gpll0 = {
> + .l_reg = 0x0004,
> + .m_reg = 0x0008,
> + .n_reg = 0x000c,
> + .config_reg = 0x0014,
> + .mode_reg = 0x0000,
> + .status_reg = 0x001c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll0",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap gpll0_vote = {
> + .enable_reg = 0x1480,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll0_vote",
> + .parent_names = (const char *[]){ "gpll0" },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
> +static struct clk_pll gpll1 = {
> + .l_reg = 0x0044,
> + .m_reg = 0x0048,
> + .n_reg = 0x004c,
> + .config_reg = 0x0054,
> + .mode_reg = 0x0040,
> + .status_reg = 0x005c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll1",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap gpll1_vote = {
> + .enable_reg = 0x1480,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll1_vote",
> + .parent_names = (const char *[]){ "gpll1" },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
> +static struct clk_pll gpll4 = {
> + .l_reg = 0x1dc4,
> + .m_reg = 0x1dc8,
> + .n_reg = 0x1dcc,
> + .config_reg = 0x1dd4,
> + .mode_reg = 0x1dc0,
> + .status_reg = 0x1ddc,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll4",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap gpll4_vote = {
> + .enable_reg = 0x1480,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll4_vote",
> + .parent_names = (const char *[]){ "gpll4" },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
> static const struct parent_map gcc_xo_gpll0_map[] = {
> { P_XO, 0 },
> { P_GPLL0, 1 }
> @@ -98,33 +179,6 @@ static const char * const gcc_xo_pcie_sleep[] = {
> "sleep_clk_src",
> };
>
> -static struct clk_pll gpll0 = {
> - .l_reg = 0x0004,
> - .m_reg = 0x0008,
> - .n_reg = 0x000c,
> - .config_reg = 0x0014,
> - .mode_reg = 0x0000,
> - .status_reg = 0x001c,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "gpll0",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_regmap gpll0_vote = {
> - .enable_reg = 0x1480,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "gpll0_vote",
> - .parent_names = (const char *[]){ "gpll0" },
> - .num_parents = 1,
> - .ops = &clk_pll_vote_ops,
> - },
> -};
> -
> static struct clk_rcg2 config_noc_clk_src = {
> .cmd_rcgr = 0x0150,
> .hid_width = 5,
> @@ -161,60 +215,6 @@ static struct clk_rcg2 system_noc_clk_src = {
> },
> };
>
> -static struct clk_pll gpll1 = {
> - .l_reg = 0x0044,
> - .m_reg = 0x0048,
> - .n_reg = 0x004c,
> - .config_reg = 0x0054,
> - .mode_reg = 0x0040,
> - .status_reg = 0x005c,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "gpll1",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_regmap gpll1_vote = {
> - .enable_reg = 0x1480,
> - .enable_mask = BIT(1),
> - .hw.init = &(struct clk_init_data){
> - .name = "gpll1_vote",
> - .parent_names = (const char *[]){ "gpll1" },
> - .num_parents = 1,
> - .ops = &clk_pll_vote_ops,
> - },
> -};
> -
> -static struct clk_pll gpll4 = {
> - .l_reg = 0x1dc4,
> - .m_reg = 0x1dc8,
> - .n_reg = 0x1dcc,
> - .config_reg = 0x1dd4,
> - .mode_reg = 0x1dc0,
> - .status_reg = 0x1ddc,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "gpll4",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_regmap gpll4_vote = {
> - .enable_reg = 0x1480,
> - .enable_mask = BIT(4),
> - .hw.init = &(struct clk_init_data){
> - .name = "gpll4_vote",
> - .parent_names = (const char *[]){ "gpll4" },
> - .num_parents = 1,
> - .ops = &clk_pll_vote_ops,
> - },
> -};
> -
> static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
> F(100000000, P_GPLL0, 6, 0, 0),
> F(200000000, P_GPLL0, 3, 0, 0),
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 06/12] clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names
2022-12-27 1:32 ` [RFC PATCH 06/12] clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
@ 2022-12-27 11:55 ` Konrad Dybcio
2022-12-27 12:19 ` Dmitry Baryshkov
0 siblings, 1 reply; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 11:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names. Use parent_hws where possible to refer parent
> clocks directly, skipping the lookup.
>
> Note, the system names for xo clocks were changed from "xo" to
> "xo_board" to follow the example of other platforms. This switches the
> clocks to use DT-provided "xo_board" clock instead of manually
> registered "xo" clock and allows us to drop qcom_cc_register_board_clk()
> call from the driver at some point.
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
This needs to be fixed (clock-output-names and fix node name) or
dt_binding_check will be angry, similar for sleep.
With that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
>
> In the same way change the looked up system "sleep_clk_src" clock to
> "sleep_clk", which is registered from DT.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/clk/qcom/gcc-apq8084.c | 730 +++++++++++++++++----------------
> 1 file changed, 371 insertions(+), 359 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
> index 05a68f645115..c26e222c78d4 100644
> --- a/drivers/clk/qcom/gcc-apq8084.c
> +++ b/drivers/clk/qcom/gcc-apq8084.c
> @@ -46,7 +46,9 @@ static struct clk_pll gpll0 = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gpll0",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo", .name = "xo_board",
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -57,7 +59,9 @@ static struct clk_regmap gpll0_vote = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gpll0_vote",
> - .parent_names = (const char *[]){ "gpll0" },
> + .parent_hws = (const struct clk_hw*[]){
> + &gpll0.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
> @@ -73,7 +77,9 @@ static struct clk_pll gpll1 = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gpll1",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo", .name = "xo_board",
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -84,7 +90,9 @@ static struct clk_regmap gpll1_vote = {
> .enable_mask = BIT(1),
> .hw.init = &(struct clk_init_data){
> .name = "gpll1_vote",
> - .parent_names = (const char *[]){ "gpll1" },
> + .parent_hws = (const struct clk_hw*[]){
> + &gpll1.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
> @@ -100,7 +108,9 @@ static struct clk_pll gpll4 = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gpll4",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo", .name = "xo_board",
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -111,7 +121,9 @@ static struct clk_regmap gpll4_vote = {
> .enable_mask = BIT(4),
> .hw.init = &(struct clk_init_data){
> .name = "gpll4_vote",
> - .parent_names = (const char *[]){ "gpll4" },
> + .parent_hws = (const struct clk_hw*[]){
> + &gpll4.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
> @@ -122,9 +134,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
> { P_GPLL0, 1 }
> };
>
> -static const char * const gcc_xo_gpll0[] = {
> - "xo",
> - "gpll0_vote",
> +static const struct clk_parent_data gcc_xo_gpll0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> };
>
> static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> @@ -133,10 +145,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> { P_GPLL4, 5 }
> };
>
> -static const char * const gcc_xo_gpll0_gpll4[] = {
> - "xo",
> - "gpll0_vote",
> - "gpll4_vote",
> +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .hw = &gpll4_vote.hw },
> };
>
> static const struct parent_map gcc_xo_sata_asic0_map[] = {
> @@ -144,9 +156,9 @@ static const struct parent_map gcc_xo_sata_asic0_map[] = {
> { P_SATA_ASIC0_CLK, 2 }
> };
>
> -static const char * const gcc_xo_sata_asic0[] = {
> - "xo",
> - "sata_asic0_clk",
> +static const struct clk_parent_data gcc_xo_sata_asic0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .fw_name = "sata_asic0_clk", .name = "sata_asic0_clk" },
> };
>
> static const struct parent_map gcc_xo_sata_rx_map[] = {
> @@ -154,9 +166,9 @@ static const struct parent_map gcc_xo_sata_rx_map[] = {
> { P_SATA_RX_CLK, 2}
> };
>
> -static const char * const gcc_xo_sata_rx[] = {
> - "xo",
> - "sata_rx_clk",
> +static const struct clk_parent_data gcc_xo_sata_rx[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .fw_name = "sata_rx_clk", .name = "sata_rx_clk" },
> };
>
> static const struct parent_map gcc_xo_pcie_map[] = {
> @@ -164,9 +176,9 @@ static const struct parent_map gcc_xo_pcie_map[] = {
> { P_PCIE_0_1_PIPE_CLK, 2 }
> };
>
> -static const char * const gcc_xo_pcie[] = {
> - "xo",
> - "pcie_pipe",
> +static const struct clk_parent_data gcc_xo_pcie[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .fw_name = "pcie_pipe", .name = "pcie_pipe" },
> };
>
> static const struct parent_map gcc_xo_pcie_sleep_map[] = {
> @@ -174,9 +186,9 @@ static const struct parent_map gcc_xo_pcie_sleep_map[] = {
> { P_SLEEP_CLK, 6 }
> };
>
> -static const char * const gcc_xo_pcie_sleep[] = {
> - "xo",
> - "sleep_clk_src",
> +static const struct clk_parent_data gcc_xo_pcie_sleep[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> };
>
> static struct clk_rcg2 config_noc_clk_src = {
> @@ -185,7 +197,7 @@ static struct clk_rcg2 config_noc_clk_src = {
> .parent_map = gcc_xo_gpll0_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "config_noc_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -197,7 +209,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
> .parent_map = gcc_xo_gpll0_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "periph_noc_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -209,7 +221,7 @@ static struct clk_rcg2 system_noc_clk_src = {
> .parent_map = gcc_xo_gpll0_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "system_noc_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -230,7 +242,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
> .freq_tbl = ftbl_gcc_ufs_axi_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ufs_axi_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -249,7 +261,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
> .freq_tbl = ftbl_gcc_usb30_master_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb30_master_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -268,7 +280,25 @@ static struct clk_rcg2 usb30_sec_master_clk_src = {
> .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb30_sec_master_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
> + F(125000000, P_GPLL0, 1, 5, 24),
> + { }
> +};
> +
> +static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
> + .cmd_rcgr = 0x1be8,
> + .hid_width = 5,
> + .parent_map = gcc_xo_gpll0_map,
> + .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "usb30_sec_mock_utmi_clk_src",
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -281,8 +311,8 @@ static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb30_sec_mock_utmi_clk",
> - .parent_names = (const char *[]){
> - "usb30_sec_mock_utmi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb30_sec_mock_utmi_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -298,8 +328,8 @@ static struct clk_branch gcc_usb30_sec_sleep_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb30_sec_sleep_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep_clk", .name = "sleep_clk",
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -321,7 +351,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -346,7 +376,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -359,7 +389,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -373,7 +403,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -386,7 +416,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -400,7 +430,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -413,7 +443,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -427,7 +457,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -440,7 +470,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -454,7 +484,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -467,7 +497,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -481,7 +511,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -514,7 +544,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart1_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -528,7 +558,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart2_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -542,7 +572,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart3_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -556,7 +586,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart4_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -570,7 +600,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart5_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -584,7 +614,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart6_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -597,7 +627,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup1_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -611,7 +641,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup1_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -624,7 +654,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup2_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -638,7 +668,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup2_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -651,7 +681,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup3_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -665,7 +695,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup3_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -678,7 +708,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup4_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -692,7 +722,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup4_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -705,7 +735,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup5_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -719,7 +749,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup5_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -732,7 +762,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup6_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -746,7 +776,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup6_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -760,7 +790,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart1_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -774,7 +804,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart2_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -788,7 +818,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart3_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -802,7 +832,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart4_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -816,7 +846,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart5_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -830,7 +860,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart6_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -851,7 +881,7 @@ static struct clk_rcg2 ce1_clk_src = {
> .freq_tbl = ftbl_gcc_ce1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ce1_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -872,7 +902,7 @@ static struct clk_rcg2 ce2_clk_src = {
> .freq_tbl = ftbl_gcc_ce2_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ce2_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -893,7 +923,7 @@ static struct clk_rcg2 ce3_clk_src = {
> .freq_tbl = ftbl_gcc_ce3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ce3_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -914,7 +944,7 @@ static struct clk_rcg2 gp1_clk_src = {
> .freq_tbl = ftbl_gcc_gp_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp1_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -928,7 +958,7 @@ static struct clk_rcg2 gp2_clk_src = {
> .freq_tbl = ftbl_gcc_gp_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp2_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -942,7 +972,7 @@ static struct clk_rcg2 gp3_clk_src = {
> .freq_tbl = ftbl_gcc_gp_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp3_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -961,7 +991,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
> .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_0_aux_clk_src",
> - .parent_names = gcc_xo_pcie_sleep,
> + .parent_data = gcc_xo_pcie_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -975,7 +1005,7 @@ static struct clk_rcg2 pcie_1_aux_clk_src = {
> .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_1_aux_clk_src",
> - .parent_names = gcc_xo_pcie_sleep,
> + .parent_data = gcc_xo_pcie_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -994,7 +1024,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
> .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_0_pipe_clk_src",
> - .parent_names = gcc_xo_pcie,
> + .parent_data = gcc_xo_pcie,
> .num_parents = ARRAY_SIZE(gcc_xo_pcie),
> .ops = &clk_rcg2_ops,
> },
> @@ -1007,7 +1037,7 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = {
> .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_1_pipe_clk_src",
> - .parent_names = gcc_xo_pcie,
> + .parent_data = gcc_xo_pcie,
> .num_parents = ARRAY_SIZE(gcc_xo_pcie),
> .ops = &clk_rcg2_ops,
> },
> @@ -1025,7 +1055,7 @@ static struct clk_rcg2 pdm2_clk_src = {
> .freq_tbl = ftbl_gcc_pdm2_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pdm2_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1045,7 +1075,7 @@ static struct clk_rcg2 sata_asic0_clk_src = {
> .freq_tbl = ftbl_gcc_sata_asic0_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sata_asic0_clk_src",
> - .parent_names = gcc_xo_sata_asic0,
> + .parent_data = gcc_xo_sata_asic0,
> .num_parents = ARRAY_SIZE(gcc_xo_sata_asic0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1065,7 +1095,7 @@ static struct clk_rcg2 sata_pmalive_clk_src = {
> .freq_tbl = ftbl_gcc_sata_pmalive_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sata_pmalive_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1085,7 +1115,7 @@ static struct clk_rcg2 sata_rx_clk_src = {
> .freq_tbl = ftbl_gcc_sata_rx_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sata_rx_clk_src",
> - .parent_names = gcc_xo_sata_rx,
> + .parent_data = gcc_xo_sata_rx,
> .num_parents = ARRAY_SIZE(gcc_xo_sata_rx),
> .ops = &clk_rcg2_ops,
> },
> @@ -1103,7 +1133,7 @@ static struct clk_rcg2 sata_rx_oob_clk_src = {
> .freq_tbl = ftbl_gcc_sata_rx_oob_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sata_rx_oob_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1130,7 +1160,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
> .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc1_apps_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll4,
> + .parent_data = gcc_xo_gpll0_gpll4,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -1144,7 +1174,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
> .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc2_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -1158,7 +1188,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
> .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc3_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -1172,7 +1202,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
> .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc4_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -1191,7 +1221,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
> .freq_tbl = ftbl_gcc_tsif_ref_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "tsif_ref_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1209,25 +1239,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
> .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb30_mock_utmi_clk_src",
> - .parent_names = gcc_xo_gpll0,
> - .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> - .ops = &clk_rcg2_ops,
> - },
> -};
> -
> -static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
> - F(125000000, P_GPLL0, 1, 5, 24),
> - { }
> -};
> -
> -static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
> - .cmd_rcgr = 0x1be8,
> - .hid_width = 5,
> - .parent_map = gcc_xo_gpll0_map,
> - .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "usb30_sec_mock_utmi_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1245,7 +1257,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
> .freq_tbl = ftbl_gcc_usb_hs_system_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hs_system_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1268,9 +1280,9 @@ static struct clk_rcg2 usb_hsic_clk_src = {
> .freq_tbl = ftbl_gcc_usb_hsic_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hsic_clk_src",
> - .parent_names = (const char *[]){
> - "xo",
> - "gpll1_vote",
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll1_vote.hw },
> },
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> @@ -1290,9 +1302,9 @@ static struct clk_rcg2 usb_hsic_ahb_clk_src = {
> .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hsic_ahb_clk_src",
> - .parent_names = (const char *[]){
> - "xo",
> - "gpll1_vote",
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll1_vote.hw },
> },
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> @@ -1311,29 +1323,12 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
> .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hsic_io_cal_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
>
> -static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
> - .halt_reg = 0x1f14,
> - .clkr = {
> - .enable_reg = 0x1f14,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "gcc_usb_hsic_mock_utmi_clk",
> - .parent_names = (const char *[]){
> - "usb_hsic_mock_utmi_clk_src",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
> F(60000000, P_GPLL0, 10, 0, 0),
> { }
> @@ -1346,12 +1341,29 @@ static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
> .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hsic_mock_utmi_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
>
> +static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
> + .halt_reg = 0x1f14,
> + .clkr = {
> + .enable_reg = 0x1f14,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb_hsic_mock_utmi_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb_hsic_mock_utmi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
> F(75000000, P_GPLL0, 8, 0, 0),
> { }
> @@ -1364,7 +1376,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
> .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hsic_system_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1378,8 +1390,8 @@ static struct clk_branch gcc_bam_dma_ahb_clk = {
> .enable_mask = BIT(12),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_bam_dma_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1395,8 +1407,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
> .enable_mask = BIT(17),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1411,8 +1423,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup1_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup1_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1428,8 +1440,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup1_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup1_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup1_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1445,8 +1457,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup2_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup2_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1462,8 +1474,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup2_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup2_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup2_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1479,8 +1491,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup3_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup3_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1496,8 +1508,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup3_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup3_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup3_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1513,8 +1525,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup4_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup4_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1530,8 +1542,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup4_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup4_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup4_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1547,8 +1559,8 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup5_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup5_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1564,8 +1576,8 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup5_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup5_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup5_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1581,8 +1593,8 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup6_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup6_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1598,8 +1610,8 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup6_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup6_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup6_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1615,8 +1627,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart1_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_uart1_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_uart1_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1632,8 +1644,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart2_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_uart2_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_uart2_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1649,8 +1661,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart3_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_uart3_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_uart3_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1666,8 +1678,8 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart4_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_uart4_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_uart4_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1683,8 +1695,8 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart5_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_uart5_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_uart5_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1700,8 +1712,8 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart6_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_uart6_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_uart6_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1718,8 +1730,8 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
> .enable_mask = BIT(15),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1734,8 +1746,8 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup1_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup1_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1751,8 +1763,8 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup1_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup1_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup1_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1768,8 +1780,8 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup2_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup2_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1785,8 +1797,8 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup2_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup2_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup2_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1802,8 +1814,8 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup3_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup3_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1819,8 +1831,8 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup3_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup3_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup3_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1836,8 +1848,8 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup4_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup4_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1853,8 +1865,8 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup4_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup4_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup4_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1870,8 +1882,8 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup5_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup5_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1887,8 +1899,8 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup5_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup5_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup5_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1904,8 +1916,8 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup6_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup6_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1921,8 +1933,8 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup6_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_qup6_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_qup6_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1938,8 +1950,8 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart1_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_uart1_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_uart1_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1955,8 +1967,8 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart2_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_uart2_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_uart2_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1972,8 +1984,8 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart3_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_uart3_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_uart3_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1989,8 +2001,8 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart4_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_uart4_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_uart4_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2006,8 +2018,8 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart5_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_uart5_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_uart5_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2023,8 +2035,8 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart6_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp2_uart6_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp2_uart6_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2041,8 +2053,8 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
> .enable_mask = BIT(10),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_boot_rom_ahb_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2058,8 +2070,8 @@ static struct clk_branch gcc_ce1_ahb_clk = {
> .enable_mask = BIT(3),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ce1_ahb_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2075,8 +2087,8 @@ static struct clk_branch gcc_ce1_axi_clk = {
> .enable_mask = BIT(4),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ce1_axi_clk",
> - .parent_names = (const char *[]){
> - "system_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2092,8 +2104,8 @@ static struct clk_branch gcc_ce1_clk = {
> .enable_mask = BIT(5),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ce1_clk",
> - .parent_names = (const char *[]){
> - "ce1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ce1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2110,8 +2122,8 @@ static struct clk_branch gcc_ce2_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ce2_ahb_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2127,8 +2139,8 @@ static struct clk_branch gcc_ce2_axi_clk = {
> .enable_mask = BIT(1),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ce2_axi_clk",
> - .parent_names = (const char *[]){
> - "system_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2144,8 +2156,8 @@ static struct clk_branch gcc_ce2_clk = {
> .enable_mask = BIT(2),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ce2_clk",
> - .parent_names = (const char *[]){
> - "ce2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ce2_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2162,8 +2174,8 @@ static struct clk_branch gcc_ce3_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ce3_ahb_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2179,8 +2191,8 @@ static struct clk_branch gcc_ce3_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ce3_axi_clk",
> - .parent_names = (const char *[]){
> - "system_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2196,8 +2208,8 @@ static struct clk_branch gcc_ce3_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ce3_clk",
> - .parent_names = (const char *[]){
> - "ce3_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ce3_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2213,8 +2225,8 @@ static struct clk_branch gcc_gp1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_gp1_clk",
> - .parent_names = (const char *[]){
> - "gp1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gp1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2230,8 +2242,8 @@ static struct clk_branch gcc_gp2_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_gp2_clk",
> - .parent_names = (const char *[]){
> - "gp2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gp2_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2247,8 +2259,8 @@ static struct clk_branch gcc_gp3_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_gp3_clk",
> - .parent_names = (const char *[]){
> - "gp3_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gp3_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2264,8 +2276,8 @@ static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ocmem_noc_cfg_ahb_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2280,8 +2292,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_aux_clk",
> - .parent_names = (const char *[]){
> - "pcie_0_aux_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcie_0_aux_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2297,8 +2309,8 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_cfg_ahb_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2314,8 +2326,8 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_mstr_axi_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2331,8 +2343,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_pipe_clk",
> - .parent_names = (const char *[]){
> - "pcie_0_pipe_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &pcie_0_pipe_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2348,8 +2360,8 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_slv_axi_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2365,8 +2377,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_aux_clk",
> - .parent_names = (const char *[]){
> - "pcie_1_aux_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcie_1_aux_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2382,8 +2394,8 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_cfg_ahb_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2399,8 +2411,8 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_mstr_axi_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2416,8 +2428,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_pipe_clk",
> - .parent_names = (const char *[]){
> - "pcie_1_pipe_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &pcie_1_pipe_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2433,8 +2445,8 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_slv_axi_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2450,8 +2462,8 @@ static struct clk_branch gcc_pdm2_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pdm2_clk",
> - .parent_names = (const char *[]){
> - "pdm2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pdm2_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2467,8 +2479,8 @@ static struct clk_branch gcc_pdm_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pdm_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2483,8 +2495,8 @@ static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_periph_noc_usb_hsic_ahb_clk",
> - .parent_names = (const char *[]){
> - "usb_hsic_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb_hsic_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2501,8 +2513,8 @@ static struct clk_branch gcc_prng_ahb_clk = {
> .enable_mask = BIT(13),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_prng_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2517,8 +2529,8 @@ static struct clk_branch gcc_sata_asic0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sata_asic0_clk",
> - .parent_names = (const char *[]){
> - "sata_asic0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sata_asic0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2534,8 +2546,8 @@ static struct clk_branch gcc_sata_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sata_axi_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2551,8 +2563,8 @@ static struct clk_branch gcc_sata_cfg_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sata_cfg_ahb_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2568,8 +2580,8 @@ static struct clk_branch gcc_sata_pmalive_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sata_pmalive_clk",
> - .parent_names = (const char *[]){
> - "sata_pmalive_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sata_pmalive_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2585,8 +2597,8 @@ static struct clk_branch gcc_sata_rx_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sata_rx_clk",
> - .parent_names = (const char *[]){
> - "sata_rx_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sata_rx_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2602,8 +2614,8 @@ static struct clk_branch gcc_sata_rx_oob_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sata_rx_oob_clk",
> - .parent_names = (const char *[]){
> - "sata_rx_oob_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sata_rx_oob_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2619,8 +2631,8 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc1_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2635,8 +2647,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc1_apps_clk",
> - .parent_names = (const char *[]){
> - "sdcc1_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sdcc1_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2652,8 +2664,8 @@ static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc1_cdccal_ff_clk",
> - .parent_names = (const char *[]){
> - "xo"
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" }
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2668,8 +2680,8 @@ static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc1_cdccal_sleep_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src"
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "sleep_clk", .name = "sleep_clk" }
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2684,8 +2696,8 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc2_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2700,8 +2712,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc2_apps_clk",
> - .parent_names = (const char *[]){
> - "sdcc2_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sdcc2_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2717,8 +2729,8 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc3_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2733,8 +2745,8 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc3_apps_clk",
> - .parent_names = (const char *[]){
> - "sdcc3_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sdcc3_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2750,8 +2762,8 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc4_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2766,8 +2778,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc4_apps_clk",
> - .parent_names = (const char *[]){
> - "sdcc4_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sdcc4_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2783,8 +2795,8 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sys_noc_ufs_axi_clk",
> - .parent_names = (const char *[]){
> - "ufs_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ufs_axi_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2800,8 +2812,8 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sys_noc_usb3_axi_clk",
> - .parent_names = (const char *[]){
> - "usb30_master_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb30_master_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2817,8 +2829,8 @@ static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sys_noc_usb3_sec_axi_clk",
> - .parent_names = (const char *[]){
> - "usb30_sec_master_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb30_sec_master_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2834,8 +2846,8 @@ static struct clk_branch gcc_tsif_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_tsif_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2850,8 +2862,8 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_tsif_inactivity_timers_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep_clk", .name = "sleep_clk",
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2867,8 +2879,8 @@ static struct clk_branch gcc_tsif_ref_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_tsif_ref_clk",
> - .parent_names = (const char *[]){
> - "tsif_ref_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &tsif_ref_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2884,8 +2896,8 @@ static struct clk_branch gcc_ufs_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_ahb_clk",
> - .parent_names = (const char *[]){
> - "config_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &config_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2901,8 +2913,8 @@ static struct clk_branch gcc_ufs_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_axi_clk",
> - .parent_names = (const char *[]){
> - "ufs_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ufs_axi_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2918,8 +2930,8 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_rx_cfg_clk",
> - .parent_names = (const char *[]){
> - "ufs_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ufs_axi_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2935,8 +2947,8 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_rx_symbol_0_clk",
> - .parent_names = (const char *[]){
> - "ufs_rx_symbol_0_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2952,8 +2964,8 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_rx_symbol_1_clk",
> - .parent_names = (const char *[]){
> - "ufs_rx_symbol_1_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2969,8 +2981,8 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_tx_cfg_clk",
> - .parent_names = (const char *[]){
> - "ufs_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ufs_axi_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2986,8 +2998,8 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_tx_symbol_0_clk",
> - .parent_names = (const char *[]){
> - "ufs_tx_symbol_0_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3003,8 +3015,8 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_tx_symbol_1_clk",
> - .parent_names = (const char *[]){
> - "ufs_tx_symbol_1_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "ufs_tx_symbol_1_clk_src", .name = "ufs_tx_symbol_1_clk_src",
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3020,8 +3032,8 @@ static struct clk_branch gcc_usb2a_phy_sleep_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb2a_phy_sleep_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep_clk", .name = "sleep_clk",
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -3036,8 +3048,8 @@ static struct clk_branch gcc_usb2b_phy_sleep_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb2b_phy_sleep_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep_clk", .name = "sleep_clk",
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -3052,8 +3064,8 @@ static struct clk_branch gcc_usb30_master_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb30_master_clk",
> - .parent_names = (const char *[]){
> - "usb30_master_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb30_master_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3069,8 +3081,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb30_sec_master_clk",
> - .parent_names = (const char *[]){
> - "usb30_sec_master_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb30_sec_master_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3086,8 +3098,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb30_mock_utmi_clk",
> - .parent_names = (const char *[]){
> - "usb30_mock_utmi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb30_mock_utmi_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3103,8 +3115,8 @@ static struct clk_branch gcc_usb30_sleep_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb30_sleep_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep_clk", .name = "sleep_clk",
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -3119,8 +3131,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hs_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -3135,8 +3147,8 @@ static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hs_inactivity_timers_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep_clk", .name = "sleep_clk",
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3152,8 +3164,8 @@ static struct clk_branch gcc_usb_hs_system_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hs_system_clk",
> - .parent_names = (const char *[]){
> - "usb_hs_system_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb_hs_system_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3169,8 +3181,8 @@ static struct clk_branch gcc_usb_hsic_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hsic_ahb_clk",
> - .parent_names = (const char *[]){
> - "periph_noc_clk_src",
> + .parent_hws = (const struct clk_hw*[]) {
> + &periph_noc_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -3185,8 +3197,8 @@ static struct clk_branch gcc_usb_hsic_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hsic_clk",
> - .parent_names = (const char *[]){
> - "usb_hsic_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb_hsic_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3202,8 +3214,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hsic_io_cal_clk",
> - .parent_names = (const char *[]){
> - "usb_hsic_io_cal_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb_hsic_io_cal_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3219,8 +3231,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hsic_io_cal_sleep_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep_clk", .name = "sleep_clk",
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -3235,8 +3247,8 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hsic_system_clk",
> - .parent_names = (const char *[]){
> - "usb_hsic_system_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb_hsic_system_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
2022-12-27 1:32 ` [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
@ 2022-12-27 11:58 ` Konrad Dybcio
2022-12-27 12:17 ` Dmitry Baryshkov
0 siblings, 1 reply; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 11:58 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Add the GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for
> the multimedia subsystem.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
I'm thinking whether it would maybe make sense to put 8974
and 8084 clocks in a single driver.. They seem close to identical.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/clk/qcom/gcc-apq8084.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
> index c26e222c78d4..7085d2ccae49 100644
> --- a/drivers/clk/qcom/gcc-apq8084.c
> +++ b/drivers/clk/qcom/gcc-apq8084.c
> @@ -1382,6 +1382,19 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
> },
> };
>
> +static struct clk_regmap gcc_mmss_gpll0_clk_src = {
> + .enable_reg = 0x1484,
> + .enable_mask = BIT(26),
> + .hw.init = &(struct clk_init_data){
> + .name = "mmss_gpll0_vote",
> + .parent_hws = (const struct clk_hw*[]){
> + &gpll0_vote.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch_simple_ops,
> + },
> +};
> +
> static struct clk_branch gcc_bam_dma_ahb_clk = {
> .halt_reg = 0x0d44,
> .halt_check = BRANCH_HALT_VOTED,
> @@ -3480,6 +3493,7 @@ static struct clk_regmap *gcc_apq8084_clocks[] = {
> [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
> [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
> [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
> + [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
> };
>
> static struct gdsc *gcc_apq8084_gdscs[] = {
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 08/12] clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parents
2022-12-27 1:32 ` [RFC PATCH 08/12] clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2022-12-27 12:00 ` Konrad Dybcio
0 siblings, 0 replies; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 12:00 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/clk/qcom/mmcc-apq8084.c | 88 ++++++++++++++++-----------------
> 1 file changed, 44 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
> index e9f971359155..4acbcb43927f 100644
> --- a/drivers/clk/qcom/mmcc-apq8084.c
> +++ b/drivers/clk/qcom/mmcc-apq8084.c
> @@ -319,7 +319,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmss_ahb_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -344,7 +344,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmss_axi_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -368,7 +368,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ocmemnoc_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -387,7 +387,7 @@ static struct clk_rcg2 csi0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -400,7 +400,7 @@ static struct clk_rcg2 csi1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -413,7 +413,7 @@ static struct clk_rcg2 csi2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi2_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -426,7 +426,7 @@ static struct clk_rcg2 csi3_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi3_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -456,7 +456,7 @@ static struct clk_rcg2 vfe0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vfe0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -469,7 +469,7 @@ static struct clk_rcg2 vfe1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vfe1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -497,7 +497,7 @@ static struct clk_rcg2 mdp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mdp_clk_src",
> .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -509,7 +509,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gfx3d_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -532,7 +532,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -545,7 +545,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -558,7 +558,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg2_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -571,7 +571,7 @@ static struct clk_rcg2 pclk0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pclk0_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_pixel_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -585,7 +585,7 @@ static struct clk_rcg2 pclk1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pclk1_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_pixel_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -610,7 +610,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vcodec0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -629,7 +629,7 @@ static struct clk_rcg2 vp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vp_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -648,7 +648,7 @@ static struct clk_rcg2 cci_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cci_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -672,7 +672,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
> - .num_parents = 7,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -686,7 +686,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
> - .num_parents = 7,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -714,7 +714,7 @@ static struct clk_rcg2 mclk0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -728,7 +728,7 @@ static struct clk_rcg2 mclk1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -742,7 +742,7 @@ static struct clk_rcg2 mclk2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk2_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -756,7 +756,7 @@ static struct clk_rcg2 mclk3_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk3_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -775,7 +775,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0phytimer_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -788,7 +788,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1phytimer_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -801,7 +801,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi2phytimer_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -824,7 +824,7 @@ static struct clk_rcg2 cpp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cpp_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -836,7 +836,7 @@ static struct clk_rcg2 byte0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "byte0_clk_src",
> .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_byte2_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -849,7 +849,7 @@ static struct clk_rcg2 byte1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "byte1_clk_src",
> .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_byte2_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -868,7 +868,7 @@ static struct clk_rcg2 edpaux_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "edpaux_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -887,7 +887,7 @@ static struct clk_rcg2 edplink_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "edplink_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_rcg2_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -907,7 +907,7 @@ static struct clk_rcg2 edppixel_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "edppixel_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
> .ops = &clk_edp_pixel_ops,
> },
> };
> @@ -925,7 +925,7 @@ static struct clk_rcg2 esc0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "esc0_clk_src",
> .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -938,7 +938,7 @@ static struct clk_rcg2 esc1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "esc1_clk_src",
> .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -956,7 +956,7 @@ static struct clk_rcg2 extpclk_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "extpclk_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_byte_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -975,7 +975,7 @@ static struct clk_rcg2 hdmi_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "hdmi_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -993,7 +993,7 @@ static struct clk_rcg2 vsync_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vsync_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1011,7 +1011,7 @@ static struct clk_rcg2 rbcpr_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "rbcpr_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1029,7 +1029,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "rbbmtimer_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1052,7 +1052,7 @@ static struct clk_rcg2 maple_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "maple_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1074,7 +1074,7 @@ static struct clk_rcg2 vdp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vdp_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1093,7 +1093,7 @@ static struct clk_rcg2 vpu_bus_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vpu_bus_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 09/12] clk: qcom: mmcc-apq8084: move clock parent tables down
2022-12-27 1:32 ` [RFC PATCH 09/12] clk: qcom: mmcc-apq8084: move clock parent tables down Dmitry Baryshkov
@ 2022-12-27 12:00 ` Konrad Dybcio
0 siblings, 0 replies; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 12:00 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Move clock parent tables down, after the PLL declrataions, so that we
> can use pll hw clock fields in the next commit.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/clk/qcom/mmcc-apq8084.c | 200 ++++++++++++++++----------------
> 1 file changed, 100 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
> index 4acbcb43927f..fee7c767132d 100644
> --- a/drivers/clk/qcom/mmcc-apq8084.c
> +++ b/drivers/clk/qcom/mmcc-apq8084.c
> @@ -40,6 +40,106 @@ enum {
> P_MMSLEEP,
> };
>
> +static struct clk_pll mmpll0 = {
> + .l_reg = 0x0004,
> + .m_reg = 0x0008,
> + .n_reg = 0x000c,
> + .config_reg = 0x0014,
> + .mode_reg = 0x0000,
> + .status_reg = 0x001c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll0",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap mmpll0_vote = {
> + .enable_reg = 0x0100,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "mmpll0_vote",
> + .parent_names = (const char *[]){ "mmpll0" },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
> +static struct clk_pll mmpll1 = {
> + .l_reg = 0x0044,
> + .m_reg = 0x0048,
> + .n_reg = 0x004c,
> + .config_reg = 0x0050,
> + .mode_reg = 0x0040,
> + .status_reg = 0x005c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll1",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap mmpll1_vote = {
> + .enable_reg = 0x0100,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "mmpll1_vote",
> + .parent_names = (const char *[]){ "mmpll1" },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
> +static struct clk_pll mmpll2 = {
> + .l_reg = 0x4104,
> + .m_reg = 0x4108,
> + .n_reg = 0x410c,
> + .config_reg = 0x4110,
> + .mode_reg = 0x4100,
> + .status_reg = 0x411c,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll2",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_pll mmpll3 = {
> + .l_reg = 0x0084,
> + .m_reg = 0x0088,
> + .n_reg = 0x008c,
> + .config_reg = 0x0090,
> + .mode_reg = 0x0080,
> + .status_reg = 0x009c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll3",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_pll mmpll4 = {
> + .l_reg = 0x00a4,
> + .m_reg = 0x00a8,
> + .n_reg = 0x00ac,
> + .config_reg = 0x00b0,
> + .mode_reg = 0x0080,
> + .status_reg = 0x00bc,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll4",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
> { P_XO, 0 },
> { P_MMPLL0, 1 },
> @@ -212,106 +312,6 @@ static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
> "sleep_clk_src",
> };
>
> -static struct clk_pll mmpll0 = {
> - .l_reg = 0x0004,
> - .m_reg = 0x0008,
> - .n_reg = 0x000c,
> - .config_reg = 0x0014,
> - .mode_reg = 0x0000,
> - .status_reg = 0x001c,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll0",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_regmap mmpll0_vote = {
> - .enable_reg = 0x0100,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmpll0_vote",
> - .parent_names = (const char *[]){ "mmpll0" },
> - .num_parents = 1,
> - .ops = &clk_pll_vote_ops,
> - },
> -};
> -
> -static struct clk_pll mmpll1 = {
> - .l_reg = 0x0044,
> - .m_reg = 0x0048,
> - .n_reg = 0x004c,
> - .config_reg = 0x0050,
> - .mode_reg = 0x0040,
> - .status_reg = 0x005c,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll1",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_regmap mmpll1_vote = {
> - .enable_reg = 0x0100,
> - .enable_mask = BIT(1),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmpll1_vote",
> - .parent_names = (const char *[]){ "mmpll1" },
> - .num_parents = 1,
> - .ops = &clk_pll_vote_ops,
> - },
> -};
> -
> -static struct clk_pll mmpll2 = {
> - .l_reg = 0x4104,
> - .m_reg = 0x4108,
> - .n_reg = 0x410c,
> - .config_reg = 0x4110,
> - .mode_reg = 0x4100,
> - .status_reg = 0x411c,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll2",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_pll mmpll3 = {
> - .l_reg = 0x0084,
> - .m_reg = 0x0088,
> - .n_reg = 0x008c,
> - .config_reg = 0x0090,
> - .mode_reg = 0x0080,
> - .status_reg = 0x009c,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll3",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_pll mmpll4 = {
> - .l_reg = 0x00a4,
> - .m_reg = 0x00a8,
> - .n_reg = 0x00ac,
> - .config_reg = 0x00b0,
> - .mode_reg = 0x0080,
> - .status_reg = 0x00bc,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll4",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> static struct clk_rcg2 mmss_ahb_clk_src = {
> .cmd_rcgr = 0x5000,
> .hid_width = 5,
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 10/12] clk: qcom: mmcc-apq8084: remove spdm clocks
2022-12-27 1:32 ` [RFC PATCH 10/12] clk: qcom: mmcc-apq8084: remove spdm clocks Dmitry Baryshkov
@ 2022-12-27 12:01 ` Konrad Dybcio
0 siblings, 0 replies; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 12:01 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Georgi Djakov
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> SPDM is used for debug/profiling and does not have any other
> functionality. These clocks can safely be removed.
>
> Suggested-by: Stephen Boyd <sboyd@kernel.org>
> Suggested-by: Georgi Djakov <djakov@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
> 1 file changed, 271 deletions(-)
>
> diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
> index fee7c767132d..631b1ff8cf01 100644
> --- a/drivers/clk/qcom/mmcc-apq8084.c
> +++ b/drivers/clk/qcom/mmcc-apq8084.c
> @@ -2364,262 +2364,6 @@ static struct clk_branch mmss_rbcpr_clk = {
> },
> };
>
> -static struct clk_branch mmss_spdm_ahb_clk = {
> - .halt_reg = 0x0230,
> - .clkr = {
> - .enable_reg = 0x0230,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_ahb_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_axi_clk = {
> - .halt_reg = 0x0210,
> - .clkr = {
> - .enable_reg = 0x0210,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_axi_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_axi_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_csi0_clk = {
> - .halt_reg = 0x023c,
> - .clkr = {
> - .enable_reg = 0x023c,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_csi0_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_csi0_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_gfx3d_clk = {
> - .halt_reg = 0x022c,
> - .clkr = {
> - .enable_reg = 0x022c,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_gfx3d_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_gfx3d_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_jpeg0_clk = {
> - .halt_reg = 0x0204,
> - .clkr = {
> - .enable_reg = 0x0204,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_jpeg0_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_jpeg0_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_jpeg1_clk = {
> - .halt_reg = 0x0208,
> - .clkr = {
> - .enable_reg = 0x0208,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_jpeg1_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_jpeg1_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_jpeg2_clk = {
> - .halt_reg = 0x0224,
> - .clkr = {
> - .enable_reg = 0x0224,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_jpeg2_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_jpeg2_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_mdp_clk = {
> - .halt_reg = 0x020c,
> - .clkr = {
> - .enable_reg = 0x020c,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_mdp_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_mdp_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_pclk0_clk = {
> - .halt_reg = 0x0234,
> - .clkr = {
> - .enable_reg = 0x0234,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_pclk0_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_pclk0_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_pclk1_clk = {
> - .halt_reg = 0x0228,
> - .clkr = {
> - .enable_reg = 0x0228,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_pclk1_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_pclk1_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_vcodec0_clk = {
> - .halt_reg = 0x0214,
> - .clkr = {
> - .enable_reg = 0x0214,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_vcodec0_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_vcodec0_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_vfe0_clk = {
> - .halt_reg = 0x0218,
> - .clkr = {
> - .enable_reg = 0x0218,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_vfe0_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_vfe0_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_vfe1_clk = {
> - .halt_reg = 0x021c,
> - .clkr = {
> - .enable_reg = 0x021c,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_vfe1_clk",
> - .parent_names = (const char *[]){
> - "mmss_spdm_vfe1_div_clk",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_rm_axi_clk = {
> - .halt_reg = 0x0304,
> - .clkr = {
> - .enable_reg = 0x0304,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_rm_axi_clk",
> - .parent_names = (const char *[]){
> - "mmss_axi_clk_src",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
> - .halt_reg = 0x0308,
> - .clkr = {
> - .enable_reg = 0x0308,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmss_spdm_rm_ocmemnoc_clk",
> - .parent_names = (const char *[]){
> - "ocmemnoc_clk_src",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> -
> static struct clk_branch mmss_misc_ahb_clk = {
> .halt_reg = 0x502c,
> .clkr = {
> @@ -3252,21 +2996,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
> [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
> [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
> [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
> - [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
> - [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
> - [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
> - [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
> - [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
> - [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
> - [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
> - [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
> - [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
> - [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
> - [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
> - [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
> - [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
> - [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
> - [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
> [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
> [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
> [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 11/12] clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names
2022-12-27 1:32 ` [RFC PATCH 11/12] clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
@ 2022-12-27 12:07 ` Konrad Dybcio
0 siblings, 0 replies; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 12:07 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names. Use parent_hws where possible to refer parent
> clocks directly, skipping the lookup.
>
> Note, the system names for xo clocks were changed from "xo" to
> "xo_board" to follow the example of other platforms. This switches the
> clocks to use DT-provided "xo_board" clock instead of manually
> registered "xo" clock and allows us to drop qcom_cc_register_board_clk()
> call from the driver at some point.
>
> In the same way change the looked up system "sleep_clk_src" clock to
> "sleep_clk", which is registered from DT.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/clk/qcom/mmcc-apq8084.c | 644 ++++++++++++++++----------------
> 1 file changed, 331 insertions(+), 313 deletions(-)
>
> diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
> index 631b1ff8cf01..02fc21208dd1 100644
> --- a/drivers/clk/qcom/mmcc-apq8084.c
> +++ b/drivers/clk/qcom/mmcc-apq8084.c
> @@ -50,7 +50,9 @@ static struct clk_pll mmpll0 = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmpll0",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" },
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -61,7 +63,9 @@ static struct clk_regmap mmpll0_vote = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmpll0_vote",
> - .parent_names = (const char *[]){ "mmpll0" },
> + .parent_hws = (const struct clk_hw*[]){
> + &mmpll0.clkr.hw
> + },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
> @@ -77,7 +81,9 @@ static struct clk_pll mmpll1 = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmpll1",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" },
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -88,7 +94,9 @@ static struct clk_regmap mmpll1_vote = {
> .enable_mask = BIT(1),
> .hw.init = &(struct clk_init_data){
> .name = "mmpll1_vote",
> - .parent_names = (const char *[]){ "mmpll1" },
> + .parent_hws = (const struct clk_hw*[]){
> + &mmpll1.clkr.hw
> + },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
> @@ -103,7 +111,9 @@ static struct clk_pll mmpll2 = {
> .status_reg = 0x411c,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmpll2",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" },
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -119,7 +129,9 @@ static struct clk_pll mmpll3 = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmpll3",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" },
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -134,7 +146,9 @@ static struct clk_pll mmpll4 = {
> .status_reg = 0x00bc,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmpll4",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" },
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -147,11 +161,11 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
> { P_GPLL0, 5 }
> };
>
> -static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
> - "xo",
> - "mmpll0_vote",
> - "mmpll1_vote",
> - "mmss_gpll0_vote",
> +static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &mmpll0_vote.hw },
> + { .hw = &mmpll1_vote.hw },
> + { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> };
>
> static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
> @@ -163,13 +177,13 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
> { P_DSI1PLL, 3 }
> };
>
> -static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
> - "xo",
> - "mmpll0_vote",
> - "hdmipll",
> - "mmss_gpll0_vote",
> - "dsi0pll",
> - "dsi1pll",
> +static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &mmpll0_vote.hw },
> + { .fw_name = "hdmipll", .name = "hdmipll" },
> + { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> + { .fw_name = "dsi0pll", .name = "dsi0pll" },
> + { .fw_name = "dsi1pll", .name = "dsi1pll" },
> };
>
> static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
> @@ -180,12 +194,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
> { P_MMPLL2, 3 }
> };
>
> -static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
> - "xo",
> - "mmpll0_vote",
> - "mmpll1_vote",
> - "mmss_gpll0_vote",
> - "mmpll2",
> +static const struct clk_parent_data mmcc_xo_mmpll0_1_2_gpll0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &mmpll0_vote.hw },
> + { .hw = &mmpll1_vote.hw },
> + { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> + { .hw = &mmpll2.clkr.hw },
> };
>
> static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
> @@ -196,12 +210,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
> { P_MMPLL3, 3 }
> };
>
> -static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
> - "xo",
> - "mmpll0_vote",
> - "mmpll1_vote",
> - "mmss_gpll0_vote",
> - "mmpll3",
> +static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &mmpll0_vote.hw },
> + { .hw = &mmpll1_vote.hw },
> + { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
> + { .hw = &mmpll3.clkr.hw },
> };
>
> static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
> @@ -213,13 +227,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
> { P_DSI1PLL, 2 }
> };
>
> -static const char * const mmcc_xo_dsi_hdmi_edp[] = {
> - "xo",
> - "edp_link_clk",
> - "hdmipll",
> - "edp_vco_div",
> - "dsi0pll",
> - "dsi1pll",
> +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> + { .fw_name = "hdmipll", .name = "hdmipll" },
> + { .fw_name = "edp_vco_div", .name = "edp_vco_div" },
> + { .fw_name = "dsi0pll", .name = "dsi0pll" },
> + { .fw_name = "dsi1pll", .name = "dsi1pll" },
> };
>
> static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
> @@ -231,13 +245,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
> { P_DSI1PLL, 2 }
> };
>
> -static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
> - "xo",
> - "edp_link_clk",
> - "hdmipll",
> - "gpll0_vote",
> - "dsi0pll",
> - "dsi1pll",
> +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> + { .fw_name = "hdmipll", .name = "hdmipll" },
> + { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
> + { .fw_name = "dsi0pll", .name = "dsi0pll" },
> + { .fw_name = "dsi1pll", .name = "dsi1pll" },
> };
>
> static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
> @@ -249,13 +263,13 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
> { P_DSI1PLL_BYTE, 2 }
> };
>
> -static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
> - "xo",
> - "edp_link_clk",
> - "hdmipll",
> - "gpll0_vote",
> - "dsi0pllbyte",
> - "dsi1pllbyte",
> +static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
> + { .fw_name = "hdmipll", .name = "hdmipll" },
> + { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
> + { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
> + { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
> };
>
> static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
> @@ -266,12 +280,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
> { P_MMPLL4, 3 }
> };
>
> -static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
> - "xo",
> - "mmpll0",
> - "mmpll1",
> - "mmpll4",
> - "gpll0",
> +static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &mmpll0.clkr.hw },
> + { .hw = &mmpll1.clkr.hw },
> + { .hw = &mmpll4.clkr.hw },
> + { .fw_name = "gpll0", .name = "gpll0" },
> };
>
> static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
> @@ -283,13 +297,13 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
> { P_GPLL1, 4 }
> };
>
> -static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
> - "xo",
> - "mmpll0",
> - "mmpll1",
> - "mmpll4",
> - "gpll1",
> - "gpll0",
> +static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &mmpll0.clkr.hw },
> + { .hw = &mmpll1.clkr.hw },
> + { .hw = &mmpll4.clkr.hw },
> + { .fw_name = "gpll1", .name = "gpll1" },
> + { .fw_name = "gpll0", .name = "gpll0" },
> };
>
> static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
> @@ -302,14 +316,14 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
> { P_MMSLEEP, 6 }
> };
>
> -static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
> - "xo",
> - "mmpll0",
> - "mmpll1",
> - "mmpll4",
> - "gpll1",
> - "gpll0",
> - "sleep_clk_src",
> +static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &mmpll0.clkr.hw },
> + { .hw = &mmpll1.clkr.hw },
> + { .hw = &mmpll4.clkr.hw },
> + { .fw_name = "gpll1", .name = "gpll1" },
> + { .fw_name = "gpll0", .name = "gpll0" },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> };
>
> static struct clk_rcg2 mmss_ahb_clk_src = {
> @@ -318,7 +332,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
> .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmss_ahb_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -343,7 +357,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
> .freq_tbl = ftbl_mmss_axi_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmss_axi_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -367,7 +381,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
> .freq_tbl = ftbl_ocmemnoc_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ocmemnoc_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -386,7 +400,7 @@ static struct clk_rcg2 csi0_clk_src = {
> .freq_tbl = ftbl_camss_csi0_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -399,7 +413,7 @@ static struct clk_rcg2 csi1_clk_src = {
> .freq_tbl = ftbl_camss_csi0_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -412,7 +426,7 @@ static struct clk_rcg2 csi2_clk_src = {
> .freq_tbl = ftbl_camss_csi0_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi2_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -425,7 +439,7 @@ static struct clk_rcg2 csi3_clk_src = {
> .freq_tbl = ftbl_camss_csi0_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi3_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -455,7 +469,7 @@ static struct clk_rcg2 vfe0_clk_src = {
> .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vfe0_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -468,7 +482,7 @@ static struct clk_rcg2 vfe1_clk_src = {
> .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vfe1_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -496,7 +510,7 @@ static struct clk_rcg2 mdp_clk_src = {
> .freq_tbl = ftbl_mdss_mdp_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mdp_clk_src",
> - .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> + .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -508,7 +522,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
> .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gfx3d_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_2_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -531,7 +545,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
> .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg0_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -544,7 +558,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
> .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg1_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -557,7 +571,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
> .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg2_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -570,7 +584,7 @@ static struct clk_rcg2 pclk0_clk_src = {
> .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pclk0_clk_src",
> - .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> + .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_pixel_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -584,7 +598,7 @@ static struct clk_rcg2 pclk1_clk_src = {
> .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pclk1_clk_src",
> - .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> + .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_pixel_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -609,7 +623,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
> .freq_tbl = ftbl_venus0_vcodec0_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vcodec0_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_3_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -628,7 +642,7 @@ static struct clk_rcg2 vp_clk_src = {
> .freq_tbl = ftbl_avsync_vp_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vp_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -647,7 +661,7 @@ static struct clk_rcg2 cci_clk_src = {
> .freq_tbl = ftbl_camss_cci_cci_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cci_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> @@ -671,7 +685,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
> .freq_tbl = ftbl_camss_gp0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp0_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -685,7 +699,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
> .freq_tbl = ftbl_camss_gp0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp1_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -713,7 +727,7 @@ static struct clk_rcg2 mclk0_clk_src = {
> .freq_tbl = ftbl_camss_mclk0_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk0_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> @@ -727,7 +741,7 @@ static struct clk_rcg2 mclk1_clk_src = {
> .freq_tbl = ftbl_camss_mclk0_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk1_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> @@ -741,7 +755,7 @@ static struct clk_rcg2 mclk2_clk_src = {
> .freq_tbl = ftbl_camss_mclk0_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk2_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> @@ -755,7 +769,7 @@ static struct clk_rcg2 mclk3_clk_src = {
> .freq_tbl = ftbl_camss_mclk0_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk3_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> @@ -774,7 +788,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
> .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0phytimer_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -787,7 +801,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
> .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1phytimer_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -800,7 +814,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
> .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi2phytimer_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -823,7 +837,7 @@ static struct clk_rcg2 cpp_clk_src = {
> .freq_tbl = ftbl_camss_vfe_cpp_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cpp_clk_src",
> - .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> + .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -835,7 +849,7 @@ static struct clk_rcg2 byte0_clk_src = {
> .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "byte0_clk_src",
> - .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> + .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_byte2_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -848,7 +862,7 @@ static struct clk_rcg2 byte1_clk_src = {
> .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "byte1_clk_src",
> - .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> + .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_byte2_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -867,7 +881,7 @@ static struct clk_rcg2 edpaux_clk_src = {
> .freq_tbl = ftbl_mdss_edpaux_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "edpaux_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -886,7 +900,7 @@ static struct clk_rcg2 edplink_clk_src = {
> .freq_tbl = ftbl_mdss_edplink_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "edplink_clk_src",
> - .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> + .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_rcg2_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -906,7 +920,7 @@ static struct clk_rcg2 edppixel_clk_src = {
> .freq_tbl = edp_pixel_freq_tbl,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "edppixel_clk_src",
> - .parent_names = mmcc_xo_dsi_hdmi_edp,
> + .parent_data = mmcc_xo_dsi_hdmi_edp,
> .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
> .ops = &clk_edp_pixel_ops,
> },
> @@ -924,7 +938,7 @@ static struct clk_rcg2 esc0_clk_src = {
> .freq_tbl = ftbl_mdss_esc0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "esc0_clk_src",
> - .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> + .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -937,7 +951,7 @@ static struct clk_rcg2 esc1_clk_src = {
> .freq_tbl = ftbl_mdss_esc0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "esc1_clk_src",
> - .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> + .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -955,7 +969,7 @@ static struct clk_rcg2 extpclk_clk_src = {
> .freq_tbl = extpclk_freq_tbl,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "extpclk_clk_src",
> - .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> + .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_byte_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -974,7 +988,7 @@ static struct clk_rcg2 hdmi_clk_src = {
> .freq_tbl = ftbl_mdss_hdmi_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "hdmi_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -992,7 +1006,7 @@ static struct clk_rcg2 vsync_clk_src = {
> .freq_tbl = ftbl_mdss_vsync_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vsync_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1010,7 +1024,7 @@ static struct clk_rcg2 rbcpr_clk_src = {
> .freq_tbl = ftbl_mmss_rbcpr_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "rbcpr_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1028,7 +1042,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = {
> .freq_tbl = ftbl_oxili_rbbmtimer_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "rbbmtimer_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1051,7 +1065,7 @@ static struct clk_rcg2 maple_clk_src = {
> .freq_tbl = ftbl_vpu_maple_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "maple_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1073,7 +1087,7 @@ static struct clk_rcg2 vdp_clk_src = {
> .freq_tbl = ftbl_vpu_vdp_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vdp_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1092,7 +1106,7 @@ static struct clk_rcg2 vpu_bus_clk_src = {
> .freq_tbl = ftbl_vpu_bus_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vpu_bus_clk_src",
> - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
> .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1105,7 +1119,9 @@ static struct clk_branch mmss_cxo_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmss_cxo_clk",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" },
> + },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1120,8 +1136,8 @@ static struct clk_branch mmss_sleepclk_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmss_sleepclk_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1137,8 +1153,8 @@ static struct clk_branch avsync_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "avsync_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1154,8 +1170,8 @@ static struct clk_branch avsync_edppixel_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "avsync_edppixel_clk",
> - .parent_names = (const char *[]){
> - "edppixel_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &edppixel_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1171,8 +1187,8 @@ static struct clk_branch avsync_extpclk_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "avsync_extpclk_clk",
> - .parent_names = (const char *[]){
> - "extpclk_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &extpclk_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1188,8 +1204,8 @@ static struct clk_branch avsync_pclk0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "avsync_pclk0_clk",
> - .parent_names = (const char *[]){
> - "pclk0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pclk0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1205,8 +1221,8 @@ static struct clk_branch avsync_pclk1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "avsync_pclk1_clk",
> - .parent_names = (const char *[]){
> - "pclk1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pclk1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1222,8 +1238,8 @@ static struct clk_branch avsync_vp_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "avsync_vp_clk",
> - .parent_names = (const char *[]){
> - "vp_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vp_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1239,8 +1255,8 @@ static struct clk_branch camss_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1256,8 +1272,8 @@ static struct clk_branch camss_cci_cci_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_cci_cci_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1272,8 +1288,8 @@ static struct clk_branch camss_cci_cci_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_cci_cci_clk",
> - .parent_names = (const char *[]){
> - "cci_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &cci_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1289,8 +1305,8 @@ static struct clk_branch camss_csi0_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi0_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1305,8 +1321,8 @@ static struct clk_branch camss_csi0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi0_clk",
> - .parent_names = (const char *[]){
> - "csi0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1322,8 +1338,8 @@ static struct clk_branch camss_csi0phy_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi0phy_clk",
> - .parent_names = (const char *[]){
> - "csi0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1339,8 +1355,8 @@ static struct clk_branch camss_csi0pix_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi0pix_clk",
> - .parent_names = (const char *[]){
> - "csi0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1356,8 +1372,8 @@ static struct clk_branch camss_csi0rdi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi0rdi_clk",
> - .parent_names = (const char *[]){
> - "csi0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1373,8 +1389,8 @@ static struct clk_branch camss_csi1_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi1_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1390,8 +1406,8 @@ static struct clk_branch camss_csi1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi1_clk",
> - .parent_names = (const char *[]){
> - "csi1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1407,8 +1423,8 @@ static struct clk_branch camss_csi1phy_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi1phy_clk",
> - .parent_names = (const char *[]){
> - "csi1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1424,8 +1440,8 @@ static struct clk_branch camss_csi1pix_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi1pix_clk",
> - .parent_names = (const char *[]){
> - "csi1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1441,8 +1457,8 @@ static struct clk_branch camss_csi1rdi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi1rdi_clk",
> - .parent_names = (const char *[]){
> - "csi1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1458,8 +1474,8 @@ static struct clk_branch camss_csi2_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi2_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1474,8 +1490,8 @@ static struct clk_branch camss_csi2_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi2_clk",
> - .parent_names = (const char *[]){
> - "csi2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi2_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1491,8 +1507,8 @@ static struct clk_branch camss_csi2phy_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi2phy_clk",
> - .parent_names = (const char *[]){
> - "csi2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi2_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1508,8 +1524,8 @@ static struct clk_branch camss_csi2pix_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi2pix_clk",
> - .parent_names = (const char *[]){
> - "csi2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi2_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1525,8 +1541,8 @@ static struct clk_branch camss_csi2rdi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi2rdi_clk",
> - .parent_names = (const char *[]){
> - "csi2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi2_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1542,8 +1558,8 @@ static struct clk_branch camss_csi3_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi3_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1558,8 +1574,8 @@ static struct clk_branch camss_csi3_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi3_clk",
> - .parent_names = (const char *[]){
> - "csi3_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi3_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1575,8 +1591,8 @@ static struct clk_branch camss_csi3phy_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi3phy_clk",
> - .parent_names = (const char *[]){
> - "csi3_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi3_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1592,8 +1608,8 @@ static struct clk_branch camss_csi3pix_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi3pix_clk",
> - .parent_names = (const char *[]){
> - "csi3_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi3_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1609,8 +1625,8 @@ static struct clk_branch camss_csi3rdi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi3rdi_clk",
> - .parent_names = (const char *[]){
> - "csi3_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi3_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1626,8 +1642,8 @@ static struct clk_branch camss_csi_vfe0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi_vfe0_clk",
> - .parent_names = (const char *[]){
> - "vfe0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vfe0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1643,8 +1659,8 @@ static struct clk_branch camss_csi_vfe1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_csi_vfe1_clk",
> - .parent_names = (const char *[]){
> - "vfe1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vfe1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1660,8 +1676,8 @@ static struct clk_branch camss_gp0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_gp0_clk",
> - .parent_names = (const char *[]){
> - "camss_gp0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_gp0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1677,8 +1693,8 @@ static struct clk_branch camss_gp1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_gp1_clk",
> - .parent_names = (const char *[]){
> - "camss_gp1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_gp1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1694,8 +1710,8 @@ static struct clk_branch camss_ispif_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_ispif_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1711,8 +1727,8 @@ static struct clk_branch camss_jpeg_jpeg0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_jpeg_jpeg0_clk",
> - .parent_names = (const char *[]){
> - "jpeg0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &jpeg0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1728,8 +1744,8 @@ static struct clk_branch camss_jpeg_jpeg1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_jpeg_jpeg1_clk",
> - .parent_names = (const char *[]){
> - "jpeg1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &jpeg1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1745,8 +1761,8 @@ static struct clk_branch camss_jpeg_jpeg2_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_jpeg_jpeg2_clk",
> - .parent_names = (const char *[]){
> - "jpeg2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &jpeg2_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1762,8 +1778,8 @@ static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_jpeg_jpeg_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1778,8 +1794,8 @@ static struct clk_branch camss_jpeg_jpeg_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_jpeg_jpeg_axi_clk",
> - .parent_names = (const char *[]){
> - "mmss_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_axi_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1794,8 +1810,8 @@ static struct clk_branch camss_mclk0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_mclk0_clk",
> - .parent_names = (const char *[]){
> - "mclk0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mclk0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1811,8 +1827,8 @@ static struct clk_branch camss_mclk1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_mclk1_clk",
> - .parent_names = (const char *[]){
> - "mclk1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mclk1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1828,8 +1844,8 @@ static struct clk_branch camss_mclk2_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_mclk2_clk",
> - .parent_names = (const char *[]){
> - "mclk2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mclk2_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1845,8 +1861,8 @@ static struct clk_branch camss_mclk3_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_mclk3_clk",
> - .parent_names = (const char *[]){
> - "mclk3_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mclk3_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1862,8 +1878,8 @@ static struct clk_branch camss_micro_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_micro_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1878,8 +1894,8 @@ static struct clk_branch camss_phy0_csi0phytimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_phy0_csi0phytimer_clk",
> - .parent_names = (const char *[]){
> - "csi0phytimer_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0phytimer_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1895,8 +1911,8 @@ static struct clk_branch camss_phy1_csi1phytimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_phy1_csi1phytimer_clk",
> - .parent_names = (const char *[]){
> - "csi1phytimer_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1phytimer_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1912,8 +1928,8 @@ static struct clk_branch camss_phy2_csi2phytimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_phy2_csi2phytimer_clk",
> - .parent_names = (const char *[]){
> - "csi2phytimer_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi2phytimer_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1929,8 +1945,8 @@ static struct clk_branch camss_top_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_top_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1946,8 +1962,8 @@ static struct clk_branch camss_vfe_cpp_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_vfe_cpp_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1963,8 +1979,8 @@ static struct clk_branch camss_vfe_cpp_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_vfe_cpp_clk",
> - .parent_names = (const char *[]){
> - "cpp_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &cpp_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1980,8 +1996,8 @@ static struct clk_branch camss_vfe_vfe0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_vfe_vfe0_clk",
> - .parent_names = (const char *[]){
> - "vfe0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vfe0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1997,8 +2013,8 @@ static struct clk_branch camss_vfe_vfe1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_vfe_vfe1_clk",
> - .parent_names = (const char *[]){
> - "vfe1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vfe1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2014,8 +2030,8 @@ static struct clk_branch camss_vfe_vfe_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_vfe_vfe_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2031,8 +2047,8 @@ static struct clk_branch camss_vfe_vfe_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "camss_vfe_vfe_axi_clk",
> - .parent_names = (const char *[]){
> - "mmss_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_axi_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2048,8 +2064,8 @@ static struct clk_branch mdss_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2065,8 +2081,8 @@ static struct clk_branch mdss_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_axi_clk",
> - .parent_names = (const char *[]){
> - "mmss_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_axi_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2082,8 +2098,8 @@ static struct clk_branch mdss_byte0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_byte0_clk",
> - .parent_names = (const char *[]){
> - "byte0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &byte0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2099,8 +2115,8 @@ static struct clk_branch mdss_byte1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_byte1_clk",
> - .parent_names = (const char *[]){
> - "byte1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &byte1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2116,8 +2132,8 @@ static struct clk_branch mdss_edpaux_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_edpaux_clk",
> - .parent_names = (const char *[]){
> - "edpaux_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &edpaux_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2133,8 +2149,8 @@ static struct clk_branch mdss_edplink_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_edplink_clk",
> - .parent_names = (const char *[]){
> - "edplink_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &edplink_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2150,8 +2166,8 @@ static struct clk_branch mdss_edppixel_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_edppixel_clk",
> - .parent_names = (const char *[]){
> - "edppixel_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &edppixel_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2167,8 +2183,8 @@ static struct clk_branch mdss_esc0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_esc0_clk",
> - .parent_names = (const char *[]){
> - "esc0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &esc0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2184,8 +2200,8 @@ static struct clk_branch mdss_esc1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_esc1_clk",
> - .parent_names = (const char *[]){
> - "esc1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &esc1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2201,8 +2217,8 @@ static struct clk_branch mdss_extpclk_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_extpclk_clk",
> - .parent_names = (const char *[]){
> - "extpclk_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &extpclk_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2218,8 +2234,8 @@ static struct clk_branch mdss_hdmi_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_hdmi_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2235,8 +2251,8 @@ static struct clk_branch mdss_hdmi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_hdmi_clk",
> - .parent_names = (const char *[]){
> - "hdmi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &hdmi_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2252,8 +2268,8 @@ static struct clk_branch mdss_mdp_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_mdp_clk",
> - .parent_names = (const char *[]){
> - "mdp_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mdp_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2269,8 +2285,8 @@ static struct clk_branch mdss_mdp_lut_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_mdp_lut_clk",
> - .parent_names = (const char *[]){
> - "mdp_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mdp_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2286,8 +2302,8 @@ static struct clk_branch mdss_pclk0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_pclk0_clk",
> - .parent_names = (const char *[]){
> - "pclk0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pclk0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2303,8 +2319,8 @@ static struct clk_branch mdss_pclk1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_pclk1_clk",
> - .parent_names = (const char *[]){
> - "pclk1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pclk1_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2320,8 +2336,8 @@ static struct clk_branch mdss_vsync_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mdss_vsync_clk",
> - .parent_names = (const char *[]){
> - "vsync_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vsync_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2337,8 +2353,8 @@ static struct clk_branch mmss_rbcpr_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmss_rbcpr_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2354,8 +2370,8 @@ static struct clk_branch mmss_rbcpr_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmss_rbcpr_clk",
> - .parent_names = (const char *[]){
> - "rbcpr_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &rbcpr_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2371,8 +2387,8 @@ static struct clk_branch mmss_misc_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmss_misc_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2388,8 +2404,8 @@ static struct clk_branch mmss_mmssnoc_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmss_mmssnoc_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2405,8 +2421,8 @@ static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmss_mmssnoc_bto_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2422,8 +2438,8 @@ static struct clk_branch mmss_mmssnoc_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmss_mmssnoc_axi_clk",
> - .parent_names = (const char *[]){
> - "mmss_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_axi_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> @@ -2439,8 +2455,8 @@ static struct clk_branch mmss_s0_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "mmss_s0_axi_clk",
> - .parent_names = (const char *[]){
> - "mmss_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_axi_clk_src.clkr.hw
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2456,8 +2472,8 @@ static struct clk_branch ocmemcx_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "ocmemcx_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2473,8 +2489,8 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "ocmemcx_ocmemnoc_clk",
> - .parent_names = (const char *[]){
> - "ocmemnoc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ocmemnoc_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2490,8 +2506,8 @@ static struct clk_branch oxili_ocmemgx_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "oxili_ocmemgx_clk",
> - .parent_names = (const char *[]){
> - "gfx3d_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gfx3d_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2507,8 +2523,8 @@ static struct clk_branch oxili_gfx3d_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "oxili_gfx3d_clk",
> - .parent_names = (const char *[]){
> - "gfx3d_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gfx3d_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2524,8 +2540,8 @@ static struct clk_branch oxili_rbbmtimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "oxili_rbbmtimer_clk",
> - .parent_names = (const char *[]){
> - "rbbmtimer_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &rbbmtimer_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2541,8 +2557,8 @@ static struct clk_branch oxilicx_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "oxilicx_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2558,8 +2574,8 @@ static struct clk_branch venus0_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "venus0_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2575,8 +2591,8 @@ static struct clk_branch venus0_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "venus0_axi_clk",
> - .parent_names = (const char *[]){
> - "mmss_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_axi_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2592,8 +2608,8 @@ static struct clk_branch venus0_core0_vcodec_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "venus0_core0_vcodec_clk",
> - .parent_names = (const char *[]){
> - "vcodec0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vcodec0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2609,8 +2625,8 @@ static struct clk_branch venus0_core1_vcodec_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "venus0_core1_vcodec_clk",
> - .parent_names = (const char *[]){
> - "vcodec0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vcodec0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2626,8 +2642,8 @@ static struct clk_branch venus0_ocmemnoc_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "venus0_ocmemnoc_clk",
> - .parent_names = (const char *[]){
> - "ocmemnoc_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ocmemnoc_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2643,8 +2659,8 @@ static struct clk_branch venus0_vcodec0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "venus0_vcodec0_clk",
> - .parent_names = (const char *[]){
> - "vcodec0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vcodec0_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2660,8 +2676,8 @@ static struct clk_branch vpu_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "vpu_ahb_clk",
> - .parent_names = (const char *[]){
> - "mmss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_ahb_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2677,8 +2693,8 @@ static struct clk_branch vpu_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "vpu_axi_clk",
> - .parent_names = (const char *[]){
> - "mmss_axi_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mmss_axi_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2694,8 +2710,8 @@ static struct clk_branch vpu_bus_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "vpu_bus_clk",
> - .parent_names = (const char *[]){
> - "vpu_bus_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vpu_bus_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2711,7 +2727,9 @@ static struct clk_branch vpu_cxo_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "vpu_cxo_clk",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "xo", .name = "xo_board" },
> + },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2726,8 +2744,8 @@ static struct clk_branch vpu_maple_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "vpu_maple_clk",
> - .parent_names = (const char *[]){
> - "maple_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &maple_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2743,8 +2761,8 @@ static struct clk_branch vpu_sleep_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "vpu_sleep_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = (const struct clk_parent_data[]){
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2760,8 +2778,8 @@ static struct clk_branch vpu_vdp_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "vpu_vdp_clk",
> - .parent_names = (const char *[]){
> - "vdp_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vdp_clk_src.clkr.hw
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device
2022-12-27 1:32 ` [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device Dmitry Baryshkov
@ 2022-12-27 12:08 ` Konrad Dybcio
2022-12-27 12:31 ` Dmitry Baryshkov
0 siblings, 1 reply; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 12:08 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Add clocks and clock-names nodes to the gcc device to bind clocks using
> the DT links.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Though - again at the end of reviewing - I noticed you could have
gone .index instead, like with qcs404.
Konrad
> arch/arm/boot/dts/qcom-apq8084.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
> index fe30abfff90a..815b6c53f7b8 100644
> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
> @@ -388,6 +388,24 @@ gcc: clock-controller@fc400000 {
> #reset-cells = <1>;
> #power-domain-cells = <1>;
> reg = <0xfc400000 0x4000>;
> + clocks = <&xo_board>,
> + <&sleep_clk>,
> + <0>, /* ufs */
> + <0>,
> + <0>,
> + <0>,
> + <0>, /* sata */
> + <0>,
> + <0>; /* pcie */
> + clock-names = "xo",
> + "sleep_clk",
> + "ufs_rx_symbol_0_clk_src",
> + "ufs_rx_symbol_1_clk_src",
> + "ufs_tx_symbol_0_clk_src",
> + "ufs_tx_symbol_1_clk_src",
> + "sata_asic0_clk",
> + "sata_rx_clk",
> + "pcie_pipe";
> };
>
> tcsr_mutex: hwlock@fd484000 {
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
2022-12-27 11:58 ` Konrad Dybcio
@ 2022-12-27 12:17 ` Dmitry Baryshkov
2022-12-27 12:19 ` Konrad Dybcio
0 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 12:17 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree
On Tue, 27 Dec 2022 at 13:58, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> > Add the GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for
> > the multimedia subsystem.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> I'm thinking whether it would maybe make sense to put 8974
> and 8084 clocks in a single driver.. They seem close to identical.
Unfortunately the bindings are quite different. So even if we pack
both gcc drivers into a single one, we'd still have to cope with
different numeric ids.
The only sensible solution that I have in mind is to have a common C
file, containing common clock definitions.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Konrad
> > drivers/clk/qcom/gcc-apq8084.c | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
> > index c26e222c78d4..7085d2ccae49 100644
> > --- a/drivers/clk/qcom/gcc-apq8084.c
> > +++ b/drivers/clk/qcom/gcc-apq8084.c
> > @@ -1382,6 +1382,19 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
> > },
> > };
> >
> > +static struct clk_regmap gcc_mmss_gpll0_clk_src = {
> > + .enable_reg = 0x1484,
> > + .enable_mask = BIT(26),
> > + .hw.init = &(struct clk_init_data){
> > + .name = "mmss_gpll0_vote",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &gpll0_vote.hw,
> > + },
> > + .num_parents = 1,
> > + .ops = &clk_branch_simple_ops,
> > + },
> > +};
> > +
> > static struct clk_branch gcc_bam_dma_ahb_clk = {
> > .halt_reg = 0x0d44,
> > .halt_check = BRANCH_HALT_VOTED,
> > @@ -3480,6 +3493,7 @@ static struct clk_regmap *gcc_apq8084_clocks[] = {
> > [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
> > [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
> > [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
> > + [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
> > };
> >
> > static struct gdsc *gcc_apq8084_gdscs[] = {
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
2022-12-27 12:17 ` Dmitry Baryshkov
@ 2022-12-27 12:19 ` Konrad Dybcio
0 siblings, 0 replies; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 12:19 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree
On 27.12.2022 13:17, Dmitry Baryshkov wrote:
> On Tue, 27 Dec 2022 at 13:58, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>>
>>
>> On 27.12.2022 02:32, Dmitry Baryshkov wrote:
>>> Add the GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for
>>> the multimedia subsystem.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>> I'm thinking whether it would maybe make sense to put 8974
>> and 8084 clocks in a single driver.. They seem close to identical.
>
> Unfortunately the bindings are quite different. So even if we pack
> both gcc drivers into a single one, we'd still have to cope with
> different numeric ids.
> The only sensible solution that I have in mind is to have a common C
> file, containing common clock definitions.
Right, let's forget it then.
Konrad
>
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>
>> Konrad
>>> drivers/clk/qcom/gcc-apq8084.c | 14 ++++++++++++++
>>> 1 file changed, 14 insertions(+)
>>>
>>> diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
>>> index c26e222c78d4..7085d2ccae49 100644
>>> --- a/drivers/clk/qcom/gcc-apq8084.c
>>> +++ b/drivers/clk/qcom/gcc-apq8084.c
>>> @@ -1382,6 +1382,19 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
>>> },
>>> };
>>>
>>> +static struct clk_regmap gcc_mmss_gpll0_clk_src = {
>>> + .enable_reg = 0x1484,
>>> + .enable_mask = BIT(26),
>>> + .hw.init = &(struct clk_init_data){
>>> + .name = "mmss_gpll0_vote",
>>> + .parent_hws = (const struct clk_hw*[]){
>>> + &gpll0_vote.hw,
>>> + },
>>> + .num_parents = 1,
>>> + .ops = &clk_branch_simple_ops,
>>> + },
>>> +};
>>> +
>>> static struct clk_branch gcc_bam_dma_ahb_clk = {
>>> .halt_reg = 0x0d44,
>>> .halt_check = BRANCH_HALT_VOTED,
>>> @@ -3480,6 +3493,7 @@ static struct clk_regmap *gcc_apq8084_clocks[] = {
>>> [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
>>> [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
>>> [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
>>> + [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
>>> };
>>>
>>> static struct gdsc *gcc_apq8084_gdscs[] = {
>
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 06/12] clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names
2022-12-27 11:55 ` Konrad Dybcio
@ 2022-12-27 12:19 ` Dmitry Baryshkov
0 siblings, 0 replies; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 12:19 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree
On Tue, 27 Dec 2022 at 13:55, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> > Convert the clock driver to specify parent data rather than parent
> > names, to actually bind using 'clock-names' specified in the DTS rather
> > than global clock names. Use parent_hws where possible to refer parent
> > clocks directly, skipping the lookup.
> >
> > Note, the system names for xo clocks were changed from "xo" to
> > "xo_board" to follow the example of other platforms. This switches the
> > clocks to use DT-provided "xo_board" clock instead of manually
> > registered "xo" clock and allows us to drop qcom_cc_register_board_clk()
> > call from the driver at some point.
>
> xo_board: xo_board {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <19200000>;
> };
>
> This needs to be fixed (clock-output-names and fix node name) or
> dt_binding_check will be angry, similar for sleep.
It has been there for quite some time. I think we should change all
*xo_board/sleep_clk clocks to proper node names + clock-output-names,
but this is a separate step.
>
>
> With that:
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Konrad
> >
> > In the same way change the looked up system "sleep_clk_src" clock to
> > "sleep_clk", which is registered from DT.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/clk/qcom/gcc-apq8084.c | 730 +++++++++++++++++----------------
> > 1 file changed, 371 insertions(+), 359 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
> > index 05a68f645115..c26e222c78d4 100644
> > --- a/drivers/clk/qcom/gcc-apq8084.c
> > +++ b/drivers/clk/qcom/gcc-apq8084.c
> > @@ -46,7 +46,9 @@ static struct clk_pll gpll0 = {
> > .status_bit = 17,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "gpll0",
> > - .parent_names = (const char *[]){ "xo" },
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "xo", .name = "xo_board",
> > + },
> > .num_parents = 1,
> > .ops = &clk_pll_ops,
> > },
> > @@ -57,7 +59,9 @@ static struct clk_regmap gpll0_vote = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gpll0_vote",
> > - .parent_names = (const char *[]){ "gpll0" },
> > + .parent_hws = (const struct clk_hw*[]){
> > + &gpll0.clkr.hw,
> > + },
> > .num_parents = 1,
> > .ops = &clk_pll_vote_ops,
> > },
> > @@ -73,7 +77,9 @@ static struct clk_pll gpll1 = {
> > .status_bit = 17,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "gpll1",
> > - .parent_names = (const char *[]){ "xo" },
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "xo", .name = "xo_board",
> > + },
> > .num_parents = 1,
> > .ops = &clk_pll_ops,
> > },
> > @@ -84,7 +90,9 @@ static struct clk_regmap gpll1_vote = {
> > .enable_mask = BIT(1),
> > .hw.init = &(struct clk_init_data){
> > .name = "gpll1_vote",
> > - .parent_names = (const char *[]){ "gpll1" },
> > + .parent_hws = (const struct clk_hw*[]){
> > + &gpll1.clkr.hw,
> > + },
> > .num_parents = 1,
> > .ops = &clk_pll_vote_ops,
> > },
> > @@ -100,7 +108,9 @@ static struct clk_pll gpll4 = {
> > .status_bit = 17,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "gpll4",
> > - .parent_names = (const char *[]){ "xo" },
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "xo", .name = "xo_board",
> > + },
> > .num_parents = 1,
> > .ops = &clk_pll_ops,
> > },
> > @@ -111,7 +121,9 @@ static struct clk_regmap gpll4_vote = {
> > .enable_mask = BIT(4),
> > .hw.init = &(struct clk_init_data){
> > .name = "gpll4_vote",
> > - .parent_names = (const char *[]){ "gpll4" },
> > + .parent_hws = (const struct clk_hw*[]){
> > + &gpll4.clkr.hw,
> > + },
> > .num_parents = 1,
> > .ops = &clk_pll_vote_ops,
> > },
> > @@ -122,9 +134,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
> > { P_GPLL0, 1 }
> > };
> >
> > -static const char * const gcc_xo_gpll0[] = {
> > - "xo",
> > - "gpll0_vote",
> > +static const struct clk_parent_data gcc_xo_gpll0[] = {
> > + { .fw_name = "xo", .name = "xo_board" },
> > + { .hw = &gpll0_vote.hw },
> > };
> >
> > static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> > @@ -133,10 +145,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> > { P_GPLL4, 5 }
> > };
> >
> > -static const char * const gcc_xo_gpll0_gpll4[] = {
> > - "xo",
> > - "gpll0_vote",
> > - "gpll4_vote",
> > +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> > + { .fw_name = "xo", .name = "xo_board" },
> > + { .hw = &gpll0_vote.hw },
> > + { .hw = &gpll4_vote.hw },
> > };
> >
> > static const struct parent_map gcc_xo_sata_asic0_map[] = {
> > @@ -144,9 +156,9 @@ static const struct parent_map gcc_xo_sata_asic0_map[] = {
> > { P_SATA_ASIC0_CLK, 2 }
> > };
> >
> > -static const char * const gcc_xo_sata_asic0[] = {
> > - "xo",
> > - "sata_asic0_clk",
> > +static const struct clk_parent_data gcc_xo_sata_asic0[] = {
> > + { .fw_name = "xo", .name = "xo_board" },
> > + { .fw_name = "sata_asic0_clk", .name = "sata_asic0_clk" },
> > };
> >
> > static const struct parent_map gcc_xo_sata_rx_map[] = {
> > @@ -154,9 +166,9 @@ static const struct parent_map gcc_xo_sata_rx_map[] = {
> > { P_SATA_RX_CLK, 2}
> > };
> >
> > -static const char * const gcc_xo_sata_rx[] = {
> > - "xo",
> > - "sata_rx_clk",
> > +static const struct clk_parent_data gcc_xo_sata_rx[] = {
> > + { .fw_name = "xo", .name = "xo_board" },
> > + { .fw_name = "sata_rx_clk", .name = "sata_rx_clk" },
> > };
> >
> > static const struct parent_map gcc_xo_pcie_map[] = {
> > @@ -164,9 +176,9 @@ static const struct parent_map gcc_xo_pcie_map[] = {
> > { P_PCIE_0_1_PIPE_CLK, 2 }
> > };
> >
> > -static const char * const gcc_xo_pcie[] = {
> > - "xo",
> > - "pcie_pipe",
> > +static const struct clk_parent_data gcc_xo_pcie[] = {
> > + { .fw_name = "xo", .name = "xo_board" },
> > + { .fw_name = "pcie_pipe", .name = "pcie_pipe" },
> > };
> >
> > static const struct parent_map gcc_xo_pcie_sleep_map[] = {
> > @@ -174,9 +186,9 @@ static const struct parent_map gcc_xo_pcie_sleep_map[] = {
> > { P_SLEEP_CLK, 6 }
> > };
> >
> > -static const char * const gcc_xo_pcie_sleep[] = {
> > - "xo",
> > - "sleep_clk_src",
> > +static const struct clk_parent_data gcc_xo_pcie_sleep[] = {
> > + { .fw_name = "xo", .name = "xo_board" },
> > + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> > };
> >
> > static struct clk_rcg2 config_noc_clk_src = {
> > @@ -185,7 +197,7 @@ static struct clk_rcg2 config_noc_clk_src = {
> > .parent_map = gcc_xo_gpll0_map,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "config_noc_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -197,7 +209,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
> > .parent_map = gcc_xo_gpll0_map,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "periph_noc_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -209,7 +221,7 @@ static struct clk_rcg2 system_noc_clk_src = {
> > .parent_map = gcc_xo_gpll0_map,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "system_noc_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -230,7 +242,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
> > .freq_tbl = ftbl_gcc_ufs_axi_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "ufs_axi_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -249,7 +261,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
> > .freq_tbl = ftbl_gcc_usb30_master_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "usb30_master_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -268,7 +280,25 @@ static struct clk_rcg2 usb30_sec_master_clk_src = {
> > .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "usb30_sec_master_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > + .ops = &clk_rcg2_ops,
> > + },
> > +};
> > +
> > +static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
> > + F(125000000, P_GPLL0, 1, 5, 24),
> > + { }
> > +};
> > +
> > +static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
> > + .cmd_rcgr = 0x1be8,
> > + .hid_width = 5,
> > + .parent_map = gcc_xo_gpll0_map,
> > + .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
> > + .clkr.hw.init = &(struct clk_init_data){
> > + .name = "usb30_sec_mock_utmi_clk_src",
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -281,8 +311,8 @@ static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb30_sec_mock_utmi_clk",
> > - .parent_names = (const char *[]){
> > - "usb30_sec_mock_utmi_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb30_sec_mock_utmi_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -298,8 +328,8 @@ static struct clk_branch gcc_usb30_sec_sleep_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb30_sec_sleep_clk",
> > - .parent_names = (const char *[]){
> > - "sleep_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "sleep_clk", .name = "sleep_clk",
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -321,7 +351,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup1_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -346,7 +376,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup1_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -359,7 +389,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup2_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -373,7 +403,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup2_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -386,7 +416,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup3_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -400,7 +430,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup3_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -413,7 +443,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup4_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -427,7 +457,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup4_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -440,7 +470,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup5_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -454,7 +484,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup5_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -467,7 +497,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup6_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -481,7 +511,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_qup6_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -514,7 +544,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_uart1_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -528,7 +558,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_uart2_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -542,7 +572,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_uart3_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -556,7 +586,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_uart4_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -570,7 +600,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_uart5_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -584,7 +614,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp1_uart6_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -597,7 +627,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup1_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -611,7 +641,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup1_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -624,7 +654,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup2_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -638,7 +668,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup2_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -651,7 +681,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup3_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -665,7 +695,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup3_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -678,7 +708,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup4_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -692,7 +722,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup4_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -705,7 +735,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup5_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -719,7 +749,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup5_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -732,7 +762,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup6_i2c_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -746,7 +776,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_qup6_spi_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -760,7 +790,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_uart1_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -774,7 +804,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_uart2_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -788,7 +818,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_uart3_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -802,7 +832,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_uart4_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -816,7 +846,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_uart5_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -830,7 +860,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "blsp2_uart6_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -851,7 +881,7 @@ static struct clk_rcg2 ce1_clk_src = {
> > .freq_tbl = ftbl_gcc_ce1_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "ce1_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -872,7 +902,7 @@ static struct clk_rcg2 ce2_clk_src = {
> > .freq_tbl = ftbl_gcc_ce2_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "ce2_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -893,7 +923,7 @@ static struct clk_rcg2 ce3_clk_src = {
> > .freq_tbl = ftbl_gcc_ce3_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "ce3_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -914,7 +944,7 @@ static struct clk_rcg2 gp1_clk_src = {
> > .freq_tbl = ftbl_gcc_gp_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "gp1_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -928,7 +958,7 @@ static struct clk_rcg2 gp2_clk_src = {
> > .freq_tbl = ftbl_gcc_gp_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "gp2_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -942,7 +972,7 @@ static struct clk_rcg2 gp3_clk_src = {
> > .freq_tbl = ftbl_gcc_gp_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "gp3_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -961,7 +991,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
> > .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "pcie_0_aux_clk_src",
> > - .parent_names = gcc_xo_pcie_sleep,
> > + .parent_data = gcc_xo_pcie_sleep,
> > .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -975,7 +1005,7 @@ static struct clk_rcg2 pcie_1_aux_clk_src = {
> > .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "pcie_1_aux_clk_src",
> > - .parent_names = gcc_xo_pcie_sleep,
> > + .parent_data = gcc_xo_pcie_sleep,
> > .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -994,7 +1024,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
> > .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "pcie_0_pipe_clk_src",
> > - .parent_names = gcc_xo_pcie,
> > + .parent_data = gcc_xo_pcie,
> > .num_parents = ARRAY_SIZE(gcc_xo_pcie),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1007,7 +1037,7 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = {
> > .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "pcie_1_pipe_clk_src",
> > - .parent_names = gcc_xo_pcie,
> > + .parent_data = gcc_xo_pcie,
> > .num_parents = ARRAY_SIZE(gcc_xo_pcie),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1025,7 +1055,7 @@ static struct clk_rcg2 pdm2_clk_src = {
> > .freq_tbl = ftbl_gcc_pdm2_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "pdm2_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1045,7 +1075,7 @@ static struct clk_rcg2 sata_asic0_clk_src = {
> > .freq_tbl = ftbl_gcc_sata_asic0_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "sata_asic0_clk_src",
> > - .parent_names = gcc_xo_sata_asic0,
> > + .parent_data = gcc_xo_sata_asic0,
> > .num_parents = ARRAY_SIZE(gcc_xo_sata_asic0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1065,7 +1095,7 @@ static struct clk_rcg2 sata_pmalive_clk_src = {
> > .freq_tbl = ftbl_gcc_sata_pmalive_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "sata_pmalive_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1085,7 +1115,7 @@ static struct clk_rcg2 sata_rx_clk_src = {
> > .freq_tbl = ftbl_gcc_sata_rx_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "sata_rx_clk_src",
> > - .parent_names = gcc_xo_sata_rx,
> > + .parent_data = gcc_xo_sata_rx,
> > .num_parents = ARRAY_SIZE(gcc_xo_sata_rx),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1103,7 +1133,7 @@ static struct clk_rcg2 sata_rx_oob_clk_src = {
> > .freq_tbl = ftbl_gcc_sata_rx_oob_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "sata_rx_oob_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1130,7 +1160,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "sdcc1_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0_gpll4,
> > + .parent_data = gcc_xo_gpll0_gpll4,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
> > .ops = &clk_rcg2_floor_ops,
> > },
> > @@ -1144,7 +1174,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "sdcc2_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_floor_ops,
> > },
> > @@ -1158,7 +1188,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "sdcc3_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_floor_ops,
> > },
> > @@ -1172,7 +1202,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
> > .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "sdcc4_apps_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_floor_ops,
> > },
> > @@ -1191,7 +1221,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
> > .freq_tbl = ftbl_gcc_tsif_ref_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "tsif_ref_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1209,25 +1239,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
> > .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "usb30_mock_utmi_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > - .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > - .ops = &clk_rcg2_ops,
> > - },
> > -};
> > -
> > -static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
> > - F(125000000, P_GPLL0, 1, 5, 24),
> > - { }
> > -};
> > -
> > -static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
> > - .cmd_rcgr = 0x1be8,
> > - .hid_width = 5,
> > - .parent_map = gcc_xo_gpll0_map,
> > - .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
> > - .clkr.hw.init = &(struct clk_init_data){
> > - .name = "usb30_sec_mock_utmi_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1245,7 +1257,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
> > .freq_tbl = ftbl_gcc_usb_hs_system_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "usb_hs_system_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1268,9 +1280,9 @@ static struct clk_rcg2 usb_hsic_clk_src = {
> > .freq_tbl = ftbl_gcc_usb_hsic_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "usb_hsic_clk_src",
> > - .parent_names = (const char *[]){
> > - "xo",
> > - "gpll1_vote",
> > + .parent_data = (const struct clk_parent_data[]){
> > + { .fw_name = "xo", .name = "xo_board" },
> > + { .hw = &gpll1_vote.hw },
> > },
> > .num_parents = 2,
> > .ops = &clk_rcg2_ops,
> > @@ -1290,9 +1302,9 @@ static struct clk_rcg2 usb_hsic_ahb_clk_src = {
> > .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "usb_hsic_ahb_clk_src",
> > - .parent_names = (const char *[]){
> > - "xo",
> > - "gpll1_vote",
> > + .parent_data = (const struct clk_parent_data[]){
> > + { .fw_name = "xo", .name = "xo_board" },
> > + { .hw = &gpll1_vote.hw },
> > },
> > .num_parents = 2,
> > .ops = &clk_rcg2_ops,
> > @@ -1311,29 +1323,12 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
> > .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "usb_hsic_io_cal_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > };
> >
> > -static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
> > - .halt_reg = 0x1f14,
> > - .clkr = {
> > - .enable_reg = 0x1f14,
> > - .enable_mask = BIT(0),
> > - .hw.init = &(struct clk_init_data){
> > - .name = "gcc_usb_hsic_mock_utmi_clk",
> > - .parent_names = (const char *[]){
> > - "usb_hsic_mock_utmi_clk_src",
> > - },
> > - .num_parents = 1,
> > - .flags = CLK_SET_RATE_PARENT,
> > - .ops = &clk_branch2_ops,
> > - },
> > - },
> > -};
> > -
> > static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
> > F(60000000, P_GPLL0, 10, 0, 0),
> > { }
> > @@ -1346,12 +1341,29 @@ static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
> > .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "usb_hsic_mock_utmi_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > };
> >
> > +static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
> > + .halt_reg = 0x1f14,
> > + .clkr = {
> > + .enable_reg = 0x1f14,
> > + .enable_mask = BIT(0),
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gcc_usb_hsic_mock_utmi_clk",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb_hsic_mock_utmi_clk_src.clkr.hw,
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + .ops = &clk_branch2_ops,
> > + },
> > + },
> > +};
> > +
> > static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
> > F(75000000, P_GPLL0, 8, 0, 0),
> > { }
> > @@ -1364,7 +1376,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = {
> > .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
> > .clkr.hw.init = &(struct clk_init_data){
> > .name = "usb_hsic_system_clk_src",
> > - .parent_names = gcc_xo_gpll0,
> > + .parent_data = gcc_xo_gpll0,
> > .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> > .ops = &clk_rcg2_ops,
> > },
> > @@ -1378,8 +1390,8 @@ static struct clk_branch gcc_bam_dma_ahb_clk = {
> > .enable_mask = BIT(12),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_bam_dma_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -1395,8 +1407,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
> > .enable_mask = BIT(17),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -1411,8 +1423,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup1_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup1_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1428,8 +1440,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup1_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup1_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup1_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1445,8 +1457,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup2_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup2_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1462,8 +1474,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup2_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup2_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup2_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1479,8 +1491,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup3_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup3_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1496,8 +1508,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup3_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup3_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup3_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1513,8 +1525,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup4_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup4_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1530,8 +1542,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup4_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup4_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup4_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1547,8 +1559,8 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup5_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup5_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1564,8 +1576,8 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup5_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup5_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup5_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1581,8 +1593,8 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup6_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup6_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1598,8 +1610,8 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_qup6_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_qup6_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_qup6_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1615,8 +1627,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_uart1_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_uart1_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_uart1_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1632,8 +1644,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_uart2_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_uart2_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_uart2_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1649,8 +1661,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_uart3_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_uart3_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_uart3_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1666,8 +1678,8 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_uart4_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_uart4_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_uart4_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1683,8 +1695,8 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_uart5_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_uart5_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_uart5_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1700,8 +1712,8 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp1_uart6_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp1_uart6_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp1_uart6_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1718,8 +1730,8 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
> > .enable_mask = BIT(15),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -1734,8 +1746,8 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup1_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup1_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1751,8 +1763,8 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup1_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup1_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup1_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1768,8 +1780,8 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup2_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup2_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1785,8 +1797,8 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup2_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup2_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup2_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1802,8 +1814,8 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup3_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup3_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1819,8 +1831,8 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup3_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup3_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup3_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1836,8 +1848,8 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup4_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup4_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1853,8 +1865,8 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup4_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup4_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup4_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1870,8 +1882,8 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup5_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup5_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1887,8 +1899,8 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup5_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup5_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup5_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1904,8 +1916,8 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup6_i2c_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup6_i2c_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1921,8 +1933,8 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_qup6_spi_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_qup6_spi_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_qup6_spi_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1938,8 +1950,8 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_uart1_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_uart1_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_uart1_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1955,8 +1967,8 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_uart2_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_uart2_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_uart2_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1972,8 +1984,8 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_uart3_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_uart3_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_uart3_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -1989,8 +2001,8 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_uart4_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_uart4_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_uart4_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2006,8 +2018,8 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_uart5_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_uart5_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_uart5_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2023,8 +2035,8 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_blsp2_uart6_apps_clk",
> > - .parent_names = (const char *[]){
> > - "blsp2_uart6_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &blsp2_uart6_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2041,8 +2053,8 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
> > .enable_mask = BIT(10),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_boot_rom_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2058,8 +2070,8 @@ static struct clk_branch gcc_ce1_ahb_clk = {
> > .enable_mask = BIT(3),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ce1_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2075,8 +2087,8 @@ static struct clk_branch gcc_ce1_axi_clk = {
> > .enable_mask = BIT(4),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ce1_axi_clk",
> > - .parent_names = (const char *[]){
> > - "system_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &system_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2092,8 +2104,8 @@ static struct clk_branch gcc_ce1_clk = {
> > .enable_mask = BIT(5),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ce1_clk",
> > - .parent_names = (const char *[]){
> > - "ce1_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &ce1_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2110,8 +2122,8 @@ static struct clk_branch gcc_ce2_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ce2_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2127,8 +2139,8 @@ static struct clk_branch gcc_ce2_axi_clk = {
> > .enable_mask = BIT(1),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ce2_axi_clk",
> > - .parent_names = (const char *[]){
> > - "system_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &system_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2144,8 +2156,8 @@ static struct clk_branch gcc_ce2_clk = {
> > .enable_mask = BIT(2),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ce2_clk",
> > - .parent_names = (const char *[]){
> > - "ce2_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &ce2_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2162,8 +2174,8 @@ static struct clk_branch gcc_ce3_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ce3_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2179,8 +2191,8 @@ static struct clk_branch gcc_ce3_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ce3_axi_clk",
> > - .parent_names = (const char *[]){
> > - "system_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &system_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2196,8 +2208,8 @@ static struct clk_branch gcc_ce3_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ce3_clk",
> > - .parent_names = (const char *[]){
> > - "ce3_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &ce3_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2213,8 +2225,8 @@ static struct clk_branch gcc_gp1_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_gp1_clk",
> > - .parent_names = (const char *[]){
> > - "gp1_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &gp1_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2230,8 +2242,8 @@ static struct clk_branch gcc_gp2_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_gp2_clk",
> > - .parent_names = (const char *[]){
> > - "gp2_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &gp2_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2247,8 +2259,8 @@ static struct clk_branch gcc_gp3_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_gp3_clk",
> > - .parent_names = (const char *[]){
> > - "gp3_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &gp3_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2264,8 +2276,8 @@ static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ocmem_noc_cfg_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2280,8 +2292,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_0_aux_clk",
> > - .parent_names = (const char *[]){
> > - "pcie_0_aux_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &pcie_0_aux_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2297,8 +2309,8 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_0_cfg_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2314,8 +2326,8 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_0_mstr_axi_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2331,8 +2343,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_0_pipe_clk",
> > - .parent_names = (const char *[]){
> > - "pcie_0_pipe_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .hw = &pcie_0_pipe_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2348,8 +2360,8 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_0_slv_axi_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2365,8 +2377,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_1_aux_clk",
> > - .parent_names = (const char *[]){
> > - "pcie_1_aux_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &pcie_1_aux_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2382,8 +2394,8 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_1_cfg_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2399,8 +2411,8 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_1_mstr_axi_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2416,8 +2428,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_1_pipe_clk",
> > - .parent_names = (const char *[]){
> > - "pcie_1_pipe_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .hw = &pcie_1_pipe_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2433,8 +2445,8 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pcie_1_slv_axi_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2450,8 +2462,8 @@ static struct clk_branch gcc_pdm2_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pdm2_clk",
> > - .parent_names = (const char *[]){
> > - "pdm2_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &pdm2_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2467,8 +2479,8 @@ static struct clk_branch gcc_pdm_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_pdm_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2483,8 +2495,8 @@ static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_periph_noc_usb_hsic_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "usb_hsic_ahb_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb_hsic_ahb_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2501,8 +2513,8 @@ static struct clk_branch gcc_prng_ahb_clk = {
> > .enable_mask = BIT(13),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_prng_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2517,8 +2529,8 @@ static struct clk_branch gcc_sata_asic0_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sata_asic0_clk",
> > - .parent_names = (const char *[]){
> > - "sata_asic0_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &sata_asic0_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2534,8 +2546,8 @@ static struct clk_branch gcc_sata_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sata_axi_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2551,8 +2563,8 @@ static struct clk_branch gcc_sata_cfg_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sata_cfg_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2568,8 +2580,8 @@ static struct clk_branch gcc_sata_pmalive_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sata_pmalive_clk",
> > - .parent_names = (const char *[]){
> > - "sata_pmalive_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &sata_pmalive_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2585,8 +2597,8 @@ static struct clk_branch gcc_sata_rx_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sata_rx_clk",
> > - .parent_names = (const char *[]){
> > - "sata_rx_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &sata_rx_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2602,8 +2614,8 @@ static struct clk_branch gcc_sata_rx_oob_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sata_rx_oob_clk",
> > - .parent_names = (const char *[]){
> > - "sata_rx_oob_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &sata_rx_oob_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2619,8 +2631,8 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc1_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2635,8 +2647,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc1_apps_clk",
> > - .parent_names = (const char *[]){
> > - "sdcc1_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &sdcc1_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2652,8 +2664,8 @@ static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc1_cdccal_ff_clk",
> > - .parent_names = (const char *[]){
> > - "xo"
> > + .parent_data = (const struct clk_parent_data[]){
> > + { .fw_name = "xo", .name = "xo_board" }
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2668,8 +2680,8 @@ static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc1_cdccal_sleep_clk",
> > - .parent_names = (const char *[]){
> > - "sleep_clk_src"
> > + .parent_data = (const struct clk_parent_data[]){
> > + { .fw_name = "sleep_clk", .name = "sleep_clk" }
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2684,8 +2696,8 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc2_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2700,8 +2712,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc2_apps_clk",
> > - .parent_names = (const char *[]){
> > - "sdcc2_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &sdcc2_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2717,8 +2729,8 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc3_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2733,8 +2745,8 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc3_apps_clk",
> > - .parent_names = (const char *[]){
> > - "sdcc3_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &sdcc3_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2750,8 +2762,8 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc4_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2766,8 +2778,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sdcc4_apps_clk",
> > - .parent_names = (const char *[]){
> > - "sdcc4_apps_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &sdcc4_apps_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2783,8 +2795,8 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sys_noc_ufs_axi_clk",
> > - .parent_names = (const char *[]){
> > - "ufs_axi_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &ufs_axi_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2800,8 +2812,8 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sys_noc_usb3_axi_clk",
> > - .parent_names = (const char *[]){
> > - "usb30_master_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb30_master_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2817,8 +2829,8 @@ static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_sys_noc_usb3_sec_axi_clk",
> > - .parent_names = (const char *[]){
> > - "usb30_sec_master_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb30_sec_master_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2834,8 +2846,8 @@ static struct clk_branch gcc_tsif_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_tsif_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -2850,8 +2862,8 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_tsif_inactivity_timers_clk",
> > - .parent_names = (const char *[]){
> > - "sleep_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "sleep_clk", .name = "sleep_clk",
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2867,8 +2879,8 @@ static struct clk_branch gcc_tsif_ref_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_tsif_ref_clk",
> > - .parent_names = (const char *[]){
> > - "tsif_ref_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &tsif_ref_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2884,8 +2896,8 @@ static struct clk_branch gcc_ufs_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ufs_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "config_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &config_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2901,8 +2913,8 @@ static struct clk_branch gcc_ufs_axi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ufs_axi_clk",
> > - .parent_names = (const char *[]){
> > - "ufs_axi_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &ufs_axi_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2918,8 +2930,8 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ufs_rx_cfg_clk",
> > - .parent_names = (const char *[]){
> > - "ufs_axi_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &ufs_axi_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2935,8 +2947,8 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ufs_rx_symbol_0_clk",
> > - .parent_names = (const char *[]){
> > - "ufs_rx_symbol_0_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2952,8 +2964,8 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ufs_rx_symbol_1_clk",
> > - .parent_names = (const char *[]){
> > - "ufs_rx_symbol_1_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2969,8 +2981,8 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ufs_tx_cfg_clk",
> > - .parent_names = (const char *[]){
> > - "ufs_axi_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &ufs_axi_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -2986,8 +2998,8 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ufs_tx_symbol_0_clk",
> > - .parent_names = (const char *[]){
> > - "ufs_tx_symbol_0_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -3003,8 +3015,8 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_ufs_tx_symbol_1_clk",
> > - .parent_names = (const char *[]){
> > - "ufs_tx_symbol_1_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "ufs_tx_symbol_1_clk_src", .name = "ufs_tx_symbol_1_clk_src",
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -3020,8 +3032,8 @@ static struct clk_branch gcc_usb2a_phy_sleep_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb2a_phy_sleep_clk",
> > - .parent_names = (const char *[]){
> > - "sleep_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "sleep_clk", .name = "sleep_clk",
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -3036,8 +3048,8 @@ static struct clk_branch gcc_usb2b_phy_sleep_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb2b_phy_sleep_clk",
> > - .parent_names = (const char *[]){
> > - "sleep_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "sleep_clk", .name = "sleep_clk",
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -3052,8 +3064,8 @@ static struct clk_branch gcc_usb30_master_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb30_master_clk",
> > - .parent_names = (const char *[]){
> > - "usb30_master_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb30_master_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -3069,8 +3081,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb30_sec_master_clk",
> > - .parent_names = (const char *[]){
> > - "usb30_sec_master_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb30_sec_master_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -3086,8 +3098,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb30_mock_utmi_clk",
> > - .parent_names = (const char *[]){
> > - "usb30_mock_utmi_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb30_mock_utmi_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -3103,8 +3115,8 @@ static struct clk_branch gcc_usb30_sleep_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb30_sleep_clk",
> > - .parent_names = (const char *[]){
> > - "sleep_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "sleep_clk", .name = "sleep_clk",
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -3119,8 +3131,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb_hs_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -3135,8 +3147,8 @@ static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb_hs_inactivity_timers_clk",
> > - .parent_names = (const char *[]){
> > - "sleep_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "sleep_clk", .name = "sleep_clk",
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -3152,8 +3164,8 @@ static struct clk_branch gcc_usb_hs_system_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb_hs_system_clk",
> > - .parent_names = (const char *[]){
> > - "usb_hs_system_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb_hs_system_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -3169,8 +3181,8 @@ static struct clk_branch gcc_usb_hsic_ahb_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb_hsic_ahb_clk",
> > - .parent_names = (const char *[]){
> > - "periph_noc_clk_src",
> > + .parent_hws = (const struct clk_hw*[]) {
> > + &periph_noc_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -3185,8 +3197,8 @@ static struct clk_branch gcc_usb_hsic_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb_hsic_clk",
> > - .parent_names = (const char *[]){
> > - "usb_hsic_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb_hsic_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -3202,8 +3214,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb_hsic_io_cal_clk",
> > - .parent_names = (const char *[]){
> > - "usb_hsic_io_cal_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb_hsic_io_cal_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
> > @@ -3219,8 +3231,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb_hsic_io_cal_sleep_clk",
> > - .parent_names = (const char *[]){
> > - "sleep_clk_src",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "sleep_clk", .name = "sleep_clk",
> > },
> > .num_parents = 1,
> > .ops = &clk_branch2_ops,
> > @@ -3235,8 +3247,8 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
> > .enable_mask = BIT(0),
> > .hw.init = &(struct clk_init_data){
> > .name = "gcc_usb_hsic_system_clk",
> > - .parent_names = (const char *[]){
> > - "usb_hsic_system_clk_src",
> > + .parent_hws = (const struct clk_hw*[]){
> > + &usb_hsic_system_clk_src.clkr.hw,
> > },
> > .num_parents = 1,
> > .flags = CLK_SET_RATE_PARENT,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device
2022-12-27 12:08 ` Konrad Dybcio
@ 2022-12-27 12:31 ` Dmitry Baryshkov
2022-12-27 13:04 ` Konrad Dybcio
0 siblings, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-27 12:31 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree
On Tue, 27 Dec 2022 at 14:08, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> > Add clocks and clock-names nodes to the gcc device to bind clocks using
> > the DT links.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Though - again at the end of reviewing - I noticed you could have
> gone .index instead, like with qcs404.
QCS404 driver was in a good shape, so I doubt there will be any
significant changes for the bindings. On the other hand the apq8084 is
in such a flux state, that I can easily imagine getting additional
clock parents and/or removing existing parents. This can better be
coped with by using the clock-names instead of indices. For example,
see my comment regarding the pcie pipe clocks. I fear that apq8084 was
not seriously touched for the last 5 years. And even back in those
days not everything was plumbed together. None of MMCC (and thus
display, camera, venus), SATA, PCIe are present in the
qcom-apq8084.dtsi.
>
> Konrad
>
> > arch/arm/boot/dts/qcom-apq8084.dtsi | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
> > index fe30abfff90a..815b6c53f7b8 100644
> > --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
> > +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
> > @@ -388,6 +388,24 @@ gcc: clock-controller@fc400000 {
> > #reset-cells = <1>;
> > #power-domain-cells = <1>;
> > reg = <0xfc400000 0x4000>;
> > + clocks = <&xo_board>,
> > + <&sleep_clk>,
> > + <0>, /* ufs */
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>, /* sata */
> > + <0>,
> > + <0>; /* pcie */
> > + clock-names = "xo",
> > + "sleep_clk",
> > + "ufs_rx_symbol_0_clk_src",
> > + "ufs_rx_symbol_1_clk_src",
> > + "ufs_tx_symbol_0_clk_src",
> > + "ufs_tx_symbol_1_clk_src",
> > + "sata_asic0_clk",
> > + "sata_rx_clk",
> > + "pcie_pipe";
> > };
> >
> > tcsr_mutex: hwlock@fd484000 {
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device
2022-12-27 12:31 ` Dmitry Baryshkov
@ 2022-12-27 13:04 ` Konrad Dybcio
0 siblings, 0 replies; 32+ messages in thread
From: Konrad Dybcio @ 2022-12-27 13:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree
On 27.12.2022 13:31, Dmitry Baryshkov wrote:
> On Tue, 27 Dec 2022 at 14:08, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>>
>>
>> On 27.12.2022 02:32, Dmitry Baryshkov wrote:
>>> Add clocks and clock-names nodes to the gcc device to bind clocks using
>>> the DT links.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>
>> Though - again at the end of reviewing - I noticed you could have
>> gone .index instead, like with qcs404.
>
> QCS404 driver was in a good shape, so I doubt there will be any
> significant changes for the bindings. On the other hand the apq8084 is
> in such a flux state, that I can easily imagine getting additional
> clock parents and/or removing existing parents. This can better be
> coped with by using the clock-names instead of indices. For example,
> see my comment regarding the pcie pipe clocks. I fear that apq8084 was
> not seriously touched for the last 5 years. And even back in those
> days not everything was plumbed together. None of MMCC (and thus
> display, camera, venus), SATA, PCIe are present in the
> qcom-apq8084.dtsi.
Sure, sounds reasonable!
Konrad
>
>>
>> Konrad
>>
>>> arch/arm/boot/dts/qcom-apq8084.dtsi | 18 ++++++++++++++++++
>>> 1 file changed, 18 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
>>> index fe30abfff90a..815b6c53f7b8 100644
>>> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
>>> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
>>> @@ -388,6 +388,24 @@ gcc: clock-controller@fc400000 {
>>> #reset-cells = <1>;
>>> #power-domain-cells = <1>;
>>> reg = <0xfc400000 0x4000>;
>>> + clocks = <&xo_board>,
>>> + <&sleep_clk>,
>>> + <0>, /* ufs */
>>> + <0>,
>>> + <0>,
>>> + <0>,
>>> + <0>, /* sata */
>>> + <0>,
>>> + <0>; /* pcie */
>>> + clock-names = "xo",
>>> + "sleep_clk",
>>> + "ufs_rx_symbol_0_clk_src",
>>> + "ufs_rx_symbol_1_clk_src",
>>> + "ufs_tx_symbol_0_clk_src",
>>> + "ufs_tx_symbol_1_clk_src",
>>> + "sata_asic0_clk",
>>> + "sata_rx_clk",
>>> + "pcie_pipe";
>>> };
>>>
>>> tcsr_mutex: hwlock@fd484000 {
>
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names
2022-12-27 1:32 ` [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names Dmitry Baryshkov
@ 2022-12-28 10:30 ` Krzysztof Kozlowski
2022-12-28 20:23 ` Dmitry Baryshkov
0 siblings, 1 reply; 32+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-28 10:30 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27/12/2022 02:32, Dmitry Baryshkov wrote:
> Define clock/clock-names properties of the GCC device node to be used
> on APQ8084 platform.
>
> Note: the driver uses a single pcie_pipe clock, however most probably
> there are two pipe clocks, one from each of PCIe QMP PHYs.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../bindings/clock/qcom,gcc-apq8084.yaml | 43 +++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> index 8ade176c24f4..02a856f14fbe 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> @@ -25,6 +25,30 @@ properties:
> compatible:
> const: qcom,gcc-apq8084
>
> + clocks:
> + items:
> + - description: XO source
> + - description: Sleep clock source
> + - description: UFS RX symbol 0 clock
> + - description: UFS RX symbol 1 clock
> + - description: UFS TX symbol 0 clock
> + - description: UFS TX symbol 1 clock
> + - description: SATA ASIC0 clock
> + - description: SATA RX clock
> + - description: PCIe PIPE clock
> +
> + clock-names:
> + items:
> + - const: xo
> + - const: sleep_clk
> + - const: ufs_rx_symbol_0_clk_src
> + - const: ufs_rx_symbol_1_clk_src
> + - const: ufs_tx_symbol_0_clk_src
> + - const: ufs_tx_symbol_1_clk_src
> + - const: sata_asic0_clk
> + - const: sata_rx_clk
> + - const: pcie_pipe
> +
> required:
> - compatible
>
> @@ -38,5 +62,24 @@ examples:
> #clock-cells = <1>;
> #reset-cells = <1>;
> #power-domain-cells = <1>;
> +
> + clocks = <&xo_board>,
> + <&sleep_clk>,
> + <&ufsphy 0>,
No IDs available yet?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 02/12] dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC
2022-12-27 1:32 ` [RFC PATCH 02/12] dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
@ 2022-12-28 10:30 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-28 10:30 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27/12/2022 02:32, Dmitry Baryshkov wrote:
> Add GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the
> multimedia subsystem.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 03/12] dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084
2022-12-27 1:32 ` [RFC PATCH 03/12] dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084 Dmitry Baryshkov
@ 2022-12-28 10:31 ` Krzysztof Kozlowski
2022-12-28 20:24 ` Dmitry Baryshkov
0 siblings, 1 reply; 32+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-28 10:31 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 27/12/2022 02:32, Dmitry Baryshkov wrote:
> Define clock/clock-names properties of the MMCC device node to be used
> on APQ8084 platform.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/clock/qcom,mmcc.yaml | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
> index e6d17426e903..fd926df80c64 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
> @@ -137,6 +137,46 @@ allOf:
> - const: edp_link_clk
> - const: edp_vco_div
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,mmcc-apq8084
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Board XO source
> + - description: Board sleep source
> + - description: MMSS GPLL0 voted clock
> + - description: GPLL0 clock
> + - description: GPLL0 voted clock
> + - description: GPLL1 clock
> + - description: DSI phy instance 0 dsi clock
> + - description: DSI phy instance 0 byte clock
> + - description: DSI phy instance 1 dsi clock
> + - description: DSI phy instance 1 byte clock
> + - description: HDMI phy PLL clock
> + - description: eDP phy PLL link clock
> + - description: eDP phy PLL vco clock
This looks like exceeding constraints set in top-level (max 10).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names
2022-12-28 10:30 ` Krzysztof Kozlowski
@ 2022-12-28 20:23 ` Dmitry Baryshkov
0 siblings, 0 replies; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-28 20:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 28/12/2022 12:30, Krzysztof Kozlowski wrote:
> On 27/12/2022 02:32, Dmitry Baryshkov wrote:
>> Define clock/clock-names properties of the GCC device node to be used
>> on APQ8084 platform.
>>
>> Note: the driver uses a single pcie_pipe clock, however most probably
>> there are two pipe clocks, one from each of PCIe QMP PHYs.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> .../bindings/clock/qcom,gcc-apq8084.yaml | 43 +++++++++++++++++++
>> 1 file changed, 43 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
>> index 8ade176c24f4..02a856f14fbe 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
>> @@ -25,6 +25,30 @@ properties:
>> compatible:
>> const: qcom,gcc-apq8084
>>
>> + clocks:
>> + items:
>> + - description: XO source
>> + - description: Sleep clock source
>> + - description: UFS RX symbol 0 clock
>> + - description: UFS RX symbol 1 clock
>> + - description: UFS TX symbol 0 clock
>> + - description: UFS TX symbol 1 clock
>> + - description: SATA ASIC0 clock
>> + - description: SATA RX clock
>> + - description: PCIe PIPE clock
>> +
>> + clock-names:
>> + items:
>> + - const: xo
>> + - const: sleep_clk
>> + - const: ufs_rx_symbol_0_clk_src
>> + - const: ufs_rx_symbol_1_clk_src
>> + - const: ufs_tx_symbol_0_clk_src
>> + - const: ufs_tx_symbol_1_clk_src
>> + - const: sata_asic0_clk
>> + - const: sata_rx_clk
>> + - const: pcie_pipe
>> +
>> required:
>> - compatible
>>
>> @@ -38,5 +62,24 @@ examples:
>> #clock-cells = <1>;
>> #reset-cells = <1>;
>> #power-domain-cells = <1>;
>> +
>> + clocks = <&xo_board>,
>> + <&sleep_clk>,
>> + <&ufsphy 0>,
>
> No IDs available yet?
No. I didn't add IDs to the UFS symbol patchset. And anyway apq8084
seems to use different amount of UFS symbol clocks (4, while other
platforms use just 3).
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [RFC PATCH 03/12] dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084
2022-12-28 10:31 ` Krzysztof Kozlowski
@ 2022-12-28 20:24 ` Dmitry Baryshkov
0 siblings, 0 replies; 32+ messages in thread
From: Dmitry Baryshkov @ 2022-12-28 20:24 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 28/12/2022 12:31, Krzysztof Kozlowski wrote:
> On 27/12/2022 02:32, Dmitry Baryshkov wrote:
>> Define clock/clock-names properties of the MMCC device node to be used
>> on APQ8084 platform.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> .../devicetree/bindings/clock/qcom,mmcc.yaml | 40 +++++++++++++++++++
>> 1 file changed, 40 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
>> index e6d17426e903..fd926df80c64 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
>> @@ -137,6 +137,46 @@ allOf:
>> - const: edp_link_clk
>> - const: edp_vco_div
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,mmcc-apq8084
>> + then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: Board XO source
>> + - description: Board sleep source
>> + - description: MMSS GPLL0 voted clock
>> + - description: GPLL0 clock
>> + - description: GPLL0 voted clock
>> + - description: GPLL1 clock
>> + - description: DSI phy instance 0 dsi clock
>> + - description: DSI phy instance 0 byte clock
>> + - description: DSI phy instance 1 dsi clock
>> + - description: DSI phy instance 1 byte clock
>> + - description: HDMI phy PLL clock
>> + - description: eDP phy PLL link clock
>> + - description: eDP phy PLL vco clock
>
> This looks like exceeding constraints set in top-level (max 10).
Ack, I'll expand it for v2.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2022-12-28 20:24 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names Dmitry Baryshkov
2022-12-28 10:30 ` Krzysztof Kozlowski
2022-12-28 20:23 ` Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 02/12] dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
2022-12-28 10:30 ` Krzysztof Kozlowski
2022-12-27 1:32 ` [RFC PATCH 03/12] dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084 Dmitry Baryshkov
2022-12-28 10:31 ` Krzysztof Kozlowski
2022-12-28 20:24 ` Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 04/12] clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-12-27 11:48 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 05/12] clk: qcom: gcc-apq8084: move PLL clocks up Dmitry Baryshkov
2022-12-27 11:49 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 06/12] clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-12-27 11:55 ` Konrad Dybcio
2022-12-27 12:19 ` Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
2022-12-27 11:58 ` Konrad Dybcio
2022-12-27 12:17 ` Dmitry Baryshkov
2022-12-27 12:19 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 08/12] clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-12-27 12:00 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 09/12] clk: qcom: mmcc-apq8084: move clock parent tables down Dmitry Baryshkov
2022-12-27 12:00 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 10/12] clk: qcom: mmcc-apq8084: remove spdm clocks Dmitry Baryshkov
2022-12-27 12:01 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 11/12] clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-12-27 12:07 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device Dmitry Baryshkov
2022-12-27 12:08 ` Konrad Dybcio
2022-12-27 12:31 ` Dmitry Baryshkov
2022-12-27 13:04 ` Konrad Dybcio
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