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From: Christoph Hellwig <hch@lst.de>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Prabhakar <prabhakar.csengg@gmail.com>,
	"Conor.Dooley" <conor.dooley@microchip.com>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Heiko Stübner" <heiko@sntech.de>, guoren <guoren@kernel.org>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>,
	"open list" <linux-kernel@vger.kernel.org>,
	devicetree@vger.kernel.org,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Nathan Chancellor" <nathan@kernel.org>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Tsukasa OI" <research_trasio@irq.a4lg.com>,
	"Jisheng Zhang" <jszhang@kernel.org>,
	"Mayuresh Chitale" <mchitale@ventanamicro.com>,
	"Christoph Hellwig" <hch@lst.de>, "Will Deacon" <will@kernel.org>
Subject: Re: [RFC PATCH v6 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management
Date: Tue, 10 Jan 2023 08:01:44 +0100	[thread overview]
Message-ID: <20230110070144.GG10289@lst.de> (raw)
In-Reply-To: <45d6eb0c-cbe3-4a83-aa12-3483638473ae@app.fastmail.com>

On Mon, Jan 09, 2023 at 01:59:12PM +0100, Arnd Bergmann wrote:
> I had another look at the arm64 side, which (like the zicbom
> variant) uses 'clean' on dma_sync_single_for_device(DMA_FROM_DEVICE),
> as that has changed not that long ago, see
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c50f11c6196f45c92ca48b16a5071615d4ae0572

which IIRC has been reverted recently.

> I'm still not sure what the correct set of operations has
> to be, but nothing in that patch description sounds ISA
> or even microarchitecture specific.

Nothing is ISA specific, and the only micro architecture related thing
is if the specific core can speculate memory accesses.  See the table
in arch/arc/mm/dma.c for details.

And as commented on the arm64 patch I really hate architectures getting
creative here, as I'd much prefer to move the choice of primitives to
the core DMA code and just provide helpers to invalidate/writeback/
writeback+invalidate from the architectures eventually.

WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Prabhakar <prabhakar.csengg@gmail.com>,
	"Conor.Dooley" <conor.dooley@microchip.com>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Heiko Stübner" <heiko@sntech.de>, guoren <guoren@kernel.org>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>,
	"open list" <linux-kernel@vger.kernel.org>,
	devicetree@vger.kernel.org,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Nathan Chancellor" <nathan@kernel.org>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Tsukasa OI" <research_trasio@irq.a4lg.com>,
	"Jisheng Zhang" <jszhang@kernel.org>,
	"Mayuresh Chitale" <mchitale@ventanamicro.com>,
	"Christoph Hellwig" <hch@lst.de>, "Will Deacon" <will@kernel.org>
Subject: Re: [RFC PATCH v6 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management
Date: Tue, 10 Jan 2023 08:01:44 +0100	[thread overview]
Message-ID: <20230110070144.GG10289@lst.de> (raw)
In-Reply-To: <45d6eb0c-cbe3-4a83-aa12-3483638473ae@app.fastmail.com>

On Mon, Jan 09, 2023 at 01:59:12PM +0100, Arnd Bergmann wrote:
> I had another look at the arm64 side, which (like the zicbom
> variant) uses 'clean' on dma_sync_single_for_device(DMA_FROM_DEVICE),
> as that has changed not that long ago, see
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c50f11c6196f45c92ca48b16a5071615d4ae0572

which IIRC has been reverted recently.

> I'm still not sure what the correct set of operations has
> to be, but nothing in that patch description sounds ISA
> or even microarchitecture specific.

Nothing is ISA specific, and the only micro architecture related thing
is if the specific core can speculate memory accesses.  See the table
in arch/arc/mm/dma.c for details.

And as commented on the arm64 patch I really hate architectures getting
creative here, as I'd much prefer to move the choice of primitives to
the core DMA code and just provide helpers to invalidate/writeback/
writeback+invalidate from the architectures eventually.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-01-10  7:02 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-06 18:55 [PATCH v6 0/6] RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support for AX45MP Prabhakar
2023-01-06 18:55 ` Prabhakar
2023-01-06 18:55 ` [RFC PATCH v6 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management Prabhakar
2023-01-06 18:55   ` Prabhakar
2023-01-06 22:31   ` Arnd Bergmann
2023-01-06 23:29     ` Conor Dooley
2023-01-06 23:29       ` Conor Dooley
2023-01-07 21:52       ` Arnd Bergmann
2023-01-07 21:52         ` Arnd Bergmann
2023-01-07 22:21         ` Conor Dooley
2023-01-07 22:21           ` Conor Dooley
2023-01-08 16:37           ` Conor Dooley
2023-01-08 16:37             ` Conor Dooley
2023-01-07 22:10     ` Lad, Prabhakar
2023-01-07 22:10       ` Lad, Prabhakar
2023-01-08  0:07       ` Arnd Bergmann
2023-01-08  0:07         ` Arnd Bergmann
2023-01-09 12:03         ` Lad, Prabhakar
2023-01-09 12:03           ` Lad, Prabhakar
2023-01-09 12:59           ` Arnd Bergmann
2023-01-09 12:59             ` Arnd Bergmann
2023-01-09 13:27             ` Conor Dooley
2023-01-09 13:27               ` Conor Dooley
2023-01-10  7:01             ` Christoph Hellwig [this message]
2023-01-10  7:01               ` Christoph Hellwig
2023-01-10 15:03               ` Arnd Bergmann
2023-01-10 15:03                 ` Arnd Bergmann
2023-01-10 15:11                 ` Will Deacon
2023-01-10 15:11                   ` Will Deacon
2023-01-13  5:48                 ` Christoph Hellwig
2023-01-13  5:48                   ` Christoph Hellwig
2023-01-20 17:04                   ` Arnd Bergmann
2023-01-20 17:04                     ` Arnd Bergmann
2023-01-21 14:37                     ` Christoph Hellwig
2023-01-21 14:37                       ` Christoph Hellwig
2023-01-21 19:30                       ` Arnd Bergmann
2023-01-21 19:30                         ` Arnd Bergmann
2023-01-22  7:27                         ` Christoph Hellwig
2023-01-22  7:27                           ` Christoph Hellwig
2023-01-22 11:04                           ` Arnd Bergmann
2023-01-22 11:04                             ` Arnd Bergmann
2023-01-23 14:46                             ` Christoph Hellwig
2023-01-23 14:46                               ` Christoph Hellwig
2023-01-06 23:47   ` Conor Dooley
2023-01-06 23:47     ` Conor Dooley
2023-01-07 22:36     ` Lad, Prabhakar
2023-01-07 22:36       ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-01-06 18:55   ` Prabhakar
2023-01-06 18:55 ` [PATCH v6 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-01-06 18:55   ` Prabhakar
2023-01-06 21:44   ` Conor Dooley
2023-01-06 21:44     ` Conor Dooley
2023-01-06 18:55 ` [PATCH v6 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-01-06 18:55   ` Prabhakar
2023-01-06 21:53   ` Conor Dooley
2023-01-06 21:53     ` Conor Dooley
2023-01-07 20:43     ` Lad, Prabhakar
2023-01-07 20:43       ` Lad, Prabhakar
2023-01-09 12:15       ` Geert Uytterhoeven
2023-01-09 12:15         ` Geert Uytterhoeven
2023-01-09 13:14         ` Lad, Prabhakar
2023-01-09 13:14           ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-01-06 18:55   ` Prabhakar
2023-01-07  0:09   ` Conor Dooley
2023-01-07  0:09     ` Conor Dooley
2023-01-07 20:49     ` Lad, Prabhakar
2023-01-07 20:49       ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-01-06 18:55   ` Prabhakar
2023-01-06 23:49   ` Conor Dooley
2023-01-06 23:49     ` Conor Dooley

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