From: Marc Zyngier <maz@kernel.org> To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Alexandru Elisei <alexandru.elisei@arm.com>, Andre Przywara <andre.przywara@arm.com>, Chase Conklin <chase.conklin@arm.com>, Christoffer Dall <christoffer.dall@arm.com>, Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>, Jintack Lim <jintack@cs.columbia.edu>, Russell King <rmk+kernel@armlinux.org.uk>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Oliver Upton <oliver.upton@linux.dev>, Zenghui Yu <yuzenghui@huawei.com> Subject: [PATCH v7 39/68] KVM: arm64: nv: Set a handler for the system instruction traps Date: Thu, 12 Jan 2023 19:18:58 +0000 [thread overview] Message-ID: <20230112191927.1814989-40-maz@kernel.org> (raw) In-Reply-To: <20230112191927.1814989-1-maz@kernel.org> When HCR.NV bit is set, execution of the EL2 translation regime address aranslation instructions and TLB maintenance instructions are trapped to EL2. In addition, execution of the EL1 translation regime address aranslation instructions and TLB maintenance instructions that are only accessible from EL2 and above are trapped to EL2. In these cases, ESR_EL2.EC will be set to 0x18. Rework the system instruction emulation framework to handle potentially all system instruction traps other than MSR/MRS instructions. Those system instructions would be AT and TLBI instructions controlled by HCR_EL2.NV, AT, and TTLB bits. Signed-off-by: Jintack Lim <jintack.lim@linaro.org> [maz: squashed two patches together, redispatched various bits around] Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 47 +++++++++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 23c457cbccda..9ab90791e849 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1853,10 +1853,6 @@ static bool access_spsr_el2(struct kvm_vcpu *vcpu, * guest... */ static const struct sys_reg_desc sys_reg_descs[] = { - { SYS_DESC(SYS_DC_ISW), access_dcsw }, - { SYS_DESC(SYS_DC_CSW), access_dcsw }, - { SYS_DESC(SYS_DC_CISW), access_dcsw }, - DBG_BCR_BVR_WCR_WVR_EL1(0), DBG_BCR_BVR_WCR_WVR_EL1(1), { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, @@ -2331,6 +2327,12 @@ static const struct sys_reg_desc sys_reg_descs[] = { EL2_REG(SP_EL2, NULL, reset_unknown, 0), }; +static struct sys_reg_desc sys_insn_descs[] = { + { SYS_DESC(SYS_DC_ISW), access_dcsw }, + { SYS_DESC(SYS_DC_CSW), access_dcsw }, + { SYS_DESC(SYS_DC_CISW), access_dcsw }, +}; + static bool trap_dbgdidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -3015,6 +3017,24 @@ static bool emulate_sys_reg(struct kvm_vcpu *vcpu, return false; } +static int emulate_sys_instr(struct kvm_vcpu *vcpu, struct sys_reg_params *p) +{ + const struct sys_reg_desc *r; + + /* Search from the system instruction table. */ + r = find_reg(p, sys_insn_descs, ARRAY_SIZE(sys_insn_descs)); + + if (likely(r)) { + perform_access(vcpu, p, r); + } else { + kvm_err("Unsupported guest sys instruction at: %lx\n", + *vcpu_pc(vcpu)); + print_sys_reg_instr(p); + kvm_inject_undefined(vcpu); + } + return 1; +} + /** * kvm_reset_sys_regs - sets system registers to reset value * @vcpu: The VCPU pointer @@ -3032,7 +3052,8 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) } /** - * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access + * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction + * trap on a guest execution * @vcpu: The VCPU pointer */ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) @@ -3046,12 +3067,19 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) params = esr_sys64_to_params(esr); params.regval = vcpu_get_reg(vcpu, Rt); - if (!emulate_sys_reg(vcpu, ¶ms)) + /* System register? */ + if (params.Op0 == 2 || params.Op0 == 3) { + if (!emulate_sys_reg(vcpu, ¶ms)) + return 1; + + if (!params.is_write) + vcpu_set_reg(vcpu, Rt, params.regval); + return 1; + } - if (!params.is_write) - vcpu_set_reg(vcpu, Rt, params.regval); - return 1; + /* Hints, PSTATE (Op0 == 0) and System instructions (Op0 == 1) */ + return emulate_sys_instr(vcpu, ¶ms); } /****************************************************************************** @@ -3483,6 +3511,7 @@ int kvm_sys_reg_table_init(void) valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); + valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); if (!valid) return -EINVAL; -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org> To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Alexandru Elisei <alexandru.elisei@arm.com>, Andre Przywara <andre.przywara@arm.com>, Chase Conklin <chase.conklin@arm.com>, Christoffer Dall <christoffer.dall@arm.com>, Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>, Jintack Lim <jintack@cs.columbia.edu>, Russell King <rmk+kernel@armlinux.org.uk>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Oliver Upton <oliver.upton@linux.dev>, Zenghui Yu <yuzenghui@huawei.com> Subject: [PATCH v7 39/68] KVM: arm64: nv: Set a handler for the system instruction traps Date: Thu, 12 Jan 2023 19:18:58 +0000 [thread overview] Message-ID: <20230112191927.1814989-40-maz@kernel.org> (raw) In-Reply-To: <20230112191927.1814989-1-maz@kernel.org> When HCR.NV bit is set, execution of the EL2 translation regime address aranslation instructions and TLB maintenance instructions are trapped to EL2. In addition, execution of the EL1 translation regime address aranslation instructions and TLB maintenance instructions that are only accessible from EL2 and above are trapped to EL2. In these cases, ESR_EL2.EC will be set to 0x18. Rework the system instruction emulation framework to handle potentially all system instruction traps other than MSR/MRS instructions. Those system instructions would be AT and TLBI instructions controlled by HCR_EL2.NV, AT, and TTLB bits. Signed-off-by: Jintack Lim <jintack.lim@linaro.org> [maz: squashed two patches together, redispatched various bits around] Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 47 +++++++++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 23c457cbccda..9ab90791e849 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1853,10 +1853,6 @@ static bool access_spsr_el2(struct kvm_vcpu *vcpu, * guest... */ static const struct sys_reg_desc sys_reg_descs[] = { - { SYS_DESC(SYS_DC_ISW), access_dcsw }, - { SYS_DESC(SYS_DC_CSW), access_dcsw }, - { SYS_DESC(SYS_DC_CISW), access_dcsw }, - DBG_BCR_BVR_WCR_WVR_EL1(0), DBG_BCR_BVR_WCR_WVR_EL1(1), { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, @@ -2331,6 +2327,12 @@ static const struct sys_reg_desc sys_reg_descs[] = { EL2_REG(SP_EL2, NULL, reset_unknown, 0), }; +static struct sys_reg_desc sys_insn_descs[] = { + { SYS_DESC(SYS_DC_ISW), access_dcsw }, + { SYS_DESC(SYS_DC_CSW), access_dcsw }, + { SYS_DESC(SYS_DC_CISW), access_dcsw }, +}; + static bool trap_dbgdidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -3015,6 +3017,24 @@ static bool emulate_sys_reg(struct kvm_vcpu *vcpu, return false; } +static int emulate_sys_instr(struct kvm_vcpu *vcpu, struct sys_reg_params *p) +{ + const struct sys_reg_desc *r; + + /* Search from the system instruction table. */ + r = find_reg(p, sys_insn_descs, ARRAY_SIZE(sys_insn_descs)); + + if (likely(r)) { + perform_access(vcpu, p, r); + } else { + kvm_err("Unsupported guest sys instruction at: %lx\n", + *vcpu_pc(vcpu)); + print_sys_reg_instr(p); + kvm_inject_undefined(vcpu); + } + return 1; +} + /** * kvm_reset_sys_regs - sets system registers to reset value * @vcpu: The VCPU pointer @@ -3032,7 +3052,8 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) } /** - * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access + * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction + * trap on a guest execution * @vcpu: The VCPU pointer */ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) @@ -3046,12 +3067,19 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) params = esr_sys64_to_params(esr); params.regval = vcpu_get_reg(vcpu, Rt); - if (!emulate_sys_reg(vcpu, ¶ms)) + /* System register? */ + if (params.Op0 == 2 || params.Op0 == 3) { + if (!emulate_sys_reg(vcpu, ¶ms)) + return 1; + + if (!params.is_write) + vcpu_set_reg(vcpu, Rt, params.regval); + return 1; + } - if (!params.is_write) - vcpu_set_reg(vcpu, Rt, params.regval); - return 1; + /* Hints, PSTATE (Op0 == 0) and System instructions (Op0 == 1) */ + return emulate_sys_instr(vcpu, ¶ms); } /****************************************************************************** @@ -3483,6 +3511,7 @@ int kvm_sys_reg_table_init(void) valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); + valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); if (!valid) return -EINVAL; -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-01-12 19:27 UTC|newest] Thread overview: 138+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-12 19:18 [PATCH v7 00/68] KVM: arm64: ARMv8.3/8.4 Nested Virtualization support Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 01/68] arm64: Add ARM64_HAS_NESTED_VIRT cpufeature Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 02/68] KVM: arm64: nv: Introduce nested virtualization VCPU feature Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 03/68] KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 04/68] KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 05/68] KVM: arm64: nv: Add EL2 system registers to vcpu context Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 06/68] KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 07/68] KVM: arm64: nv: Handle HCR_EL2.NV system register traps Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 08/68] KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 09/68] KVM: arm64: nv: Support virtual EL2 exceptions Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 10/68] KVM: arm64: nv: Inject HVC exceptions to the virtual EL2 Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 11/68] KVM: arm64: nv: Handle trapped ERET from " Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 12/68] KVM: arm64: nv: Add non-VHE-EL2->EL1 translation helpers Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 13/68] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg() Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 14/68] KVM: arm64: nv: Handle SPSR_EL2 specially Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 15/68] KVM: arm64: nv: Handle HCR_EL2.E2H specially Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 16/68] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 17/68] KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 18/68] KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 19/68] KVM: arm64: nv: Add accessors for SPSR_EL1, ELR_EL1 and VBAR_EL1 from " Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 20/68] KVM: arm64: nv: Trap CPACR_EL1 access in " Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 21/68] KVM: arm64: nv: Handle PSCI call via smc from the guest Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 22/68] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 23/68] KVM: arm64: nv: Respect virtual CPTR_EL2.{TFP,FPEN} settings Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 24/68] KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 25/68] KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 26/68] KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 27/68] KVM: arm64: nv: Allow a sysreg to be hidden from userspace only Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 28/68] KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2 Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 29/68] KVM: arm64: nv: Forward debug traps to the nested guest Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 30/68] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 31/68] KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2 changes Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 32/68] KVM: arm64: nv: Filter out unsupported features from ID regs Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 33/68] KVM: arm64: nv: Hide RAS from nested guests Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 34/68] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 35/68] KVM: arm64: nv: Implement nested Stage-2 page table walk logic Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 36/68] KVM: arm64: nv: Handle shadow stage 2 page faults Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 37/68] KVM: arm64: nv: Restrict S2 RD/WR permissions to match the guest's Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 38/68] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier [this message] 2023-01-12 19:18 ` [PATCH v7 39/68] KVM: arm64: nv: Set a handler for the system instruction traps Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 40/68] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 41/68] KVM: arm64: nv: Trap and emulate TLBI " Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 42/68] KVM: arm64: nv: Fold guest's HCR_EL2 configuration into the host's Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 43/68] KVM: arm64: nv: arch_timer: Support hyp timer emulation Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 44/68] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 45/68] KVM: arm64: nv: Load timer before the GIC Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 46/68] KVM: arm64: nv: Nested GICv3 Support Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 47/68] KVM: arm64: nv: Don't load the GICv4 context on entering a nested guest Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 48/68] KVM: arm64: nv: vgic: Emulate the HW bit in software Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 49/68] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 50/68] KVM: arm64: nv: Implement maintenance interrupt forwarding Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 51/68] KVM: arm64: nv: Deal with broken VGIC on maintenance interrupt delivery Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 52/68] KVM: arm64: nv: Add nested GICv3 tracepoints Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 53/68] KVM: arm64: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 54/68] KVM: arm64: nv: Add handling of FEAT_TTL TLB invalidation Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 55/68] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 56/68] KVM: arm64: nv: Tag shadow S2 entries with nested level Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 57/68] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 58/68] KVM: arm64: nv: Map VNCR-capable registers to a separate page Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 59/68] KVM: arm64: nv: Move nested vgic state into the sysreg file Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 60/68] KVM: arm64: Add FEAT_NV2 cpu feature Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 61/68] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 62/68] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 63/68] KVM: arm64: nv: Allocate VNCR page when required Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 64/68] KVM: arm64: nv: Enable ARMv8.4-NV support Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 65/68] KVM: arm64: nv: Fast-track 'InHost' exception returns Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 66/68] KVM: arm64: nv: Fast-track EL1 TLBIs for VHE guests Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 67/68] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 68/68] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV is on Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier
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