From: Marc Zyngier <maz@kernel.org> To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Alexandru Elisei <alexandru.elisei@arm.com>, Andre Przywara <andre.przywara@arm.com>, Chase Conklin <chase.conklin@arm.com>, Christoffer Dall <christoffer.dall@arm.com>, Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>, Jintack Lim <jintack@cs.columbia.edu>, Russell King <rmk+kernel@armlinux.org.uk>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Oliver Upton <oliver.upton@linux.dev>, Zenghui Yu <yuzenghui@huawei.com> Subject: [PATCH v7 58/68] KVM: arm64: nv: Map VNCR-capable registers to a separate page Date: Thu, 12 Jan 2023 19:19:17 +0000 [thread overview] Message-ID: <20230112191927.1814989-59-maz@kernel.org> (raw) In-Reply-To: <20230112191927.1814989-1-maz@kernel.org> With ARMv8.4-NV, registers that can be directly accessed in memory by the guest have to live at architected offsets in a special page. Let's annotate the sysreg enum to reflect the offset at which they are in this page, whith a little twist: If running on HW that doesn't have the ARMv8.4-NV feature, or even a VM that doesn't use NV, we store all the system registers in the usual sys_regs array. The only difference with the pre-8.4 situation is that VNCR-capable registers are at a "similar" offset as in the VNCR page (we can compute the actual offset at compile time), and that the sys_regs array is both bigger and sparse. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/include/asm/kvm_host.h | 104 ++++++++++++++++++++---------- arch/arm64/tools/cpucaps | 1 + 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 4a71cb1442dd..deabf860a3c5 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -26,6 +26,7 @@ #include <asm/fpsimd.h> #include <asm/kvm.h> #include <asm/kvm_asm.h> +#include <asm/vncr_mapping.h> #define __KVM_HAVE_ARCH_INTC_INITIALIZED @@ -290,31 +291,32 @@ struct kvm_vcpu_fault_info { u64 disr_el1; /* Deferred [SError] Status Register */ }; +/* + * VNCR() just places the VNCR_capable registers in the enum after + * __VNCR_START__, and the value (after correction) to be an 8-byte offset + * from the VNCR base. As we don't require the enum to be otherwise ordered, + * we need the terrible hack below to ensure that we correctly size the + * sys_regs array, no matter what. + * + * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful + * treasure trove of bit hacks: + * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax + */ +#define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) +#define VNCR(r) \ + __before_##r, \ + r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ + __after_##r = __MAX__(__before_##r - 1, r) + enum vcpu_sysreg { __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ MPIDR_EL1, /* MultiProcessor Affinity Register */ CSSELR_EL1, /* Cache Size Selection Register */ - SCTLR_EL1, /* System Control Register */ - ACTLR_EL1, /* Auxiliary Control Register */ - CPACR_EL1, /* Coprocessor Access Control */ - ZCR_EL1, /* SVE Control */ - TTBR0_EL1, /* Translation Table Base Register 0 */ - TTBR1_EL1, /* Translation Table Base Register 1 */ - TCR_EL1, /* Translation Control Register */ - ESR_EL1, /* Exception Syndrome Register */ - AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ - AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ - FAR_EL1, /* Fault Address Register */ - MAIR_EL1, /* Memory Attribute Indirection Register */ - VBAR_EL1, /* Vector Base Address Register */ - CONTEXTIDR_EL1, /* Context ID Register */ TPIDR_EL0, /* Thread ID, User R/W */ TPIDRRO_EL0, /* Thread ID, User R/O */ TPIDR_EL1, /* Thread ID, Privileged */ - AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ CNTKCTL_EL1, /* Timer Control Register (EL1) */ PAR_EL1, /* Physical Address Register */ - MDSCR_EL1, /* Monitor Debug System Control Register */ MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ OSLSR_EL1, /* OS Lock Status Register */ DISR_EL1, /* Deferred Interrupt Status Register */ @@ -345,20 +347,9 @@ enum vcpu_sysreg { APGAKEYLO_EL1, APGAKEYHI_EL1, - ELR_EL1, - SP_EL1, - SPSR_EL1, - - CNTVOFF_EL2, - CNTV_CVAL_EL0, - CNTV_CTL_EL0, - CNTP_CVAL_EL0, - CNTP_CTL_EL0, - /* Memory Tagging Extension registers */ RGSR_EL1, /* Random Allocation Tag Seed Register */ GCR_EL1, /* Tag Control Register */ - TFSR_EL1, /* Tag Fault Status Register (EL1) */ TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ /* 32bit specific registers. */ @@ -368,20 +359,14 @@ enum vcpu_sysreg { DBGVCR32_EL2, /* Debug Vector Catch Register */ /* EL2 registers */ - VPIDR_EL2, /* Virtualization Processor ID Register */ - VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */ SCTLR_EL2, /* System Control Register (EL2) */ ACTLR_EL2, /* Auxiliary Control Register (EL2) */ - HCR_EL2, /* Hypervisor Configuration Register */ MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ - HSTR_EL2, /* Hypervisor System Trap Register */ HACR_EL2, /* Hypervisor Auxiliary Control Register */ TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ TCR_EL2, /* Translation Control Register (EL2) */ - VTTBR_EL2, /* Virtualization Translation Table Base Register */ - VTCR_EL2, /* Virtualization Translation Control Register */ SPSR_EL2, /* EL2 saved program status register */ ELR_EL2, /* EL2 exception link register */ AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ @@ -394,7 +379,6 @@ enum vcpu_sysreg { VBAR_EL2, /* Vector Base Address Register (EL2) */ RVBAR_EL2, /* Reset Vector Base Address Register */ CONTEXTIDR_EL2, /* Context ID Register (EL2) */ - TPIDR_EL2, /* EL2 Software Thread ID Register */ CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ SP_EL2, /* EL2 Stack Pointer */ CNTHP_CTL_EL2, @@ -402,6 +386,42 @@ enum vcpu_sysreg { CNTHV_CTL_EL2, CNTHV_CVAL_EL2, + __VNCR_START__, /* Any VNCR-capable reg goes after this point */ + + VNCR(SCTLR_EL1),/* System Control Register */ + VNCR(ACTLR_EL1),/* Auxiliary Control Register */ + VNCR(CPACR_EL1),/* Coprocessor Access Control */ + VNCR(ZCR_EL1), /* SVE Control */ + VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ + VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ + VNCR(TCR_EL1), /* Translation Control Register */ + VNCR(ESR_EL1), /* Exception Syndrome Register */ + VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ + VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ + VNCR(FAR_EL1), /* Fault Address Register */ + VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ + VNCR(VBAR_EL1), /* Vector Base Address Register */ + VNCR(CONTEXTIDR_EL1), /* Context ID Register */ + VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ + VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ + VNCR(ELR_EL1), + VNCR(SP_EL1), + VNCR(SPSR_EL1), + VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ + VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ + VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ + VNCR(HCR_EL2), /* Hypervisor Configuration Register */ + VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ + VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ + VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ + VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ + + VNCR(CNTVOFF_EL2), + VNCR(CNTV_CVAL_EL0), + VNCR(CNTV_CTL_EL0), + VNCR(CNTP_CVAL_EL0), + VNCR(CNTP_CTL_EL0), + NR_SYS_REGS /* Nothing after this line! */ }; @@ -418,6 +438,9 @@ struct kvm_cpu_context { u64 sys_regs[NR_SYS_REGS]; struct kvm_vcpu *__hyp_running_vcpu; + + /* This pointer has to be 4kB aligned. */ + u64 *vncr_array; }; struct kvm_host_data { @@ -756,8 +779,19 @@ struct kvm_vcpu_arch { * accessed by a running VCPU. For example, for userspace access or * for system registers that are never context switched, but only * emulated. + * + * Don't bother with VNCR-based accesses in the nVHE code, it has no + * business dealing with NV. */ -#define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)]) +static inline u64 *__ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) +{ +#if !defined (__KVM_NVHE_HYPERVISOR__) + if (unlikely(cpus_have_final_cap(ARM64_HAS_ENHANCED_NESTED_VIRT) && + r >= __VNCR_START__ && ctxt->vncr_array)) + return &ctxt->vncr_array[r - __VNCR_START__]; +#endif + return (u64 *)&ctxt->sys_regs[r]; +} #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 19813aef60bf..ef31e5b1e66b 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -23,6 +23,7 @@ HAS_DCPOP HAS_DIT HAS_E0PD HAS_ECV +HAS_ENHANCED_NESTED_VIRT HAS_EPAN HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH_QARMA3 -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org> To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Alexandru Elisei <alexandru.elisei@arm.com>, Andre Przywara <andre.przywara@arm.com>, Chase Conklin <chase.conklin@arm.com>, Christoffer Dall <christoffer.dall@arm.com>, Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>, Jintack Lim <jintack@cs.columbia.edu>, Russell King <rmk+kernel@armlinux.org.uk>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Oliver Upton <oliver.upton@linux.dev>, Zenghui Yu <yuzenghui@huawei.com> Subject: [PATCH v7 58/68] KVM: arm64: nv: Map VNCR-capable registers to a separate page Date: Thu, 12 Jan 2023 19:19:17 +0000 [thread overview] Message-ID: <20230112191927.1814989-59-maz@kernel.org> (raw) In-Reply-To: <20230112191927.1814989-1-maz@kernel.org> With ARMv8.4-NV, registers that can be directly accessed in memory by the guest have to live at architected offsets in a special page. Let's annotate the sysreg enum to reflect the offset at which they are in this page, whith a little twist: If running on HW that doesn't have the ARMv8.4-NV feature, or even a VM that doesn't use NV, we store all the system registers in the usual sys_regs array. The only difference with the pre-8.4 situation is that VNCR-capable registers are at a "similar" offset as in the VNCR page (we can compute the actual offset at compile time), and that the sys_regs array is both bigger and sparse. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/include/asm/kvm_host.h | 104 ++++++++++++++++++++---------- arch/arm64/tools/cpucaps | 1 + 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 4a71cb1442dd..deabf860a3c5 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -26,6 +26,7 @@ #include <asm/fpsimd.h> #include <asm/kvm.h> #include <asm/kvm_asm.h> +#include <asm/vncr_mapping.h> #define __KVM_HAVE_ARCH_INTC_INITIALIZED @@ -290,31 +291,32 @@ struct kvm_vcpu_fault_info { u64 disr_el1; /* Deferred [SError] Status Register */ }; +/* + * VNCR() just places the VNCR_capable registers in the enum after + * __VNCR_START__, and the value (after correction) to be an 8-byte offset + * from the VNCR base. As we don't require the enum to be otherwise ordered, + * we need the terrible hack below to ensure that we correctly size the + * sys_regs array, no matter what. + * + * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful + * treasure trove of bit hacks: + * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax + */ +#define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) +#define VNCR(r) \ + __before_##r, \ + r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ + __after_##r = __MAX__(__before_##r - 1, r) + enum vcpu_sysreg { __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ MPIDR_EL1, /* MultiProcessor Affinity Register */ CSSELR_EL1, /* Cache Size Selection Register */ - SCTLR_EL1, /* System Control Register */ - ACTLR_EL1, /* Auxiliary Control Register */ - CPACR_EL1, /* Coprocessor Access Control */ - ZCR_EL1, /* SVE Control */ - TTBR0_EL1, /* Translation Table Base Register 0 */ - TTBR1_EL1, /* Translation Table Base Register 1 */ - TCR_EL1, /* Translation Control Register */ - ESR_EL1, /* Exception Syndrome Register */ - AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ - AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ - FAR_EL1, /* Fault Address Register */ - MAIR_EL1, /* Memory Attribute Indirection Register */ - VBAR_EL1, /* Vector Base Address Register */ - CONTEXTIDR_EL1, /* Context ID Register */ TPIDR_EL0, /* Thread ID, User R/W */ TPIDRRO_EL0, /* Thread ID, User R/O */ TPIDR_EL1, /* Thread ID, Privileged */ - AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ CNTKCTL_EL1, /* Timer Control Register (EL1) */ PAR_EL1, /* Physical Address Register */ - MDSCR_EL1, /* Monitor Debug System Control Register */ MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ OSLSR_EL1, /* OS Lock Status Register */ DISR_EL1, /* Deferred Interrupt Status Register */ @@ -345,20 +347,9 @@ enum vcpu_sysreg { APGAKEYLO_EL1, APGAKEYHI_EL1, - ELR_EL1, - SP_EL1, - SPSR_EL1, - - CNTVOFF_EL2, - CNTV_CVAL_EL0, - CNTV_CTL_EL0, - CNTP_CVAL_EL0, - CNTP_CTL_EL0, - /* Memory Tagging Extension registers */ RGSR_EL1, /* Random Allocation Tag Seed Register */ GCR_EL1, /* Tag Control Register */ - TFSR_EL1, /* Tag Fault Status Register (EL1) */ TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ /* 32bit specific registers. */ @@ -368,20 +359,14 @@ enum vcpu_sysreg { DBGVCR32_EL2, /* Debug Vector Catch Register */ /* EL2 registers */ - VPIDR_EL2, /* Virtualization Processor ID Register */ - VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */ SCTLR_EL2, /* System Control Register (EL2) */ ACTLR_EL2, /* Auxiliary Control Register (EL2) */ - HCR_EL2, /* Hypervisor Configuration Register */ MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ - HSTR_EL2, /* Hypervisor System Trap Register */ HACR_EL2, /* Hypervisor Auxiliary Control Register */ TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ TCR_EL2, /* Translation Control Register (EL2) */ - VTTBR_EL2, /* Virtualization Translation Table Base Register */ - VTCR_EL2, /* Virtualization Translation Control Register */ SPSR_EL2, /* EL2 saved program status register */ ELR_EL2, /* EL2 exception link register */ AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ @@ -394,7 +379,6 @@ enum vcpu_sysreg { VBAR_EL2, /* Vector Base Address Register (EL2) */ RVBAR_EL2, /* Reset Vector Base Address Register */ CONTEXTIDR_EL2, /* Context ID Register (EL2) */ - TPIDR_EL2, /* EL2 Software Thread ID Register */ CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ SP_EL2, /* EL2 Stack Pointer */ CNTHP_CTL_EL2, @@ -402,6 +386,42 @@ enum vcpu_sysreg { CNTHV_CTL_EL2, CNTHV_CVAL_EL2, + __VNCR_START__, /* Any VNCR-capable reg goes after this point */ + + VNCR(SCTLR_EL1),/* System Control Register */ + VNCR(ACTLR_EL1),/* Auxiliary Control Register */ + VNCR(CPACR_EL1),/* Coprocessor Access Control */ + VNCR(ZCR_EL1), /* SVE Control */ + VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ + VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ + VNCR(TCR_EL1), /* Translation Control Register */ + VNCR(ESR_EL1), /* Exception Syndrome Register */ + VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ + VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ + VNCR(FAR_EL1), /* Fault Address Register */ + VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ + VNCR(VBAR_EL1), /* Vector Base Address Register */ + VNCR(CONTEXTIDR_EL1), /* Context ID Register */ + VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ + VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ + VNCR(ELR_EL1), + VNCR(SP_EL1), + VNCR(SPSR_EL1), + VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ + VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ + VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ + VNCR(HCR_EL2), /* Hypervisor Configuration Register */ + VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ + VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ + VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ + VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ + + VNCR(CNTVOFF_EL2), + VNCR(CNTV_CVAL_EL0), + VNCR(CNTV_CTL_EL0), + VNCR(CNTP_CVAL_EL0), + VNCR(CNTP_CTL_EL0), + NR_SYS_REGS /* Nothing after this line! */ }; @@ -418,6 +438,9 @@ struct kvm_cpu_context { u64 sys_regs[NR_SYS_REGS]; struct kvm_vcpu *__hyp_running_vcpu; + + /* This pointer has to be 4kB aligned. */ + u64 *vncr_array; }; struct kvm_host_data { @@ -756,8 +779,19 @@ struct kvm_vcpu_arch { * accessed by a running VCPU. For example, for userspace access or * for system registers that are never context switched, but only * emulated. + * + * Don't bother with VNCR-based accesses in the nVHE code, it has no + * business dealing with NV. */ -#define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)]) +static inline u64 *__ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) +{ +#if !defined (__KVM_NVHE_HYPERVISOR__) + if (unlikely(cpus_have_final_cap(ARM64_HAS_ENHANCED_NESTED_VIRT) && + r >= __VNCR_START__ && ctxt->vncr_array)) + return &ctxt->vncr_array[r - __VNCR_START__]; +#endif + return (u64 *)&ctxt->sys_regs[r]; +} #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 19813aef60bf..ef31e5b1e66b 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -23,6 +23,7 @@ HAS_DCPOP HAS_DIT HAS_E0PD HAS_ECV +HAS_ENHANCED_NESTED_VIRT HAS_EPAN HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH_QARMA3 -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-01-12 19:29 UTC|newest] Thread overview: 138+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-12 19:18 [PATCH v7 00/68] KVM: arm64: ARMv8.3/8.4 Nested Virtualization support Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 01/68] arm64: Add ARM64_HAS_NESTED_VIRT cpufeature Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 02/68] KVM: arm64: nv: Introduce nested virtualization VCPU feature Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 03/68] KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 04/68] KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 05/68] KVM: arm64: nv: Add EL2 system registers to vcpu context Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 06/68] KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 07/68] KVM: arm64: nv: Handle HCR_EL2.NV system register traps Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 08/68] KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 09/68] KVM: arm64: nv: Support virtual EL2 exceptions Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 10/68] KVM: arm64: nv: Inject HVC exceptions to the virtual EL2 Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 11/68] KVM: arm64: nv: Handle trapped ERET from " Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 12/68] KVM: arm64: nv: Add non-VHE-EL2->EL1 translation helpers Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 13/68] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg() Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 14/68] KVM: arm64: nv: Handle SPSR_EL2 specially Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 15/68] KVM: arm64: nv: Handle HCR_EL2.E2H specially Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 16/68] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 17/68] KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 18/68] KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 19/68] KVM: arm64: nv: Add accessors for SPSR_EL1, ELR_EL1 and VBAR_EL1 from " Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 20/68] KVM: arm64: nv: Trap CPACR_EL1 access in " Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 21/68] KVM: arm64: nv: Handle PSCI call via smc from the guest Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 22/68] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 23/68] KVM: arm64: nv: Respect virtual CPTR_EL2.{TFP,FPEN} settings Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 24/68] KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 25/68] KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 26/68] KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 27/68] KVM: arm64: nv: Allow a sysreg to be hidden from userspace only Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 28/68] KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2 Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 29/68] KVM: arm64: nv: Forward debug traps to the nested guest Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 30/68] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 31/68] KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2 changes Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 32/68] KVM: arm64: nv: Filter out unsupported features from ID regs Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 33/68] KVM: arm64: nv: Hide RAS from nested guests Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 34/68] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 35/68] KVM: arm64: nv: Implement nested Stage-2 page table walk logic Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 36/68] KVM: arm64: nv: Handle shadow stage 2 page faults Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 37/68] KVM: arm64: nv: Restrict S2 RD/WR permissions to match the guest's Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 38/68] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 39/68] KVM: arm64: nv: Set a handler for the system instruction traps Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:18 ` [PATCH v7 40/68] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 Marc Zyngier 2023-01-12 19:18 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 41/68] KVM: arm64: nv: Trap and emulate TLBI " Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 42/68] KVM: arm64: nv: Fold guest's HCR_EL2 configuration into the host's Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 43/68] KVM: arm64: nv: arch_timer: Support hyp timer emulation Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 44/68] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 45/68] KVM: arm64: nv: Load timer before the GIC Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 46/68] KVM: arm64: nv: Nested GICv3 Support Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 47/68] KVM: arm64: nv: Don't load the GICv4 context on entering a nested guest Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 48/68] KVM: arm64: nv: vgic: Emulate the HW bit in software Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 49/68] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 50/68] KVM: arm64: nv: Implement maintenance interrupt forwarding Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 51/68] KVM: arm64: nv: Deal with broken VGIC on maintenance interrupt delivery Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 52/68] KVM: arm64: nv: Add nested GICv3 tracepoints Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 53/68] KVM: arm64: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 54/68] KVM: arm64: nv: Add handling of FEAT_TTL TLB invalidation Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 55/68] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 56/68] KVM: arm64: nv: Tag shadow S2 entries with nested level Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 57/68] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier [this message] 2023-01-12 19:19 ` [PATCH v7 58/68] KVM: arm64: nv: Map VNCR-capable registers to a separate page Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 59/68] KVM: arm64: nv: Move nested vgic state into the sysreg file Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 60/68] KVM: arm64: Add FEAT_NV2 cpu feature Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 61/68] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 62/68] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 63/68] KVM: arm64: nv: Allocate VNCR page when required Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 64/68] KVM: arm64: nv: Enable ARMv8.4-NV support Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 65/68] KVM: arm64: nv: Fast-track 'InHost' exception returns Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 66/68] KVM: arm64: nv: Fast-track EL1 TLBIs for VHE guests Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 67/68] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier 2023-01-12 19:19 ` [PATCH v7 68/68] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV is on Marc Zyngier 2023-01-12 19:19 ` Marc Zyngier
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