From: Christoph Muellner <christoph.muellner@vrull.eu>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Heiko Stübner" <heiko.stuebner@vrull.eu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Nelson Chu" <nelson@rivosinc.com>,
"Kito Cheng" <kito.cheng@sifive.com>,
"Cooper Qu" <cooper.qu@linux.alibaba.com>,
"Lifang Xia" <lifang_xia@linux.alibaba.com>,
"Yunhai Shang" <yunhai@linux.alibaba.com>,
"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v3 00/14] Add support for the T-Head vendor extensions
Date: Tue, 24 Jan 2023 20:59:31 +0100 [thread overview]
Message-ID: <20230124195945.181842-1-christoph.muellner@vrull.eu> (raw)
From: Christoph Müllner <christoph.muellner@vrull.eu>
This series introduces support for the T-Head vendor extensions,
which are implemented e.g. in the XuanTie C906 and XuanTie C910:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSync
The xthead* extensions are documented here:
https://github.com/T-head-Semi/thead-extension-spec/releases/latest
The "th." instruction prefix prevents future conflicts with standard
extensions and has been documentented in the RISC-V toolchain conventions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Note, that the T-Head vendor extensions do not contain all
vendor-specific functionality of the T-Head SoCs
(e.g. no vendor-specific CSRs are included).
Instead the extensions cover coherent functionality,
that is exposed to S and U mode.
To enable the extensions above, the following two methods are possible:
* add the extension to the arch string
E.g. QEMU_CPU="any,xtheadcmo=true,xtheadsync=true"
* implicitly select the extensions via CPU selection
E.g. QEMU_CPU="thead-c906"
Major changes in v2:
- Add ISA_EXT_DATA_ENTRY()s
- Use single decoder for XThead extensions
- Simplify a lot of translation functions
- Fix RV32 behaviour
- Added XTheadFmv
- Addressed all comments of v1
Major changes in v3:
- Drop XMAE patch
- Rename priv level test macros
Christoph Müllner (14):
RISC-V: Adding XTheadCmo ISA extension
RISC-V: Adding XTheadSync ISA extension
RISC-V: Adding XTheadBa ISA extension
RISC-V: Adding XTheadBb ISA extension
RISC-V: Adding XTheadBs ISA extension
RISC-V: Adding XTheadCondMov ISA extension
RISC-V: Adding T-Head multiply-accumulate instructions
RISC-V: Adding T-Head MemPair extension
RISC-V: Adding T-Head MemIdx extension
RISC-V: Adding T-Head FMemIdx extension
RISC-V: Set minimum priv version for Zfh to 1.11
RISC-V: Add initial support for T-Head C906
RISC-V: Adding XTheadFmv ISA extension
target/riscv: add a MAINTAINERS entry for XThead* extension support
MAINTAINERS | 8 +
target/riscv/cpu.c | 54 +-
target/riscv/cpu.h | 13 +
target/riscv/cpu_vendorid.h | 6 +
target/riscv/helper.h | 1 +
target/riscv/insn_trans/trans_xthead.c.inc | 1081 ++++++++++++++++++++
target/riscv/meson.build | 1 +
target/riscv/op_helper.c | 6 +
target/riscv/translate.c | 31 +
target/riscv/xthead.decode | 185 ++++
10 files changed, 1385 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/cpu_vendorid.h
create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc
create mode 100644 target/riscv/xthead.decode
--
2.39.0
next reply other threads:[~2023-01-24 20:01 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-24 19:59 Christoph Muellner [this message]
2023-01-24 19:59 ` [PATCH v3 01/14] RISC-V: Adding XTheadCmo ISA extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 02/14] RISC-V: Adding XTheadSync " Christoph Muellner
2023-01-24 20:21 ` Richard Henderson
2023-01-30 14:05 ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 03/14] RISC-V: Adding XTheadBa " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 04/14] RISC-V: Adding XTheadBb " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 05/14] RISC-V: Adding XTheadBs " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 06/14] RISC-V: Adding XTheadCondMov " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2023-01-24 20:44 ` Richard Henderson
2023-01-30 2:03 ` LIU Zhiwei
2023-01-30 5:43 ` Richard Henderson
2023-01-30 8:41 ` LIU Zhiwei
2023-01-30 19:03 ` Richard Henderson
2023-01-31 2:34 ` LIU Zhiwei
2023-01-31 18:01 ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2023-01-24 21:21 ` Richard Henderson
2023-01-30 9:04 ` LIU Zhiwei
2023-01-31 18:01 ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 10/14] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 12/14] RISC-V: Add initial support for T-Head C906 Christoph Muellner
2023-01-24 21:26 ` Richard Henderson
2023-01-30 9:06 ` LIU Zhiwei
2023-01-31 18:01 ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 13/14] RISC-V: Adding XTheadFmv ISA extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Christoph Muellner
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