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From: "Christoph Müllner" <christoph.muellner@vrull.eu>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Heiko Stübner" <heiko.stuebner@vrull.eu>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Nelson Chu" <nelson@rivosinc.com>,
	"Kito Cheng" <kito.cheng@sifive.com>,
	"Cooper Qu" <cooper.qu@linux.alibaba.com>,
	"Lifang Xia" <lifang_xia@linux.alibaba.com>,
	"Yunhai Shang" <yunhai@linux.alibaba.com>,
	"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH v3 12/14] RISC-V: Add initial support for T-Head C906
Date: Tue, 31 Jan 2023 19:01:54 +0100	[thread overview]
Message-ID: <CAEg0e7jH2Y8=2aKABAdL0JkMLOgJyUL1ciwDsA4ePaAt=bRSeQ@mail.gmail.com> (raw)
In-Reply-To: <64af1437-b910-e5b3-c462-0ef0c416ba39@linaro.org>

On Tue, Jan 24, 2023 at 10:26 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 1/24/23 09:59, Christoph Muellner wrote:
> > +++ b/target/riscv/cpu.h
> > @@ -27,6 +27,7 @@
> >   #include "qom/object.h"
> >   #include "qemu/int128.h"
> >   #include "cpu_bits.h"
> > +#include "cpu_vendorid.h"
>
> I don't see that this ID is required for all users of riscv/cpu.h.
> This include should be limited to cpu.c.

Fixed in v4.

Thank you!

>
>
> r~


  parent reply	other threads:[~2023-01-31 18:07 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-24 19:59 [PATCH v3 00/14] Add support for the T-Head vendor extensions Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 01/14] RISC-V: Adding XTheadCmo ISA extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 02/14] RISC-V: Adding XTheadSync " Christoph Muellner
2023-01-24 20:21   ` Richard Henderson
2023-01-30 14:05     ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 03/14] RISC-V: Adding XTheadBa " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 04/14] RISC-V: Adding XTheadBb " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 05/14] RISC-V: Adding XTheadBs " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 06/14] RISC-V: Adding XTheadCondMov " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2023-01-24 20:44   ` Richard Henderson
2023-01-30  2:03     ` LIU Zhiwei
2023-01-30  5:43       ` Richard Henderson
2023-01-30  8:41         ` LIU Zhiwei
2023-01-30 19:03           ` Richard Henderson
2023-01-31  2:34             ` LIU Zhiwei
2023-01-31 18:01     ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2023-01-24 21:21   ` Richard Henderson
2023-01-30  9:04     ` LIU Zhiwei
2023-01-31 18:01     ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 10/14] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 12/14] RISC-V: Add initial support for T-Head C906 Christoph Muellner
2023-01-24 21:26   ` Richard Henderson
2023-01-30  9:06     ` LIU Zhiwei
2023-01-31 18:01     ` Christoph Müllner [this message]
2023-01-24 19:59 ` [PATCH v3 13/14] RISC-V: Adding XTheadFmv ISA extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Christoph Muellner

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