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From: Richard Henderson <richard.henderson@linaro.org>
To: "LIU Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Christoph Muellner" <christoph.muellner@vrull.eu>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Heiko Stübner" <heiko.stuebner@vrull.eu>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Nelson Chu" <nelson@rivosinc.com>,
	"Kito Cheng" <kito.cheng@sifive.com>,
	"Cooper Qu" <cooper.qu@linux.alibaba.com>,
	"Lifang Xia" <lifang_xia@linux.alibaba.com>,
	"Yunhai Shang" <yunhai@linux.alibaba.com>
Subject: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension
Date: Sun, 29 Jan 2023 19:43:43 -1000	[thread overview]
Message-ID: <7f8383f6-e860-5e3e-e89c-dfdac4e05dc5@linaro.org> (raw)
In-Reply-To: <8385d954-678e-d78d-c3ae-d74a4a902907@linux.alibaba.com>

On 1/29/23 16:03, LIU Zhiwei wrote:
> Thanks. It's a bug. We should load all memory addresses to  local TCG temps first.
> 
> Do you think we should probe all the memory addresses for the store pair instructions? If 
> so, can we avoid the use of a helper function?

Depends on what the hardware does.  Even with a trap in the middle the stores are 
restartable, since no register state changes.

But if you'd like no changes verifying both stores, for this case you can pack the pair 
into a larger data type: TCGv_i64 for pair of 32-bit, and TCGv_i128 for pair of 64-bit.
Patches for TCGv_i128 [1] are just finishing review; patches to describe atomicity of the 
larger operation are also on list [2]. Anyway, the idea is that you issue one TCG memory 
operation, the entire operation is validated, and then the stores happen.


> The main reason is that assembler can do this check. Is it necessary to check this in QEMU?

Yes.  Conciser what happens when the insn is encoded with .long.  Does the hardware trap 
an illegal instruction?  Is the behavior simply unspecified?  The manual could be improved 
to specify, akin to the Arm terms: UNDEFINED, CONSTRAINED UNPREDICTABLE, IMPLEMENTATION 
DEFINED, etc.


r~

[1] https://patchew.org/QEMU/20230126043824.54819-1-richard.henderson@linaro.org/
[2] https://patchew.org/QEMU/20221118094754.242910-1-richard.henderson@linaro.org/


  reply	other threads:[~2023-01-30  5:44 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-24 19:59 [PATCH v3 00/14] Add support for the T-Head vendor extensions Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 01/14] RISC-V: Adding XTheadCmo ISA extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 02/14] RISC-V: Adding XTheadSync " Christoph Muellner
2023-01-24 20:21   ` Richard Henderson
2023-01-30 14:05     ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 03/14] RISC-V: Adding XTheadBa " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 04/14] RISC-V: Adding XTheadBb " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 05/14] RISC-V: Adding XTheadBs " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 06/14] RISC-V: Adding XTheadCondMov " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2023-01-24 20:44   ` Richard Henderson
2023-01-30  2:03     ` LIU Zhiwei
2023-01-30  5:43       ` Richard Henderson [this message]
2023-01-30  8:41         ` LIU Zhiwei
2023-01-30 19:03           ` Richard Henderson
2023-01-31  2:34             ` LIU Zhiwei
2023-01-31 18:01     ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2023-01-24 21:21   ` Richard Henderson
2023-01-30  9:04     ` LIU Zhiwei
2023-01-31 18:01     ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 10/14] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 12/14] RISC-V: Add initial support for T-Head C906 Christoph Muellner
2023-01-24 21:26   ` Richard Henderson
2023-01-30  9:06     ` LIU Zhiwei
2023-01-31 18:01     ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 13/14] RISC-V: Adding XTheadFmv ISA extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Christoph Muellner

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