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From: Dhruva Gole <d-gole@ti.com>
To: Mark Brown <broonie@kernel.org>
Cc: <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Vaishnav Achath <vaishnav.a@ti.com>, Dhruva Gole <d-gole@ti.com>,
	<linux-mtd@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<Takahiro.Kuwano@infineon.com>,
	Pratyush Yadav <ptyadav@amazon.de>
Subject: [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads
Date: Wed, 25 Jan 2023 13:40:23 +0530	[thread overview]
Message-ID: <20230125081023.1573712-5-d-gole@ti.com> (raw)
In-Reply-To: <20230125081023.1573712-1-d-gole@ti.com>

Fix the issue where some flash chips like cypress S25HS256T return the
value of the same register over and over in DAC mode.

For example in the TI K3-AM62x Processors refer [0] Technical Reference
Manual there is a layer of digital logic in front of the QSPI/OSPI
Drive when used in DAC mode. This is part of the Flash Subsystem (FSS)
which provides access to external Flash devices.

The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for
OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit
mode enabled by default.

Thus, by default controller operates in 32 bit mode causing it to always
align all data to 4 bytes from a 4byte aligned address. In some flash
chips like cypress for example if we try to read some regs in DAC mode
then it keeps sending the value of the first register that was requested
and inorder to read the next reg, we have to stop and re-initiate a new
transaction.

This causes wrong register values to be read than what is desired when
registers are read in DAC mode. Hence if the data.nbytes is very less
then prefer STIG mode for such small reads.

[0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf

Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
 drivers/spi/spi-cadence-quadspi.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index a6d0f1b0bb49..2954c06a7f57 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1359,7 +1359,13 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
 	cqspi_configure(f_pdata, mem->spi->max_speed_hz);

 	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
-		if (!op->addr.nbytes)
+	/*
+	 * Performing reads in DAC mode forces to read minimum 4 bytes
+	 * which is unsupported on some flash devices during register
+	 * reads, prefer STIG mode for such small reads.
+	 */
+		if (!op->addr.nbytes ||
+		    op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 			return cqspi_command_read(f_pdata, op);

 		return cqspi_read(f_pdata, op);
--
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Dhruva Gole <d-gole@ti.com>
To: Mark Brown <broonie@kernel.org>
Cc: <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Vaishnav Achath <vaishnav.a@ti.com>, Dhruva Gole <d-gole@ti.com>,
	<linux-mtd@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<Takahiro.Kuwano@infineon.com>,
	Pratyush Yadav <ptyadav@amazon.de>
Subject: [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads
Date: Wed, 25 Jan 2023 13:40:23 +0530	[thread overview]
Message-ID: <20230125081023.1573712-5-d-gole@ti.com> (raw)
In-Reply-To: <20230125081023.1573712-1-d-gole@ti.com>

Fix the issue where some flash chips like cypress S25HS256T return the
value of the same register over and over in DAC mode.

For example in the TI K3-AM62x Processors refer [0] Technical Reference
Manual there is a layer of digital logic in front of the QSPI/OSPI
Drive when used in DAC mode. This is part of the Flash Subsystem (FSS)
which provides access to external Flash devices.

The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for
OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit
mode enabled by default.

Thus, by default controller operates in 32 bit mode causing it to always
align all data to 4 bytes from a 4byte aligned address. In some flash
chips like cypress for example if we try to read some regs in DAC mode
then it keeps sending the value of the first register that was requested
and inorder to read the next reg, we have to stop and re-initiate a new
transaction.

This causes wrong register values to be read than what is desired when
registers are read in DAC mode. Hence if the data.nbytes is very less
then prefer STIG mode for such small reads.

[0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf

Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
 drivers/spi/spi-cadence-quadspi.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index a6d0f1b0bb49..2954c06a7f57 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1359,7 +1359,13 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
 	cqspi_configure(f_pdata, mem->spi->max_speed_hz);

 	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
-		if (!op->addr.nbytes)
+	/*
+	 * Performing reads in DAC mode forces to read minimum 4 bytes
+	 * which is unsupported on some flash devices during register
+	 * reads, prefer STIG mode for such small reads.
+	 */
+		if (!op->addr.nbytes ||
+		    op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 			return cqspi_command_read(f_pdata, op);

 		return cqspi_read(f_pdata, op);
--
2.25.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Dhruva Gole <d-gole@ti.com>
To: Mark Brown <broonie@kernel.org>
Cc: <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Vaishnav Achath <vaishnav.a@ti.com>, Dhruva Gole <d-gole@ti.com>,
	<linux-mtd@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<Takahiro.Kuwano@infineon.com>,
	Pratyush Yadav <ptyadav@amazon.de>
Subject: [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads
Date: Wed, 25 Jan 2023 13:40:23 +0530	[thread overview]
Message-ID: <20230125081023.1573712-5-d-gole@ti.com> (raw)
In-Reply-To: <20230125081023.1573712-1-d-gole@ti.com>

Fix the issue where some flash chips like cypress S25HS256T return the
value of the same register over and over in DAC mode.

For example in the TI K3-AM62x Processors refer [0] Technical Reference
Manual there is a layer of digital logic in front of the QSPI/OSPI
Drive when used in DAC mode. This is part of the Flash Subsystem (FSS)
which provides access to external Flash devices.

The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for
OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit
mode enabled by default.

Thus, by default controller operates in 32 bit mode causing it to always
align all data to 4 bytes from a 4byte aligned address. In some flash
chips like cypress for example if we try to read some regs in DAC mode
then it keeps sending the value of the first register that was requested
and inorder to read the next reg, we have to stop and re-initiate a new
transaction.

This causes wrong register values to be read than what is desired when
registers are read in DAC mode. Hence if the data.nbytes is very less
then prefer STIG mode for such small reads.

[0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf

Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
 drivers/spi/spi-cadence-quadspi.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index a6d0f1b0bb49..2954c06a7f57 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1359,7 +1359,13 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
 	cqspi_configure(f_pdata, mem->spi->max_speed_hz);

 	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
-		if (!op->addr.nbytes)
+	/*
+	 * Performing reads in DAC mode forces to read minimum 4 bytes
+	 * which is unsupported on some flash devices during register
+	 * reads, prefer STIG mode for such small reads.
+	 */
+		if (!op->addr.nbytes ||
+		    op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 			return cqspi_command_read(f_pdata, op);

 		return cqspi_read(f_pdata, op);
--
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2023-01-25  8:11 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-25  8:10 [PATCH v2 0/4] STIG Mode Fixes for spi-cadence-qspi driver Dhruva Gole
2023-01-25  8:10 ` Dhruva Gole
2023-01-25  8:10 ` Dhruva Gole
2023-01-25  8:10 ` [PATCH v2 1/4] spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion Dhruva Gole
2023-01-25  8:10   ` Dhruva Gole
2023-01-25  8:10   ` Dhruva Gole
2023-01-27 15:16   ` Pratyush Yadav
2023-01-27 15:16     ` Pratyush Yadav
2023-01-27 15:16     ` Pratyush Yadav
2023-02-07 13:06     ` Gole, Dhruva
2023-02-07 13:06       ` Gole, Dhruva
2023-02-07 13:06       ` Gole, Dhruva
2023-01-25  8:10 ` [PATCH v2 2/4] spi: cadence-quadspi: Add flag for direct mode writes Dhruva Gole
2023-01-25  8:10   ` Dhruva Gole
2023-01-25  8:10   ` Dhruva Gole
2023-01-25  8:10 ` [PATCH v2 3/4] spi: cadence-quadspi: setup ADDR Bits in cmd reads Dhruva Gole
2023-01-25  8:10   ` Dhruva Gole
2023-01-25  8:10   ` Dhruva Gole
2023-01-25  8:10 ` Dhruva Gole [this message]
2023-01-25  8:10   ` [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads Dhruva Gole
2023-01-25  8:10   ` Dhruva Gole
2023-04-26  2:34   ` Yoshitaka Ikeda
2023-04-26  2:34     ` Yoshitaka Ikeda
2023-04-26  2:34     ` Yoshitaka Ikeda
2023-04-26  7:39     ` Dhruva Gole
2023-04-26  7:39       ` Dhruva Gole
2023-04-26  7:39       ` Dhruva Gole
2023-04-27  0:41       ` Yoshitaka Ikeda
2023-04-27  0:41         ` Yoshitaka Ikeda
2023-04-27  0:41         ` Yoshitaka Ikeda
2023-04-27 13:25         ` Dhruva Gole
2023-04-27 13:25           ` Dhruva Gole
2023-04-27 13:25           ` Dhruva Gole
2023-05-08  0:36           ` Yoshitaka Ikeda
2023-05-08  0:36             ` Yoshitaka Ikeda
2023-05-08  0:36             ` Yoshitaka Ikeda
2023-05-08  5:29             ` Dhruva Gole
2023-05-08  5:29               ` Dhruva Gole
2023-05-08  7:44               ` Yoshitaka Ikeda
2023-05-08  7:44                 ` Yoshitaka Ikeda
2023-05-30  2:56                 ` Yoshitaka Ikeda
2023-05-30  2:56                   ` Yoshitaka Ikeda
2023-05-30  2:56                   ` Yoshitaka Ikeda
2023-02-14 21:10 ` [PATCH v2 0/4] STIG Mode Fixes for spi-cadence-qspi driver Mark Brown
2023-02-14 21:10   ` Mark Brown
2023-02-14 21:10   ` Mark Brown

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