From: Yoshitaka Ikeda <ikeda@nskint.co.jp>
To: Dhruva Gole <d-gole@ti.com>
Cc: "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Vaishnav Achath <vaishnav.a@ti.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"Takahiro.Kuwano@infineon.com" <Takahiro.Kuwano@infineon.com>,
Pratyush Yadav <ptyadav@amazon.de>,
Mark Brown <broonie@kernel.org>,
Yoshitaka Ikeda <ikeda@nskint.co.jp>
Subject: RE: [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads
Date: Thu, 27 Apr 2023 00:41:36 +0000 [thread overview]
Message-ID: <OSZPR01MB7004D229048A950C93B40CC88B6A9@OSZPR01MB7004.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <044a723e-b81e-f6f2-8bf7-3680a10abc86@ti.com>
Hi Dhruva,
> Please can you send me the register fields information for the CQSPI
> controller used in this device?
> I wanted to verify if atall there were any mismatch between the controller I
> have tested with vs your SOC's controller.
You can find it in the pdf that can be obtained by pressing the download button in the upper right corner of the following website.
- https://www.intel.com/content/www/us/en/docs/programmable/683126/15-0/introduction.html
The description is as follows:
- 15. Quad SPI Flash
- Quad SPI Flash Controller Address Map and Register Definitions
--
Thanks and Regards,
Yoshitaka Ikeda
WARNING: multiple messages have this Message-ID (diff)
From: Yoshitaka Ikeda <ikeda@nskint.co.jp>
To: Dhruva Gole <d-gole@ti.com>
Cc: "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Vaishnav Achath <vaishnav.a@ti.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"Takahiro.Kuwano@infineon.com" <Takahiro.Kuwano@infineon.com>,
Pratyush Yadav <ptyadav@amazon.de>,
Mark Brown <broonie@kernel.org>,
Yoshitaka Ikeda <ikeda@nskint.co.jp>
Subject: RE: [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads
Date: Thu, 27 Apr 2023 00:41:36 +0000 [thread overview]
Message-ID: <OSZPR01MB7004D229048A950C93B40CC88B6A9@OSZPR01MB7004.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <044a723e-b81e-f6f2-8bf7-3680a10abc86@ti.com>
Hi Dhruva,
> Please can you send me the register fields information for the CQSPI
> controller used in this device?
> I wanted to verify if atall there were any mismatch between the controller I
> have tested with vs your SOC's controller.
You can find it in the pdf that can be obtained by pressing the download button in the upper right corner of the following website.
- https://www.intel.com/content/www/us/en/docs/programmable/683126/15-0/introduction.html
The description is as follows:
- 15. Quad SPI Flash
- Quad SPI Flash Controller Address Map and Register Definitions
--
Thanks and Regards,
Yoshitaka Ikeda
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Yoshitaka Ikeda <ikeda@nskint.co.jp>
To: Dhruva Gole <d-gole@ti.com>
Cc: "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Vaishnav Achath <vaishnav.a@ti.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"Takahiro.Kuwano@infineon.com" <Takahiro.Kuwano@infineon.com>,
Pratyush Yadav <ptyadav@amazon.de>,
Mark Brown <broonie@kernel.org>,
Yoshitaka Ikeda <ikeda@nskint.co.jp>
Subject: RE: [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads
Date: Thu, 27 Apr 2023 00:41:36 +0000 [thread overview]
Message-ID: <OSZPR01MB7004D229048A950C93B40CC88B6A9@OSZPR01MB7004.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <044a723e-b81e-f6f2-8bf7-3680a10abc86@ti.com>
Hi Dhruva,
> Please can you send me the register fields information for the CQSPI
> controller used in this device?
> I wanted to verify if atall there were any mismatch between the controller I
> have tested with vs your SOC's controller.
You can find it in the pdf that can be obtained by pressing the download button in the upper right corner of the following website.
- https://www.intel.com/content/www/us/en/docs/programmable/683126/15-0/introduction.html
The description is as follows:
- 15. Quad SPI Flash
- Quad SPI Flash Controller Address Map and Register Definitions
--
Thanks and Regards,
Yoshitaka Ikeda
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-04-27 0:41 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-25 8:10 [PATCH v2 0/4] STIG Mode Fixes for spi-cadence-qspi driver Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-01-25 8:10 ` [PATCH v2 1/4] spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-01-27 15:16 ` Pratyush Yadav
2023-01-27 15:16 ` Pratyush Yadav
2023-01-27 15:16 ` Pratyush Yadav
2023-02-07 13:06 ` Gole, Dhruva
2023-02-07 13:06 ` Gole, Dhruva
2023-02-07 13:06 ` Gole, Dhruva
2023-01-25 8:10 ` [PATCH v2 2/4] spi: cadence-quadspi: Add flag for direct mode writes Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-01-25 8:10 ` [PATCH v2 3/4] spi: cadence-quadspi: setup ADDR Bits in cmd reads Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-01-25 8:10 ` [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-01-25 8:10 ` Dhruva Gole
2023-04-26 2:34 ` Yoshitaka Ikeda
2023-04-26 2:34 ` Yoshitaka Ikeda
2023-04-26 2:34 ` Yoshitaka Ikeda
2023-04-26 7:39 ` Dhruva Gole
2023-04-26 7:39 ` Dhruva Gole
2023-04-26 7:39 ` Dhruva Gole
2023-04-27 0:41 ` Yoshitaka Ikeda [this message]
2023-04-27 0:41 ` Yoshitaka Ikeda
2023-04-27 0:41 ` Yoshitaka Ikeda
2023-04-27 13:25 ` Dhruva Gole
2023-04-27 13:25 ` Dhruva Gole
2023-04-27 13:25 ` Dhruva Gole
2023-05-08 0:36 ` Yoshitaka Ikeda
2023-05-08 0:36 ` Yoshitaka Ikeda
2023-05-08 0:36 ` Yoshitaka Ikeda
2023-05-08 5:29 ` Dhruva Gole
2023-05-08 5:29 ` Dhruva Gole
2023-05-08 7:44 ` Yoshitaka Ikeda
2023-05-08 7:44 ` Yoshitaka Ikeda
2023-05-30 2:56 ` Yoshitaka Ikeda
2023-05-30 2:56 ` Yoshitaka Ikeda
2023-05-30 2:56 ` Yoshitaka Ikeda
2023-02-14 21:10 ` [PATCH v2 0/4] STIG Mode Fixes for spi-cadence-qspi driver Mark Brown
2023-02-14 21:10 ` Mark Brown
2023-02-14 21:10 ` Mark Brown
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=OSZPR01MB7004D229048A950C93B40CC88B6A9@OSZPR01MB7004.jpnprd01.prod.outlook.com \
--to=ikeda@nskint.co.jp \
--cc=Takahiro.Kuwano@infineon.com \
--cc=broonie@kernel.org \
--cc=d-gole@ti.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-spi@vger.kernel.org \
--cc=ptyadav@amazon.de \
--cc=vaishnav.a@ti.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.