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From: Evan Green <evan@rivosinc.com>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: Conor Dooley <conor@kernel.org>,
	vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com,
	Evan Green <evan@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <apatel@ventanamicro.com>,
	Atish Patra <atishp@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Qinglin Pan <panqinglin2020@iscas.ac.cn>,
	Randy Dunlap <rdunlap@infradead.org>,
	Sunil V L <sunilvl@ventanamicro.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH v2 1/6] RISC-V: Move struct riscv_cpuinfo to new header
Date: Mon,  6 Feb 2023 12:14:50 -0800	[thread overview]
Message-ID: <20230206201455.1790329-2-evan@rivosinc.com> (raw)
In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com>

In preparation for tracking and exposing microarchitectural details to
userspace (like whether or not unaligned accesses are fast), move the
riscv_cpuinfo struct out to its own new cpufeatures.h header. It will
need to be used by more than just cpu.c.

Signed-off-by: Evan Green <evan@rivosinc.com>
---

(no changes since v1)

 arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++
 arch/riscv/kernel/cpu.c             |  8 ++------
 2 files changed, 23 insertions(+), 6 deletions(-)
 create mode 100644 arch/riscv/include/asm/cpufeature.h

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
new file mode 100644
index 000000000000..66c251d98290
--- /dev/null
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2022 Rivos, Inc
+ */
+
+#ifndef _ASM_CPUFEATURE_H
+#define _ASM_CPUFEATURE_H
+
+/*
+ * These are probed via a device_initcall(), via either the SBI or directly
+ * from the cooresponding CSRs.
+ */
+struct riscv_cpuinfo {
+	unsigned long mvendorid;
+	unsigned long marchid;
+	unsigned long mimpid;
+};
+
+DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
+
+#endif
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 1b9a5a66e55a..684e5419d37d 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -7,6 +7,7 @@
 #include <linux/init.h>
 #include <linux/seq_file.h>
 #include <linux/of.h>
+#include <asm/cpufeature.h>
 #include <asm/csr.h>
 #include <asm/hwcap.h>
 #include <asm/sbi.h>
@@ -70,12 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
 	return -1;
 }
 
-struct riscv_cpuinfo {
-	unsigned long mvendorid;
-	unsigned long marchid;
-	unsigned long mimpid;
-};
-static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
+DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
 
 unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
 {
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Evan Green <evan@rivosinc.com>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: Anup Patel <apatel@ventanamicro.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	heiko@sntech.de, Atish Patra <atishp@rivosinc.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	vineetg@rivosinc.com, linux-kernel@vger.kernel.org,
	Conor Dooley <conor@kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Evan Green <evan@rivosinc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	slewis@rivosinc.com, Paul Walmsley <paul.walmsley@sifive.com>,
	Qinglin Pan <panqinglin2020@iscas.ac.cn>,
	linux-riscv@lists.infradead.org
Subject: [PATCH v2 1/6] RISC-V: Move struct riscv_cpuinfo to new header
Date: Mon,  6 Feb 2023 12:14:50 -0800	[thread overview]
Message-ID: <20230206201455.1790329-2-evan@rivosinc.com> (raw)
In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com>

In preparation for tracking and exposing microarchitectural details to
userspace (like whether or not unaligned accesses are fast), move the
riscv_cpuinfo struct out to its own new cpufeatures.h header. It will
need to be used by more than just cpu.c.

Signed-off-by: Evan Green <evan@rivosinc.com>
---

(no changes since v1)

 arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++
 arch/riscv/kernel/cpu.c             |  8 ++------
 2 files changed, 23 insertions(+), 6 deletions(-)
 create mode 100644 arch/riscv/include/asm/cpufeature.h

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
new file mode 100644
index 000000000000..66c251d98290
--- /dev/null
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2022 Rivos, Inc
+ */
+
+#ifndef _ASM_CPUFEATURE_H
+#define _ASM_CPUFEATURE_H
+
+/*
+ * These are probed via a device_initcall(), via either the SBI or directly
+ * from the cooresponding CSRs.
+ */
+struct riscv_cpuinfo {
+	unsigned long mvendorid;
+	unsigned long marchid;
+	unsigned long mimpid;
+};
+
+DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
+
+#endif
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 1b9a5a66e55a..684e5419d37d 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -7,6 +7,7 @@
 #include <linux/init.h>
 #include <linux/seq_file.h>
 #include <linux/of.h>
+#include <asm/cpufeature.h>
 #include <asm/csr.h>
 #include <asm/hwcap.h>
 #include <asm/sbi.h>
@@ -70,12 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
 	return -1;
 }
 
-struct riscv_cpuinfo {
-	unsigned long mvendorid;
-	unsigned long marchid;
-	unsigned long mimpid;
-};
-static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
+DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
 
 unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
 {
-- 
2.25.1


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2023-02-06 20:15 UTC|newest]

Thread overview: 91+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-06 20:14 [PATCH v2 0/6] RISC-V Hardware Probing User Interface Evan Green
2023-02-06 20:14 ` Evan Green
2023-02-06 20:14 ` Evan Green [this message]
2023-02-06 20:14   ` [PATCH v2 1/6] RISC-V: Move struct riscv_cpuinfo to new header Evan Green
2023-02-14 21:38   ` Conor Dooley
2023-02-14 21:38     ` Conor Dooley
2023-02-14 21:57     ` Evan Green
2023-02-14 21:57       ` Evan Green
2023-02-06 20:14 ` [PATCH v2 2/6] RISC-V: Add a syscall for HW probing Evan Green
2023-02-06 20:14   ` Evan Green
2023-02-07  6:13   ` Greg KH
2023-02-07  6:13     ` Greg KH
2023-02-07  6:32     ` Conor Dooley
2023-02-07  6:32       ` Conor Dooley
2023-02-09 17:09       ` Evan Green
2023-02-09 17:09         ` Evan Green
2023-02-09 17:13         ` Greg KH
2023-02-09 17:13           ` Greg KH
2023-02-09 17:22           ` Jessica Clarke
2023-02-09 17:22             ` Jessica Clarke
2023-02-10  6:48             ` Greg KH
2023-02-10  6:48               ` Greg KH
2023-02-09 18:41           ` Evan Green
2023-02-09 18:41             ` Evan Green
2023-02-10  6:50             ` Greg KH
2023-02-10  6:50               ` Greg KH
2023-02-07 23:16   ` kernel test robot
2023-02-07 23:16     ` kernel test robot
2023-02-14 23:51   ` Conor Dooley
2023-02-14 23:51     ` Conor Dooley
2023-02-15  8:04     ` Andrew Jones
2023-02-15  8:04       ` Andrew Jones
2023-02-15 20:49     ` Evan Green
2023-02-15 20:49       ` Evan Green
2023-02-15 21:10       ` Conor Dooley
2023-02-15 21:10         ` Conor Dooley
2023-02-15  9:56   ` Arnd Bergmann
2023-02-15  9:56     ` Arnd Bergmann
2023-02-15 21:14     ` Evan Green
2023-02-15 21:14       ` Evan Green
2023-02-15 22:43       ` Jessica Clarke
2023-02-15 22:43         ` Jessica Clarke
2023-02-16 13:28         ` Arnd Bergmann
2023-02-16 13:28           ` Arnd Bergmann
2023-02-16 23:18           ` Evan Green
2023-02-16 23:18             ` Evan Green
2023-02-06 20:14 ` [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Evan Green
2023-02-06 20:14   ` Evan Green
2023-02-08  5:06   ` kernel test robot
2023-02-15 21:25   ` Conor Dooley
2023-02-15 21:25     ` Conor Dooley
2023-02-15 22:09   ` Conor Dooley
2023-02-15 22:09     ` Conor Dooley
2023-02-06 20:14 ` [PATCH v2 4/6] dt-bindings: Add RISC-V misaligned access performance Evan Green
2023-02-06 20:14   ` Evan Green
2023-02-06 21:49   ` Rob Herring
2023-02-06 21:49     ` Rob Herring
2023-02-07 17:05   ` Rob Herring
2023-02-07 17:05     ` Rob Herring
2023-02-08 12:45     ` David Laight
2023-02-08 12:45       ` David Laight
2023-02-09 16:51       ` Palmer Dabbelt
2023-02-09 16:51         ` Palmer Dabbelt
2023-02-28 14:56         ` Rob Herring
2023-02-28 14:56           ` Rob Herring
2023-02-14 21:26   ` Conor Dooley
2023-02-14 21:26     ` Conor Dooley
2023-02-15 20:50     ` Evan Green
2023-02-15 20:50       ` Evan Green
2023-02-06 20:14 ` [PATCH v2 5/6] RISC-V: hwprobe: Support probing of " Evan Green
2023-02-06 20:14   ` Evan Green
2023-02-07  7:02   ` kernel test robot
2023-02-07  7:02     ` kernel test robot
2023-02-15 21:57   ` Conor Dooley
2023-02-15 21:57     ` Conor Dooley
2023-02-18  0:15     ` Evan Green
2023-02-18  0:15       ` Evan Green
2023-02-06 20:14 ` [PATCH v2 6/6] selftests: Test the new RISC-V hwprobe interface Evan Green
2023-02-06 20:14   ` Evan Green
2023-02-06 21:27   ` Mark Brown
2023-02-06 21:27     ` Mark Brown
2023-02-09 18:44     ` Evan Green
2023-02-09 18:44       ` Evan Green
2023-02-06 21:11 ` [PATCH v2 0/6] RISC-V Hardware Probing User Interface Jessica Clarke
2023-02-06 21:11   ` Jessica Clarke
2023-02-06 22:47   ` Heinrich Schuchardt
2023-02-06 22:47     ` Heinrich Schuchardt
2023-02-09 16:56     ` Palmer Dabbelt
2023-02-09 16:56       ` Palmer Dabbelt
2023-02-06 22:32 ` Conor Dooley
2023-02-06 22:32   ` Conor Dooley

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