From: Conor Dooley <conor@kernel.org> To: Evan Green <evan@rivosinc.com> Cc: Palmer Dabbelt <palmer@rivosinc.com>, vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Albert Ou <aou@eecs.berkeley.edu>, Andrew Bresticker <abrestic@rivosinc.com>, Celeste Liu <coelacanthus@outlook.com>, Guo Ren <guoren@kernel.org>, Jonathan Corbet <corbet@lwn.net>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, dram <dramforever@live.com>, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Wed, 15 Feb 2023 21:25:18 +0000 [thread overview] Message-ID: <Y+1NvsLlbo8HvV5w@spud> (raw) In-Reply-To: <20230206201455.1790329-4-evan@rivosinc.com> [-- Attachment #1: Type: text/plain, Size: 2891 bytes --] On Mon, Feb 06, 2023 at 12:14:52PM -0800, Evan Green wrote: > From: Palmer Dabbelt <palmer@rivosinc.com> > > We have an implicit set of base behaviors that userspace depends on, > which are mostly defined in various ISA specifications. > > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> > Signed-off-by: Evan Green <evan@rivosinc.com> > --- > > (no changes since v1) > > Documentation/riscv/hwprobe.rst | 16 ++++++++++++++++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 6 +++++- > arch/riscv/kernel/sys_riscv.c | 23 +++++++++++++++++++++++ > 4 files changed, 45 insertions(+), 2 deletions(-) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 97771090e972..ce186967861f 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -35,3 +35,19 @@ The following keys are defined: > specifications. > * :RISCV_HWPROBE_KEY_MIMPLID:: Contains the value of :mimplid:, as per the ISA > specifications. > +* :RISCV_HWPROBE_KEY_BASE_BEHAVIOR:: A bitmask containing the base user-visible > + behavior that this kernel supports. The following base user ABIs are defined: > + * :RISCV_HWPROBE_BASE_BEHAVIOR_IMA:: Support for rv32ima or rv64ima, as > + defined by version 2.2 of the user ISA and version 1.10 of the privileged > + ISA, with the following known exceptions (more exceptions may be added, > + but only if it can be demonstrated that the user ABI is not broken): > + * The :fence.i: instruction cannot be directly executed by userspace > + programs (it may still be executed in userspace via a > + kernel-controlled mechanism such as the vDSO). I don't really do the whole rst thing at all, are we able to have newlines between list items? If we can, I think one would go nicely here. > +* :RISCV_HWPROBE_KEY_IMA_EXT_0:: A bitmask containing the extensions that are > + compatible with the :RISCV_HWPROBE_BASE_BEHAVIOR_IMA: base system behavior. Why do we specifically care if they're compatible with IMA? What's the "fear" here? > + * :RISCV_HWPROBE_IMA_FD:: The F and D extensions are supported, as defined Also, is this IMA and FD thing a kinda commitment to only supporting hardware that has IMA* or IMAFD* I know that's what we do now, but only under the hood? As per usual, I'm probably missing something. What is it? > + by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, > + not minNum/maxNum") of the RISC-V ISA manual. > + * :RISCV_HWPROBE_IMA_C:: The C extension is supported, as defined by > + version 2.2 of the RISC-V ISA manual. See, this seems to be how we have to treat specs, list the exact versions! I don't even have to look to know that this was in the v1 ;) [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org> To: Evan Green <evan@rivosinc.com> Cc: Palmer Dabbelt <palmer@rivosinc.com>, vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Albert Ou <aou@eecs.berkeley.edu>, Andrew Bresticker <abrestic@rivosinc.com>, Celeste Liu <coelacanthus@outlook.com>, Guo Ren <guoren@kernel.org>, Jonathan Corbet <corbet@lwn.net>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, dram <dramforever@live.com>, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Wed, 15 Feb 2023 21:25:18 +0000 [thread overview] Message-ID: <Y+1NvsLlbo8HvV5w@spud> (raw) In-Reply-To: <20230206201455.1790329-4-evan@rivosinc.com> [-- Attachment #1.1: Type: text/plain, Size: 2891 bytes --] On Mon, Feb 06, 2023 at 12:14:52PM -0800, Evan Green wrote: > From: Palmer Dabbelt <palmer@rivosinc.com> > > We have an implicit set of base behaviors that userspace depends on, > which are mostly defined in various ISA specifications. > > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> > Signed-off-by: Evan Green <evan@rivosinc.com> > --- > > (no changes since v1) > > Documentation/riscv/hwprobe.rst | 16 ++++++++++++++++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 6 +++++- > arch/riscv/kernel/sys_riscv.c | 23 +++++++++++++++++++++++ > 4 files changed, 45 insertions(+), 2 deletions(-) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 97771090e972..ce186967861f 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -35,3 +35,19 @@ The following keys are defined: > specifications. > * :RISCV_HWPROBE_KEY_MIMPLID:: Contains the value of :mimplid:, as per the ISA > specifications. > +* :RISCV_HWPROBE_KEY_BASE_BEHAVIOR:: A bitmask containing the base user-visible > + behavior that this kernel supports. The following base user ABIs are defined: > + * :RISCV_HWPROBE_BASE_BEHAVIOR_IMA:: Support for rv32ima or rv64ima, as > + defined by version 2.2 of the user ISA and version 1.10 of the privileged > + ISA, with the following known exceptions (more exceptions may be added, > + but only if it can be demonstrated that the user ABI is not broken): > + * The :fence.i: instruction cannot be directly executed by userspace > + programs (it may still be executed in userspace via a > + kernel-controlled mechanism such as the vDSO). I don't really do the whole rst thing at all, are we able to have newlines between list items? If we can, I think one would go nicely here. > +* :RISCV_HWPROBE_KEY_IMA_EXT_0:: A bitmask containing the extensions that are > + compatible with the :RISCV_HWPROBE_BASE_BEHAVIOR_IMA: base system behavior. Why do we specifically care if they're compatible with IMA? What's the "fear" here? > + * :RISCV_HWPROBE_IMA_FD:: The F and D extensions are supported, as defined Also, is this IMA and FD thing a kinda commitment to only supporting hardware that has IMA* or IMAFD* I know that's what we do now, but only under the hood? As per usual, I'm probably missing something. What is it? > + by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, > + not minNum/maxNum") of the RISC-V ISA manual. > + * :RISCV_HWPROBE_IMA_C:: The C extension is supported, as defined by > + version 2.2 of the RISC-V ISA manual. See, this seems to be how we have to treat specs, list the exact versions! I don't even have to look to know that this was in the v1 ;) [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-15 21:25 UTC|newest] Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-06 20:14 [PATCH v2 0/6] RISC-V Hardware Probing User Interface Evan Green 2023-02-06 20:14 ` Evan Green 2023-02-06 20:14 ` [PATCH v2 1/6] RISC-V: Move struct riscv_cpuinfo to new header Evan Green 2023-02-06 20:14 ` Evan Green 2023-02-14 21:38 ` Conor Dooley 2023-02-14 21:38 ` Conor Dooley 2023-02-14 21:57 ` Evan Green 2023-02-14 21:57 ` Evan Green 2023-02-06 20:14 ` [PATCH v2 2/6] RISC-V: Add a syscall for HW probing Evan Green 2023-02-06 20:14 ` Evan Green 2023-02-07 6:13 ` Greg KH 2023-02-07 6:13 ` Greg KH 2023-02-07 6:32 ` Conor Dooley 2023-02-07 6:32 ` Conor Dooley 2023-02-09 17:09 ` Evan Green 2023-02-09 17:09 ` Evan Green 2023-02-09 17:13 ` Greg KH 2023-02-09 17:13 ` Greg KH 2023-02-09 17:22 ` Jessica Clarke 2023-02-09 17:22 ` Jessica Clarke 2023-02-10 6:48 ` Greg KH 2023-02-10 6:48 ` Greg KH 2023-02-09 18:41 ` Evan Green 2023-02-09 18:41 ` Evan Green 2023-02-10 6:50 ` Greg KH 2023-02-10 6:50 ` Greg KH 2023-02-07 23:16 ` kernel test robot 2023-02-07 23:16 ` kernel test robot 2023-02-14 23:51 ` Conor Dooley 2023-02-14 23:51 ` Conor Dooley 2023-02-15 8:04 ` Andrew Jones 2023-02-15 8:04 ` Andrew Jones 2023-02-15 20:49 ` Evan Green 2023-02-15 20:49 ` Evan Green 2023-02-15 21:10 ` Conor Dooley 2023-02-15 21:10 ` Conor Dooley 2023-02-15 9:56 ` Arnd Bergmann 2023-02-15 9:56 ` Arnd Bergmann 2023-02-15 21:14 ` Evan Green 2023-02-15 21:14 ` Evan Green 2023-02-15 22:43 ` Jessica Clarke 2023-02-15 22:43 ` Jessica Clarke 2023-02-16 13:28 ` Arnd Bergmann 2023-02-16 13:28 ` Arnd Bergmann 2023-02-16 23:18 ` Evan Green 2023-02-16 23:18 ` Evan Green 2023-02-06 20:14 ` [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Evan Green 2023-02-06 20:14 ` Evan Green 2023-02-08 5:06 ` kernel test robot 2023-02-15 21:25 ` Conor Dooley [this message] 2023-02-15 21:25 ` Conor Dooley 2023-02-15 22:09 ` Conor Dooley 2023-02-15 22:09 ` Conor Dooley 2023-02-06 20:14 ` [PATCH v2 4/6] dt-bindings: Add RISC-V misaligned access performance Evan Green 2023-02-06 20:14 ` Evan Green 2023-02-06 21:49 ` Rob Herring 2023-02-06 21:49 ` Rob Herring 2023-02-07 17:05 ` Rob Herring 2023-02-07 17:05 ` Rob Herring 2023-02-08 12:45 ` David Laight 2023-02-08 12:45 ` David Laight 2023-02-09 16:51 ` Palmer Dabbelt 2023-02-09 16:51 ` Palmer Dabbelt 2023-02-28 14:56 ` Rob Herring 2023-02-28 14:56 ` Rob Herring 2023-02-14 21:26 ` Conor Dooley 2023-02-14 21:26 ` Conor Dooley 2023-02-15 20:50 ` Evan Green 2023-02-15 20:50 ` Evan Green 2023-02-06 20:14 ` [PATCH v2 5/6] RISC-V: hwprobe: Support probing of " Evan Green 2023-02-06 20:14 ` Evan Green 2023-02-07 7:02 ` kernel test robot 2023-02-07 7:02 ` kernel test robot 2023-02-15 21:57 ` Conor Dooley 2023-02-15 21:57 ` Conor Dooley 2023-02-18 0:15 ` Evan Green 2023-02-18 0:15 ` Evan Green 2023-02-06 20:14 ` [PATCH v2 6/6] selftests: Test the new RISC-V hwprobe interface Evan Green 2023-02-06 20:14 ` Evan Green 2023-02-06 21:27 ` Mark Brown 2023-02-06 21:27 ` Mark Brown 2023-02-09 18:44 ` Evan Green 2023-02-09 18:44 ` Evan Green 2023-02-06 21:11 ` [PATCH v2 0/6] RISC-V Hardware Probing User Interface Jessica Clarke 2023-02-06 21:11 ` Jessica Clarke 2023-02-06 22:47 ` Heinrich Schuchardt 2023-02-06 22:47 ` Heinrich Schuchardt 2023-02-09 16:56 ` Palmer Dabbelt 2023-02-09 16:56 ` Palmer Dabbelt 2023-02-06 22:32 ` Conor Dooley 2023-02-06 22:32 ` Conor Dooley
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