* [PATCH v4 0/4] StarFive's SDIO/eMMC driver support
@ 2023-02-15 11:32 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 11:32 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
William Qiu, linux-kernel
Hi,
This patchset adds initial rudimentary support for the StarFive
designware mobile storage host controller driver. And this driver will
be used in StarFive's VisionFive 2 board. The main purpose of adding
this driver is to accommodate the ultra-high speed mode of eMMC.
The last patch should be applied after the patchset [1]:
[1] https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
Changes v3->v4:
- Added documentation to describe StarFive System Controller Registers.
- Added aon_syscon and stg_syscon node.
- Fixed some checkpatch errors/warnings.
Changes v2->v3:
- Wraped commit message according to Linux coding style.
- Rephrased the description of the patches.
- Changed the description of syscon regsiter.
- Dropped redundant properties.
Changes v1->v2:
- Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
- Changed the type of 'starfive,syscon' and modify its description.
- Deleted unused head files like '#include <linux/gpio.h>'.
- Added comment for the 'rise_point' and 'fall_point'.
- Changed the API 'num_caps' to 'common_caps'.
- Changed the node name 'sys_syscon' to 'syscon'.
- Changed the node name 'sdio' to 'mmc'.
The patch series is based on v6.1.
William Qiu (4):
dt-bindings: mmc: Add StarFive MMC module
mmc: starfive: Add sdio/emmc driver support
riscv: dts: starfive: Add mmc node
dt-bindings: syscon: Add StarFive syscon doc
.../bindings/mmc/starfive,jh7110-mmc.yaml | 77 ++++++++
.../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++
MAINTAINERS | 11 ++
.../jh7110-starfive-visionfive-2.dtsi | 23 +++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++
drivers/mmc/host/Kconfig | 10 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/dw_mmc-starfive.c | 186 ++++++++++++++++++
8 files changed, 406 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
--
2.34.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
2023-02-15 11:32 ` William Qiu
@ 2023-02-15 11:32 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 11:32 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
William Qiu, linux-kernel
Add documentation to describe StarFive designware mobile storage
host controller driver.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
new file mode 100644
index 000000000000..51e1b04e799f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive Designware Mobile Storage Host Controller
+
+description:
+ StarFive uses the Synopsys designware mobile storage host controller
+ to interface a SoC with storage medium such as eMMC or SD/MMC cards.
+
+allOf:
+ - $ref: synopsys-dw-mshc-common.yaml#
+
+maintainers:
+ - William Qiu <william.qiu@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-mmc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: biu clock
+ - description: ciu clock
+
+ clock-names:
+ items:
+ - const: biu
+ - const: ciu
+
+ interrupts:
+ maxItems: 1
+
+ starfive,sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register Controller syscon node
+ - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
+ - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
+ - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
+ description:
+ Should be four parameters, the phandle to System Register Controller
+ syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
+ for MMC controller.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - starfive,sysreg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@16010000 {
+ compatible = "starfive,jh7110-mmc";
+ reg = <0x16010000 0x10000>;
+ clocks = <&syscrg 91>,
+ <&syscrg 93>;
+ clock-names = "biu","ciu";
+ resets = <&syscrg 64>;
+ reset-names = "reset";
+ interrupts = <74>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ data-addr = <0>;
+ starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
@ 2023-02-15 11:32 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 11:32 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
William Qiu, linux-kernel
Add documentation to describe StarFive designware mobile storage
host controller driver.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
new file mode 100644
index 000000000000..51e1b04e799f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive Designware Mobile Storage Host Controller
+
+description:
+ StarFive uses the Synopsys designware mobile storage host controller
+ to interface a SoC with storage medium such as eMMC or SD/MMC cards.
+
+allOf:
+ - $ref: synopsys-dw-mshc-common.yaml#
+
+maintainers:
+ - William Qiu <william.qiu@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-mmc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: biu clock
+ - description: ciu clock
+
+ clock-names:
+ items:
+ - const: biu
+ - const: ciu
+
+ interrupts:
+ maxItems: 1
+
+ starfive,sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register Controller syscon node
+ - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
+ - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
+ - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
+ description:
+ Should be four parameters, the phandle to System Register Controller
+ syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
+ for MMC controller.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - starfive,sysreg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@16010000 {
+ compatible = "starfive,jh7110-mmc";
+ reg = <0x16010000 0x10000>;
+ clocks = <&syscrg 91>,
+ <&syscrg 93>;
+ clock-names = "biu","ciu";
+ resets = <&syscrg 64>;
+ reset-names = "reset";
+ interrupts = <74>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ data-addr = <0>;
+ starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
+ };
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
2023-02-15 11:32 ` William Qiu
@ 2023-02-15 11:59 ` Shengyu Qu
-1 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-02-15 11:59 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
Hello William,
Are you sure changing driver is better than changing yaml bindings? All
previous version sent was syscon and sysreg seems not consistent with
other codes.
Best regards,
Shengyu
> Add documentation to describe StarFive designware mobile storage
> host controller driver.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
> new file mode 100644
> index 000000000000..51e1b04e799f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive Designware Mobile Storage Host Controller
> +
> +description:
> + StarFive uses the Synopsys designware mobile storage host controller
> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
> +
> +allOf:
> + - $ref: synopsys-dw-mshc-common.yaml#
> +
> +maintainers:
> + - William Qiu <william.qiu@starfivetech.com>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-mmc
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: biu clock
> + - description: ciu clock
> +
> + clock-names:
> + items:
> + - const: biu
> + - const: ciu
> +
> + interrupts:
> + maxItems: 1
> +
> + starfive,sysreg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to System Register Controller syscon node
> + - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
> + - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
> + description:
> + Should be four parameters, the phandle to System Register Controller
> + syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
> + for MMC controller.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - starfive,sysreg
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + mmc@16010000 {
> + compatible = "starfive,jh7110-mmc";
> + reg = <0x16010000 0x10000>;
> + clocks = <&syscrg 91>,
> + <&syscrg 93>;
> + clock-names = "biu","ciu";
> + resets = <&syscrg 64>;
> + reset-names = "reset";
> + interrupts = <74>;
> + fifo-depth = <32>;
> + fifo-watermark-aligned;
> + data-addr = <0>;
> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
> + };
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
@ 2023-02-15 11:59 ` Shengyu Qu
0 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-02-15 11:59 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
Hello William,
Are you sure changing driver is better than changing yaml bindings? All
previous version sent was syscon and sysreg seems not consistent with
other codes.
Best regards,
Shengyu
> Add documentation to describe StarFive designware mobile storage
> host controller driver.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
> new file mode 100644
> index 000000000000..51e1b04e799f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive Designware Mobile Storage Host Controller
> +
> +description:
> + StarFive uses the Synopsys designware mobile storage host controller
> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
> +
> +allOf:
> + - $ref: synopsys-dw-mshc-common.yaml#
> +
> +maintainers:
> + - William Qiu <william.qiu@starfivetech.com>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-mmc
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: biu clock
> + - description: ciu clock
> +
> + clock-names:
> + items:
> + - const: biu
> + - const: ciu
> +
> + interrupts:
> + maxItems: 1
> +
> + starfive,sysreg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to System Register Controller syscon node
> + - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
> + - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
> + description:
> + Should be four parameters, the phandle to System Register Controller
> + syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
> + for MMC controller.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - starfive,sysreg
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + mmc@16010000 {
> + compatible = "starfive,jh7110-mmc";
> + reg = <0x16010000 0x10000>;
> + clocks = <&syscrg 91>,
> + <&syscrg 93>;
> + clock-names = "biu","ciu";
> + resets = <&syscrg 64>;
> + reset-names = "reset";
> + interrupts = <74>;
> + fifo-depth = <32>;
> + fifo-watermark-aligned;
> + data-addr = <0>;
> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
> + };
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
2023-02-15 11:59 ` Shengyu Qu
@ 2023-02-15 12:08 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 12:08 UTC (permalink / raw)
To: Shengyu Qu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/2/15 19:59, Shengyu Qu wrote:
> Hello William,
>
> Are you sure changing driver is better than changing yaml bindings? All
>
> previous version sent was syscon and sysreg seems not consistent with
>
> other codes.
>
> Best regards,
>
> Shengyu
>
Hi Shengyu,
After discussing with colleagues, we decided to restore the lable name to
sys_syscon, and sysreg was just a unique name for the functionality of MMC,
which will be used in all future versions.
Thanks for taking time reviewing this patch series.
Best Regards
William
>> Add documentation to describe StarFive designware mobile storage
>> host controller driver.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
>> 1 file changed, 77 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> new file mode 100644
>> index 000000000000..51e1b04e799f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> @@ -0,0 +1,77 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive Designware Mobile Storage Host Controller
>> +
>> +description:
>> + StarFive uses the Synopsys designware mobile storage host controller
>> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
>> +
>> +allOf:
>> + - $ref: synopsys-dw-mshc-common.yaml#
>> +
>> +maintainers:
>> + - William Qiu <william.qiu@starfivetech.com>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-mmc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: biu clock
>> + - description: ciu clock
>> +
>> + clock-names:
>> + items:
>> + - const: biu
>> + - const: ciu
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + starfive,sysreg:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to System Register Controller syscon node
>> + - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>> + - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>> + description:
>> + Should be four parameters, the phandle to System Register Controller
>> + syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
>> + for MMC controller.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - interrupts
>> + - starfive,sysreg
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + mmc@16010000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x16010000 0x10000>;
>> + clocks = <&syscrg 91>,
>> + <&syscrg 93>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg 64>;
>> + reset-names = "reset";
>> + interrupts = <74>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> + };
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
@ 2023-02-15 12:08 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 12:08 UTC (permalink / raw)
To: Shengyu Qu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/2/15 19:59, Shengyu Qu wrote:
> Hello William,
>
> Are you sure changing driver is better than changing yaml bindings? All
>
> previous version sent was syscon and sysreg seems not consistent with
>
> other codes.
>
> Best regards,
>
> Shengyu
>
Hi Shengyu,
After discussing with colleagues, we decided to restore the lable name to
sys_syscon, and sysreg was just a unique name for the functionality of MMC,
which will be used in all future versions.
Thanks for taking time reviewing this patch series.
Best Regards
William
>> Add documentation to describe StarFive designware mobile storage
>> host controller driver.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
>> 1 file changed, 77 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> new file mode 100644
>> index 000000000000..51e1b04e799f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> @@ -0,0 +1,77 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive Designware Mobile Storage Host Controller
>> +
>> +description:
>> + StarFive uses the Synopsys designware mobile storage host controller
>> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
>> +
>> +allOf:
>> + - $ref: synopsys-dw-mshc-common.yaml#
>> +
>> +maintainers:
>> + - William Qiu <william.qiu@starfivetech.com>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-mmc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: biu clock
>> + - description: ciu clock
>> +
>> + clock-names:
>> + items:
>> + - const: biu
>> + - const: ciu
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + starfive,sysreg:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to System Register Controller syscon node
>> + - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>> + - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>> + description:
>> + Should be four parameters, the phandle to System Register Controller
>> + syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
>> + for MMC controller.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - interrupts
>> + - starfive,sysreg
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + mmc@16010000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x16010000 0x10000>;
>> + clocks = <&syscrg 91>,
>> + <&syscrg 93>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg 64>;
>> + reset-names = "reset";
>> + interrupts = <74>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> + };
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
2023-02-15 12:08 ` William Qiu
@ 2023-02-15 16:49 ` Shengyu Qu
-1 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-02-15 16:49 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1: Type: text/plain, Size: 4296 bytes --]
Hello William,
Thanks for your reply. So there's v5 series? Btw, please fix maintainer
information:
https://patchwork.kernel.org/project/linux-riscv/patch/20230215080203.27445-1-lukas.bulwahn@gmail.com/
Best regards,
Shengyu
>
> On 2023/2/15 19:59, Shengyu Qu wrote:
>> Hello William,
>>
>> Are you sure changing driver is better than changing yaml bindings? All
>>
>> previous version sent was syscon and sysreg seems not consistent with
>>
>> other codes.
>>
>> Best regards,
>>
>> Shengyu
>>
> Hi Shengyu,
>
> After discussing with colleagues, we decided to restore the lable name to
> sys_syscon, and sysreg was just a unique name for the functionality of MMC,
> which will be used in all future versions.
>
> Thanks for taking time reviewing this patch series.
>
> Best Regards
> William
>
>>> Add documentation to describe StarFive designware mobile storage
>>> host controller driver.
>>>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> ---
>>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
>>> 1 file changed, 77 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>> new file mode 100644
>>> index 000000000000..51e1b04e799f
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>> @@ -0,0 +1,77 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: StarFive Designware Mobile Storage Host Controller
>>> +
>>> +description:
>>> + StarFive uses the Synopsys designware mobile storage host controller
>>> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
>>> +
>>> +allOf:
>>> + - $ref: synopsys-dw-mshc-common.yaml#
>>> +
>>> +maintainers:
>>> + - William Qiu <william.qiu@starfivetech.com>
>>> +
>>> +properties:
>>> + compatible:
>>> + const: starfive,jh7110-mmc
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + clocks:
>>> + items:
>>> + - description: biu clock
>>> + - description: ciu clock
>>> +
>>> + clock-names:
>>> + items:
>>> + - const: biu
>>> + - const: ciu
>>> +
>>> + interrupts:
>>> + maxItems: 1
>>> +
>>> + starfive,sysreg:
>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>> + items:
>>> + - items:
>>> + - description: phandle to System Register Controller syscon node
>>> + - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>> + - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>> + description:
>>> + Should be four parameters, the phandle to System Register Controller
>>> + syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
>>> + for MMC controller.
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - clocks
>>> + - clock-names
>>> + - interrupts
>>> + - starfive,sysreg
>>> +
>>> +unevaluatedProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + mmc@16010000 {
>>> + compatible = "starfive,jh7110-mmc";
>>> + reg = <0x16010000 0x10000>;
>>> + clocks = <&syscrg 91>,
>>> + <&syscrg 93>;
>>> + clock-names = "biu","ciu";
>>> + resets = <&syscrg 64>;
>>> + reset-names = "reset";
>>> + interrupts = <74>;
>>> + fifo-depth = <32>;
>>> + fifo-watermark-aligned;
>>> + data-addr = <0>;
>>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>>> + };
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
@ 2023-02-15 16:49 ` Shengyu Qu
0 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-02-15 16:49 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1.1: Type: text/plain, Size: 4296 bytes --]
Hello William,
Thanks for your reply. So there's v5 series? Btw, please fix maintainer
information:
https://patchwork.kernel.org/project/linux-riscv/patch/20230215080203.27445-1-lukas.bulwahn@gmail.com/
Best regards,
Shengyu
>
> On 2023/2/15 19:59, Shengyu Qu wrote:
>> Hello William,
>>
>> Are you sure changing driver is better than changing yaml bindings? All
>>
>> previous version sent was syscon and sysreg seems not consistent with
>>
>> other codes.
>>
>> Best regards,
>>
>> Shengyu
>>
> Hi Shengyu,
>
> After discussing with colleagues, we decided to restore the lable name to
> sys_syscon, and sysreg was just a unique name for the functionality of MMC,
> which will be used in all future versions.
>
> Thanks for taking time reviewing this patch series.
>
> Best Regards
> William
>
>>> Add documentation to describe StarFive designware mobile storage
>>> host controller driver.
>>>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> ---
>>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
>>> 1 file changed, 77 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>> new file mode 100644
>>> index 000000000000..51e1b04e799f
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>> @@ -0,0 +1,77 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: StarFive Designware Mobile Storage Host Controller
>>> +
>>> +description:
>>> + StarFive uses the Synopsys designware mobile storage host controller
>>> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
>>> +
>>> +allOf:
>>> + - $ref: synopsys-dw-mshc-common.yaml#
>>> +
>>> +maintainers:
>>> + - William Qiu <william.qiu@starfivetech.com>
>>> +
>>> +properties:
>>> + compatible:
>>> + const: starfive,jh7110-mmc
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + clocks:
>>> + items:
>>> + - description: biu clock
>>> + - description: ciu clock
>>> +
>>> + clock-names:
>>> + items:
>>> + - const: biu
>>> + - const: ciu
>>> +
>>> + interrupts:
>>> + maxItems: 1
>>> +
>>> + starfive,sysreg:
>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>> + items:
>>> + - items:
>>> + - description: phandle to System Register Controller syscon node
>>> + - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>> + - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>> + description:
>>> + Should be four parameters, the phandle to System Register Controller
>>> + syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
>>> + for MMC controller.
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - clocks
>>> + - clock-names
>>> + - interrupts
>>> + - starfive,sysreg
>>> +
>>> +unevaluatedProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + mmc@16010000 {
>>> + compatible = "starfive,jh7110-mmc";
>>> + reg = <0x16010000 0x10000>;
>>> + clocks = <&syscrg 91>,
>>> + <&syscrg 93>;
>>> + clock-names = "biu","ciu";
>>> + resets = <&syscrg 64>;
>>> + reset-names = "reset";
>>> + interrupts = <74>;
>>> + fifo-depth = <32>;
>>> + fifo-watermark-aligned;
>>> + data-addr = <0>;
>>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>>> + };
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
[parent not found: <202302160545.31G5jiuf087662@SH1-CSMTP-DB111.sundns.com>]
* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
[not found] ` <202302160545.31G5jiuf087662@SH1-CSMTP-DB111.sundns.com>
@ 2023-02-16 5:51 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-16 5:51 UTC (permalink / raw)
To: Shengyu Qu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/2/16 0:49, Shengyu Qu wrote:
> Hello William,
>
> Thanks for your reply. So there's v5 series? Btw, please fix maintainer information:
>
> https://patchwork.kernel.org/project/linux-riscv/patch/20230215080203.27445-1-lukas.bulwahn@gmail.com/
>
> Best regards,
>
> Shengyu
>
Hi Shengyu,
Here is v4 series, and I fixed the maintainer information in this series which
Uffe would merge in his next branch.
Thanks for taking time to review this patch series.
Best Regards
William
>>
>> On 2023/2/15 19:59, Shengyu Qu wrote:
>>> Hello William,
>>>
>>> Are you sure changing driver is better than changing yaml bindings? All
>>>
>>> previous version sent was syscon and sysreg seems not consistent with
>>>
>>> other codes.
>>>
>>> Best regards,
>>>
>>> Shengyu
>>>
>> Hi Shengyu,
>>
>> After discussing with colleagues, we decided to restore the lable name to
>> sys_syscon, and sysreg was just a unique name for the functionality of MMC,
>> which will be used in all future versions.
>>
>> Thanks for taking time reviewing this patch series.
>>
>> Best Regards
>> William
>>
>>>> Add documentation to describe StarFive designware mobile storage
>>>> host controller driver.
>>>>
>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> ---
>>>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
>>>> 1 file changed, 77 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>>> new file mode 100644
>>>> index 000000000000..51e1b04e799f
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>>> @@ -0,0 +1,77 @@
>>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: StarFive Designware Mobile Storage Host Controller
>>>> +
>>>> +description:
>>>> + StarFive uses the Synopsys designware mobile storage host controller
>>>> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
>>>> +
>>>> +allOf:
>>>> + - $ref: synopsys-dw-mshc-common.yaml#
>>>> +
>>>> +maintainers:
>>>> + - William Qiu <william.qiu@starfivetech.com>
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + const: starfive,jh7110-mmc
>>>> +
>>>> + reg:
>>>> + maxItems: 1
>>>> +
>>>> + clocks:
>>>> + items:
>>>> + - description: biu clock
>>>> + - description: ciu clock
>>>> +
>>>> + clock-names:
>>>> + items:
>>>> + - const: biu
>>>> + - const: ciu
>>>> +
>>>> + interrupts:
>>>> + maxItems: 1
>>>> +
>>>> + starfive,sysreg:
>>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>>> + items:
>>>> + - items:
>>>> + - description: phandle to System Register Controller syscon node
>>>> + - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>>> + - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>>> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>>> + description:
>>>> + Should be four parameters, the phandle to System Register Controller
>>>> + syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
>>>> + for MMC controller.
>>>> +
>>>> +required:
>>>> + - compatible
>>>> + - reg
>>>> + - clocks
>>>> + - clock-names
>>>> + - interrupts
>>>> + - starfive,sysreg
>>>> +
>>>> +unevaluatedProperties: false
>>>> +
>>>> +examples:
>>>> + - |
>>>> + mmc@16010000 {
>>>> + compatible = "starfive,jh7110-mmc";
>>>> + reg = <0x16010000 0x10000>;
>>>> + clocks = <&syscrg 91>,
>>>> + <&syscrg 93>;
>>>> + clock-names = "biu","ciu";
>>>> + resets = <&syscrg 64>;
>>>> + reset-names = "reset";
>>>> + interrupts = <74>;
>>>> + fifo-depth = <32>;
>>>> + fifo-watermark-aligned;
>>>> + data-addr = <0>;
>>>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>>>> + };
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
@ 2023-02-16 5:51 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-16 5:51 UTC (permalink / raw)
To: Shengyu Qu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/2/16 0:49, Shengyu Qu wrote:
> Hello William,
>
> Thanks for your reply. So there's v5 series? Btw, please fix maintainer information:
>
> https://patchwork.kernel.org/project/linux-riscv/patch/20230215080203.27445-1-lukas.bulwahn@gmail.com/
>
> Best regards,
>
> Shengyu
>
Hi Shengyu,
Here is v4 series, and I fixed the maintainer information in this series which
Uffe would merge in his next branch.
Thanks for taking time to review this patch series.
Best Regards
William
>>
>> On 2023/2/15 19:59, Shengyu Qu wrote:
>>> Hello William,
>>>
>>> Are you sure changing driver is better than changing yaml bindings? All
>>>
>>> previous version sent was syscon and sysreg seems not consistent with
>>>
>>> other codes.
>>>
>>> Best regards,
>>>
>>> Shengyu
>>>
>> Hi Shengyu,
>>
>> After discussing with colleagues, we decided to restore the lable name to
>> sys_syscon, and sysreg was just a unique name for the functionality of MMC,
>> which will be used in all future versions.
>>
>> Thanks for taking time reviewing this patch series.
>>
>> Best Regards
>> William
>>
>>>> Add documentation to describe StarFive designware mobile storage
>>>> host controller driver.
>>>>
>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> ---
>>>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
>>>> 1 file changed, 77 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>>> new file mode 100644
>>>> index 000000000000..51e1b04e799f
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>>> @@ -0,0 +1,77 @@
>>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: StarFive Designware Mobile Storage Host Controller
>>>> +
>>>> +description:
>>>> + StarFive uses the Synopsys designware mobile storage host controller
>>>> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
>>>> +
>>>> +allOf:
>>>> + - $ref: synopsys-dw-mshc-common.yaml#
>>>> +
>>>> +maintainers:
>>>> + - William Qiu <william.qiu@starfivetech.com>
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + const: starfive,jh7110-mmc
>>>> +
>>>> + reg:
>>>> + maxItems: 1
>>>> +
>>>> + clocks:
>>>> + items:
>>>> + - description: biu clock
>>>> + - description: ciu clock
>>>> +
>>>> + clock-names:
>>>> + items:
>>>> + - const: biu
>>>> + - const: ciu
>>>> +
>>>> + interrupts:
>>>> + maxItems: 1
>>>> +
>>>> + starfive,sysreg:
>>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>>> + items:
>>>> + - items:
>>>> + - description: phandle to System Register Controller syscon node
>>>> + - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>>> + - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>>> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller
>>>> + description:
>>>> + Should be four parameters, the phandle to System Register Controller
>>>> + syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register
>>>> + for MMC controller.
>>>> +
>>>> +required:
>>>> + - compatible
>>>> + - reg
>>>> + - clocks
>>>> + - clock-names
>>>> + - interrupts
>>>> + - starfive,sysreg
>>>> +
>>>> +unevaluatedProperties: false
>>>> +
>>>> +examples:
>>>> + - |
>>>> + mmc@16010000 {
>>>> + compatible = "starfive,jh7110-mmc";
>>>> + reg = <0x16010000 0x10000>;
>>>> + clocks = <&syscrg 91>,
>>>> + <&syscrg 93>;
>>>> + clock-names = "biu","ciu";
>>>> + resets = <&syscrg 64>;
>>>> + reset-names = "reset";
>>>> + interrupts = <74>;
>>>> + fifo-depth = <32>;
>>>> + fifo-watermark-aligned;
>>>> + data-addr = <0>;
>>>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>>>> + };
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
2023-02-15 11:59 ` Shengyu Qu
@ 2023-02-16 10:21 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-16 10:21 UTC (permalink / raw)
To: Shengyu Qu, William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 15/02/2023 12:59, Shengyu Qu wrote:
> Hello William,
>
> Are you sure changing driver is better than changing yaml bindings? All
What do you mean - changing driver? This is new driver, new code, isn't it?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
@ 2023-02-16 10:21 ` Krzysztof Kozlowski
0 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-16 10:21 UTC (permalink / raw)
To: Shengyu Qu, William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 15/02/2023 12:59, Shengyu Qu wrote:
> Hello William,
>
> Are you sure changing driver is better than changing yaml bindings? All
What do you mean - changing driver? This is new driver, new code, isn't it?
Best regards,
Krzysztof
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
2023-02-16 10:21 ` Krzysztof Kozlowski
@ 2023-02-16 10:31 ` Conor Dooley
-1 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-02-16 10:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Shengyu Qu, William Qiu, linux-riscv, devicetree, linux-mmc,
Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
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On Thu, Feb 16, 2023 at 11:21:16AM +0100, Krzysztof Kozlowski wrote:
> On 15/02/2023 12:59, Shengyu Qu wrote:
> > Hello William,
> >
> > Are you sure changing driver is better than changing yaml bindings? All
>
> What do you mean - changing driver? This is new driver, new code, isn't it?
Changing w.r.t. the v3 that was applied I suppose.
The v3 was dropped and patches 1 & 2 here have been applied instead, so
this request from Shengyu is moot now anyway.
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
@ 2023-02-16 10:31 ` Conor Dooley
0 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-02-16 10:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Shengyu Qu, William Qiu, linux-riscv, devicetree, linux-mmc,
Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
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On Thu, Feb 16, 2023 at 11:21:16AM +0100, Krzysztof Kozlowski wrote:
> On 15/02/2023 12:59, Shengyu Qu wrote:
> > Hello William,
> >
> > Are you sure changing driver is better than changing yaml bindings? All
>
> What do you mean - changing driver? This is new driver, new code, isn't it?
Changing w.r.t. the v3 that was applied I suppose.
The v3 was dropped and patches 1 & 2 here have been applied instead, so
this request from Shengyu is moot now anyway.
Cheers,
Conor.
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
2023-02-16 10:31 ` Conor Dooley
@ 2023-02-16 10:39 ` Shengyu Qu
-1 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-02-16 10:39 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski
Cc: William Qiu, linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
[-- Attachment #1.1.1: Type: text/plain, Size: 588 bytes --]
> On Thu, Feb 16, 2023 at 11:21:16AM +0100, Krzysztof Kozlowski wrote:
>> On 15/02/2023 12:59, Shengyu Qu wrote:
>>> Hello William,
>>>
>>> Are you sure changing driver is better than changing yaml bindings? All
>> What do you mean - changing driver? This is new driver, new code, isn't it?
> Changing w.r.t. the v3 that was applied I suppose.
> The v3 was dropped and patches 1 & 2 here have been applied instead, so
> this request from Shengyu is moot now anyway.
>
> Cheers,
> Conor.
That's my mistake. I misunderstood current situation :(
Best regards,
Shengyu
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^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
@ 2023-02-16 10:39 ` Shengyu Qu
0 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-02-16 10:39 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski
Cc: William Qiu, linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
[-- Attachment #1.1.1.1: Type: text/plain, Size: 588 bytes --]
> On Thu, Feb 16, 2023 at 11:21:16AM +0100, Krzysztof Kozlowski wrote:
>> On 15/02/2023 12:59, Shengyu Qu wrote:
>>> Hello William,
>>>
>>> Are you sure changing driver is better than changing yaml bindings? All
>> What do you mean - changing driver? This is new driver, new code, isn't it?
> Changing w.r.t. the v3 that was applied I suppose.
> The v3 was dropped and patches 1 & 2 here have been applied instead, so
> this request from Shengyu is moot now anyway.
>
> Cheers,
> Conor.
That's my mistake. I misunderstood current situation :(
Best regards,
Shengyu
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
[parent not found: <a7b51602-3ba4-d822-4da0-f6e51e7dddea@outlook.com>]
* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
[not found] ` <a7b51602-3ba4-d822-4da0-f6e51e7dddea@outlook.com>
@ 2023-02-15 12:03 ` Shengyu Qu
0 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-02-15 12:03 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1: Type: text/plain, Size: 3740 bytes --]
Sorry, forgot what I said. I didn't see Krzysztof's reply on V3 serires.
Best regards,
Shengyu
> Hello William,
>
> Are you sure changing driver is better than changing yaml bindings? All
>
> previous version sent was syscon and sysreg seems not consistent with
>
> other codes.
>
> Best regards,
>
> Shengyu
>
>> Add documentation to describe StarFive designware mobile storage
>> host controller driver.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
>> 1 file changed, 77 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> new file mode 100644
>> index 000000000000..51e1b04e799f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> @@ -0,0 +1,77 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive Designware Mobile Storage Host Controller
>> +
>> +description:
>> + StarFive uses the Synopsys designware mobile storage host controller
>> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
>> +
>> +allOf:
>> + - $ref: synopsys-dw-mshc-common.yaml#
>> +
>> +maintainers:
>> + - William Qiu <william.qiu@starfivetech.com>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-mmc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: biu clock
>> + - description: ciu clock
>> +
>> + clock-names:
>> + items:
>> + - const: biu
>> + - const: ciu
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + starfive,sysreg:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to System Register Controller
>> syscon node
>> + - description: offset of SYS_SYSCONSAIF__SYSCFG register
>> for MMC controller
>> + - description: shift of SYS_SYSCONSAIF__SYSCFG register
>> for MMC controller
>> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for
>> MMC controller
>> + description:
>> + Should be four parameters, the phandle to System Register
>> Controller
>> + syscon node and the offset/shift/mask of
>> SYS_SYSCONSAIF__SYSCFG register
>> + for MMC controller.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - interrupts
>> + - starfive,sysreg
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + mmc@16010000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x16010000 0x10000>;
>> + clocks = <&syscrg 91>,
>> + <&syscrg 93>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg 64>;
>> + reset-names = "reset";
>> + interrupts = <74>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> + };
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 1/4] dt-bindings: mmc: Add StarFive MMC module
@ 2023-02-15 12:03 ` Shengyu Qu
0 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-02-15 12:03 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1.1: Type: text/plain, Size: 3740 bytes --]
Sorry, forgot what I said. I didn't see Krzysztof's reply on V3 serires.
Best regards,
Shengyu
> Hello William,
>
> Are you sure changing driver is better than changing yaml bindings? All
>
> previous version sent was syscon and sysreg seems not consistent with
>
> other codes.
>
> Best regards,
>
> Shengyu
>
>> Add documentation to describe StarFive designware mobile storage
>> host controller driver.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 +++++++++++++++++++
>> 1 file changed, 77 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> new file mode 100644
>> index 000000000000..51e1b04e799f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> @@ -0,0 +1,77 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive Designware Mobile Storage Host Controller
>> +
>> +description:
>> + StarFive uses the Synopsys designware mobile storage host controller
>> + to interface a SoC with storage medium such as eMMC or SD/MMC cards.
>> +
>> +allOf:
>> + - $ref: synopsys-dw-mshc-common.yaml#
>> +
>> +maintainers:
>> + - William Qiu <william.qiu@starfivetech.com>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-mmc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: biu clock
>> + - description: ciu clock
>> +
>> + clock-names:
>> + items:
>> + - const: biu
>> + - const: ciu
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + starfive,sysreg:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to System Register Controller
>> syscon node
>> + - description: offset of SYS_SYSCONSAIF__SYSCFG register
>> for MMC controller
>> + - description: shift of SYS_SYSCONSAIF__SYSCFG register
>> for MMC controller
>> + - description: mask of SYS_SYSCONSAIF__SYSCFG register for
>> MMC controller
>> + description:
>> + Should be four parameters, the phandle to System Register
>> Controller
>> + syscon node and the offset/shift/mask of
>> SYS_SYSCONSAIF__SYSCFG register
>> + for MMC controller.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - interrupts
>> + - starfive,sysreg
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + mmc@16010000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x16010000 0x10000>;
>> + clocks = <&syscrg 91>,
>> + <&syscrg 93>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg 64>;
>> + reset-names = "reset";
>> + interrupts = <74>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> + };
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_______________________________________________
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^ permalink raw reply [flat|nested] 94+ messages in thread
* [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
2023-02-15 11:32 ` William Qiu
@ 2023-02-15 11:32 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 11:32 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
William Qiu, linux-kernel
Add sdio/emmc driver support for StarFive JH7110 soc.
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
MAINTAINERS | 6 +
drivers/mmc/host/Kconfig | 10 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
4 files changed, 203 insertions(+)
create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 85e8f83161d7..644ac9479a6e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19640,6 +19640,12 @@ F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
F: drivers/clk/starfive/clk-starfive-jh71*
F: include/dt-bindings/clock/starfive?jh71*.h
+STARFIVE JH7110 MMC/SD/SDIO DRIVER
+M: William Qiu <william.qiu@starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/mmc/starfive*
+F: drivers/mmc/host/dw_mmc-starfive.c
+
STARFIVE JH71X0 PINCTRL DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
M: Jianlong Huang <jianlong.huang@starfivetech.com>
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index fb1062a6394c..b87262503403 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -871,6 +871,16 @@ config MMC_DW_ROCKCHIP
Synopsys DesignWare Memory Card Interface driver. Select this option
for platforms based on RK3066, RK3188 and RK3288 SoC's.
+config MMC_DW_STARFIVE
+ tristate "StarFive specific extensions for Synopsys DW Memory Card Interface"
+ depends on SOC_STARFIVE
+ depends on MMC_DW
+ select MMC_DW_PLTFM
+ help
+ This selects support for StarFive JH7110 SoC specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on StarFive JH7110 SoC.
+
config MMC_SH_MMCIF
tristate "SuperH Internal MMCIF support"
depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 4e4ceb32c4b4..32c0e5564b9a 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
+obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
obj-$(CONFIG_MMC_VUB300) += vub300.o
diff --git a/drivers/mmc/host/dw_mmc-starfive.c b/drivers/mmc/host/dw_mmc-starfive.c
new file mode 100644
index 000000000000..40f5969b07a6
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc-starfive.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive Designware Mobile Storage Host Controller Driver
+ *
+ * Copyright (c) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mmc/host.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "dw_mmc.h"
+#include "dw_mmc-pltfm.h"
+
+#define ALL_INT_CLR 0x1ffff
+#define MAX_DELAY_CHAIN 32
+
+struct starfive_priv {
+ struct device *dev;
+ struct regmap *reg_syscon;
+ u32 syscon_offset;
+ u32 syscon_shift;
+ u32 syscon_mask;
+};
+
+static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
+{
+ int ret;
+ unsigned int clock;
+
+ if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
+ clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
+ ret = clk_set_rate(host->ciu_clk, clock);
+ if (ret)
+ dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
+ host->bus_hz = clk_get_rate(host->ciu_clk);
+ } else {
+ dev_dbg(host->dev, "Using the internal divider\n");
+ }
+}
+
+static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
+ u32 opcode)
+{
+ static const int grade = MAX_DELAY_CHAIN;
+ struct dw_mci *host = slot->host;
+ struct starfive_priv *priv = host->priv;
+ int rise_point = -1, fall_point = -1;
+ int err, prev_err;
+ int i;
+ bool found = 0;
+ u32 regval;
+
+ /*
+ * Use grade as the max delay chain, and use the rise_point and
+ * fall_point to ensure the best sampling point of a data input
+ * signals.
+ */
+ for (i = 0; i < grade; i++) {
+ regval = i << priv->syscon_shift;
+ err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
+ priv->syscon_mask, regval);
+ if (err)
+ return err;
+ mci_writel(host, RINTSTS, ALL_INT_CLR);
+
+ err = mmc_send_tuning(slot->mmc, opcode, NULL);
+ if (!err)
+ found = 1;
+
+ if (i > 0) {
+ if (err && !prev_err)
+ fall_point = i - 1;
+ if (!err && prev_err)
+ rise_point = i;
+ }
+
+ if (rise_point != -1 && fall_point != -1)
+ goto tuning_out;
+
+ prev_err = err;
+ err = 0;
+ }
+
+tuning_out:
+ if (found) {
+ if (rise_point == -1)
+ rise_point = 0;
+ if (fall_point == -1)
+ fall_point = grade - 1;
+ if (fall_point < rise_point) {
+ if ((rise_point + fall_point) >
+ (grade - 1))
+ i = fall_point / 2;
+ else
+ i = (rise_point + grade - 1) / 2;
+ } else {
+ i = (rise_point + fall_point) / 2;
+ }
+
+ regval = i << priv->syscon_shift;
+ err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
+ priv->syscon_mask, regval);
+ if (err)
+ return err;
+ mci_writel(host, RINTSTS, ALL_INT_CLR);
+
+ dev_info(host->dev, "Found valid delay chain! use it [delay=%d]\n", i);
+ } else {
+ dev_err(host->dev, "No valid delay chain! use default\n");
+ err = -EINVAL;
+ }
+
+ mci_writel(host, RINTSTS, ALL_INT_CLR);
+ return err;
+}
+
+static int dw_mci_starfive_parse_dt(struct dw_mci *host)
+{
+ struct of_phandle_args args;
+ struct starfive_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
+ "starfive,sysreg", 3, 0, &args);
+ if (ret) {
+ dev_err(host->dev, "Failed to parse starfive,sysreg\n");
+ return -EINVAL;
+ }
+
+ priv->reg_syscon = syscon_node_to_regmap(args.np);
+ of_node_put(args.np);
+ if (IS_ERR(priv->reg_syscon))
+ return PTR_ERR(priv->reg_syscon);
+
+ priv->syscon_offset = args.args[0];
+ priv->syscon_shift = args.args[1];
+ priv->syscon_mask = args.args[2];
+
+ host->priv = priv;
+
+ return 0;
+}
+
+static const struct dw_mci_drv_data starfive_data = {
+ .common_caps = MMC_CAP_CMD23,
+ .set_ios = dw_mci_starfive_set_ios,
+ .parse_dt = dw_mci_starfive_parse_dt,
+ .execute_tuning = dw_mci_starfive_execute_tuning,
+};
+
+static const struct of_device_id dw_mci_starfive_match[] = {
+ { .compatible = "starfive,jh7110-mmc",
+ .data = &starfive_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
+
+static int dw_mci_starfive_probe(struct platform_device *pdev)
+{
+ return dw_mci_pltfm_register(pdev, &starfive_data);
+}
+
+static struct platform_driver dw_mci_starfive_driver = {
+ .probe = dw_mci_starfive_probe,
+ .remove = dw_mci_pltfm_remove,
+ .driver = {
+ .name = "dwmmc_starfive",
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ .of_match_table = dw_mci_starfive_match,
+ },
+};
+module_platform_driver(dw_mci_starfive_driver);
+
+MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dwmmc_starfive");
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
@ 2023-02-15 11:32 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 11:32 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
William Qiu, linux-kernel
Add sdio/emmc driver support for StarFive JH7110 soc.
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
MAINTAINERS | 6 +
drivers/mmc/host/Kconfig | 10 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
4 files changed, 203 insertions(+)
create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 85e8f83161d7..644ac9479a6e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19640,6 +19640,12 @@ F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
F: drivers/clk/starfive/clk-starfive-jh71*
F: include/dt-bindings/clock/starfive?jh71*.h
+STARFIVE JH7110 MMC/SD/SDIO DRIVER
+M: William Qiu <william.qiu@starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/mmc/starfive*
+F: drivers/mmc/host/dw_mmc-starfive.c
+
STARFIVE JH71X0 PINCTRL DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
M: Jianlong Huang <jianlong.huang@starfivetech.com>
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index fb1062a6394c..b87262503403 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -871,6 +871,16 @@ config MMC_DW_ROCKCHIP
Synopsys DesignWare Memory Card Interface driver. Select this option
for platforms based on RK3066, RK3188 and RK3288 SoC's.
+config MMC_DW_STARFIVE
+ tristate "StarFive specific extensions for Synopsys DW Memory Card Interface"
+ depends on SOC_STARFIVE
+ depends on MMC_DW
+ select MMC_DW_PLTFM
+ help
+ This selects support for StarFive JH7110 SoC specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on StarFive JH7110 SoC.
+
config MMC_SH_MMCIF
tristate "SuperH Internal MMCIF support"
depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 4e4ceb32c4b4..32c0e5564b9a 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
+obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
obj-$(CONFIG_MMC_VUB300) += vub300.o
diff --git a/drivers/mmc/host/dw_mmc-starfive.c b/drivers/mmc/host/dw_mmc-starfive.c
new file mode 100644
index 000000000000..40f5969b07a6
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc-starfive.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive Designware Mobile Storage Host Controller Driver
+ *
+ * Copyright (c) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mmc/host.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "dw_mmc.h"
+#include "dw_mmc-pltfm.h"
+
+#define ALL_INT_CLR 0x1ffff
+#define MAX_DELAY_CHAIN 32
+
+struct starfive_priv {
+ struct device *dev;
+ struct regmap *reg_syscon;
+ u32 syscon_offset;
+ u32 syscon_shift;
+ u32 syscon_mask;
+};
+
+static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
+{
+ int ret;
+ unsigned int clock;
+
+ if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
+ clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
+ ret = clk_set_rate(host->ciu_clk, clock);
+ if (ret)
+ dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
+ host->bus_hz = clk_get_rate(host->ciu_clk);
+ } else {
+ dev_dbg(host->dev, "Using the internal divider\n");
+ }
+}
+
+static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
+ u32 opcode)
+{
+ static const int grade = MAX_DELAY_CHAIN;
+ struct dw_mci *host = slot->host;
+ struct starfive_priv *priv = host->priv;
+ int rise_point = -1, fall_point = -1;
+ int err, prev_err;
+ int i;
+ bool found = 0;
+ u32 regval;
+
+ /*
+ * Use grade as the max delay chain, and use the rise_point and
+ * fall_point to ensure the best sampling point of a data input
+ * signals.
+ */
+ for (i = 0; i < grade; i++) {
+ regval = i << priv->syscon_shift;
+ err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
+ priv->syscon_mask, regval);
+ if (err)
+ return err;
+ mci_writel(host, RINTSTS, ALL_INT_CLR);
+
+ err = mmc_send_tuning(slot->mmc, opcode, NULL);
+ if (!err)
+ found = 1;
+
+ if (i > 0) {
+ if (err && !prev_err)
+ fall_point = i - 1;
+ if (!err && prev_err)
+ rise_point = i;
+ }
+
+ if (rise_point != -1 && fall_point != -1)
+ goto tuning_out;
+
+ prev_err = err;
+ err = 0;
+ }
+
+tuning_out:
+ if (found) {
+ if (rise_point == -1)
+ rise_point = 0;
+ if (fall_point == -1)
+ fall_point = grade - 1;
+ if (fall_point < rise_point) {
+ if ((rise_point + fall_point) >
+ (grade - 1))
+ i = fall_point / 2;
+ else
+ i = (rise_point + grade - 1) / 2;
+ } else {
+ i = (rise_point + fall_point) / 2;
+ }
+
+ regval = i << priv->syscon_shift;
+ err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
+ priv->syscon_mask, regval);
+ if (err)
+ return err;
+ mci_writel(host, RINTSTS, ALL_INT_CLR);
+
+ dev_info(host->dev, "Found valid delay chain! use it [delay=%d]\n", i);
+ } else {
+ dev_err(host->dev, "No valid delay chain! use default\n");
+ err = -EINVAL;
+ }
+
+ mci_writel(host, RINTSTS, ALL_INT_CLR);
+ return err;
+}
+
+static int dw_mci_starfive_parse_dt(struct dw_mci *host)
+{
+ struct of_phandle_args args;
+ struct starfive_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
+ "starfive,sysreg", 3, 0, &args);
+ if (ret) {
+ dev_err(host->dev, "Failed to parse starfive,sysreg\n");
+ return -EINVAL;
+ }
+
+ priv->reg_syscon = syscon_node_to_regmap(args.np);
+ of_node_put(args.np);
+ if (IS_ERR(priv->reg_syscon))
+ return PTR_ERR(priv->reg_syscon);
+
+ priv->syscon_offset = args.args[0];
+ priv->syscon_shift = args.args[1];
+ priv->syscon_mask = args.args[2];
+
+ host->priv = priv;
+
+ return 0;
+}
+
+static const struct dw_mci_drv_data starfive_data = {
+ .common_caps = MMC_CAP_CMD23,
+ .set_ios = dw_mci_starfive_set_ios,
+ .parse_dt = dw_mci_starfive_parse_dt,
+ .execute_tuning = dw_mci_starfive_execute_tuning,
+};
+
+static const struct of_device_id dw_mci_starfive_match[] = {
+ { .compatible = "starfive,jh7110-mmc",
+ .data = &starfive_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
+
+static int dw_mci_starfive_probe(struct platform_device *pdev)
+{
+ return dw_mci_pltfm_register(pdev, &starfive_data);
+}
+
+static struct platform_driver dw_mci_starfive_driver = {
+ .probe = dw_mci_starfive_probe,
+ .remove = dw_mci_pltfm_remove,
+ .driver = {
+ .name = "dwmmc_starfive",
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ .of_match_table = dw_mci_starfive_match,
+ },
+};
+module_platform_driver(dw_mci_starfive_driver);
+
+MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dwmmc_starfive");
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
2023-02-15 11:32 ` William Qiu
@ 2023-03-27 16:01 ` Shengyu Qu
-1 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-03-27 16:01 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1: Type: text/plain, Size: 8892 bytes --]
Hello William,
I'm digging into downstream mmc driver these days and found a problem
that current version mainline driver doesn't has a voltage switch
function for
it. Downstream older version has one but was deleted in this commit [1].
It was deleted since vf2's SD slot doesn't have 1.8V input but commiter
forgot
that vf2's eMMC slot has a proper 1.8V input.
So could you add voltage switch function for mainline? I've met a eMMC speed
problem possibly due to it.
Best regards,
Shengyu
[1]
https://github.com/starfive-tech/linux/commit/8037d59091d276e74be38e5fafaaebe36eaa77e1
在 2023/2/15 19:32, William Qiu 写道:
> Add sdio/emmc driver support for StarFive JH7110 soc.
>
> Tested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
> MAINTAINERS | 6 +
> drivers/mmc/host/Kconfig | 10 ++
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
> 4 files changed, 203 insertions(+)
> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 85e8f83161d7..644ac9479a6e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19640,6 +19640,12 @@ F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
> F: drivers/clk/starfive/clk-starfive-jh71*
> F: include/dt-bindings/clock/starfive?jh71*.h
>
> +STARFIVE JH7110 MMC/SD/SDIO DRIVER
> +M: William Qiu <william.qiu@starfivetech.com>
> +S: Supported
> +F: Documentation/devicetree/bindings/mmc/starfive*
> +F: drivers/mmc/host/dw_mmc-starfive.c
> +
> STARFIVE JH71X0 PINCTRL DRIVERS
> M: Emil Renner Berthing <kernel@esmil.dk>
> M: Jianlong Huang <jianlong.huang@starfivetech.com>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index fb1062a6394c..b87262503403 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -871,6 +871,16 @@ config MMC_DW_ROCKCHIP
> Synopsys DesignWare Memory Card Interface driver. Select this option
> for platforms based on RK3066, RK3188 and RK3288 SoC's.
>
> +config MMC_DW_STARFIVE
> + tristate "StarFive specific extensions for Synopsys DW Memory Card Interface"
> + depends on SOC_STARFIVE
> + depends on MMC_DW
> + select MMC_DW_PLTFM
> + help
> + This selects support for StarFive JH7110 SoC specific extensions to the
> + Synopsys DesignWare Memory Card Interface driver. Select this option
> + for platforms based on StarFive JH7110 SoC.
> +
> config MMC_SH_MMCIF
> tristate "SuperH Internal MMCIF support"
> depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 4e4ceb32c4b4..32c0e5564b9a 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
> obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
> obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
> obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
> +obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
> obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
> obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
> obj-$(CONFIG_MMC_VUB300) += vub300.o
> diff --git a/drivers/mmc/host/dw_mmc-starfive.c b/drivers/mmc/host/dw_mmc-starfive.c
> new file mode 100644
> index 000000000000..40f5969b07a6
> --- /dev/null
> +++ b/drivers/mmc/host/dw_mmc-starfive.c
> @@ -0,0 +1,186 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * StarFive Designware Mobile Storage Host Controller Driver
> + *
> + * Copyright (c) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mmc/host.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "dw_mmc.h"
> +#include "dw_mmc-pltfm.h"
> +
> +#define ALL_INT_CLR 0x1ffff
> +#define MAX_DELAY_CHAIN 32
> +
> +struct starfive_priv {
> + struct device *dev;
> + struct regmap *reg_syscon;
> + u32 syscon_offset;
> + u32 syscon_shift;
> + u32 syscon_mask;
> +};
> +
> +static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
> +{
> + int ret;
> + unsigned int clock;
> +
> + if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
> + clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
> + ret = clk_set_rate(host->ciu_clk, clock);
> + if (ret)
> + dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
> + host->bus_hz = clk_get_rate(host->ciu_clk);
> + } else {
> + dev_dbg(host->dev, "Using the internal divider\n");
> + }
> +}
> +
> +static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
> + u32 opcode)
> +{
> + static const int grade = MAX_DELAY_CHAIN;
> + struct dw_mci *host = slot->host;
> + struct starfive_priv *priv = host->priv;
> + int rise_point = -1, fall_point = -1;
> + int err, prev_err;
> + int i;
> + bool found = 0;
> + u32 regval;
> +
> + /*
> + * Use grade as the max delay chain, and use the rise_point and
> + * fall_point to ensure the best sampling point of a data input
> + * signals.
> + */
> + for (i = 0; i < grade; i++) {
> + regval = i << priv->syscon_shift;
> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
> + priv->syscon_mask, regval);
> + if (err)
> + return err;
> + mci_writel(host, RINTSTS, ALL_INT_CLR);
> +
> + err = mmc_send_tuning(slot->mmc, opcode, NULL);
> + if (!err)
> + found = 1;
> +
> + if (i > 0) {
> + if (err && !prev_err)
> + fall_point = i - 1;
> + if (!err && prev_err)
> + rise_point = i;
> + }
> +
> + if (rise_point != -1 && fall_point != -1)
> + goto tuning_out;
> +
> + prev_err = err;
> + err = 0;
> + }
> +
> +tuning_out:
> + if (found) {
> + if (rise_point == -1)
> + rise_point = 0;
> + if (fall_point == -1)
> + fall_point = grade - 1;
> + if (fall_point < rise_point) {
> + if ((rise_point + fall_point) >
> + (grade - 1))
> + i = fall_point / 2;
> + else
> + i = (rise_point + grade - 1) / 2;
> + } else {
> + i = (rise_point + fall_point) / 2;
> + }
> +
> + regval = i << priv->syscon_shift;
> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
> + priv->syscon_mask, regval);
> + if (err)
> + return err;
> + mci_writel(host, RINTSTS, ALL_INT_CLR);
> +
> + dev_info(host->dev, "Found valid delay chain! use it [delay=%d]\n", i);
> + } else {
> + dev_err(host->dev, "No valid delay chain! use default\n");
> + err = -EINVAL;
> + }
> +
> + mci_writel(host, RINTSTS, ALL_INT_CLR);
> + return err;
> +}
> +
> +static int dw_mci_starfive_parse_dt(struct dw_mci *host)
> +{
> + struct of_phandle_args args;
> + struct starfive_priv *priv;
> + int ret;
> +
> + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
> + "starfive,sysreg", 3, 0, &args);
> + if (ret) {
> + dev_err(host->dev, "Failed to parse starfive,sysreg\n");
> + return -EINVAL;
> + }
> +
> + priv->reg_syscon = syscon_node_to_regmap(args.np);
> + of_node_put(args.np);
> + if (IS_ERR(priv->reg_syscon))
> + return PTR_ERR(priv->reg_syscon);
> +
> + priv->syscon_offset = args.args[0];
> + priv->syscon_shift = args.args[1];
> + priv->syscon_mask = args.args[2];
> +
> + host->priv = priv;
> +
> + return 0;
> +}
> +
> +static const struct dw_mci_drv_data starfive_data = {
> + .common_caps = MMC_CAP_CMD23,
> + .set_ios = dw_mci_starfive_set_ios,
> + .parse_dt = dw_mci_starfive_parse_dt,
> + .execute_tuning = dw_mci_starfive_execute_tuning,
> +};
> +
> +static const struct of_device_id dw_mci_starfive_match[] = {
> + { .compatible = "starfive,jh7110-mmc",
> + .data = &starfive_data },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
> +
> +static int dw_mci_starfive_probe(struct platform_device *pdev)
> +{
> + return dw_mci_pltfm_register(pdev, &starfive_data);
> +}
> +
> +static struct platform_driver dw_mci_starfive_driver = {
> + .probe = dw_mci_starfive_probe,
> + .remove = dw_mci_pltfm_remove,
> + .driver = {
> + .name = "dwmmc_starfive",
> + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> + .of_match_table = dw_mci_starfive_match,
> + },
> +};
> +module_platform_driver(dw_mci_starfive_driver);
> +
> +MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:dwmmc_starfive");
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
@ 2023-03-27 16:01 ` Shengyu Qu
0 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-03-27 16:01 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1.1: Type: text/plain, Size: 8892 bytes --]
Hello William,
I'm digging into downstream mmc driver these days and found a problem
that current version mainline driver doesn't has a voltage switch
function for
it. Downstream older version has one but was deleted in this commit [1].
It was deleted since vf2's SD slot doesn't have 1.8V input but commiter
forgot
that vf2's eMMC slot has a proper 1.8V input.
So could you add voltage switch function for mainline? I've met a eMMC speed
problem possibly due to it.
Best regards,
Shengyu
[1]
https://github.com/starfive-tech/linux/commit/8037d59091d276e74be38e5fafaaebe36eaa77e1
在 2023/2/15 19:32, William Qiu 写道:
> Add sdio/emmc driver support for StarFive JH7110 soc.
>
> Tested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
> MAINTAINERS | 6 +
> drivers/mmc/host/Kconfig | 10 ++
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
> 4 files changed, 203 insertions(+)
> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 85e8f83161d7..644ac9479a6e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19640,6 +19640,12 @@ F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
> F: drivers/clk/starfive/clk-starfive-jh71*
> F: include/dt-bindings/clock/starfive?jh71*.h
>
> +STARFIVE JH7110 MMC/SD/SDIO DRIVER
> +M: William Qiu <william.qiu@starfivetech.com>
> +S: Supported
> +F: Documentation/devicetree/bindings/mmc/starfive*
> +F: drivers/mmc/host/dw_mmc-starfive.c
> +
> STARFIVE JH71X0 PINCTRL DRIVERS
> M: Emil Renner Berthing <kernel@esmil.dk>
> M: Jianlong Huang <jianlong.huang@starfivetech.com>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index fb1062a6394c..b87262503403 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -871,6 +871,16 @@ config MMC_DW_ROCKCHIP
> Synopsys DesignWare Memory Card Interface driver. Select this option
> for platforms based on RK3066, RK3188 and RK3288 SoC's.
>
> +config MMC_DW_STARFIVE
> + tristate "StarFive specific extensions for Synopsys DW Memory Card Interface"
> + depends on SOC_STARFIVE
> + depends on MMC_DW
> + select MMC_DW_PLTFM
> + help
> + This selects support for StarFive JH7110 SoC specific extensions to the
> + Synopsys DesignWare Memory Card Interface driver. Select this option
> + for platforms based on StarFive JH7110 SoC.
> +
> config MMC_SH_MMCIF
> tristate "SuperH Internal MMCIF support"
> depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 4e4ceb32c4b4..32c0e5564b9a 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
> obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
> obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
> obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
> +obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
> obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
> obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
> obj-$(CONFIG_MMC_VUB300) += vub300.o
> diff --git a/drivers/mmc/host/dw_mmc-starfive.c b/drivers/mmc/host/dw_mmc-starfive.c
> new file mode 100644
> index 000000000000..40f5969b07a6
> --- /dev/null
> +++ b/drivers/mmc/host/dw_mmc-starfive.c
> @@ -0,0 +1,186 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * StarFive Designware Mobile Storage Host Controller Driver
> + *
> + * Copyright (c) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mmc/host.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "dw_mmc.h"
> +#include "dw_mmc-pltfm.h"
> +
> +#define ALL_INT_CLR 0x1ffff
> +#define MAX_DELAY_CHAIN 32
> +
> +struct starfive_priv {
> + struct device *dev;
> + struct regmap *reg_syscon;
> + u32 syscon_offset;
> + u32 syscon_shift;
> + u32 syscon_mask;
> +};
> +
> +static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
> +{
> + int ret;
> + unsigned int clock;
> +
> + if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
> + clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
> + ret = clk_set_rate(host->ciu_clk, clock);
> + if (ret)
> + dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
> + host->bus_hz = clk_get_rate(host->ciu_clk);
> + } else {
> + dev_dbg(host->dev, "Using the internal divider\n");
> + }
> +}
> +
> +static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
> + u32 opcode)
> +{
> + static const int grade = MAX_DELAY_CHAIN;
> + struct dw_mci *host = slot->host;
> + struct starfive_priv *priv = host->priv;
> + int rise_point = -1, fall_point = -1;
> + int err, prev_err;
> + int i;
> + bool found = 0;
> + u32 regval;
> +
> + /*
> + * Use grade as the max delay chain, and use the rise_point and
> + * fall_point to ensure the best sampling point of a data input
> + * signals.
> + */
> + for (i = 0; i < grade; i++) {
> + regval = i << priv->syscon_shift;
> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
> + priv->syscon_mask, regval);
> + if (err)
> + return err;
> + mci_writel(host, RINTSTS, ALL_INT_CLR);
> +
> + err = mmc_send_tuning(slot->mmc, opcode, NULL);
> + if (!err)
> + found = 1;
> +
> + if (i > 0) {
> + if (err && !prev_err)
> + fall_point = i - 1;
> + if (!err && prev_err)
> + rise_point = i;
> + }
> +
> + if (rise_point != -1 && fall_point != -1)
> + goto tuning_out;
> +
> + prev_err = err;
> + err = 0;
> + }
> +
> +tuning_out:
> + if (found) {
> + if (rise_point == -1)
> + rise_point = 0;
> + if (fall_point == -1)
> + fall_point = grade - 1;
> + if (fall_point < rise_point) {
> + if ((rise_point + fall_point) >
> + (grade - 1))
> + i = fall_point / 2;
> + else
> + i = (rise_point + grade - 1) / 2;
> + } else {
> + i = (rise_point + fall_point) / 2;
> + }
> +
> + regval = i << priv->syscon_shift;
> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
> + priv->syscon_mask, regval);
> + if (err)
> + return err;
> + mci_writel(host, RINTSTS, ALL_INT_CLR);
> +
> + dev_info(host->dev, "Found valid delay chain! use it [delay=%d]\n", i);
> + } else {
> + dev_err(host->dev, "No valid delay chain! use default\n");
> + err = -EINVAL;
> + }
> +
> + mci_writel(host, RINTSTS, ALL_INT_CLR);
> + return err;
> +}
> +
> +static int dw_mci_starfive_parse_dt(struct dw_mci *host)
> +{
> + struct of_phandle_args args;
> + struct starfive_priv *priv;
> + int ret;
> +
> + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
> + "starfive,sysreg", 3, 0, &args);
> + if (ret) {
> + dev_err(host->dev, "Failed to parse starfive,sysreg\n");
> + return -EINVAL;
> + }
> +
> + priv->reg_syscon = syscon_node_to_regmap(args.np);
> + of_node_put(args.np);
> + if (IS_ERR(priv->reg_syscon))
> + return PTR_ERR(priv->reg_syscon);
> +
> + priv->syscon_offset = args.args[0];
> + priv->syscon_shift = args.args[1];
> + priv->syscon_mask = args.args[2];
> +
> + host->priv = priv;
> +
> + return 0;
> +}
> +
> +static const struct dw_mci_drv_data starfive_data = {
> + .common_caps = MMC_CAP_CMD23,
> + .set_ios = dw_mci_starfive_set_ios,
> + .parse_dt = dw_mci_starfive_parse_dt,
> + .execute_tuning = dw_mci_starfive_execute_tuning,
> +};
> +
> +static const struct of_device_id dw_mci_starfive_match[] = {
> + { .compatible = "starfive,jh7110-mmc",
> + .data = &starfive_data },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
> +
> +static int dw_mci_starfive_probe(struct platform_device *pdev)
> +{
> + return dw_mci_pltfm_register(pdev, &starfive_data);
> +}
> +
> +static struct platform_driver dw_mci_starfive_driver = {
> + .probe = dw_mci_starfive_probe,
> + .remove = dw_mci_pltfm_remove,
> + .driver = {
> + .name = "dwmmc_starfive",
> + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> + .of_match_table = dw_mci_starfive_match,
> + },
> +};
> +module_platform_driver(dw_mci_starfive_driver);
> +
> +MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:dwmmc_starfive");
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
2023-03-27 16:01 ` Shengyu Qu
@ 2023-03-28 16:08 ` Shengyu Qu
-1 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-03-28 16:08 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1: Type: text/plain, Size: 11290 bytes --]
Hello William,
Sorry for making noise about this, but seems deleted voltage swtich function
doesn't help about this. But there's still a problem about eMMC speed.
Currently
only about 20MB/s maximum reading speed could be reached when using eMMC
on VF2, any idea about this?
Best regards,
Shengyu
在 2023/3/28 0:01, Shengyu Qu 写道:
> Hello William,
>
> I'm digging into downstream mmc driver these days and found a problem
>
> that current version mainline driver doesn't has a voltage switch
> function for
>
> it. Downstream older version has one but was deleted in this commit [1].
>
> It was deleted since vf2's SD slot doesn't have 1.8V input but
> commiter forgot
>
> that vf2's eMMC slot has a proper 1.8V input.
>
> So could you add voltage switch function for mainline? I've met a eMMC
> speed
>
> problem possibly due to it.
>
> Best regards,
>
> Shengyu
>
> [1]
> https://github.com/starfive-tech/linux/commit/8037d59091d276e74be38e5fafaaebe36eaa77e1
>
> 在 2023/2/15 19:32, William Qiu 写道:
>> Add sdio/emmc driver support for StarFive JH7110 soc.
>>
>> Tested-by: Conor Dooley <conor.dooley@microchip.com>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> MAINTAINERS | 6 +
>> drivers/mmc/host/Kconfig | 10 ++
>> drivers/mmc/host/Makefile | 1 +
>> drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
>> 4 files changed, 203 insertions(+)
>> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 85e8f83161d7..644ac9479a6e 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -19640,6 +19640,12 @@ F:
>> Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
>> F: drivers/clk/starfive/clk-starfive-jh71*
>> F: include/dt-bindings/clock/starfive?jh71*.h
>> +STARFIVE JH7110 MMC/SD/SDIO DRIVER
>> +M: William Qiu <william.qiu@starfivetech.com>
>> +S: Supported
>> +F: Documentation/devicetree/bindings/mmc/starfive*
>> +F: drivers/mmc/host/dw_mmc-starfive.c
>> +
>> STARFIVE JH71X0 PINCTRL DRIVERS
>> M: Emil Renner Berthing <kernel@esmil.dk>
>> M: Jianlong Huang <jianlong.huang@starfivetech.com>
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index fb1062a6394c..b87262503403 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -871,6 +871,16 @@ config MMC_DW_ROCKCHIP
>> Synopsys DesignWare Memory Card Interface driver. Select this
>> option
>> for platforms based on RK3066, RK3188 and RK3288 SoC's.
>> +config MMC_DW_STARFIVE
>> + tristate "StarFive specific extensions for Synopsys DW Memory
>> Card Interface"
>> + depends on SOC_STARFIVE
>> + depends on MMC_DW
>> + select MMC_DW_PLTFM
>> + help
>> + This selects support for StarFive JH7110 SoC specific
>> extensions to the
>> + Synopsys DesignWare Memory Card Interface driver. Select this
>> option
>> + for platforms based on StarFive JH7110 SoC.
>> +
>> config MMC_SH_MMCIF
>> tristate "SuperH Internal MMCIF support"
>> depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> index 4e4ceb32c4b4..32c0e5564b9a 100644
>> --- a/drivers/mmc/host/Makefile
>> +++ b/drivers/mmc/host/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) +=
>> dw_mmc-hi3798cv200.o
>> obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
>> obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
>> obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
>> +obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
>> obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
>> obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
>> obj-$(CONFIG_MMC_VUB300) += vub300.o
>> diff --git a/drivers/mmc/host/dw_mmc-starfive.c
>> b/drivers/mmc/host/dw_mmc-starfive.c
>> new file mode 100644
>> index 000000000000..40f5969b07a6
>> --- /dev/null
>> +++ b/drivers/mmc/host/dw_mmc-starfive.c
>> @@ -0,0 +1,186 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * StarFive Designware Mobile Storage Host Controller Driver
>> + *
>> + * Copyright (c) 2022 StarFive Technology Co., Ltd.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/mmc/host.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include "dw_mmc.h"
>> +#include "dw_mmc-pltfm.h"
>> +
>> +#define ALL_INT_CLR 0x1ffff
>> +#define MAX_DELAY_CHAIN 32
>> +
>> +struct starfive_priv {
>> + struct device *dev;
>> + struct regmap *reg_syscon;
>> + u32 syscon_offset;
>> + u32 syscon_shift;
>> + u32 syscon_mask;
>> +};
>> +
>> +static void dw_mci_starfive_set_ios(struct dw_mci *host, struct
>> mmc_ios *ios)
>> +{
>> + int ret;
>> + unsigned int clock;
>> +
>> + if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing ==
>> MMC_TIMING_UHS_DDR50) {
>> + clock = (ios->clock > 50000000 && ios->clock <= 52000000) ?
>> 100000000 : ios->clock;
>> + ret = clk_set_rate(host->ciu_clk, clock);
>> + if (ret)
>> + dev_dbg(host->dev, "Use an external frequency divider
>> %uHz\n", ios->clock);
>> + host->bus_hz = clk_get_rate(host->ciu_clk);
>> + } else {
>> + dev_dbg(host->dev, "Using the internal divider\n");
>> + }
>> +}
>> +
>> +static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
>> + u32 opcode)
>> +{
>> + static const int grade = MAX_DELAY_CHAIN;
>> + struct dw_mci *host = slot->host;
>> + struct starfive_priv *priv = host->priv;
>> + int rise_point = -1, fall_point = -1;
>> + int err, prev_err;
>> + int i;
>> + bool found = 0;
>> + u32 regval;
>> +
>> + /*
>> + * Use grade as the max delay chain, and use the rise_point and
>> + * fall_point to ensure the best sampling point of a data input
>> + * signals.
>> + */
>> + for (i = 0; i < grade; i++) {
>> + regval = i << priv->syscon_shift;
>> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>> + priv->syscon_mask, regval);
>> + if (err)
>> + return err;
>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>> +
>> + err = mmc_send_tuning(slot->mmc, opcode, NULL);
>> + if (!err)
>> + found = 1;
>> +
>> + if (i > 0) {
>> + if (err && !prev_err)
>> + fall_point = i - 1;
>> + if (!err && prev_err)
>> + rise_point = i;
>> + }
>> +
>> + if (rise_point != -1 && fall_point != -1)
>> + goto tuning_out;
>> +
>> + prev_err = err;
>> + err = 0;
>> + }
>> +
>> +tuning_out:
>> + if (found) {
>> + if (rise_point == -1)
>> + rise_point = 0;
>> + if (fall_point == -1)
>> + fall_point = grade - 1;
>> + if (fall_point < rise_point) {
>> + if ((rise_point + fall_point) >
>> + (grade - 1))
>> + i = fall_point / 2;
>> + else
>> + i = (rise_point + grade - 1) / 2;
>> + } else {
>> + i = (rise_point + fall_point) / 2;
>> + }
>> +
>> + regval = i << priv->syscon_shift;
>> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>> + priv->syscon_mask, regval);
>> + if (err)
>> + return err;
>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>> +
>> + dev_info(host->dev, "Found valid delay chain! use it
>> [delay=%d]\n", i);
>> + } else {
>> + dev_err(host->dev, "No valid delay chain! use default\n");
>> + err = -EINVAL;
>> + }
>> +
>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>> + return err;
>> +}
>> +
>> +static int dw_mci_starfive_parse_dt(struct dw_mci *host)
>> +{
>> + struct of_phandle_args args;
>> + struct starfive_priv *priv;
>> + int ret;
>> +
>> + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
>> + "starfive,sysreg", 3, 0, &args);
>> + if (ret) {
>> + dev_err(host->dev, "Failed to parse starfive,sysreg\n");
>> + return -EINVAL;
>> + }
>> +
>> + priv->reg_syscon = syscon_node_to_regmap(args.np);
>> + of_node_put(args.np);
>> + if (IS_ERR(priv->reg_syscon))
>> + return PTR_ERR(priv->reg_syscon);
>> +
>> + priv->syscon_offset = args.args[0];
>> + priv->syscon_shift = args.args[1];
>> + priv->syscon_mask = args.args[2];
>> +
>> + host->priv = priv;
>> +
>> + return 0;
>> +}
>> +
>> +static const struct dw_mci_drv_data starfive_data = {
>> + .common_caps = MMC_CAP_CMD23,
>> + .set_ios = dw_mci_starfive_set_ios,
>> + .parse_dt = dw_mci_starfive_parse_dt,
>> + .execute_tuning = dw_mci_starfive_execute_tuning,
>> +};
>> +
>> +static const struct of_device_id dw_mci_starfive_match[] = {
>> + { .compatible = "starfive,jh7110-mmc",
>> + .data = &starfive_data },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
>> +
>> +static int dw_mci_starfive_probe(struct platform_device *pdev)
>> +{
>> + return dw_mci_pltfm_register(pdev, &starfive_data);
>> +}
>> +
>> +static struct platform_driver dw_mci_starfive_driver = {
>> + .probe = dw_mci_starfive_probe,
>> + .remove = dw_mci_pltfm_remove,
>> + .driver = {
>> + .name = "dwmmc_starfive",
>> + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
>> + .of_match_table = dw_mci_starfive_match,
>> + },
>> +};
>> +module_platform_driver(dw_mci_starfive_driver);
>> +
>> +MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver
>> Extension");
>> +MODULE_LICENSE("GPL");
>> +MODULE_ALIAS("platform:dwmmc_starfive");
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
@ 2023-03-28 16:08 ` Shengyu Qu
0 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-03-28 16:08 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1.1: Type: text/plain, Size: 11290 bytes --]
Hello William,
Sorry for making noise about this, but seems deleted voltage swtich function
doesn't help about this. But there's still a problem about eMMC speed.
Currently
only about 20MB/s maximum reading speed could be reached when using eMMC
on VF2, any idea about this?
Best regards,
Shengyu
在 2023/3/28 0:01, Shengyu Qu 写道:
> Hello William,
>
> I'm digging into downstream mmc driver these days and found a problem
>
> that current version mainline driver doesn't has a voltage switch
> function for
>
> it. Downstream older version has one but was deleted in this commit [1].
>
> It was deleted since vf2's SD slot doesn't have 1.8V input but
> commiter forgot
>
> that vf2's eMMC slot has a proper 1.8V input.
>
> So could you add voltage switch function for mainline? I've met a eMMC
> speed
>
> problem possibly due to it.
>
> Best regards,
>
> Shengyu
>
> [1]
> https://github.com/starfive-tech/linux/commit/8037d59091d276e74be38e5fafaaebe36eaa77e1
>
> 在 2023/2/15 19:32, William Qiu 写道:
>> Add sdio/emmc driver support for StarFive JH7110 soc.
>>
>> Tested-by: Conor Dooley <conor.dooley@microchip.com>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> MAINTAINERS | 6 +
>> drivers/mmc/host/Kconfig | 10 ++
>> drivers/mmc/host/Makefile | 1 +
>> drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
>> 4 files changed, 203 insertions(+)
>> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 85e8f83161d7..644ac9479a6e 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -19640,6 +19640,12 @@ F:
>> Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
>> F: drivers/clk/starfive/clk-starfive-jh71*
>> F: include/dt-bindings/clock/starfive?jh71*.h
>> +STARFIVE JH7110 MMC/SD/SDIO DRIVER
>> +M: William Qiu <william.qiu@starfivetech.com>
>> +S: Supported
>> +F: Documentation/devicetree/bindings/mmc/starfive*
>> +F: drivers/mmc/host/dw_mmc-starfive.c
>> +
>> STARFIVE JH71X0 PINCTRL DRIVERS
>> M: Emil Renner Berthing <kernel@esmil.dk>
>> M: Jianlong Huang <jianlong.huang@starfivetech.com>
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index fb1062a6394c..b87262503403 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -871,6 +871,16 @@ config MMC_DW_ROCKCHIP
>> Synopsys DesignWare Memory Card Interface driver. Select this
>> option
>> for platforms based on RK3066, RK3188 and RK3288 SoC's.
>> +config MMC_DW_STARFIVE
>> + tristate "StarFive specific extensions for Synopsys DW Memory
>> Card Interface"
>> + depends on SOC_STARFIVE
>> + depends on MMC_DW
>> + select MMC_DW_PLTFM
>> + help
>> + This selects support for StarFive JH7110 SoC specific
>> extensions to the
>> + Synopsys DesignWare Memory Card Interface driver. Select this
>> option
>> + for platforms based on StarFive JH7110 SoC.
>> +
>> config MMC_SH_MMCIF
>> tristate "SuperH Internal MMCIF support"
>> depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> index 4e4ceb32c4b4..32c0e5564b9a 100644
>> --- a/drivers/mmc/host/Makefile
>> +++ b/drivers/mmc/host/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) +=
>> dw_mmc-hi3798cv200.o
>> obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
>> obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
>> obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
>> +obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
>> obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
>> obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
>> obj-$(CONFIG_MMC_VUB300) += vub300.o
>> diff --git a/drivers/mmc/host/dw_mmc-starfive.c
>> b/drivers/mmc/host/dw_mmc-starfive.c
>> new file mode 100644
>> index 000000000000..40f5969b07a6
>> --- /dev/null
>> +++ b/drivers/mmc/host/dw_mmc-starfive.c
>> @@ -0,0 +1,186 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * StarFive Designware Mobile Storage Host Controller Driver
>> + *
>> + * Copyright (c) 2022 StarFive Technology Co., Ltd.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/mmc/host.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include "dw_mmc.h"
>> +#include "dw_mmc-pltfm.h"
>> +
>> +#define ALL_INT_CLR 0x1ffff
>> +#define MAX_DELAY_CHAIN 32
>> +
>> +struct starfive_priv {
>> + struct device *dev;
>> + struct regmap *reg_syscon;
>> + u32 syscon_offset;
>> + u32 syscon_shift;
>> + u32 syscon_mask;
>> +};
>> +
>> +static void dw_mci_starfive_set_ios(struct dw_mci *host, struct
>> mmc_ios *ios)
>> +{
>> + int ret;
>> + unsigned int clock;
>> +
>> + if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing ==
>> MMC_TIMING_UHS_DDR50) {
>> + clock = (ios->clock > 50000000 && ios->clock <= 52000000) ?
>> 100000000 : ios->clock;
>> + ret = clk_set_rate(host->ciu_clk, clock);
>> + if (ret)
>> + dev_dbg(host->dev, "Use an external frequency divider
>> %uHz\n", ios->clock);
>> + host->bus_hz = clk_get_rate(host->ciu_clk);
>> + } else {
>> + dev_dbg(host->dev, "Using the internal divider\n");
>> + }
>> +}
>> +
>> +static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
>> + u32 opcode)
>> +{
>> + static const int grade = MAX_DELAY_CHAIN;
>> + struct dw_mci *host = slot->host;
>> + struct starfive_priv *priv = host->priv;
>> + int rise_point = -1, fall_point = -1;
>> + int err, prev_err;
>> + int i;
>> + bool found = 0;
>> + u32 regval;
>> +
>> + /*
>> + * Use grade as the max delay chain, and use the rise_point and
>> + * fall_point to ensure the best sampling point of a data input
>> + * signals.
>> + */
>> + for (i = 0; i < grade; i++) {
>> + regval = i << priv->syscon_shift;
>> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>> + priv->syscon_mask, regval);
>> + if (err)
>> + return err;
>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>> +
>> + err = mmc_send_tuning(slot->mmc, opcode, NULL);
>> + if (!err)
>> + found = 1;
>> +
>> + if (i > 0) {
>> + if (err && !prev_err)
>> + fall_point = i - 1;
>> + if (!err && prev_err)
>> + rise_point = i;
>> + }
>> +
>> + if (rise_point != -1 && fall_point != -1)
>> + goto tuning_out;
>> +
>> + prev_err = err;
>> + err = 0;
>> + }
>> +
>> +tuning_out:
>> + if (found) {
>> + if (rise_point == -1)
>> + rise_point = 0;
>> + if (fall_point == -1)
>> + fall_point = grade - 1;
>> + if (fall_point < rise_point) {
>> + if ((rise_point + fall_point) >
>> + (grade - 1))
>> + i = fall_point / 2;
>> + else
>> + i = (rise_point + grade - 1) / 2;
>> + } else {
>> + i = (rise_point + fall_point) / 2;
>> + }
>> +
>> + regval = i << priv->syscon_shift;
>> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>> + priv->syscon_mask, regval);
>> + if (err)
>> + return err;
>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>> +
>> + dev_info(host->dev, "Found valid delay chain! use it
>> [delay=%d]\n", i);
>> + } else {
>> + dev_err(host->dev, "No valid delay chain! use default\n");
>> + err = -EINVAL;
>> + }
>> +
>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>> + return err;
>> +}
>> +
>> +static int dw_mci_starfive_parse_dt(struct dw_mci *host)
>> +{
>> + struct of_phandle_args args;
>> + struct starfive_priv *priv;
>> + int ret;
>> +
>> + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
>> + "starfive,sysreg", 3, 0, &args);
>> + if (ret) {
>> + dev_err(host->dev, "Failed to parse starfive,sysreg\n");
>> + return -EINVAL;
>> + }
>> +
>> + priv->reg_syscon = syscon_node_to_regmap(args.np);
>> + of_node_put(args.np);
>> + if (IS_ERR(priv->reg_syscon))
>> + return PTR_ERR(priv->reg_syscon);
>> +
>> + priv->syscon_offset = args.args[0];
>> + priv->syscon_shift = args.args[1];
>> + priv->syscon_mask = args.args[2];
>> +
>> + host->priv = priv;
>> +
>> + return 0;
>> +}
>> +
>> +static const struct dw_mci_drv_data starfive_data = {
>> + .common_caps = MMC_CAP_CMD23,
>> + .set_ios = dw_mci_starfive_set_ios,
>> + .parse_dt = dw_mci_starfive_parse_dt,
>> + .execute_tuning = dw_mci_starfive_execute_tuning,
>> +};
>> +
>> +static const struct of_device_id dw_mci_starfive_match[] = {
>> + { .compatible = "starfive,jh7110-mmc",
>> + .data = &starfive_data },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
>> +
>> +static int dw_mci_starfive_probe(struct platform_device *pdev)
>> +{
>> + return dw_mci_pltfm_register(pdev, &starfive_data);
>> +}
>> +
>> +static struct platform_driver dw_mci_starfive_driver = {
>> + .probe = dw_mci_starfive_probe,
>> + .remove = dw_mci_pltfm_remove,
>> + .driver = {
>> + .name = "dwmmc_starfive",
>> + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
>> + .of_match_table = dw_mci_starfive_match,
>> + },
>> +};
>> +module_platform_driver(dw_mci_starfive_driver);
>> +
>> +MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver
>> Extension");
>> +MODULE_LICENSE("GPL");
>> +MODULE_ALIAS("platform:dwmmc_starfive");
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
2023-03-28 16:08 ` Shengyu Qu
@ 2023-03-31 9:33 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-03-31 9:33 UTC (permalink / raw)
To: Shengyu Qu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/3/29 0:08, Shengyu Qu wrote:
> Hello William,
>
> Sorry for making noise about this, but seems deleted voltage swtich function
>
> doesn't help about this. But there's still a problem about eMMC speed. Currently
>
> only about 20MB/s maximum reading speed could be reached when using eMMC
>
> on VF2, any idea about this?
>
> Best regards,
>
> Shengyu
>
> 在 2023/3/28 0:01, Shengyu Qu 写道:
>> Hello William,
>>
>> I'm digging into downstream mmc driver these days and found a problem
>>
>> that current version mainline driver doesn't has a voltage switch function for
>>
>> it. Downstream older version has one but was deleted in this commit [1].
>>
>> It was deleted since vf2's SD slot doesn't have 1.8V input but commiter forgot
>>
>> that vf2's eMMC slot has a proper 1.8V input.
>>
>> So could you add voltage switch function for mainline? I've met a eMMC speed
>>
>> problem possibly due to it.
>>
>> Best regards,
>>
>> Shengyu
>>
Hi Shengyu,
Sorry for the late reply.
First of all, I will consider adding voltage switch function, but the implementation
method is to configure the pmic register configuration in dts, and the implementation
interface will use the voltage switch function in dw_mmc.c.
As for speed, the main reason for the low rate is the clock of JH7110 and the
associated IO driving strength, in this limit, the maximum reading speed I tested was
about 50Mb/s.
I will try to reproduce your problem and try to solve it. Thanks for suggestions.
Best regards,
William
>> [1] https://github.com/starfive-tech/linux/commit/8037d59091d276e74be38e5fafaaebe36eaa77e1
>>
>> 在 2023/2/15 19:32, William Qiu 写道:
>>> Add sdio/emmc driver support for StarFive JH7110 soc.
>>>
>>> Tested-by: Conor Dooley <conor.dooley@microchip.com>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> ---
>>> MAINTAINERS | 6 +
>>> drivers/mmc/host/Kconfig | 10 ++
>>> drivers/mmc/host/Makefile | 1 +
>>> drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
>>> 4 files changed, 203 insertions(+)
>>> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 85e8f83161d7..644ac9479a6e 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -19640,6 +19640,12 @@ F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
>>> F: drivers/clk/starfive/clk-starfive-jh71*
>>> F: include/dt-bindings/clock/starfive?jh71*.h
>>> +STARFIVE JH7110 MMC/SD/SDIO DRIVER
>>> +M: William Qiu <william.qiu@starfivetech.com>
>>> +S: Supported
>>> +F: Documentation/devicetree/bindings/mmc/starfive*
>>> +F: drivers/mmc/host/dw_mmc-starfive.c
>>> +
>>> STARFIVE JH71X0 PINCTRL DRIVERS
>>> M: Emil Renner Berthing <kernel@esmil.dk>
>>> M: Jianlong Huang <jianlong.huang@starfivetech.com>
>>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>>> index fb1062a6394c..b87262503403 100644
>>> --- a/drivers/mmc/host/Kconfig
>>> +++ b/drivers/mmc/host/Kconfig
>>> @@ -871,6 +871,16 @@ config MMC_DW_ROCKCHIP
>>> Synopsys DesignWare Memory Card Interface driver. Select this option
>>> for platforms based on RK3066, RK3188 and RK3288 SoC's.
>>> +config MMC_DW_STARFIVE
>>> + tristate "StarFive specific extensions for Synopsys DW Memory Card Interface"
>>> + depends on SOC_STARFIVE
>>> + depends on MMC_DW
>>> + select MMC_DW_PLTFM
>>> + help
>>> + This selects support for StarFive JH7110 SoC specific extensions to the
>>> + Synopsys DesignWare Memory Card Interface driver. Select this option
>>> + for platforms based on StarFive JH7110 SoC.
>>> +
>>> config MMC_SH_MMCIF
>>> tristate "SuperH Internal MMCIF support"
>>> depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
>>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>>> index 4e4ceb32c4b4..32c0e5564b9a 100644
>>> --- a/drivers/mmc/host/Makefile
>>> +++ b/drivers/mmc/host/Makefile
>>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
>>> obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
>>> obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
>>> obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
>>> +obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
>>> obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
>>> obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
>>> obj-$(CONFIG_MMC_VUB300) += vub300.o
>>> diff --git a/drivers/mmc/host/dw_mmc-starfive.c b/drivers/mmc/host/dw_mmc-starfive.c
>>> new file mode 100644
>>> index 000000000000..40f5969b07a6
>>> --- /dev/null
>>> +++ b/drivers/mmc/host/dw_mmc-starfive.c
>>> @@ -0,0 +1,186 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * StarFive Designware Mobile Storage Host Controller Driver
>>> + *
>>> + * Copyright (c) 2022 StarFive Technology Co., Ltd.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/mmc/host.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/regmap.h>
>>> +
>>> +#include "dw_mmc.h"
>>> +#include "dw_mmc-pltfm.h"
>>> +
>>> +#define ALL_INT_CLR 0x1ffff
>>> +#define MAX_DELAY_CHAIN 32
>>> +
>>> +struct starfive_priv {
>>> + struct device *dev;
>>> + struct regmap *reg_syscon;
>>> + u32 syscon_offset;
>>> + u32 syscon_shift;
>>> + u32 syscon_mask;
>>> +};
>>> +
>>> +static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>>> +{
>>> + int ret;
>>> + unsigned int clock;
>>> +
>>> + if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
>>> + clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
>>> + ret = clk_set_rate(host->ciu_clk, clock);
>>> + if (ret)
>>> + dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
>>> + host->bus_hz = clk_get_rate(host->ciu_clk);
>>> + } else {
>>> + dev_dbg(host->dev, "Using the internal divider\n");
>>> + }
>>> +}
>>> +
>>> +static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
>>> + u32 opcode)
>>> +{
>>> + static const int grade = MAX_DELAY_CHAIN;
>>> + struct dw_mci *host = slot->host;
>>> + struct starfive_priv *priv = host->priv;
>>> + int rise_point = -1, fall_point = -1;
>>> + int err, prev_err;
>>> + int i;
>>> + bool found = 0;
>>> + u32 regval;
>>> +
>>> + /*
>>> + * Use grade as the max delay chain, and use the rise_point and
>>> + * fall_point to ensure the best sampling point of a data input
>>> + * signals.
>>> + */
>>> + for (i = 0; i < grade; i++) {
>>> + regval = i << priv->syscon_shift;
>>> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>>> + priv->syscon_mask, regval);
>>> + if (err)
>>> + return err;
>>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>>> +
>>> + err = mmc_send_tuning(slot->mmc, opcode, NULL);
>>> + if (!err)
>>> + found = 1;
>>> +
>>> + if (i > 0) {
>>> + if (err && !prev_err)
>>> + fall_point = i - 1;
>>> + if (!err && prev_err)
>>> + rise_point = i;
>>> + }
>>> +
>>> + if (rise_point != -1 && fall_point != -1)
>>> + goto tuning_out;
>>> +
>>> + prev_err = err;
>>> + err = 0;
>>> + }
>>> +
>>> +tuning_out:
>>> + if (found) {
>>> + if (rise_point == -1)
>>> + rise_point = 0;
>>> + if (fall_point == -1)
>>> + fall_point = grade - 1;
>>> + if (fall_point < rise_point) {
>>> + if ((rise_point + fall_point) >
>>> + (grade - 1))
>>> + i = fall_point / 2;
>>> + else
>>> + i = (rise_point + grade - 1) / 2;
>>> + } else {
>>> + i = (rise_point + fall_point) / 2;
>>> + }
>>> +
>>> + regval = i << priv->syscon_shift;
>>> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>>> + priv->syscon_mask, regval);
>>> + if (err)
>>> + return err;
>>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>>> +
>>> + dev_info(host->dev, "Found valid delay chain! use it [delay=%d]\n", i);
>>> + } else {
>>> + dev_err(host->dev, "No valid delay chain! use default\n");
>>> + err = -EINVAL;
>>> + }
>>> +
>>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>>> + return err;
>>> +}
>>> +
>>> +static int dw_mci_starfive_parse_dt(struct dw_mci *host)
>>> +{
>>> + struct of_phandle_args args;
>>> + struct starfive_priv *priv;
>>> + int ret;
>>> +
>>> + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>>> + if (!priv)
>>> + return -ENOMEM;
>>> +
>>> + ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
>>> + "starfive,sysreg", 3, 0, &args);
>>> + if (ret) {
>>> + dev_err(host->dev, "Failed to parse starfive,sysreg\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + priv->reg_syscon = syscon_node_to_regmap(args.np);
>>> + of_node_put(args.np);
>>> + if (IS_ERR(priv->reg_syscon))
>>> + return PTR_ERR(priv->reg_syscon);
>>> +
>>> + priv->syscon_offset = args.args[0];
>>> + priv->syscon_shift = args.args[1];
>>> + priv->syscon_mask = args.args[2];
>>> +
>>> + host->priv = priv;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct dw_mci_drv_data starfive_data = {
>>> + .common_caps = MMC_CAP_CMD23,
>>> + .set_ios = dw_mci_starfive_set_ios,
>>> + .parse_dt = dw_mci_starfive_parse_dt,
>>> + .execute_tuning = dw_mci_starfive_execute_tuning,
>>> +};
>>> +
>>> +static const struct of_device_id dw_mci_starfive_match[] = {
>>> + { .compatible = "starfive,jh7110-mmc",
>>> + .data = &starfive_data },
>>> + {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
>>> +
>>> +static int dw_mci_starfive_probe(struct platform_device *pdev)
>>> +{
>>> + return dw_mci_pltfm_register(pdev, &starfive_data);
>>> +}
>>> +
>>> +static struct platform_driver dw_mci_starfive_driver = {
>>> + .probe = dw_mci_starfive_probe,
>>> + .remove = dw_mci_pltfm_remove,
>>> + .driver = {
>>> + .name = "dwmmc_starfive",
>>> + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
>>> + .of_match_table = dw_mci_starfive_match,
>>> + },
>>> +};
>>> +module_platform_driver(dw_mci_starfive_driver);
>>> +
>>> +MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
>>> +MODULE_LICENSE("GPL");
>>> +MODULE_ALIAS("platform:dwmmc_starfive");
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
@ 2023-03-31 9:33 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-03-31 9:33 UTC (permalink / raw)
To: Shengyu Qu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/3/29 0:08, Shengyu Qu wrote:
> Hello William,
>
> Sorry for making noise about this, but seems deleted voltage swtich function
>
> doesn't help about this. But there's still a problem about eMMC speed. Currently
>
> only about 20MB/s maximum reading speed could be reached when using eMMC
>
> on VF2, any idea about this?
>
> Best regards,
>
> Shengyu
>
> 在 2023/3/28 0:01, Shengyu Qu 写道:
>> Hello William,
>>
>> I'm digging into downstream mmc driver these days and found a problem
>>
>> that current version mainline driver doesn't has a voltage switch function for
>>
>> it. Downstream older version has one but was deleted in this commit [1].
>>
>> It was deleted since vf2's SD slot doesn't have 1.8V input but commiter forgot
>>
>> that vf2's eMMC slot has a proper 1.8V input.
>>
>> So could you add voltage switch function for mainline? I've met a eMMC speed
>>
>> problem possibly due to it.
>>
>> Best regards,
>>
>> Shengyu
>>
Hi Shengyu,
Sorry for the late reply.
First of all, I will consider adding voltage switch function, but the implementation
method is to configure the pmic register configuration in dts, and the implementation
interface will use the voltage switch function in dw_mmc.c.
As for speed, the main reason for the low rate is the clock of JH7110 and the
associated IO driving strength, in this limit, the maximum reading speed I tested was
about 50Mb/s.
I will try to reproduce your problem and try to solve it. Thanks for suggestions.
Best regards,
William
>> [1] https://github.com/starfive-tech/linux/commit/8037d59091d276e74be38e5fafaaebe36eaa77e1
>>
>> 在 2023/2/15 19:32, William Qiu 写道:
>>> Add sdio/emmc driver support for StarFive JH7110 soc.
>>>
>>> Tested-by: Conor Dooley <conor.dooley@microchip.com>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> ---
>>> MAINTAINERS | 6 +
>>> drivers/mmc/host/Kconfig | 10 ++
>>> drivers/mmc/host/Makefile | 1 +
>>> drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
>>> 4 files changed, 203 insertions(+)
>>> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 85e8f83161d7..644ac9479a6e 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -19640,6 +19640,12 @@ F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
>>> F: drivers/clk/starfive/clk-starfive-jh71*
>>> F: include/dt-bindings/clock/starfive?jh71*.h
>>> +STARFIVE JH7110 MMC/SD/SDIO DRIVER
>>> +M: William Qiu <william.qiu@starfivetech.com>
>>> +S: Supported
>>> +F: Documentation/devicetree/bindings/mmc/starfive*
>>> +F: drivers/mmc/host/dw_mmc-starfive.c
>>> +
>>> STARFIVE JH71X0 PINCTRL DRIVERS
>>> M: Emil Renner Berthing <kernel@esmil.dk>
>>> M: Jianlong Huang <jianlong.huang@starfivetech.com>
>>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>>> index fb1062a6394c..b87262503403 100644
>>> --- a/drivers/mmc/host/Kconfig
>>> +++ b/drivers/mmc/host/Kconfig
>>> @@ -871,6 +871,16 @@ config MMC_DW_ROCKCHIP
>>> Synopsys DesignWare Memory Card Interface driver. Select this option
>>> for platforms based on RK3066, RK3188 and RK3288 SoC's.
>>> +config MMC_DW_STARFIVE
>>> + tristate "StarFive specific extensions for Synopsys DW Memory Card Interface"
>>> + depends on SOC_STARFIVE
>>> + depends on MMC_DW
>>> + select MMC_DW_PLTFM
>>> + help
>>> + This selects support for StarFive JH7110 SoC specific extensions to the
>>> + Synopsys DesignWare Memory Card Interface driver. Select this option
>>> + for platforms based on StarFive JH7110 SoC.
>>> +
>>> config MMC_SH_MMCIF
>>> tristate "SuperH Internal MMCIF support"
>>> depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
>>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>>> index 4e4ceb32c4b4..32c0e5564b9a 100644
>>> --- a/drivers/mmc/host/Makefile
>>> +++ b/drivers/mmc/host/Makefile
>>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
>>> obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
>>> obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
>>> obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
>>> +obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
>>> obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
>>> obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
>>> obj-$(CONFIG_MMC_VUB300) += vub300.o
>>> diff --git a/drivers/mmc/host/dw_mmc-starfive.c b/drivers/mmc/host/dw_mmc-starfive.c
>>> new file mode 100644
>>> index 000000000000..40f5969b07a6
>>> --- /dev/null
>>> +++ b/drivers/mmc/host/dw_mmc-starfive.c
>>> @@ -0,0 +1,186 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * StarFive Designware Mobile Storage Host Controller Driver
>>> + *
>>> + * Copyright (c) 2022 StarFive Technology Co., Ltd.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/mmc/host.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/regmap.h>
>>> +
>>> +#include "dw_mmc.h"
>>> +#include "dw_mmc-pltfm.h"
>>> +
>>> +#define ALL_INT_CLR 0x1ffff
>>> +#define MAX_DELAY_CHAIN 32
>>> +
>>> +struct starfive_priv {
>>> + struct device *dev;
>>> + struct regmap *reg_syscon;
>>> + u32 syscon_offset;
>>> + u32 syscon_shift;
>>> + u32 syscon_mask;
>>> +};
>>> +
>>> +static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>>> +{
>>> + int ret;
>>> + unsigned int clock;
>>> +
>>> + if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
>>> + clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
>>> + ret = clk_set_rate(host->ciu_clk, clock);
>>> + if (ret)
>>> + dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
>>> + host->bus_hz = clk_get_rate(host->ciu_clk);
>>> + } else {
>>> + dev_dbg(host->dev, "Using the internal divider\n");
>>> + }
>>> +}
>>> +
>>> +static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
>>> + u32 opcode)
>>> +{
>>> + static const int grade = MAX_DELAY_CHAIN;
>>> + struct dw_mci *host = slot->host;
>>> + struct starfive_priv *priv = host->priv;
>>> + int rise_point = -1, fall_point = -1;
>>> + int err, prev_err;
>>> + int i;
>>> + bool found = 0;
>>> + u32 regval;
>>> +
>>> + /*
>>> + * Use grade as the max delay chain, and use the rise_point and
>>> + * fall_point to ensure the best sampling point of a data input
>>> + * signals.
>>> + */
>>> + for (i = 0; i < grade; i++) {
>>> + regval = i << priv->syscon_shift;
>>> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>>> + priv->syscon_mask, regval);
>>> + if (err)
>>> + return err;
>>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>>> +
>>> + err = mmc_send_tuning(slot->mmc, opcode, NULL);
>>> + if (!err)
>>> + found = 1;
>>> +
>>> + if (i > 0) {
>>> + if (err && !prev_err)
>>> + fall_point = i - 1;
>>> + if (!err && prev_err)
>>> + rise_point = i;
>>> + }
>>> +
>>> + if (rise_point != -1 && fall_point != -1)
>>> + goto tuning_out;
>>> +
>>> + prev_err = err;
>>> + err = 0;
>>> + }
>>> +
>>> +tuning_out:
>>> + if (found) {
>>> + if (rise_point == -1)
>>> + rise_point = 0;
>>> + if (fall_point == -1)
>>> + fall_point = grade - 1;
>>> + if (fall_point < rise_point) {
>>> + if ((rise_point + fall_point) >
>>> + (grade - 1))
>>> + i = fall_point / 2;
>>> + else
>>> + i = (rise_point + grade - 1) / 2;
>>> + } else {
>>> + i = (rise_point + fall_point) / 2;
>>> + }
>>> +
>>> + regval = i << priv->syscon_shift;
>>> + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>>> + priv->syscon_mask, regval);
>>> + if (err)
>>> + return err;
>>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>>> +
>>> + dev_info(host->dev, "Found valid delay chain! use it [delay=%d]\n", i);
>>> + } else {
>>> + dev_err(host->dev, "No valid delay chain! use default\n");
>>> + err = -EINVAL;
>>> + }
>>> +
>>> + mci_writel(host, RINTSTS, ALL_INT_CLR);
>>> + return err;
>>> +}
>>> +
>>> +static int dw_mci_starfive_parse_dt(struct dw_mci *host)
>>> +{
>>> + struct of_phandle_args args;
>>> + struct starfive_priv *priv;
>>> + int ret;
>>> +
>>> + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>>> + if (!priv)
>>> + return -ENOMEM;
>>> +
>>> + ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
>>> + "starfive,sysreg", 3, 0, &args);
>>> + if (ret) {
>>> + dev_err(host->dev, "Failed to parse starfive,sysreg\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + priv->reg_syscon = syscon_node_to_regmap(args.np);
>>> + of_node_put(args.np);
>>> + if (IS_ERR(priv->reg_syscon))
>>> + return PTR_ERR(priv->reg_syscon);
>>> +
>>> + priv->syscon_offset = args.args[0];
>>> + priv->syscon_shift = args.args[1];
>>> + priv->syscon_mask = args.args[2];
>>> +
>>> + host->priv = priv;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct dw_mci_drv_data starfive_data = {
>>> + .common_caps = MMC_CAP_CMD23,
>>> + .set_ios = dw_mci_starfive_set_ios,
>>> + .parse_dt = dw_mci_starfive_parse_dt,
>>> + .execute_tuning = dw_mci_starfive_execute_tuning,
>>> +};
>>> +
>>> +static const struct of_device_id dw_mci_starfive_match[] = {
>>> + { .compatible = "starfive,jh7110-mmc",
>>> + .data = &starfive_data },
>>> + {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
>>> +
>>> +static int dw_mci_starfive_probe(struct platform_device *pdev)
>>> +{
>>> + return dw_mci_pltfm_register(pdev, &starfive_data);
>>> +}
>>> +
>>> +static struct platform_driver dw_mci_starfive_driver = {
>>> + .probe = dw_mci_starfive_probe,
>>> + .remove = dw_mci_pltfm_remove,
>>> + .driver = {
>>> + .name = "dwmmc_starfive",
>>> + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
>>> + .of_match_table = dw_mci_starfive_match,
>>> + },
>>> +};
>>> +module_platform_driver(dw_mci_starfive_driver);
>>> +
>>> +MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
>>> +MODULE_LICENSE("GPL");
>>> +MODULE_ALIAS("platform:dwmmc_starfive");
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
2023-03-31 9:33 ` William Qiu
@ 2023-04-10 18:04 ` Shengyu Qu
-1 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-04-10 18:04 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1: Type: text/plain, Size: 2185 bytes --]
Hello William,
> On 2023/3/29 0:08, Shengyu Qu wrote:
>> Hello William,
>>
>> Sorry for making noise about this, but seems deleted voltage swtich function
>>
>> doesn't help about this. But there's still a problem about eMMC speed. Currently
>>
>> only about 20MB/s maximum reading speed could be reached when using eMMC
>>
>> on VF2, any idea about this?
>>
>> Best regards,
>>
>> Shengyu
>>
>> 在 2023/3/28 0:01, Shengyu Qu 写道:
>>> Hello William,
>>>
>>> I'm digging into downstream mmc driver these days and found a problem
>>>
>>> that current version mainline driver doesn't has a voltage switch function for
>>>
>>> it. Downstream older version has one but was deleted in this commit [1].
>>>
>>> It was deleted since vf2's SD slot doesn't have 1.8V input but commiter forgot
>>>
>>> that vf2's eMMC slot has a proper 1.8V input.
>>>
>>> So could you add voltage switch function for mainline? I've met a eMMC speed
>>>
>>> problem possibly due to it.
>>>
>>> Best regards,
>>>
>>> Shengyu
>>>
>
> Hi Shengyu,
>
> Sorry for the late reply.
>
> First of all, I will consider adding voltage switch function, but the implementation
> method is to configure the pmic register configuration in dts, and the implementation
> interface will use the voltage switch function in dw_mmc.c.
>
> As for speed, the main reason for the low rate is the clock of JH7110 and the
> associated IO driving strength, in this limit, the maximum reading speed I tested was
> about 50Mb/s.
>
> I will try to reproduce your problem and try to solve it. Thanks for suggestions.
>
> Best regards,
> William
I found out the reason and fixed that. dmwci driver needs vqmmc supply
configured in device tree and a successful voltage change to actually
enable 1.8v mode, even 1.8 supply actually already physically exists.
So to solve this problem, I wrote AXP15060 driver and device tree
bindings basing on -upstream branch and gets over 75MB/s read speed. The
driver series is already under review here:
https://lore.kernel.org/all/TY3P286MB26117891DFB2DD615A7C54EF98969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
Best regards,
Shengyu
[-- Attachment #1.1.2: OpenPGP public key --]
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^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
@ 2023-04-10 18:04 ` Shengyu Qu
0 siblings, 0 replies; 94+ messages in thread
From: Shengyu Qu @ 2023-04-10 18:04 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
[-- Attachment #1.1.1.1: Type: text/plain, Size: 2185 bytes --]
Hello William,
> On 2023/3/29 0:08, Shengyu Qu wrote:
>> Hello William,
>>
>> Sorry for making noise about this, but seems deleted voltage swtich function
>>
>> doesn't help about this. But there's still a problem about eMMC speed. Currently
>>
>> only about 20MB/s maximum reading speed could be reached when using eMMC
>>
>> on VF2, any idea about this?
>>
>> Best regards,
>>
>> Shengyu
>>
>> 在 2023/3/28 0:01, Shengyu Qu 写道:
>>> Hello William,
>>>
>>> I'm digging into downstream mmc driver these days and found a problem
>>>
>>> that current version mainline driver doesn't has a voltage switch function for
>>>
>>> it. Downstream older version has one but was deleted in this commit [1].
>>>
>>> It was deleted since vf2's SD slot doesn't have 1.8V input but commiter forgot
>>>
>>> that vf2's eMMC slot has a proper 1.8V input.
>>>
>>> So could you add voltage switch function for mainline? I've met a eMMC speed
>>>
>>> problem possibly due to it.
>>>
>>> Best regards,
>>>
>>> Shengyu
>>>
>
> Hi Shengyu,
>
> Sorry for the late reply.
>
> First of all, I will consider adding voltage switch function, but the implementation
> method is to configure the pmic register configuration in dts, and the implementation
> interface will use the voltage switch function in dw_mmc.c.
>
> As for speed, the main reason for the low rate is the clock of JH7110 and the
> associated IO driving strength, in this limit, the maximum reading speed I tested was
> about 50Mb/s.
>
> I will try to reproduce your problem and try to solve it. Thanks for suggestions.
>
> Best regards,
> William
I found out the reason and fixed that. dmwci driver needs vqmmc supply
configured in device tree and a successful voltage change to actually
enable 1.8v mode, even 1.8 supply actually already physically exists.
So to solve this problem, I wrote AXP15060 driver and device tree
bindings basing on -upstream branch and gets over 75MB/s read speed. The
driver series is already under review here:
https://lore.kernel.org/all/TY3P286MB26117891DFB2DD615A7C54EF98969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
Best regards,
Shengyu
[-- Attachment #1.1.1.2: OpenPGP public key --]
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[-- Attachment #1.2: OpenPGP digital signature --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
2023-04-10 18:04 ` Shengyu Qu
@ 2023-04-11 2:54 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-04-11 2:54 UTC (permalink / raw)
To: Shengyu Qu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/4/11 2:04, Shengyu Qu wrote:
> Hello William,
>
>> On 2023/3/29 0:08, Shengyu Qu wrote:
>>> Hello William,
>>>
>>> Sorry for making noise about this, but seems deleted voltage swtich function
>>>
>>> doesn't help about this. But there's still a problem about eMMC speed. Currently
>>>
>>> only about 20MB/s maximum reading speed could be reached when using eMMC
>>>
>>> on VF2, any idea about this?
>>>
>>> Best regards,
>>>
>>> Shengyu
>>>
>>> 在 2023/3/28 0:01, Shengyu Qu 写道:
>>>> Hello William,
>>>>
>>>> I'm digging into downstream mmc driver these days and found a problem
>>>>
>>>> that current version mainline driver doesn't has a voltage switch function for
>>>>
>>>> it. Downstream older version has one but was deleted in this commit [1].
>>>>
>>>> It was deleted since vf2's SD slot doesn't have 1.8V input but commiter forgot
>>>>
>>>> that vf2's eMMC slot has a proper 1.8V input.
>>>>
>>>> So could you add voltage switch function for mainline? I've met a eMMC speed
>>>>
>>>> problem possibly due to it.
>>>>
>>>> Best regards,
>>>>
>>>> Shengyu
>>>>
>>
>> Hi Shengyu,
>>
>> Sorry for the late reply.
>>
>> First of all, I will consider adding voltage switch function, but the implementation
>> method is to configure the pmic register configuration in dts, and the implementation
>> interface will use the voltage switch function in dw_mmc.c.
>>
>> As for speed, the main reason for the low rate is the clock of JH7110 and the
>> associated IO driving strength, in this limit, the maximum reading speed I tested was
>> about 50Mb/s.
>>
>> I will try to reproduce your problem and try to solve it. Thanks for suggestions.
>>
>> Best regards,
>> William
> I found out the reason and fixed that. dmwci driver needs vqmmc supply
> configured in device tree and a successful voltage change to actually
> enable 1.8v mode, even 1.8 supply actually already physically exists.
> So to solve this problem, I wrote AXP15060 driver and device tree
> bindings basing on -upstream branch and gets over 75MB/s read speed. The
> driver series is already under review here:
>
> https://lore.kernel.org/all/TY3P286MB26117891DFB2DD615A7C54EF98969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
>
> Best regards,
> Shengyu
Hi Shengyu,
Thanks for the patch series. I will try it on my branch.
Best regards,
William
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 2/4] mmc: starfive: Add sdio/emmc driver support
@ 2023-04-11 2:54 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-04-11 2:54 UTC (permalink / raw)
To: Shengyu Qu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/4/11 2:04, Shengyu Qu wrote:
> Hello William,
>
>> On 2023/3/29 0:08, Shengyu Qu wrote:
>>> Hello William,
>>>
>>> Sorry for making noise about this, but seems deleted voltage swtich function
>>>
>>> doesn't help about this. But there's still a problem about eMMC speed. Currently
>>>
>>> only about 20MB/s maximum reading speed could be reached when using eMMC
>>>
>>> on VF2, any idea about this?
>>>
>>> Best regards,
>>>
>>> Shengyu
>>>
>>> 在 2023/3/28 0:01, Shengyu Qu 写道:
>>>> Hello William,
>>>>
>>>> I'm digging into downstream mmc driver these days and found a problem
>>>>
>>>> that current version mainline driver doesn't has a voltage switch function for
>>>>
>>>> it. Downstream older version has one but was deleted in this commit [1].
>>>>
>>>> It was deleted since vf2's SD slot doesn't have 1.8V input but commiter forgot
>>>>
>>>> that vf2's eMMC slot has a proper 1.8V input.
>>>>
>>>> So could you add voltage switch function for mainline? I've met a eMMC speed
>>>>
>>>> problem possibly due to it.
>>>>
>>>> Best regards,
>>>>
>>>> Shengyu
>>>>
>>
>> Hi Shengyu,
>>
>> Sorry for the late reply.
>>
>> First of all, I will consider adding voltage switch function, but the implementation
>> method is to configure the pmic register configuration in dts, and the implementation
>> interface will use the voltage switch function in dw_mmc.c.
>>
>> As for speed, the main reason for the low rate is the clock of JH7110 and the
>> associated IO driving strength, in this limit, the maximum reading speed I tested was
>> about 50Mb/s.
>>
>> I will try to reproduce your problem and try to solve it. Thanks for suggestions.
>>
>> Best regards,
>> William
> I found out the reason and fixed that. dmwci driver needs vqmmc supply
> configured in device tree and a successful voltage change to actually
> enable 1.8v mode, even 1.8 supply actually already physically exists.
> So to solve this problem, I wrote AXP15060 driver and device tree
> bindings basing on -upstream branch and gets over 75MB/s read speed. The
> driver series is already under review here:
>
> https://lore.kernel.org/all/TY3P286MB26117891DFB2DD615A7C54EF98969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
>
> Best regards,
> Shengyu
Hi Shengyu,
Thanks for the patch series. I will try it on my branch.
Best regards,
William
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
2023-02-15 11:32 ` William Qiu
@ 2023-02-15 11:32 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 11:32 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
William Qiu, linux-kernel
Add the mmc node for the StarFive JH7110 SoC.
Set mmco node to emmc and set mmc1 node to sd.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index c60280b89c73..e1a0248e907f 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -42,6 +42,29 @@ &rtc_osc {
clock-frequency = <32768>;
};
+&mmc0 {
+ max-frequency = <100000000>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ cap-mmc-hw-reset;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
+&mmc1 {
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
&gmac0_rmii_refin {
clock-frequency = <50000000>;
};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 64d260ea1f29..17f7b3ee6ca3 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -314,6 +314,11 @@ uart2: serial@10020000 {
status = "disabled";
};
+ stg_syscon: syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
+
uart3: serial@12000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
@@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
#reset-cells = <1>;
};
+ sys_syscon: syscon@13030000 {
+ compatible = "starfive,jh7110-sys-syscon", "syscon";
+ reg = <0x0 0x13030000 0x0 0x1000>;
+ };
+
gpio: gpio@13040000 {
compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
@@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
#reset-cells = <1>;
};
+ aon_syscon: syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ };
+
gpioa: gpio@17020000 {
compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
@@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
gpio-controller;
#gpio-cells = <2>;
};
+
+ mmc0: mmc@16010000 {
+ compatible = "starfive,jh7110-mmc";
+ reg = <0x0 0x16010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
+ <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+ clock-names = "biu","ciu";
+ resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
+ reset-names = "reset";
+ interrupts = <74>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ data-addr = <0>;
+ starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@16020000 {
+ compatible = "starfive,jh7110-mmc";
+ reg = <0x0 0x16020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
+ <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+ clock-names = "biu","ciu";
+ resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
+ reset-names = "reset";
+ interrupts = <75>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ data-addr = <0>;
+ starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
+ status = "disabled";
+ };
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
@ 2023-02-15 11:32 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 11:32 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
William Qiu, linux-kernel
Add the mmc node for the StarFive JH7110 SoC.
Set mmco node to emmc and set mmc1 node to sd.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index c60280b89c73..e1a0248e907f 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -42,6 +42,29 @@ &rtc_osc {
clock-frequency = <32768>;
};
+&mmc0 {
+ max-frequency = <100000000>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ cap-mmc-hw-reset;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
+&mmc1 {
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
&gmac0_rmii_refin {
clock-frequency = <50000000>;
};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 64d260ea1f29..17f7b3ee6ca3 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -314,6 +314,11 @@ uart2: serial@10020000 {
status = "disabled";
};
+ stg_syscon: syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
+
uart3: serial@12000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
@@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
#reset-cells = <1>;
};
+ sys_syscon: syscon@13030000 {
+ compatible = "starfive,jh7110-sys-syscon", "syscon";
+ reg = <0x0 0x13030000 0x0 0x1000>;
+ };
+
gpio: gpio@13040000 {
compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
@@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
#reset-cells = <1>;
};
+ aon_syscon: syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ };
+
gpioa: gpio@17020000 {
compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
@@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
gpio-controller;
#gpio-cells = <2>;
};
+
+ mmc0: mmc@16010000 {
+ compatible = "starfive,jh7110-mmc";
+ reg = <0x0 0x16010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
+ <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+ clock-names = "biu","ciu";
+ resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
+ reset-names = "reset";
+ interrupts = <74>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ data-addr = <0>;
+ starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@16020000 {
+ compatible = "starfive,jh7110-mmc";
+ reg = <0x0 0x16020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
+ <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+ clock-names = "biu","ciu";
+ resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
+ reset-names = "reset";
+ interrupts = <75>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ data-addr = <0>;
+ starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
+ status = "disabled";
+ };
};
};
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
2023-02-15 11:32 ` William Qiu
@ 2023-02-15 12:12 ` Emil Renner Berthing
-1 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-15 12:12 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
>
> Add the mmc node for the StarFive JH7110 SoC.
> Set mmco node to emmc and set mmc1 node to sd.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
> 2 files changed, 70 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index c60280b89c73..e1a0248e907f 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -42,6 +42,29 @@ &rtc_osc {
> clock-frequency = <32768>;
> };
>
> +&mmc0 {
> + max-frequency = <100000000>;
> + bus-width = <8>;
> + cap-mmc-highspeed;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + non-removable;
> + cap-mmc-hw-reset;
> + post-power-on-delay-ms = <200>;
> + status = "okay";
> +};
> +
> +&mmc1 {
> + max-frequency = <100000000>;
> + bus-width = <4>;
> + no-sdio;
> + no-mmc;
> + broken-cd;
> + cap-sd-highspeed;
> + post-power-on-delay-ms = <200>;
> + status = "okay";
> +};
> +
> &gmac0_rmii_refin {
> clock-frequency = <50000000>;
> };
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 64d260ea1f29..17f7b3ee6ca3 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -314,6 +314,11 @@ uart2: serial@10020000 {
> status = "disabled";
> };
>
> + stg_syscon: syscon@10240000 {
> + compatible = "starfive,jh7110-stg-syscon", "syscon";
> + reg = <0x0 0x10240000 0x0 0x1000>;
> + };
> +
> uart3: serial@12000000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x0 0x12000000 0x0 0x10000>;
> @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
> #reset-cells = <1>;
> };
>
> + sys_syscon: syscon@13030000 {
> + compatible = "starfive,jh7110-sys-syscon", "syscon";
> + reg = <0x0 0x13030000 0x0 0x1000>;
> + };
> +
> gpio: gpio@13040000 {
> compatible = "starfive,jh7110-sys-pinctrl";
> reg = <0x0 0x13040000 0x0 0x10000>;
> @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
> #reset-cells = <1>;
> };
>
> + aon_syscon: syscon@17010000 {
> + compatible = "starfive,jh7110-aon-syscon", "syscon";
> + reg = <0x0 0x17010000 0x0 0x1000>;
> + };
> +
> gpioa: gpio@17020000 {
> compatible = "starfive,jh7110-aon-pinctrl";
> reg = <0x0 0x17020000 0x0 0x10000>;
> @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
> gpio-controller;
> #gpio-cells = <2>;
> };
> +
> + mmc0: mmc@16010000 {
> + compatible = "starfive,jh7110-mmc";
> + reg = <0x0 0x16010000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
> + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> + clock-names = "biu","ciu";
> + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
> + reset-names = "reset";
> + interrupts = <74>;
> + fifo-depth = <32>;
> + fifo-watermark-aligned;
> + data-addr = <0>;
> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
> + status = "disabled";
> + };
> +
> + mmc1: mmc@16020000 {
> + compatible = "starfive,jh7110-mmc";
> + reg = <0x0 0x16020000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
> + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> + clock-names = "biu","ciu";
> + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
> + reset-names = "reset";
> + interrupts = <75>;
> + fifo-depth = <32>;
> + fifo-watermark-aligned;
> + data-addr = <0>;
> + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
> + status = "disabled";
> + };
Hi William,
These nodes still don't seem to be sorted by address, eg. by the
number after the @
Also please move the dt-binding patch before this one, so dtb_check
won't fail no matter where git bisect happens to land.
/Emil
> };
> };
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
@ 2023-02-15 12:12 ` Emil Renner Berthing
0 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-15 12:12 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
>
> Add the mmc node for the StarFive JH7110 SoC.
> Set mmco node to emmc and set mmc1 node to sd.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
> 2 files changed, 70 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index c60280b89c73..e1a0248e907f 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -42,6 +42,29 @@ &rtc_osc {
> clock-frequency = <32768>;
> };
>
> +&mmc0 {
> + max-frequency = <100000000>;
> + bus-width = <8>;
> + cap-mmc-highspeed;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + non-removable;
> + cap-mmc-hw-reset;
> + post-power-on-delay-ms = <200>;
> + status = "okay";
> +};
> +
> +&mmc1 {
> + max-frequency = <100000000>;
> + bus-width = <4>;
> + no-sdio;
> + no-mmc;
> + broken-cd;
> + cap-sd-highspeed;
> + post-power-on-delay-ms = <200>;
> + status = "okay";
> +};
> +
> &gmac0_rmii_refin {
> clock-frequency = <50000000>;
> };
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 64d260ea1f29..17f7b3ee6ca3 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -314,6 +314,11 @@ uart2: serial@10020000 {
> status = "disabled";
> };
>
> + stg_syscon: syscon@10240000 {
> + compatible = "starfive,jh7110-stg-syscon", "syscon";
> + reg = <0x0 0x10240000 0x0 0x1000>;
> + };
> +
> uart3: serial@12000000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x0 0x12000000 0x0 0x10000>;
> @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
> #reset-cells = <1>;
> };
>
> + sys_syscon: syscon@13030000 {
> + compatible = "starfive,jh7110-sys-syscon", "syscon";
> + reg = <0x0 0x13030000 0x0 0x1000>;
> + };
> +
> gpio: gpio@13040000 {
> compatible = "starfive,jh7110-sys-pinctrl";
> reg = <0x0 0x13040000 0x0 0x10000>;
> @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
> #reset-cells = <1>;
> };
>
> + aon_syscon: syscon@17010000 {
> + compatible = "starfive,jh7110-aon-syscon", "syscon";
> + reg = <0x0 0x17010000 0x0 0x1000>;
> + };
> +
> gpioa: gpio@17020000 {
> compatible = "starfive,jh7110-aon-pinctrl";
> reg = <0x0 0x17020000 0x0 0x10000>;
> @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
> gpio-controller;
> #gpio-cells = <2>;
> };
> +
> + mmc0: mmc@16010000 {
> + compatible = "starfive,jh7110-mmc";
> + reg = <0x0 0x16010000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
> + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> + clock-names = "biu","ciu";
> + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
> + reset-names = "reset";
> + interrupts = <74>;
> + fifo-depth = <32>;
> + fifo-watermark-aligned;
> + data-addr = <0>;
> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
> + status = "disabled";
> + };
> +
> + mmc1: mmc@16020000 {
> + compatible = "starfive,jh7110-mmc";
> + reg = <0x0 0x16020000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
> + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> + clock-names = "biu","ciu";
> + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
> + reset-names = "reset";
> + interrupts = <75>;
> + fifo-depth = <32>;
> + fifo-watermark-aligned;
> + data-addr = <0>;
> + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
> + status = "disabled";
> + };
Hi William,
These nodes still don't seem to be sorted by address, eg. by the
number after the @
Also please move the dt-binding patch before this one, so dtb_check
won't fail no matter where git bisect happens to land.
/Emil
> };
> };
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
2023-02-15 12:12 ` Emil Renner Berthing
@ 2023-02-15 12:22 ` Emil Renner Berthing
-1 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-15 12:22 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Wed, 15 Feb 2023 at 13:12, Emil Renner Berthing
<emil.renner.berthing@canonical.com> wrote:
>
> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
> >
> > Add the mmc node for the StarFive JH7110 SoC.
> > Set mmco node to emmc and set mmc1 node to sd.
> >
> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> > ---
> > .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
> > 2 files changed, 70 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > index c60280b89c73..e1a0248e907f 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > @@ -42,6 +42,29 @@ &rtc_osc {
> > clock-frequency = <32768>;
> > };
> >
> > +&mmc0 {
> > + max-frequency = <100000000>;
> > + bus-width = <8>;
> > + cap-mmc-highspeed;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + non-removable;
> > + cap-mmc-hw-reset;
> > + post-power-on-delay-ms = <200>;
> > + status = "okay";
> > +};
> > +
> > +&mmc1 {
> > + max-frequency = <100000000>;
> > + bus-width = <4>;
> > + no-sdio;
> > + no-mmc;
> > + broken-cd;
> > + cap-sd-highspeed;
> > + post-power-on-delay-ms = <200>;
> > + status = "okay";
> > +};
These nodes are also still oddly placed in the middle of the external
clocks. Again please keep the external clocks at the top and then
order the nodes alphabetically to have some sort of system.
> > &gmac0_rmii_refin {
> > clock-frequency = <50000000>;
> > };
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 64d260ea1f29..17f7b3ee6ca3 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -314,6 +314,11 @@ uart2: serial@10020000 {
> > status = "disabled";
> > };
> >
> > + stg_syscon: syscon@10240000 {
> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
> > + reg = <0x0 0x10240000 0x0 0x1000>;
> > + };
> > +
> > uart3: serial@12000000 {
> > compatible = "snps,dw-apb-uart";
> > reg = <0x0 0x12000000 0x0 0x10000>;
> > @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
> > #reset-cells = <1>;
> > };
> >
> > + sys_syscon: syscon@13030000 {
> > + compatible = "starfive,jh7110-sys-syscon", "syscon";
> > + reg = <0x0 0x13030000 0x0 0x1000>;
> > + };
> > +
> > gpio: gpio@13040000 {
> > compatible = "starfive,jh7110-sys-pinctrl";
> > reg = <0x0 0x13040000 0x0 0x10000>;
> > @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
> > #reset-cells = <1>;
> > };
> >
> > + aon_syscon: syscon@17010000 {
> > + compatible = "starfive,jh7110-aon-syscon", "syscon";
> > + reg = <0x0 0x17010000 0x0 0x1000>;
> > + };
> > +
> > gpioa: gpio@17020000 {
> > compatible = "starfive,jh7110-aon-pinctrl";
> > reg = <0x0 0x17020000 0x0 0x10000>;
> > @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
> > gpio-controller;
> > #gpio-cells = <2>;
> > };
> > +
> > + mmc0: mmc@16010000 {
> > + compatible = "starfive,jh7110-mmc";
> > + reg = <0x0 0x16010000 0x0 0x10000>;
> > + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
> > + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> > + clock-names = "biu","ciu";
> > + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
> > + reset-names = "reset";
> > + interrupts = <74>;
> > + fifo-depth = <32>;
> > + fifo-watermark-aligned;
> > + data-addr = <0>;
> > + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
> > + status = "disabled";
> > + };
> > +
> > + mmc1: mmc@16020000 {
> > + compatible = "starfive,jh7110-mmc";
> > + reg = <0x0 0x16020000 0x0 0x10000>;
> > + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
> > + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> > + clock-names = "biu","ciu";
> > + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
> > + reset-names = "reset";
> > + interrupts = <75>;
> > + fifo-depth = <32>;
> > + fifo-watermark-aligned;
> > + data-addr = <0>;
> > + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
> > + status = "disabled";
> > + };
>
> Hi William,
>
> These nodes still don't seem to be sorted by address, eg. by the
> number after the @
> Also please move the dt-binding patch before this one, so dtb_check
> won't fail no matter where git bisect happens to land.
>
> /Emil
>
> > };
> > };
> > --
> > 2.34.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
@ 2023-02-15 12:22 ` Emil Renner Berthing
0 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-15 12:22 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Wed, 15 Feb 2023 at 13:12, Emil Renner Berthing
<emil.renner.berthing@canonical.com> wrote:
>
> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
> >
> > Add the mmc node for the StarFive JH7110 SoC.
> > Set mmco node to emmc and set mmc1 node to sd.
> >
> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> > ---
> > .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
> > 2 files changed, 70 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > index c60280b89c73..e1a0248e907f 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > @@ -42,6 +42,29 @@ &rtc_osc {
> > clock-frequency = <32768>;
> > };
> >
> > +&mmc0 {
> > + max-frequency = <100000000>;
> > + bus-width = <8>;
> > + cap-mmc-highspeed;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + non-removable;
> > + cap-mmc-hw-reset;
> > + post-power-on-delay-ms = <200>;
> > + status = "okay";
> > +};
> > +
> > +&mmc1 {
> > + max-frequency = <100000000>;
> > + bus-width = <4>;
> > + no-sdio;
> > + no-mmc;
> > + broken-cd;
> > + cap-sd-highspeed;
> > + post-power-on-delay-ms = <200>;
> > + status = "okay";
> > +};
These nodes are also still oddly placed in the middle of the external
clocks. Again please keep the external clocks at the top and then
order the nodes alphabetically to have some sort of system.
> > &gmac0_rmii_refin {
> > clock-frequency = <50000000>;
> > };
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 64d260ea1f29..17f7b3ee6ca3 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -314,6 +314,11 @@ uart2: serial@10020000 {
> > status = "disabled";
> > };
> >
> > + stg_syscon: syscon@10240000 {
> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
> > + reg = <0x0 0x10240000 0x0 0x1000>;
> > + };
> > +
> > uart3: serial@12000000 {
> > compatible = "snps,dw-apb-uart";
> > reg = <0x0 0x12000000 0x0 0x10000>;
> > @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
> > #reset-cells = <1>;
> > };
> >
> > + sys_syscon: syscon@13030000 {
> > + compatible = "starfive,jh7110-sys-syscon", "syscon";
> > + reg = <0x0 0x13030000 0x0 0x1000>;
> > + };
> > +
> > gpio: gpio@13040000 {
> > compatible = "starfive,jh7110-sys-pinctrl";
> > reg = <0x0 0x13040000 0x0 0x10000>;
> > @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
> > #reset-cells = <1>;
> > };
> >
> > + aon_syscon: syscon@17010000 {
> > + compatible = "starfive,jh7110-aon-syscon", "syscon";
> > + reg = <0x0 0x17010000 0x0 0x1000>;
> > + };
> > +
> > gpioa: gpio@17020000 {
> > compatible = "starfive,jh7110-aon-pinctrl";
> > reg = <0x0 0x17020000 0x0 0x10000>;
> > @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
> > gpio-controller;
> > #gpio-cells = <2>;
> > };
> > +
> > + mmc0: mmc@16010000 {
> > + compatible = "starfive,jh7110-mmc";
> > + reg = <0x0 0x16010000 0x0 0x10000>;
> > + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
> > + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> > + clock-names = "biu","ciu";
> > + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
> > + reset-names = "reset";
> > + interrupts = <74>;
> > + fifo-depth = <32>;
> > + fifo-watermark-aligned;
> > + data-addr = <0>;
> > + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
> > + status = "disabled";
> > + };
> > +
> > + mmc1: mmc@16020000 {
> > + compatible = "starfive,jh7110-mmc";
> > + reg = <0x0 0x16020000 0x0 0x10000>;
> > + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
> > + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> > + clock-names = "biu","ciu";
> > + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
> > + reset-names = "reset";
> > + interrupts = <75>;
> > + fifo-depth = <32>;
> > + fifo-watermark-aligned;
> > + data-addr = <0>;
> > + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
> > + status = "disabled";
> > + };
>
> Hi William,
>
> These nodes still don't seem to be sorted by address, eg. by the
> number after the @
> Also please move the dt-binding patch before this one, so dtb_check
> won't fail no matter where git bisect happens to land.
>
> /Emil
>
> > };
> > };
> > --
> > 2.34.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
2023-02-15 12:22 ` Emil Renner Berthing
@ 2023-02-15 12:26 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 12:26 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/2/15 20:22, Emil Renner Berthing wrote:
> On Wed, 15 Feb 2023 at 13:12, Emil Renner Berthing
> <emil.renner.berthing@canonical.com> wrote:
>>
>> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
>> >
>> > Add the mmc node for the StarFive JH7110 SoC.
>> > Set mmco node to emmc and set mmc1 node to sd.
>> >
>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> > ---
>> > .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
>> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
>> > 2 files changed, 70 insertions(+)
>> >
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> > index c60280b89c73..e1a0248e907f 100644
>> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> > @@ -42,6 +42,29 @@ &rtc_osc {
>> > clock-frequency = <32768>;
>> > };
>> >
>> > +&mmc0 {
>> > + max-frequency = <100000000>;
>> > + bus-width = <8>;
>> > + cap-mmc-highspeed;
>> > + mmc-ddr-1_8v;
>> > + mmc-hs200-1_8v;
>> > + non-removable;
>> > + cap-mmc-hw-reset;
>> > + post-power-on-delay-ms = <200>;
>> > + status = "okay";
>> > +};
>> > +
>> > +&mmc1 {
>> > + max-frequency = <100000000>;
>> > + bus-width = <4>;
>> > + no-sdio;
>> > + no-mmc;
>> > + broken-cd;
>> > + cap-sd-highspeed;
>> > + post-power-on-delay-ms = <200>;
>> > + status = "okay";
>> > +};
>
> These nodes are also still oddly placed in the middle of the external
> clocks. Again please keep the external clocks at the top and then
> order the nodes alphabetically to have some sort of system.
>
Hi Emil,
I'll update it in next version.
Best Regards
William
>> > &gmac0_rmii_refin {
>> > clock-frequency = <50000000>;
>> > };
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > index 64d260ea1f29..17f7b3ee6ca3 100644
>> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > @@ -314,6 +314,11 @@ uart2: serial@10020000 {
>> > status = "disabled";
>> > };
>> >
>> > + stg_syscon: syscon@10240000 {
>> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> > + reg = <0x0 0x10240000 0x0 0x1000>;
>> > + };
>> > +
>> > uart3: serial@12000000 {
>> > compatible = "snps,dw-apb-uart";
>> > reg = <0x0 0x12000000 0x0 0x10000>;
>> > @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
>> > #reset-cells = <1>;
>> > };
>> >
>> > + sys_syscon: syscon@13030000 {
>> > + compatible = "starfive,jh7110-sys-syscon", "syscon";
>> > + reg = <0x0 0x13030000 0x0 0x1000>;
>> > + };
>> > +
>> > gpio: gpio@13040000 {
>> > compatible = "starfive,jh7110-sys-pinctrl";
>> > reg = <0x0 0x13040000 0x0 0x10000>;
>> > @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
>> > #reset-cells = <1>;
>> > };
>> >
>> > + aon_syscon: syscon@17010000 {
>> > + compatible = "starfive,jh7110-aon-syscon", "syscon";
>> > + reg = <0x0 0x17010000 0x0 0x1000>;
>> > + };
>> > +
>> > gpioa: gpio@17020000 {
>> > compatible = "starfive,jh7110-aon-pinctrl";
>> > reg = <0x0 0x17020000 0x0 0x10000>;
>> > @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
>> > gpio-controller;
>> > #gpio-cells = <2>;
>> > };
>> > +
>> > + mmc0: mmc@16010000 {
>> > + compatible = "starfive,jh7110-mmc";
>> > + reg = <0x0 0x16010000 0x0 0x10000>;
>> > + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
>> > + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
>> > + clock-names = "biu","ciu";
>> > + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
>> > + reset-names = "reset";
>> > + interrupts = <74>;
>> > + fifo-depth = <32>;
>> > + fifo-watermark-aligned;
>> > + data-addr = <0>;
>> > + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> > + status = "disabled";
>> > + };
>> > +
>> > + mmc1: mmc@16020000 {
>> > + compatible = "starfive,jh7110-mmc";
>> > + reg = <0x0 0x16020000 0x0 0x10000>;
>> > + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
>> > + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
>> > + clock-names = "biu","ciu";
>> > + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
>> > + reset-names = "reset";
>> > + interrupts = <75>;
>> > + fifo-depth = <32>;
>> > + fifo-watermark-aligned;
>> > + data-addr = <0>;
>> > + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
>> > + status = "disabled";
>> > + };
>>
>> Hi William,
>>
>> These nodes still don't seem to be sorted by address, eg. by the
>> number after the @
>> Also please move the dt-binding patch before this one, so dtb_check
>> won't fail no matter where git bisect happens to land.
>>
>> /Emil
>>
>> > };
>> > };
>> > --
>> > 2.34.1
>> >
>> >
>> > _______________________________________________
>> > linux-riscv mailing list
>> > linux-riscv@lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
@ 2023-02-15 12:26 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 12:26 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/2/15 20:22, Emil Renner Berthing wrote:
> On Wed, 15 Feb 2023 at 13:12, Emil Renner Berthing
> <emil.renner.berthing@canonical.com> wrote:
>>
>> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
>> >
>> > Add the mmc node for the StarFive JH7110 SoC.
>> > Set mmco node to emmc and set mmc1 node to sd.
>> >
>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> > ---
>> > .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
>> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
>> > 2 files changed, 70 insertions(+)
>> >
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> > index c60280b89c73..e1a0248e907f 100644
>> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> > @@ -42,6 +42,29 @@ &rtc_osc {
>> > clock-frequency = <32768>;
>> > };
>> >
>> > +&mmc0 {
>> > + max-frequency = <100000000>;
>> > + bus-width = <8>;
>> > + cap-mmc-highspeed;
>> > + mmc-ddr-1_8v;
>> > + mmc-hs200-1_8v;
>> > + non-removable;
>> > + cap-mmc-hw-reset;
>> > + post-power-on-delay-ms = <200>;
>> > + status = "okay";
>> > +};
>> > +
>> > +&mmc1 {
>> > + max-frequency = <100000000>;
>> > + bus-width = <4>;
>> > + no-sdio;
>> > + no-mmc;
>> > + broken-cd;
>> > + cap-sd-highspeed;
>> > + post-power-on-delay-ms = <200>;
>> > + status = "okay";
>> > +};
>
> These nodes are also still oddly placed in the middle of the external
> clocks. Again please keep the external clocks at the top and then
> order the nodes alphabetically to have some sort of system.
>
Hi Emil,
I'll update it in next version.
Best Regards
William
>> > &gmac0_rmii_refin {
>> > clock-frequency = <50000000>;
>> > };
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > index 64d260ea1f29..17f7b3ee6ca3 100644
>> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > @@ -314,6 +314,11 @@ uart2: serial@10020000 {
>> > status = "disabled";
>> > };
>> >
>> > + stg_syscon: syscon@10240000 {
>> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> > + reg = <0x0 0x10240000 0x0 0x1000>;
>> > + };
>> > +
>> > uart3: serial@12000000 {
>> > compatible = "snps,dw-apb-uart";
>> > reg = <0x0 0x12000000 0x0 0x10000>;
>> > @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
>> > #reset-cells = <1>;
>> > };
>> >
>> > + sys_syscon: syscon@13030000 {
>> > + compatible = "starfive,jh7110-sys-syscon", "syscon";
>> > + reg = <0x0 0x13030000 0x0 0x1000>;
>> > + };
>> > +
>> > gpio: gpio@13040000 {
>> > compatible = "starfive,jh7110-sys-pinctrl";
>> > reg = <0x0 0x13040000 0x0 0x10000>;
>> > @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
>> > #reset-cells = <1>;
>> > };
>> >
>> > + aon_syscon: syscon@17010000 {
>> > + compatible = "starfive,jh7110-aon-syscon", "syscon";
>> > + reg = <0x0 0x17010000 0x0 0x1000>;
>> > + };
>> > +
>> > gpioa: gpio@17020000 {
>> > compatible = "starfive,jh7110-aon-pinctrl";
>> > reg = <0x0 0x17020000 0x0 0x10000>;
>> > @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
>> > gpio-controller;
>> > #gpio-cells = <2>;
>> > };
>> > +
>> > + mmc0: mmc@16010000 {
>> > + compatible = "starfive,jh7110-mmc";
>> > + reg = <0x0 0x16010000 0x0 0x10000>;
>> > + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
>> > + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
>> > + clock-names = "biu","ciu";
>> > + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
>> > + reset-names = "reset";
>> > + interrupts = <74>;
>> > + fifo-depth = <32>;
>> > + fifo-watermark-aligned;
>> > + data-addr = <0>;
>> > + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> > + status = "disabled";
>> > + };
>> > +
>> > + mmc1: mmc@16020000 {
>> > + compatible = "starfive,jh7110-mmc";
>> > + reg = <0x0 0x16020000 0x0 0x10000>;
>> > + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
>> > + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
>> > + clock-names = "biu","ciu";
>> > + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
>> > + reset-names = "reset";
>> > + interrupts = <75>;
>> > + fifo-depth = <32>;
>> > + fifo-watermark-aligned;
>> > + data-addr = <0>;
>> > + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
>> > + status = "disabled";
>> > + };
>>
>> Hi William,
>>
>> These nodes still don't seem to be sorted by address, eg. by the
>> number after the @
>> Also please move the dt-binding patch before this one, so dtb_check
>> won't fail no matter where git bisect happens to land.
>>
>> /Emil
>>
>> > };
>> > };
>> > --
>> > 2.34.1
>> >
>> >
>> > _______________________________________________
>> > linux-riscv mailing list
>> > linux-riscv@lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
2023-02-15 12:26 ` William Qiu
@ 2023-08-05 13:14 ` Emil Renner Berthing
-1 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-08-05 13:14 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Wed, 15 Feb 2023 at 13:26, William Qiu <william.qiu@starfivetech.com> wrote:
> On 2023/2/15 20:22, Emil Renner Berthing wrote:
> > On Wed, 15 Feb 2023 at 13:12, Emil Renner Berthing
> > <emil.renner.berthing@canonical.com> wrote:
> >>
> >> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
> >> >
> >> > Add the mmc node for the StarFive JH7110 SoC.
> >> > Set mmco node to emmc and set mmc1 node to sd.
> >> >
> >> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >> > ---
> >> > .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
> >> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
> >> > 2 files changed, 70 insertions(+)
> >> >
> >> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >> > index c60280b89c73..e1a0248e907f 100644
> >> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >> > @@ -42,6 +42,29 @@ &rtc_osc {
> >> > clock-frequency = <32768>;
> >> > };
> >> >
> >> > +&mmc0 {
> >> > + max-frequency = <100000000>;
> >> > + bus-width = <8>;
> >> > + cap-mmc-highspeed;
> >> > + mmc-ddr-1_8v;
> >> > + mmc-hs200-1_8v;
> >> > + non-removable;
> >> > + cap-mmc-hw-reset;
> >> > + post-power-on-delay-ms = <200>;
> >> > + status = "okay";
> >> > +};
> >> > +
> >> > +&mmc1 {
> >> > + max-frequency = <100000000>;
> >> > + bus-width = <4>;
> >> > + no-sdio;
> >> > + no-mmc;
> >> > + broken-cd;
> >> > + cap-sd-highspeed;
> >> > + post-power-on-delay-ms = <200>;
> >> > + status = "okay";
> >> > +};
> >
> > These nodes are also still oddly placed in the middle of the external
> > clocks. Again please keep the external clocks at the top and then
> > order the nodes alphabetically to have some sort of system.
> >
>
>
> Hi Emil,
>
> I'll update it in next version.
Hi William,
It seems the mmc nodes are still missing from the upstream device
tree. The sysreg nodes have been added in Conors riscv-dt-for-next[1]
branch, so I don't see any missing dependencies. Could you please
update and send a new version of this?
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-dt-for-next
/Emil
> Best Regards
> William
>
> >> > &gmac0_rmii_refin {
> >> > clock-frequency = <50000000>;
> >> > };
> >> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> > index 64d260ea1f29..17f7b3ee6ca3 100644
> >> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> > @@ -314,6 +314,11 @@ uart2: serial@10020000 {
> >> > status = "disabled";
> >> > };
> >> >
> >> > + stg_syscon: syscon@10240000 {
> >> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
> >> > + reg = <0x0 0x10240000 0x0 0x1000>;
> >> > + };
> >> > +
> >> > uart3: serial@12000000 {
> >> > compatible = "snps,dw-apb-uart";
> >> > reg = <0x0 0x12000000 0x0 0x10000>;
> >> > @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
> >> > #reset-cells = <1>;
> >> > };
> >> >
> >> > + sys_syscon: syscon@13030000 {
> >> > + compatible = "starfive,jh7110-sys-syscon", "syscon";
> >> > + reg = <0x0 0x13030000 0x0 0x1000>;
> >> > + };
> >> > +
> >> > gpio: gpio@13040000 {
> >> > compatible = "starfive,jh7110-sys-pinctrl";
> >> > reg = <0x0 0x13040000 0x0 0x10000>;
> >> > @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
> >> > #reset-cells = <1>;
> >> > };
> >> >
> >> > + aon_syscon: syscon@17010000 {
> >> > + compatible = "starfive,jh7110-aon-syscon", "syscon";
> >> > + reg = <0x0 0x17010000 0x0 0x1000>;
> >> > + };
> >> > +
> >> > gpioa: gpio@17020000 {
> >> > compatible = "starfive,jh7110-aon-pinctrl";
> >> > reg = <0x0 0x17020000 0x0 0x10000>;
> >> > @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
> >> > gpio-controller;
> >> > #gpio-cells = <2>;
> >> > };
> >> > +
> >> > + mmc0: mmc@16010000 {
> >> > + compatible = "starfive,jh7110-mmc";
> >> > + reg = <0x0 0x16010000 0x0 0x10000>;
> >> > + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
> >> > + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> >> > + clock-names = "biu","ciu";
> >> > + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
> >> > + reset-names = "reset";
> >> > + interrupts = <74>;
> >> > + fifo-depth = <32>;
> >> > + fifo-watermark-aligned;
> >> > + data-addr = <0>;
> >> > + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
> >> > + status = "disabled";
> >> > + };
> >> > +
> >> > + mmc1: mmc@16020000 {
> >> > + compatible = "starfive,jh7110-mmc";
> >> > + reg = <0x0 0x16020000 0x0 0x10000>;
> >> > + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
> >> > + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> >> > + clock-names = "biu","ciu";
> >> > + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
> >> > + reset-names = "reset";
> >> > + interrupts = <75>;
> >> > + fifo-depth = <32>;
> >> > + fifo-watermark-aligned;
> >> > + data-addr = <0>;
> >> > + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
> >> > + status = "disabled";
> >> > + };
> >>
> >> Hi William,
> >>
> >> These nodes still don't seem to be sorted by address, eg. by the
> >> number after the @
> >> Also please move the dt-binding patch before this one, so dtb_check
> >> won't fail no matter where git bisect happens to land.
> >>
> >> /Emil
> >>
> >> > };
> >> > };
> >> > --
> >> > 2.34.1
> >> >
> >> >
> >> > _______________________________________________
> >> > linux-riscv mailing list
> >> > linux-riscv@lists.infradead.org
> >> > http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
@ 2023-08-05 13:14 ` Emil Renner Berthing
0 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-08-05 13:14 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Wed, 15 Feb 2023 at 13:26, William Qiu <william.qiu@starfivetech.com> wrote:
> On 2023/2/15 20:22, Emil Renner Berthing wrote:
> > On Wed, 15 Feb 2023 at 13:12, Emil Renner Berthing
> > <emil.renner.berthing@canonical.com> wrote:
> >>
> >> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
> >> >
> >> > Add the mmc node for the StarFive JH7110 SoC.
> >> > Set mmco node to emmc and set mmc1 node to sd.
> >> >
> >> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >> > ---
> >> > .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
> >> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
> >> > 2 files changed, 70 insertions(+)
> >> >
> >> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >> > index c60280b89c73..e1a0248e907f 100644
> >> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >> > @@ -42,6 +42,29 @@ &rtc_osc {
> >> > clock-frequency = <32768>;
> >> > };
> >> >
> >> > +&mmc0 {
> >> > + max-frequency = <100000000>;
> >> > + bus-width = <8>;
> >> > + cap-mmc-highspeed;
> >> > + mmc-ddr-1_8v;
> >> > + mmc-hs200-1_8v;
> >> > + non-removable;
> >> > + cap-mmc-hw-reset;
> >> > + post-power-on-delay-ms = <200>;
> >> > + status = "okay";
> >> > +};
> >> > +
> >> > +&mmc1 {
> >> > + max-frequency = <100000000>;
> >> > + bus-width = <4>;
> >> > + no-sdio;
> >> > + no-mmc;
> >> > + broken-cd;
> >> > + cap-sd-highspeed;
> >> > + post-power-on-delay-ms = <200>;
> >> > + status = "okay";
> >> > +};
> >
> > These nodes are also still oddly placed in the middle of the external
> > clocks. Again please keep the external clocks at the top and then
> > order the nodes alphabetically to have some sort of system.
> >
>
>
> Hi Emil,
>
> I'll update it in next version.
Hi William,
It seems the mmc nodes are still missing from the upstream device
tree. The sysreg nodes have been added in Conors riscv-dt-for-next[1]
branch, so I don't see any missing dependencies. Could you please
update and send a new version of this?
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-dt-for-next
/Emil
> Best Regards
> William
>
> >> > &gmac0_rmii_refin {
> >> > clock-frequency = <50000000>;
> >> > };
> >> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> > index 64d260ea1f29..17f7b3ee6ca3 100644
> >> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> > @@ -314,6 +314,11 @@ uart2: serial@10020000 {
> >> > status = "disabled";
> >> > };
> >> >
> >> > + stg_syscon: syscon@10240000 {
> >> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
> >> > + reg = <0x0 0x10240000 0x0 0x1000>;
> >> > + };
> >> > +
> >> > uart3: serial@12000000 {
> >> > compatible = "snps,dw-apb-uart";
> >> > reg = <0x0 0x12000000 0x0 0x10000>;
> >> > @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
> >> > #reset-cells = <1>;
> >> > };
> >> >
> >> > + sys_syscon: syscon@13030000 {
> >> > + compatible = "starfive,jh7110-sys-syscon", "syscon";
> >> > + reg = <0x0 0x13030000 0x0 0x1000>;
> >> > + };
> >> > +
> >> > gpio: gpio@13040000 {
> >> > compatible = "starfive,jh7110-sys-pinctrl";
> >> > reg = <0x0 0x13040000 0x0 0x10000>;
> >> > @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
> >> > #reset-cells = <1>;
> >> > };
> >> >
> >> > + aon_syscon: syscon@17010000 {
> >> > + compatible = "starfive,jh7110-aon-syscon", "syscon";
> >> > + reg = <0x0 0x17010000 0x0 0x1000>;
> >> > + };
> >> > +
> >> > gpioa: gpio@17020000 {
> >> > compatible = "starfive,jh7110-aon-pinctrl";
> >> > reg = <0x0 0x17020000 0x0 0x10000>;
> >> > @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
> >> > gpio-controller;
> >> > #gpio-cells = <2>;
> >> > };
> >> > +
> >> > + mmc0: mmc@16010000 {
> >> > + compatible = "starfive,jh7110-mmc";
> >> > + reg = <0x0 0x16010000 0x0 0x10000>;
> >> > + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
> >> > + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> >> > + clock-names = "biu","ciu";
> >> > + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
> >> > + reset-names = "reset";
> >> > + interrupts = <74>;
> >> > + fifo-depth = <32>;
> >> > + fifo-watermark-aligned;
> >> > + data-addr = <0>;
> >> > + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
> >> > + status = "disabled";
> >> > + };
> >> > +
> >> > + mmc1: mmc@16020000 {
> >> > + compatible = "starfive,jh7110-mmc";
> >> > + reg = <0x0 0x16020000 0x0 0x10000>;
> >> > + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
> >> > + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> >> > + clock-names = "biu","ciu";
> >> > + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
> >> > + reset-names = "reset";
> >> > + interrupts = <75>;
> >> > + fifo-depth = <32>;
> >> > + fifo-watermark-aligned;
> >> > + data-addr = <0>;
> >> > + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
> >> > + status = "disabled";
> >> > + };
> >>
> >> Hi William,
> >>
> >> These nodes still don't seem to be sorted by address, eg. by the
> >> number after the @
> >> Also please move the dt-binding patch before this one, so dtb_check
> >> won't fail no matter where git bisect happens to land.
> >>
> >> /Emil
> >>
> >> > };
> >> > };
> >> > --
> >> > 2.34.1
> >> >
> >> >
> >> > _______________________________________________
> >> > linux-riscv mailing list
> >> > linux-riscv@lists.infradead.org
> >> > http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
2023-08-05 13:14 ` Emil Renner Berthing
@ 2023-08-07 1:51 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-08-07 1:51 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/8/5 21:14, Emil Renner Berthing wrote:
> On Wed, 15 Feb 2023 at 13:26, William Qiu <william.qiu@starfivetech.com> wrote:
>> On 2023/2/15 20:22, Emil Renner Berthing wrote:
>> > On Wed, 15 Feb 2023 at 13:12, Emil Renner Berthing
>> > <emil.renner.berthing@canonical.com> wrote:
>> >>
>> >> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
>> >> >
>> >> > Add the mmc node for the StarFive JH7110 SoC.
>> >> > Set mmco node to emmc and set mmc1 node to sd.
>> >> >
>> >> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> >> > ---
>> >> > .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
>> >> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
>> >> > 2 files changed, 70 insertions(+)
>> >> >
>> >> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> >> > index c60280b89c73..e1a0248e907f 100644
>> >> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> >> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> >> > @@ -42,6 +42,29 @@ &rtc_osc {
>> >> > clock-frequency = <32768>;
>> >> > };
>> >> >
>> >> > +&mmc0 {
>> >> > + max-frequency = <100000000>;
>> >> > + bus-width = <8>;
>> >> > + cap-mmc-highspeed;
>> >> > + mmc-ddr-1_8v;
>> >> > + mmc-hs200-1_8v;
>> >> > + non-removable;
>> >> > + cap-mmc-hw-reset;
>> >> > + post-power-on-delay-ms = <200>;
>> >> > + status = "okay";
>> >> > +};
>> >> > +
>> >> > +&mmc1 {
>> >> > + max-frequency = <100000000>;
>> >> > + bus-width = <4>;
>> >> > + no-sdio;
>> >> > + no-mmc;
>> >> > + broken-cd;
>> >> > + cap-sd-highspeed;
>> >> > + post-power-on-delay-ms = <200>;
>> >> > + status = "okay";
>> >> > +};
>> >
>> > These nodes are also still oddly placed in the middle of the external
>> > clocks. Again please keep the external clocks at the top and then
>> > order the nodes alphabetically to have some sort of system.
>> >
>>
>>
>> Hi Emil,
>>
>> I'll update it in next version.
>
> Hi William,
>
> It seems the mmc nodes are still missing from the upstream device
> tree. The sysreg nodes have been added in Conors riscv-dt-for-next[1]
> branch, so I don't see any missing dependencies. Could you please
> update and send a new version of this?
>
> [1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-dt-for-next
>
> /Emil
>
Hi Emil,
I will start to do the upstream work of this part from this week.
Since the mmc driver has some modifications, I will send a separate
patch series.
Best Regards,
William
>> Best Regards
>> William
>>
>> >> > &gmac0_rmii_refin {
>> >> > clock-frequency = <50000000>;
>> >> > };
>> >> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> >> > index 64d260ea1f29..17f7b3ee6ca3 100644
>> >> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> >> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> >> > @@ -314,6 +314,11 @@ uart2: serial@10020000 {
>> >> > status = "disabled";
>> >> > };
>> >> >
>> >> > + stg_syscon: syscon@10240000 {
>> >> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> >> > + reg = <0x0 0x10240000 0x0 0x1000>;
>> >> > + };
>> >> > +
>> >> > uart3: serial@12000000 {
>> >> > compatible = "snps,dw-apb-uart";
>> >> > reg = <0x0 0x12000000 0x0 0x10000>;
>> >> > @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
>> >> > #reset-cells = <1>;
>> >> > };
>> >> >
>> >> > + sys_syscon: syscon@13030000 {
>> >> > + compatible = "starfive,jh7110-sys-syscon", "syscon";
>> >> > + reg = <0x0 0x13030000 0x0 0x1000>;
>> >> > + };
>> >> > +
>> >> > gpio: gpio@13040000 {
>> >> > compatible = "starfive,jh7110-sys-pinctrl";
>> >> > reg = <0x0 0x13040000 0x0 0x10000>;
>> >> > @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
>> >> > #reset-cells = <1>;
>> >> > };
>> >> >
>> >> > + aon_syscon: syscon@17010000 {
>> >> > + compatible = "starfive,jh7110-aon-syscon", "syscon";
>> >> > + reg = <0x0 0x17010000 0x0 0x1000>;
>> >> > + };
>> >> > +
>> >> > gpioa: gpio@17020000 {
>> >> > compatible = "starfive,jh7110-aon-pinctrl";
>> >> > reg = <0x0 0x17020000 0x0 0x10000>;
>> >> > @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
>> >> > gpio-controller;
>> >> > #gpio-cells = <2>;
>> >> > };
>> >> > +
>> >> > + mmc0: mmc@16010000 {
>> >> > + compatible = "starfive,jh7110-mmc";
>> >> > + reg = <0x0 0x16010000 0x0 0x10000>;
>> >> > + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
>> >> > + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
>> >> > + clock-names = "biu","ciu";
>> >> > + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
>> >> > + reset-names = "reset";
>> >> > + interrupts = <74>;
>> >> > + fifo-depth = <32>;
>> >> > + fifo-watermark-aligned;
>> >> > + data-addr = <0>;
>> >> > + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> >> > + status = "disabled";
>> >> > + };
>> >> > +
>> >> > + mmc1: mmc@16020000 {
>> >> > + compatible = "starfive,jh7110-mmc";
>> >> > + reg = <0x0 0x16020000 0x0 0x10000>;
>> >> > + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
>> >> > + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
>> >> > + clock-names = "biu","ciu";
>> >> > + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
>> >> > + reset-names = "reset";
>> >> > + interrupts = <75>;
>> >> > + fifo-depth = <32>;
>> >> > + fifo-watermark-aligned;
>> >> > + data-addr = <0>;
>> >> > + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
>> >> > + status = "disabled";
>> >> > + };
>> >>
>> >> Hi William,
>> >>
>> >> These nodes still don't seem to be sorted by address, eg. by the
>> >> number after the @
>> >> Also please move the dt-binding patch before this one, so dtb_check
>> >> won't fail no matter where git bisect happens to land.
>> >>
>> >> /Emil
>> >>
>> >> > };
>> >> > };
>> >> > --
>> >> > 2.34.1
>> >> >
>> >> >
>> >> > _______________________________________________
>> >> > linux-riscv mailing list
>> >> > linux-riscv@lists.infradead.org
>> >> > http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
@ 2023-08-07 1:51 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-08-07 1:51 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/8/5 21:14, Emil Renner Berthing wrote:
> On Wed, 15 Feb 2023 at 13:26, William Qiu <william.qiu@starfivetech.com> wrote:
>> On 2023/2/15 20:22, Emil Renner Berthing wrote:
>> > On Wed, 15 Feb 2023 at 13:12, Emil Renner Berthing
>> > <emil.renner.berthing@canonical.com> wrote:
>> >>
>> >> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
>> >> >
>> >> > Add the mmc node for the StarFive JH7110 SoC.
>> >> > Set mmco node to emmc and set mmc1 node to sd.
>> >> >
>> >> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> >> > ---
>> >> > .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
>> >> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
>> >> > 2 files changed, 70 insertions(+)
>> >> >
>> >> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> >> > index c60280b89c73..e1a0248e907f 100644
>> >> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> >> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> >> > @@ -42,6 +42,29 @@ &rtc_osc {
>> >> > clock-frequency = <32768>;
>> >> > };
>> >> >
>> >> > +&mmc0 {
>> >> > + max-frequency = <100000000>;
>> >> > + bus-width = <8>;
>> >> > + cap-mmc-highspeed;
>> >> > + mmc-ddr-1_8v;
>> >> > + mmc-hs200-1_8v;
>> >> > + non-removable;
>> >> > + cap-mmc-hw-reset;
>> >> > + post-power-on-delay-ms = <200>;
>> >> > + status = "okay";
>> >> > +};
>> >> > +
>> >> > +&mmc1 {
>> >> > + max-frequency = <100000000>;
>> >> > + bus-width = <4>;
>> >> > + no-sdio;
>> >> > + no-mmc;
>> >> > + broken-cd;
>> >> > + cap-sd-highspeed;
>> >> > + post-power-on-delay-ms = <200>;
>> >> > + status = "okay";
>> >> > +};
>> >
>> > These nodes are also still oddly placed in the middle of the external
>> > clocks. Again please keep the external clocks at the top and then
>> > order the nodes alphabetically to have some sort of system.
>> >
>>
>>
>> Hi Emil,
>>
>> I'll update it in next version.
>
> Hi William,
>
> It seems the mmc nodes are still missing from the upstream device
> tree. The sysreg nodes have been added in Conors riscv-dt-for-next[1]
> branch, so I don't see any missing dependencies. Could you please
> update and send a new version of this?
>
> [1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-dt-for-next
>
> /Emil
>
Hi Emil,
I will start to do the upstream work of this part from this week.
Since the mmc driver has some modifications, I will send a separate
patch series.
Best Regards,
William
>> Best Regards
>> William
>>
>> >> > &gmac0_rmii_refin {
>> >> > clock-frequency = <50000000>;
>> >> > };
>> >> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> >> > index 64d260ea1f29..17f7b3ee6ca3 100644
>> >> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> >> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> >> > @@ -314,6 +314,11 @@ uart2: serial@10020000 {
>> >> > status = "disabled";
>> >> > };
>> >> >
>> >> > + stg_syscon: syscon@10240000 {
>> >> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> >> > + reg = <0x0 0x10240000 0x0 0x1000>;
>> >> > + };
>> >> > +
>> >> > uart3: serial@12000000 {
>> >> > compatible = "snps,dw-apb-uart";
>> >> > reg = <0x0 0x12000000 0x0 0x10000>;
>> >> > @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
>> >> > #reset-cells = <1>;
>> >> > };
>> >> >
>> >> > + sys_syscon: syscon@13030000 {
>> >> > + compatible = "starfive,jh7110-sys-syscon", "syscon";
>> >> > + reg = <0x0 0x13030000 0x0 0x1000>;
>> >> > + };
>> >> > +
>> >> > gpio: gpio@13040000 {
>> >> > compatible = "starfive,jh7110-sys-pinctrl";
>> >> > reg = <0x0 0x13040000 0x0 0x10000>;
>> >> > @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
>> >> > #reset-cells = <1>;
>> >> > };
>> >> >
>> >> > + aon_syscon: syscon@17010000 {
>> >> > + compatible = "starfive,jh7110-aon-syscon", "syscon";
>> >> > + reg = <0x0 0x17010000 0x0 0x1000>;
>> >> > + };
>> >> > +
>> >> > gpioa: gpio@17020000 {
>> >> > compatible = "starfive,jh7110-aon-pinctrl";
>> >> > reg = <0x0 0x17020000 0x0 0x10000>;
>> >> > @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
>> >> > gpio-controller;
>> >> > #gpio-cells = <2>;
>> >> > };
>> >> > +
>> >> > + mmc0: mmc@16010000 {
>> >> > + compatible = "starfive,jh7110-mmc";
>> >> > + reg = <0x0 0x16010000 0x0 0x10000>;
>> >> > + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
>> >> > + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
>> >> > + clock-names = "biu","ciu";
>> >> > + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
>> >> > + reset-names = "reset";
>> >> > + interrupts = <74>;
>> >> > + fifo-depth = <32>;
>> >> > + fifo-watermark-aligned;
>> >> > + data-addr = <0>;
>> >> > + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> >> > + status = "disabled";
>> >> > + };
>> >> > +
>> >> > + mmc1: mmc@16020000 {
>> >> > + compatible = "starfive,jh7110-mmc";
>> >> > + reg = <0x0 0x16020000 0x0 0x10000>;
>> >> > + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
>> >> > + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
>> >> > + clock-names = "biu","ciu";
>> >> > + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
>> >> > + reset-names = "reset";
>> >> > + interrupts = <75>;
>> >> > + fifo-depth = <32>;
>> >> > + fifo-watermark-aligned;
>> >> > + data-addr = <0>;
>> >> > + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
>> >> > + status = "disabled";
>> >> > + };
>> >>
>> >> Hi William,
>> >>
>> >> These nodes still don't seem to be sorted by address, eg. by the
>> >> number after the @
>> >> Also please move the dt-binding patch before this one, so dtb_check
>> >> won't fail no matter where git bisect happens to land.
>> >>
>> >> /Emil
>> >>
>> >> > };
>> >> > };
>> >> > --
>> >> > 2.34.1
>> >> >
>> >> >
>> >> > _______________________________________________
>> >> > linux-riscv mailing list
>> >> > linux-riscv@lists.infradead.org
>> >> > http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
2023-02-15 12:12 ` Emil Renner Berthing
@ 2023-02-15 12:26 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 12:26 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/2/15 20:12, Emil Renner Berthing wrote:
> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
>>
>> Add the mmc node for the StarFive JH7110 SoC.
>> Set mmco node to emmc and set mmc1 node to sd.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
>> 2 files changed, 70 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index c60280b89c73..e1a0248e907f 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -42,6 +42,29 @@ &rtc_osc {
>> clock-frequency = <32768>;
>> };
>>
>> +&mmc0 {
>> + max-frequency = <100000000>;
>> + bus-width = <8>;
>> + cap-mmc-highspeed;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + non-removable;
>> + cap-mmc-hw-reset;
>> + post-power-on-delay-ms = <200>;
>> + status = "okay";
>> +};
>> +
>> +&mmc1 {
>> + max-frequency = <100000000>;
>> + bus-width = <4>;
>> + no-sdio;
>> + no-mmc;
>> + broken-cd;
>> + cap-sd-highspeed;
>> + post-power-on-delay-ms = <200>;
>> + status = "okay";
>> +};
>> +
>> &gmac0_rmii_refin {
>> clock-frequency = <50000000>;
>> };
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 64d260ea1f29..17f7b3ee6ca3 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -314,6 +314,11 @@ uart2: serial@10020000 {
>> status = "disabled";
>> };
>>
>> + stg_syscon: syscon@10240000 {
>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> + reg = <0x0 0x10240000 0x0 0x1000>;
>> + };
>> +
>> uart3: serial@12000000 {
>> compatible = "snps,dw-apb-uart";
>> reg = <0x0 0x12000000 0x0 0x10000>;
>> @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
>> #reset-cells = <1>;
>> };
>>
>> + sys_syscon: syscon@13030000 {
>> + compatible = "starfive,jh7110-sys-syscon", "syscon";
>> + reg = <0x0 0x13030000 0x0 0x1000>;
>> + };
>> +
>> gpio: gpio@13040000 {
>> compatible = "starfive,jh7110-sys-pinctrl";
>> reg = <0x0 0x13040000 0x0 0x10000>;
>> @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
>> #reset-cells = <1>;
>> };
>>
>> + aon_syscon: syscon@17010000 {
>> + compatible = "starfive,jh7110-aon-syscon", "syscon";
>> + reg = <0x0 0x17010000 0x0 0x1000>;
>> + };
>> +
>> gpioa: gpio@17020000 {
>> compatible = "starfive,jh7110-aon-pinctrl";
>> reg = <0x0 0x17020000 0x0 0x10000>;
>> @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
>> gpio-controller;
>> #gpio-cells = <2>;
>> };
>> +
>> + mmc0: mmc@16010000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x0 0x16010000 0x0 0x10000>;
>> + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
>> + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
>> + reset-names = "reset";
>> + interrupts = <74>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc@16020000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x0 0x16020000 0x0 0x10000>;
>> + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
>> + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
>> + reset-names = "reset";
>> + interrupts = <75>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
>> + status = "disabled";
>> + };
>
> Hi William,
>
> These nodes still don't seem to be sorted by address, eg. by the
> number after the @
> Also please move the dt-binding patch before this one, so dtb_check
> won't fail no matter where git bisect happens to land.
>
> /Emil
>
Hi Emil,
I'll update it in next version.
Best Regards
William
>> };
>> };
>> --
>> 2.34.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
@ 2023-02-15 12:26 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 12:26 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/2/15 20:12, Emil Renner Berthing wrote:
> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@starfivetech.com> wrote:
>>
>> Add the mmc node for the StarFive JH7110 SoC.
>> Set mmco node to emmc and set mmc1 node to sd.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
>> 2 files changed, 70 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index c60280b89c73..e1a0248e907f 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -42,6 +42,29 @@ &rtc_osc {
>> clock-frequency = <32768>;
>> };
>>
>> +&mmc0 {
>> + max-frequency = <100000000>;
>> + bus-width = <8>;
>> + cap-mmc-highspeed;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + non-removable;
>> + cap-mmc-hw-reset;
>> + post-power-on-delay-ms = <200>;
>> + status = "okay";
>> +};
>> +
>> +&mmc1 {
>> + max-frequency = <100000000>;
>> + bus-width = <4>;
>> + no-sdio;
>> + no-mmc;
>> + broken-cd;
>> + cap-sd-highspeed;
>> + post-power-on-delay-ms = <200>;
>> + status = "okay";
>> +};
>> +
>> &gmac0_rmii_refin {
>> clock-frequency = <50000000>;
>> };
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 64d260ea1f29..17f7b3ee6ca3 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -314,6 +314,11 @@ uart2: serial@10020000 {
>> status = "disabled";
>> };
>>
>> + stg_syscon: syscon@10240000 {
>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> + reg = <0x0 0x10240000 0x0 0x1000>;
>> + };
>> +
>> uart3: serial@12000000 {
>> compatible = "snps,dw-apb-uart";
>> reg = <0x0 0x12000000 0x0 0x10000>;
>> @@ -370,6 +375,11 @@ syscrg: clock-controller@13020000 {
>> #reset-cells = <1>;
>> };
>>
>> + sys_syscon: syscon@13030000 {
>> + compatible = "starfive,jh7110-sys-syscon", "syscon";
>> + reg = <0x0 0x13030000 0x0 0x1000>;
>> + };
>> +
>> gpio: gpio@13040000 {
>> compatible = "starfive,jh7110-sys-pinctrl";
>> reg = <0x0 0x13040000 0x0 0x10000>;
>> @@ -397,6 +407,11 @@ aoncrg: clock-controller@17000000 {
>> #reset-cells = <1>;
>> };
>>
>> + aon_syscon: syscon@17010000 {
>> + compatible = "starfive,jh7110-aon-syscon", "syscon";
>> + reg = <0x0 0x17010000 0x0 0x1000>;
>> + };
>> +
>> gpioa: gpio@17020000 {
>> compatible = "starfive,jh7110-aon-pinctrl";
>> reg = <0x0 0x17020000 0x0 0x10000>;
>> @@ -407,5 +422,37 @@ gpioa: gpio@17020000 {
>> gpio-controller;
>> #gpio-cells = <2>;
>> };
>> +
>> + mmc0: mmc@16010000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x0 0x16010000 0x0 0x10000>;
>> + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
>> + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
>> + reset-names = "reset";
>> + interrupts = <74>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc@16020000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x0 0x16020000 0x0 0x10000>;
>> + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
>> + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
>> + reset-names = "reset";
>> + interrupts = <75>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
>> + status = "disabled";
>> + };
>
> Hi William,
>
> These nodes still don't seem to be sorted by address, eg. by the
> number after the @
> Also please move the dt-binding patch before this one, so dtb_check
> won't fail no matter where git bisect happens to land.
>
> /Emil
>
Hi Emil,
I'll update it in next version.
Best Regards
William
>> };
>> };
>> --
>> 2.34.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-15 11:32 ` William Qiu
@ 2023-02-15 11:32 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 11:32 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
William Qiu, linux-kernel
Add documentation to describe StarFive System Controller Registers.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
.../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
MAINTAINERS | 5 ++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
new file mode 100644
index 000000000000..fa4d8522a454
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC system controller
+
+maintainers:
+ - William Qiu <william.qiu@starfivetech.com>
+
+description: |
+ The StarFive JH7110 SoC system controller provides register information such
+ as offset, mask and shift to configure related modules such as MMC and PCIe.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - starfive,jh7110-stg-syscon
+ - starfive,jh7110-sys-syscon
+ - starfive,jh7110-aon-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x10240000 0x1000>;
+ };
+
+ syscon@13030000 {
+ compatible = "starfive,jh7110-sys-syscon", "syscon";
+ reg = <0x13030000 0x1000>;
+ };
+
+ syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x17010000 0x1000>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 644ac9479a6e..fc9d1781516a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19665,6 +19665,11 @@ F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
F: drivers/reset/starfive/reset-starfive-jh71*
F: include/dt-bindings/reset/starfive?jh71*.h
+STARFIVE JH7110 SYSCON
+M: William Qiu <william.qiu@starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
--
2.34.1
^ permalink raw reply related [flat|nested] 94+ messages in thread* [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-15 11:32 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-15 11:32 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
William Qiu, linux-kernel
Add documentation to describe StarFive System Controller Registers.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
.../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
MAINTAINERS | 5 ++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
new file mode 100644
index 000000000000..fa4d8522a454
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC system controller
+
+maintainers:
+ - William Qiu <william.qiu@starfivetech.com>
+
+description: |
+ The StarFive JH7110 SoC system controller provides register information such
+ as offset, mask and shift to configure related modules such as MMC and PCIe.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - starfive,jh7110-stg-syscon
+ - starfive,jh7110-sys-syscon
+ - starfive,jh7110-aon-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x10240000 0x1000>;
+ };
+
+ syscon@13030000 {
+ compatible = "starfive,jh7110-sys-syscon", "syscon";
+ reg = <0x13030000 0x1000>;
+ };
+
+ syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x17010000 0x1000>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 644ac9479a6e..fc9d1781516a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19665,6 +19665,11 @@ F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
F: drivers/reset/starfive/reset-starfive-jh71*
F: include/dt-bindings/reset/starfive?jh71*.h
+STARFIVE JH7110 SYSCON
+M: William Qiu <william.qiu@starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-15 11:32 ` William Qiu
@ 2023-02-16 10:23 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-16 10:23 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 15/02/2023 12:32, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
Thank you for your patch. There is something to discuss/improve.
> +properties:
> + compatible:
> + items:
> + - enum:
> + - starfive,jh7110-stg-syscon
> + - starfive,jh7110-sys-syscon
> + - starfive,jh7110-aon-syscon
Maybe keep them ordered alphabetically?
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + syscon@10240000 {
> + compatible = "starfive,jh7110-stg-syscon", "syscon";
> + reg = <0x10240000 0x1000>;
> + };
Keep only one example. All others are the same.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-16 10:23 ` Krzysztof Kozlowski
0 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-16 10:23 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 15/02/2023 12:32, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
Thank you for your patch. There is something to discuss/improve.
> +properties:
> + compatible:
> + items:
> + - enum:
> + - starfive,jh7110-stg-syscon
> + - starfive,jh7110-sys-syscon
> + - starfive,jh7110-aon-syscon
Maybe keep them ordered alphabetically?
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + syscon@10240000 {
> + compatible = "starfive,jh7110-stg-syscon", "syscon";
> + reg = <0x10240000 0x1000>;
> + };
Keep only one example. All others are the same.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-16 10:23 ` Krzysztof Kozlowski
@ 2023-02-16 10:29 ` Conor Dooley
-1 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-02-16 10:29 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1256 bytes --]
On Thu, Feb 16, 2023 at 11:23:00AM +0100, Krzysztof Kozlowski wrote:
> On 15/02/2023 12:32, William Qiu wrote:
> > Add documentation to describe StarFive System Controller Registers.
> >
> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> > ---
>
> Thank you for your patch. There is something to discuss/improve.
>
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - starfive,jh7110-stg-syscon
> > + - starfive,jh7110-sys-syscon
> > + - starfive,jh7110-aon-syscon
>
> Maybe keep them ordered alphabetically?
>
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + syscon@10240000 {
> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
> > + reg = <0x10240000 0x1000>;
> > + };
>
> Keep only one example. All others are the same.
With these fixed:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
@Krzysztof, I assume the location of the binding is okay with you since
you didn't object to it & I suppose this one is up to me to apply if so.
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-16 10:29 ` Conor Dooley
0 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-02-16 10:29 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1256 bytes --]
On Thu, Feb 16, 2023 at 11:23:00AM +0100, Krzysztof Kozlowski wrote:
> On 15/02/2023 12:32, William Qiu wrote:
> > Add documentation to describe StarFive System Controller Registers.
> >
> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> > ---
>
> Thank you for your patch. There is something to discuss/improve.
>
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - starfive,jh7110-stg-syscon
> > + - starfive,jh7110-sys-syscon
> > + - starfive,jh7110-aon-syscon
>
> Maybe keep them ordered alphabetically?
>
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + syscon@10240000 {
> > + compatible = "starfive,jh7110-stg-syscon", "syscon";
> > + reg = <0x10240000 0x1000>;
> > + };
>
> Keep only one example. All others are the same.
With these fixed:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
@Krzysztof, I assume the location of the binding is okay with you since
you didn't object to it & I suppose this one is up to me to apply if so.
Cheers,
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-16 10:29 ` Conor Dooley
@ 2023-02-16 10:31 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-16 10:31 UTC (permalink / raw)
To: Conor Dooley
Cc: William Qiu, linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 16/02/2023 11:29, Conor Dooley wrote:
> On Thu, Feb 16, 2023 at 11:23:00AM +0100, Krzysztof Kozlowski wrote:
>> On 15/02/2023 12:32, William Qiu wrote:
>>> Add documentation to describe StarFive System Controller Registers.
>>>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> ---
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - starfive,jh7110-stg-syscon
>>> + - starfive,jh7110-sys-syscon
>>> + - starfive,jh7110-aon-syscon
>>
>> Maybe keep them ordered alphabetically?
>>
>>> + - const: syscon
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + syscon@10240000 {
>>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
>>> + reg = <0x10240000 0x1000>;
>>> + };
>>
>> Keep only one example. All others are the same.
>
> With these fixed:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> @Krzysztof, I assume the location of the binding is okay with you since
> you didn't object to it & I suppose this one is up to me to apply if so.
Yeah, generic sysreg devices go to soc. If their primary functions were
different (e.g. clock controller which also is syscon), then they should
go to respective directories, but it's not the case here, I think.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-16 10:31 ` Krzysztof Kozlowski
0 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-16 10:31 UTC (permalink / raw)
To: Conor Dooley
Cc: William Qiu, linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 16/02/2023 11:29, Conor Dooley wrote:
> On Thu, Feb 16, 2023 at 11:23:00AM +0100, Krzysztof Kozlowski wrote:
>> On 15/02/2023 12:32, William Qiu wrote:
>>> Add documentation to describe StarFive System Controller Registers.
>>>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> ---
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - starfive,jh7110-stg-syscon
>>> + - starfive,jh7110-sys-syscon
>>> + - starfive,jh7110-aon-syscon
>>
>> Maybe keep them ordered alphabetically?
>>
>>> + - const: syscon
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + syscon@10240000 {
>>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
>>> + reg = <0x10240000 0x1000>;
>>> + };
>>
>> Keep only one example. All others are the same.
>
> With these fixed:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> @Krzysztof, I assume the location of the binding is okay with you since
> you didn't object to it & I suppose this one is up to me to apply if so.
Yeah, generic sysreg devices go to soc. If their primary functions were
different (e.g. clock controller which also is syscon), then they should
go to respective directories, but it's not the case here, I think.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-16 10:31 ` Krzysztof Kozlowski
@ 2023-03-06 14:04 ` Conor Dooley
-1 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-03-06 14:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2054 bytes --]
Hey William,
On Thu, Feb 16, 2023 at 11:31:45AM +0100, Krzysztof Kozlowski wrote:
> On 16/02/2023 11:29, Conor Dooley wrote:
> > On Thu, Feb 16, 2023 at 11:23:00AM +0100, Krzysztof Kozlowski wrote:
> >> On 15/02/2023 12:32, William Qiu wrote:
> >>> Add documentation to describe StarFive System Controller Registers.
> >>>
> >>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>> ---
> >>
> >> Thank you for your patch. There is something to discuss/improve.
Could you please submit a v5 of this, with the bits below fixed,
whenever Hal sends their next version of the base dts series?
There's no maintainers coverage for a soc/starfive subdirectory of
dt-bindings yet, so please CC conor@kernel.org &
linux-riscv@lists.infradead.com on the patch.
Thanks,
Conor.
> >>
> >>> +properties:
> >>> + compatible:
> >>> + items:
> >>> + - enum:
> >>> + - starfive,jh7110-stg-syscon
> >>> + - starfive,jh7110-sys-syscon
> >>> + - starfive,jh7110-aon-syscon
> >>
> >> Maybe keep them ordered alphabetically?
> >>
> >>> + - const: syscon
> >>> +
> >>> + reg:
> >>> + maxItems: 1
> >>> +
> >>> +required:
> >>> + - compatible
> >>> + - reg
> >>> +
> >>> +additionalProperties: false
> >>> +
> >>> +examples:
> >>> + - |
> >>> + syscon@10240000 {
> >>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
> >>> + reg = <0x10240000 0x1000>;
> >>> + };
> >>
> >> Keep only one example. All others are the same.
> >
> > With these fixed:
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> >
> > @Krzysztof, I assume the location of the binding is okay with you since
> > you didn't object to it & I suppose this one is up to me to apply if so.
>
> Yeah, generic sysreg devices go to soc. If their primary functions were
> different (e.g. clock controller which also is syscon), then they should
> go to respective directories, but it's not the case here, I think.
>
> Best regards,
> Krzysztof
>
>
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-03-06 14:04 ` Conor Dooley
0 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-03-06 14:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 2054 bytes --]
Hey William,
On Thu, Feb 16, 2023 at 11:31:45AM +0100, Krzysztof Kozlowski wrote:
> On 16/02/2023 11:29, Conor Dooley wrote:
> > On Thu, Feb 16, 2023 at 11:23:00AM +0100, Krzysztof Kozlowski wrote:
> >> On 15/02/2023 12:32, William Qiu wrote:
> >>> Add documentation to describe StarFive System Controller Registers.
> >>>
> >>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>> ---
> >>
> >> Thank you for your patch. There is something to discuss/improve.
Could you please submit a v5 of this, with the bits below fixed,
whenever Hal sends their next version of the base dts series?
There's no maintainers coverage for a soc/starfive subdirectory of
dt-bindings yet, so please CC conor@kernel.org &
linux-riscv@lists.infradead.com on the patch.
Thanks,
Conor.
> >>
> >>> +properties:
> >>> + compatible:
> >>> + items:
> >>> + - enum:
> >>> + - starfive,jh7110-stg-syscon
> >>> + - starfive,jh7110-sys-syscon
> >>> + - starfive,jh7110-aon-syscon
> >>
> >> Maybe keep them ordered alphabetically?
> >>
> >>> + - const: syscon
> >>> +
> >>> + reg:
> >>> + maxItems: 1
> >>> +
> >>> +required:
> >>> + - compatible
> >>> + - reg
> >>> +
> >>> +additionalProperties: false
> >>> +
> >>> +examples:
> >>> + - |
> >>> + syscon@10240000 {
> >>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
> >>> + reg = <0x10240000 0x1000>;
> >>> + };
> >>
> >> Keep only one example. All others are the same.
> >
> > With these fixed:
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> >
> > @Krzysztof, I assume the location of the binding is okay with you since
> > you didn't object to it & I suppose this one is up to me to apply if so.
>
> Yeah, generic sysreg devices go to soc. If their primary functions were
> different (e.g. clock controller which also is syscon), then they should
> go to respective directories, but it's not the case here, I think.
>
> Best regards,
> Krzysztof
>
>
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-03-06 14:04 ` Conor Dooley
@ 2023-03-07 1:43 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-03-07 1:43 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/3/6 22:04, Conor Dooley wrote:
> Hey William,
>
> On Thu, Feb 16, 2023 at 11:31:45AM +0100, Krzysztof Kozlowski wrote:
>> On 16/02/2023 11:29, Conor Dooley wrote:
>> > On Thu, Feb 16, 2023 at 11:23:00AM +0100, Krzysztof Kozlowski wrote:
>> >> On 15/02/2023 12:32, William Qiu wrote:
>> >>> Add documentation to describe StarFive System Controller Registers.
>> >>>
>> >>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> >>> ---
>> >>
>> >> Thank you for your patch. There is something to discuss/improve.
>
> Could you please submit a v5 of this, with the bits below fixed,
> whenever Hal sends their next version of the base dts series?
> There's no maintainers coverage for a soc/starfive subdirectory of
> dt-bindings yet, so please CC conor@kernel.org &
> linux-riscv@lists.infradead.com on the patch.
>
> Thanks,
> Conor.
>
I'll do it today.
Best regards
William
>> >>
>> >>> +properties:
>> >>> + compatible:
>> >>> + items:
>> >>> + - enum:
>> >>> + - starfive,jh7110-stg-syscon
>> >>> + - starfive,jh7110-sys-syscon
>> >>> + - starfive,jh7110-aon-syscon
>> >>
>> >> Maybe keep them ordered alphabetically?
>> >>
>> >>> + - const: syscon
>> >>> +
>> >>> + reg:
>> >>> + maxItems: 1
>> >>> +
>> >>> +required:
>> >>> + - compatible
>> >>> + - reg
>> >>> +
>> >>> +additionalProperties: false
>> >>> +
>> >>> +examples:
>> >>> + - |
>> >>> + syscon@10240000 {
>> >>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> >>> + reg = <0x10240000 0x1000>;
>> >>> + };
>> >>
>> >> Keep only one example. All others are the same.
>> >
>> > With these fixed:
>> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> >
>> > @Krzysztof, I assume the location of the binding is okay with you since
>> > you didn't object to it & I suppose this one is up to me to apply if so.
>>
>> Yeah, generic sysreg devices go to soc. If their primary functions were
>> different (e.g. clock controller which also is syscon), then they should
>> go to respective directories, but it's not the case here, I think.
>>
>> Best regards,
>> Krzysztof
>>
>>
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-03-07 1:43 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-03-07 1:43 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/3/6 22:04, Conor Dooley wrote:
> Hey William,
>
> On Thu, Feb 16, 2023 at 11:31:45AM +0100, Krzysztof Kozlowski wrote:
>> On 16/02/2023 11:29, Conor Dooley wrote:
>> > On Thu, Feb 16, 2023 at 11:23:00AM +0100, Krzysztof Kozlowski wrote:
>> >> On 15/02/2023 12:32, William Qiu wrote:
>> >>> Add documentation to describe StarFive System Controller Registers.
>> >>>
>> >>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> >>> ---
>> >>
>> >> Thank you for your patch. There is something to discuss/improve.
>
> Could you please submit a v5 of this, with the bits below fixed,
> whenever Hal sends their next version of the base dts series?
> There's no maintainers coverage for a soc/starfive subdirectory of
> dt-bindings yet, so please CC conor@kernel.org &
> linux-riscv@lists.infradead.com on the patch.
>
> Thanks,
> Conor.
>
I'll do it today.
Best regards
William
>> >>
>> >>> +properties:
>> >>> + compatible:
>> >>> + items:
>> >>> + - enum:
>> >>> + - starfive,jh7110-stg-syscon
>> >>> + - starfive,jh7110-sys-syscon
>> >>> + - starfive,jh7110-aon-syscon
>> >>
>> >> Maybe keep them ordered alphabetically?
>> >>
>> >>> + - const: syscon
>> >>> +
>> >>> + reg:
>> >>> + maxItems: 1
>> >>> +
>> >>> +required:
>> >>> + - compatible
>> >>> + - reg
>> >>> +
>> >>> +additionalProperties: false
>> >>> +
>> >>> +examples:
>> >>> + - |
>> >>> + syscon@10240000 {
>> >>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> >>> + reg = <0x10240000 0x1000>;
>> >>> + };
>> >>
>> >> Keep only one example. All others are the same.
>> >
>> > With these fixed:
>> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> >
>> > @Krzysztof, I assume the location of the binding is okay with you since
>> > you didn't object to it & I suppose this one is up to me to apply if so.
>>
>> Yeah, generic sysreg devices go to soc. If their primary functions were
>> different (e.g. clock controller which also is syscon), then they should
>> go to respective directories, but it's not the case here, I think.
>>
>> Best regards,
>> Krzysztof
>>
>>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-16 10:23 ` Krzysztof Kozlowski
@ 2023-02-16 10:30 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-16 10:30 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/2/16 18:23, Krzysztof Kozlowski wrote:
> On 15/02/2023 12:32, William Qiu wrote:
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>
> Thank you for your patch. There is something to discuss/improve.
>
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - starfive,jh7110-stg-syscon
>> + - starfive,jh7110-sys-syscon
>> + - starfive,jh7110-aon-syscon
>
> Maybe keep them ordered alphabetically?
>
I'm sorting by register address, or I can keep them ordered
alphabetically，which is better?
>> + - const: syscon
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + syscon@10240000 {
>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> + reg = <0x10240000 0x1000>;
>> + };
>
> Keep only one example. All others are the same.
>
Will update in next version.
Thanks for taking times to review this patch series.
Best regards
William
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-16 10:30 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-16 10:30 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 2023/2/16 18:23, Krzysztof Kozlowski wrote:
> On 15/02/2023 12:32, William Qiu wrote:
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>
> Thank you for your patch. There is something to discuss/improve.
>
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - starfive,jh7110-stg-syscon
>> + - starfive,jh7110-sys-syscon
>> + - starfive,jh7110-aon-syscon
>
> Maybe keep them ordered alphabetically?
>
I'm sorting by register address, or I can keep them ordered
alphabetically，which is better?
>> + - const: syscon
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + syscon@10240000 {
>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> + reg = <0x10240000 0x1000>;
>> + };
>
> Keep only one example. All others are the same.
>
Will update in next version.
Thanks for taking times to review this patch series.
Best regards
William
>
> Best regards,
> Krzysztof
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-16 10:30 ` William Qiu
@ 2023-02-16 10:32 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-16 10:32 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 16/02/2023 11:30, William Qiu wrote:
>
>
> On 2023/2/16 18:23, Krzysztof Kozlowski wrote:
>> On 15/02/2023 12:32, William Qiu wrote:
>>> Add documentation to describe StarFive System Controller Registers.
>>>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> ---
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - starfive,jh7110-stg-syscon
>>> + - starfive,jh7110-sys-syscon
>>> + - starfive,jh7110-aon-syscon
>>
>> Maybe keep them ordered alphabetically?
>>
>
> I'm sorting by register address, or I can keep them ordered
> alphabetically，which is better?
We don't know register address here, so I propose alphabetically.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-16 10:32 ` Krzysztof Kozlowski
0 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-16 10:32 UTC (permalink / raw)
To: William Qiu, linux-riscv, devicetree, linux-mmc
Cc: Rob Herring, Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson,
linux-kernel
On 16/02/2023 11:30, William Qiu wrote:
>
>
> On 2023/2/16 18:23, Krzysztof Kozlowski wrote:
>> On 15/02/2023 12:32, William Qiu wrote:
>>> Add documentation to describe StarFive System Controller Registers.
>>>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> ---
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - starfive,jh7110-stg-syscon
>>> + - starfive,jh7110-sys-syscon
>>> + - starfive,jh7110-aon-syscon
>>
>> Maybe keep them ordered alphabetically?
>>
>
> I'm sorting by register address, or I can keep them ordered
> alphabetically，which is better?
We don't know register address here, so I propose alphabetically.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-15 11:32 ` William Qiu
@ 2023-02-20 23:43 ` Rob Herring
-1 siblings, 0 replies; 94+ messages in thread
From: Rob Herring @ 2023-02-20 23:43 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> MAINTAINERS | 5 ++
> 2 files changed, 56 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..fa4d8522a454
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
> +
> +maintainers:
> + - William Qiu <william.qiu@starfivetech.com>
> +
> +description: |
> + The StarFive JH7110 SoC system controller provides register information such
> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - starfive,jh7110-stg-syscon
> + - starfive,jh7110-sys-syscon
> + - starfive,jh7110-aon-syscon
Is 'syscon' really part of what the blocks are called? Is just 'stg',
'sys' and 'aon' not unique enough?
Rob
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-20 23:43 ` Rob Herring
0 siblings, 0 replies; 94+ messages in thread
From: Rob Herring @ 2023-02-20 23:43 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> MAINTAINERS | 5 ++
> 2 files changed, 56 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..fa4d8522a454
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
> +
> +maintainers:
> + - William Qiu <william.qiu@starfivetech.com>
> +
> +description: |
> + The StarFive JH7110 SoC system controller provides register information such
> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - starfive,jh7110-stg-syscon
> + - starfive,jh7110-sys-syscon
> + - starfive,jh7110-aon-syscon
Is 'syscon' really part of what the blocks are called? Is just 'stg',
'sys' and 'aon' not unique enough?
Rob
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-20 23:43 ` Rob Herring
@ 2023-02-21 2:44 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-21 2:44 UTC (permalink / raw)
To: Rob Herring
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/2/21 7:43, Rob Herring wrote:
> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>> MAINTAINERS | 5 ++
>> 2 files changed, 56 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> new file mode 100644
>> index 000000000000..fa4d8522a454
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> @@ -0,0 +1,51 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SoC system controller
>> +
>> +maintainers:
>> + - William Qiu <william.qiu@starfivetech.com>
>> +
>> +description: |
>> + The StarFive JH7110 SoC system controller provides register information such
>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - starfive,jh7110-stg-syscon
>> + - starfive,jh7110-sys-syscon
>> + - starfive,jh7110-aon-syscon
>
> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> 'sys' and 'aon' not unique enough?
>
> Rob
Hi Rob,
In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
controller, so 'syscon' is added to avoid confusion.
Best regards
William
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-21 2:44 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-21 2:44 UTC (permalink / raw)
To: Rob Herring
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/2/21 7:43, Rob Herring wrote:
> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>> MAINTAINERS | 5 ++
>> 2 files changed, 56 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> new file mode 100644
>> index 000000000000..fa4d8522a454
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> @@ -0,0 +1,51 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SoC system controller
>> +
>> +maintainers:
>> + - William Qiu <william.qiu@starfivetech.com>
>> +
>> +description: |
>> + The StarFive JH7110 SoC system controller provides register information such
>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - starfive,jh7110-stg-syscon
>> + - starfive,jh7110-sys-syscon
>> + - starfive,jh7110-aon-syscon
>
> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> 'sys' and 'aon' not unique enough?
>
> Rob
Hi Rob,
In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
controller, so 'syscon' is added to avoid confusion.
Best regards
William
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-21 2:44 ` William Qiu
@ 2023-02-27 22:29 ` Rob Herring
-1 siblings, 0 replies; 94+ messages in thread
From: Rob Herring @ 2023-02-27 22:29 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>
>
> On 2023/2/21 7:43, Rob Herring wrote:
> > On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >> Add documentation to describe StarFive System Controller Registers.
> >>
> >> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >> ---
> >> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >> MAINTAINERS | 5 ++
> >> 2 files changed, 56 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >> new file mode 100644
> >> index 000000000000..fa4d8522a454
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >> @@ -0,0 +1,51 @@
> >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: StarFive JH7110 SoC system controller
> >> +
> >> +maintainers:
> >> + - William Qiu <william.qiu@starfivetech.com>
> >> +
> >> +description: |
> >> + The StarFive JH7110 SoC system controller provides register information such
> >> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >> +
> >> +properties:
> >> + compatible:
> >> + items:
> >> + - enum:
> >> + - starfive,jh7110-stg-syscon
> >> + - starfive,jh7110-sys-syscon
> >> + - starfive,jh7110-aon-syscon
> >
> > Is 'syscon' really part of what the blocks are called? Is just 'stg',
> > 'sys' and 'aon' not unique enough?
> >
> > Rob
> Hi Rob,
>
> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> controller, so 'syscon' is added to avoid confusion.
You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
different h/w blocks and unrelated to each other? Or 'syscrg' is the
clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
of 'sys-syscon' or possibly just all one node. Please provide details on
the entire h/w block so we can provide better input on the bindings.
Rob
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-27 22:29 ` Rob Herring
0 siblings, 0 replies; 94+ messages in thread
From: Rob Herring @ 2023-02-27 22:29 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>
>
> On 2023/2/21 7:43, Rob Herring wrote:
> > On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >> Add documentation to describe StarFive System Controller Registers.
> >>
> >> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >> ---
> >> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >> MAINTAINERS | 5 ++
> >> 2 files changed, 56 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >> new file mode 100644
> >> index 000000000000..fa4d8522a454
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >> @@ -0,0 +1,51 @@
> >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: StarFive JH7110 SoC system controller
> >> +
> >> +maintainers:
> >> + - William Qiu <william.qiu@starfivetech.com>
> >> +
> >> +description: |
> >> + The StarFive JH7110 SoC system controller provides register information such
> >> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >> +
> >> +properties:
> >> + compatible:
> >> + items:
> >> + - enum:
> >> + - starfive,jh7110-stg-syscon
> >> + - starfive,jh7110-sys-syscon
> >> + - starfive,jh7110-aon-syscon
> >
> > Is 'syscon' really part of what the blocks are called? Is just 'stg',
> > 'sys' and 'aon' not unique enough?
> >
> > Rob
> Hi Rob,
>
> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> controller, so 'syscon' is added to avoid confusion.
You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
different h/w blocks and unrelated to each other? Or 'syscrg' is the
clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
of 'sys-syscon' or possibly just all one node. Please provide details on
the entire h/w block so we can provide better input on the bindings.
Rob
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-27 22:29 ` Rob Herring
@ 2023-02-28 9:05 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-28 9:05 UTC (permalink / raw)
To: Rob Herring
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/2/28 6:29, Rob Herring wrote:
> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>>
>>
>> On 2023/2/21 7:43, Rob Herring wrote:
>> > On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>> >> Add documentation to describe StarFive System Controller Registers.
>> >>
>> >> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> >> ---
>> >> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>> >> MAINTAINERS | 5 ++
>> >> 2 files changed, 56 insertions(+)
>> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> >> new file mode 100644
>> >> index 000000000000..fa4d8522a454
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> >> @@ -0,0 +1,51 @@
>> >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> >> +%YAML 1.2
>> >> +---
>> >> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> >> +
>> >> +title: StarFive JH7110 SoC system controller
>> >> +
>> >> +maintainers:
>> >> + - William Qiu <william.qiu@starfivetech.com>
>> >> +
>> >> +description: |
>> >> + The StarFive JH7110 SoC system controller provides register information such
>> >> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>> >> +
>> >> +properties:
>> >> + compatible:
>> >> + items:
>> >> + - enum:
>> >> + - starfive,jh7110-stg-syscon
>> >> + - starfive,jh7110-sys-syscon
>> >> + - starfive,jh7110-aon-syscon
>> >
>> > Is 'syscon' really part of what the blocks are called? Is just 'stg',
>> > 'sys' and 'aon' not unique enough?
>> >
>> > Rob
>> Hi Rob,
>>
>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
>> controller, so 'syscon' is added to avoid confusion.
>
> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> of 'sys-syscon' or possibly just all one node. Please provide details on
> the entire h/w block so we can provide better input on the bindings.
>
> Rob
Hi Rob,
It's my description that's problematic.'syscon' here refers to the hardware module
inside our JH7110, which is different from the syscon interface in linux. The syscon
I added now uses the syscon interface of linux to read and write the syscon register
in our JH7110. So we decided to name it that way.
Best regards
William
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-28 9:05 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-28 9:05 UTC (permalink / raw)
To: Rob Herring
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On 2023/2/28 6:29, Rob Herring wrote:
> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>>
>>
>> On 2023/2/21 7:43, Rob Herring wrote:
>> > On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>> >> Add documentation to describe StarFive System Controller Registers.
>> >>
>> >> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> >> ---
>> >> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>> >> MAINTAINERS | 5 ++
>> >> 2 files changed, 56 insertions(+)
>> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> >> new file mode 100644
>> >> index 000000000000..fa4d8522a454
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> >> @@ -0,0 +1,51 @@
>> >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> >> +%YAML 1.2
>> >> +---
>> >> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> >> +
>> >> +title: StarFive JH7110 SoC system controller
>> >> +
>> >> +maintainers:
>> >> + - William Qiu <william.qiu@starfivetech.com>
>> >> +
>> >> +description: |
>> >> + The StarFive JH7110 SoC system controller provides register information such
>> >> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>> >> +
>> >> +properties:
>> >> + compatible:
>> >> + items:
>> >> + - enum:
>> >> + - starfive,jh7110-stg-syscon
>> >> + - starfive,jh7110-sys-syscon
>> >> + - starfive,jh7110-aon-syscon
>> >
>> > Is 'syscon' really part of what the blocks are called? Is just 'stg',
>> > 'sys' and 'aon' not unique enough?
>> >
>> > Rob
>> Hi Rob,
>>
>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
>> controller, so 'syscon' is added to avoid confusion.
>
> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> of 'sys-syscon' or possibly just all one node. Please provide details on
> the entire h/w block so we can provide better input on the bindings.
>
> Rob
Hi Rob,
It's my description that's problematic.'syscon' here refers to the hardware module
inside our JH7110, which is different from the syscon interface in linux. The syscon
I added now uses the syscon interface of linux to read and write the syscon register
in our JH7110. So we decided to name it that way.
Best regards
William
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-28 9:05 ` William Qiu
@ 2023-02-28 10:37 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-28 10:37 UTC (permalink / raw)
To: William Qiu, Rob Herring
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On 28/02/2023 10:05, William Qiu wrote:
>
>
> On 2023/2/28 6:29, Rob Herring wrote:
>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>>>
>>>
>>> On 2023/2/21 7:43, Rob Herring wrote:
>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>>>>> Add documentation to describe StarFive System Controller Registers.
>>>>>
>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>>> ---
>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>>>>> MAINTAINERS | 5 ++
>>>>> 2 files changed, 56 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..fa4d8522a454
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>> @@ -0,0 +1,51 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: StarFive JH7110 SoC system controller
>>>>> +
>>>>> +maintainers:
>>>>> + - William Qiu <william.qiu@starfivetech.com>
>>>>> +
>>>>> +description: |
>>>>> + The StarFive JH7110 SoC system controller provides register information such
>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>>> +
>>>>> +properties:
>>>>> + compatible:
>>>>> + items:
>>>>> + - enum:
>>>>> + - starfive,jh7110-stg-syscon
>>>>> + - starfive,jh7110-sys-syscon
>>>>> + - starfive,jh7110-aon-syscon
>>>>
>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
>>>> 'sys' and 'aon' not unique enough?
>>>>
>>>> Rob
>>> Hi Rob,
>>>
>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
>>> controller, so 'syscon' is added to avoid confusion.
>>
>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
>> of 'sys-syscon' or possibly just all one node. Please provide details on
>> the entire h/w block so we can provide better input on the bindings.
>>
>> Rob
>
> Hi Rob,
>
> It's my description that's problematic.'syscon' here refers to the hardware module
> inside our JH7110, which is different from the syscon interface in linux. The syscon
> I added now uses the syscon interface of linux to read and write the syscon register
> in our JH7110. So we decided to name it that way.
You didn't really answer Rob's questions.
Also, syscon is Linux term, so are you sure hardware module is called
like this? Hardware engineers took pure Linux name and used it?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-28 10:37 ` Krzysztof Kozlowski
0 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-28 10:37 UTC (permalink / raw)
To: William Qiu, Rob Herring
Cc: linux-riscv, devicetree, linux-mmc, Krzysztof Kozlowski,
Jaehoon Chung, Ulf Hansson, linux-kernel
On 28/02/2023 10:05, William Qiu wrote:
>
>
> On 2023/2/28 6:29, Rob Herring wrote:
>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>>>
>>>
>>> On 2023/2/21 7:43, Rob Herring wrote:
>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>>>>> Add documentation to describe StarFive System Controller Registers.
>>>>>
>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>>> ---
>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>>>>> MAINTAINERS | 5 ++
>>>>> 2 files changed, 56 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..fa4d8522a454
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>> @@ -0,0 +1,51 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: StarFive JH7110 SoC system controller
>>>>> +
>>>>> +maintainers:
>>>>> + - William Qiu <william.qiu@starfivetech.com>
>>>>> +
>>>>> +description: |
>>>>> + The StarFive JH7110 SoC system controller provides register information such
>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>>> +
>>>>> +properties:
>>>>> + compatible:
>>>>> + items:
>>>>> + - enum:
>>>>> + - starfive,jh7110-stg-syscon
>>>>> + - starfive,jh7110-sys-syscon
>>>>> + - starfive,jh7110-aon-syscon
>>>>
>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
>>>> 'sys' and 'aon' not unique enough?
>>>>
>>>> Rob
>>> Hi Rob,
>>>
>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
>>> controller, so 'syscon' is added to avoid confusion.
>>
>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
>> of 'sys-syscon' or possibly just all one node. Please provide details on
>> the entire h/w block so we can provide better input on the bindings.
>>
>> Rob
>
> Hi Rob,
>
> It's my description that's problematic.'syscon' here refers to the hardware module
> inside our JH7110, which is different from the syscon interface in linux. The syscon
> I added now uses the syscon interface of linux to read and write the syscon register
> in our JH7110. So we decided to name it that way.
You didn't really answer Rob's questions.
Also, syscon is Linux term, so are you sure hardware module is called
like this? Hardware engineers took pure Linux name and used it?
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-28 10:37 ` Krzysztof Kozlowski
@ 2023-02-28 11:02 ` Emil Renner Berthing
-1 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-28 11:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 28/02/2023 10:05, William Qiu wrote:
> >
> >
> > On 2023/2/28 6:29, Rob Herring wrote:
> >> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
> >>>
> >>>
> >>> On 2023/2/21 7:43, Rob Herring wrote:
> >>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >>>>> Add documentation to describe StarFive System Controller Registers.
> >>>>>
> >>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>>>> ---
> >>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >>>>> MAINTAINERS | 5 ++
> >>>>> 2 files changed, 56 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>> new file mode 100644
> >>>>> index 000000000000..fa4d8522a454
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>> @@ -0,0 +1,51 @@
> >>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>>>> +%YAML 1.2
> >>>>> +---
> >>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>> +
> >>>>> +title: StarFive JH7110 SoC system controller
> >>>>> +
> >>>>> +maintainers:
> >>>>> + - William Qiu <william.qiu@starfivetech.com>
> >>>>> +
> >>>>> +description: |
> >>>>> + The StarFive JH7110 SoC system controller provides register information such
> >>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >>>>> +
> >>>>> +properties:
> >>>>> + compatible:
> >>>>> + items:
> >>>>> + - enum:
> >>>>> + - starfive,jh7110-stg-syscon
> >>>>> + - starfive,jh7110-sys-syscon
> >>>>> + - starfive,jh7110-aon-syscon
> >>>>
> >>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> >>>> 'sys' and 'aon' not unique enough?
> >>>>
> >>>> Rob
> >>> Hi Rob,
> >>>
> >>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> >>> controller, so 'syscon' is added to avoid confusion.
> >>
> >> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> >> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> >> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> >> of 'sys-syscon' or possibly just all one node. Please provide details on
> >> the entire h/w block so we can provide better input on the bindings.
> >>
> >> Rob
> >
> > Hi Rob,
> >
> > It's my description that's problematic.'syscon' here refers to the hardware module
> > inside our JH7110, which is different from the syscon interface in linux. The syscon
> > I added now uses the syscon interface of linux to read and write the syscon register
> > in our JH7110. So we decided to name it that way.
>
> You didn't really answer Rob's questions.
>
> Also, syscon is Linux term, so are you sure hardware module is called
> like this? Hardware engineers took pure Linux name and used it?
Yes, from the documentation I could find[1] there are CRG blocks
(Clock and Reset Generator) and SYSCON blocks:
SYS CRG
STG CRG
AON CRG
SYS SYSCON
STG SYSCON
AON SYSCON
The CRG blocks contain registers to control clocks and resets that
follow a pattern used by the clock and reset drivers. The SYSCON
blocks just seem to contain registers to control whatever didn't fit
in any other blocks, but might be vaguely related to the peripherals
that run off clocks controlled by the corresponding CRG block.
[1]: https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/system_control_registers.html
/Emil
> Best regards,
> Krzysztof
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-28 11:02 ` Emil Renner Berthing
0 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-28 11:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 28/02/2023 10:05, William Qiu wrote:
> >
> >
> > On 2023/2/28 6:29, Rob Herring wrote:
> >> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
> >>>
> >>>
> >>> On 2023/2/21 7:43, Rob Herring wrote:
> >>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >>>>> Add documentation to describe StarFive System Controller Registers.
> >>>>>
> >>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>>>> ---
> >>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >>>>> MAINTAINERS | 5 ++
> >>>>> 2 files changed, 56 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>> new file mode 100644
> >>>>> index 000000000000..fa4d8522a454
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>> @@ -0,0 +1,51 @@
> >>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>>>> +%YAML 1.2
> >>>>> +---
> >>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>> +
> >>>>> +title: StarFive JH7110 SoC system controller
> >>>>> +
> >>>>> +maintainers:
> >>>>> + - William Qiu <william.qiu@starfivetech.com>
> >>>>> +
> >>>>> +description: |
> >>>>> + The StarFive JH7110 SoC system controller provides register information such
> >>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >>>>> +
> >>>>> +properties:
> >>>>> + compatible:
> >>>>> + items:
> >>>>> + - enum:
> >>>>> + - starfive,jh7110-stg-syscon
> >>>>> + - starfive,jh7110-sys-syscon
> >>>>> + - starfive,jh7110-aon-syscon
> >>>>
> >>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> >>>> 'sys' and 'aon' not unique enough?
> >>>>
> >>>> Rob
> >>> Hi Rob,
> >>>
> >>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> >>> controller, so 'syscon' is added to avoid confusion.
> >>
> >> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> >> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> >> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> >> of 'sys-syscon' or possibly just all one node. Please provide details on
> >> the entire h/w block so we can provide better input on the bindings.
> >>
> >> Rob
> >
> > Hi Rob,
> >
> > It's my description that's problematic.'syscon' here refers to the hardware module
> > inside our JH7110, which is different from the syscon interface in linux. The syscon
> > I added now uses the syscon interface of linux to read and write the syscon register
> > in our JH7110. So we decided to name it that way.
>
> You didn't really answer Rob's questions.
>
> Also, syscon is Linux term, so are you sure hardware module is called
> like this? Hardware engineers took pure Linux name and used it?
Yes, from the documentation I could find[1] there are CRG blocks
(Clock and Reset Generator) and SYSCON blocks:
SYS CRG
STG CRG
AON CRG
SYS SYSCON
STG SYSCON
AON SYSCON
The CRG blocks contain registers to control clocks and resets that
follow a pattern used by the clock and reset drivers. The SYSCON
blocks just seem to contain registers to control whatever didn't fit
in any other blocks, but might be vaguely related to the peripherals
that run off clocks controlled by the corresponding CRG block.
[1]: https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/system_control_registers.html
/Emil
> Best regards,
> Krzysztof
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-28 11:02 ` Emil Renner Berthing
@ 2023-02-28 11:28 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-28 11:28 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 28/02/2023 12:02, Emil Renner Berthing wrote:
> On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 28/02/2023 10:05, William Qiu wrote:
>>>
>>>
>>> On 2023/2/28 6:29, Rob Herring wrote:
>>>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>>>>>
>>>>>
>>>>> On 2023/2/21 7:43, Rob Herring wrote:
>>>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>>>>>>> Add documentation to describe StarFive System Controller Registers.
>>>>>>>
>>>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>>>>> ---
>>>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>>>>>>> MAINTAINERS | 5 ++
>>>>>>> 2 files changed, 56 insertions(+)
>>>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..fa4d8522a454
>>>>>>> --- /dev/null
>>>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>> @@ -0,0 +1,51 @@
>>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>>>>> +%YAML 1.2
>>>>>>> +---
>>>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>>> +
>>>>>>> +title: StarFive JH7110 SoC system controller
>>>>>>> +
>>>>>>> +maintainers:
>>>>>>> + - William Qiu <william.qiu@starfivetech.com>
>>>>>>> +
>>>>>>> +description: |
>>>>>>> + The StarFive JH7110 SoC system controller provides register information such
>>>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>>>>> +
>>>>>>> +properties:
>>>>>>> + compatible:
>>>>>>> + items:
>>>>>>> + - enum:
>>>>>>> + - starfive,jh7110-stg-syscon
>>>>>>> + - starfive,jh7110-sys-syscon
>>>>>>> + - starfive,jh7110-aon-syscon
>>>>>>
>>>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
>>>>>> 'sys' and 'aon' not unique enough?
>>>>>>
>>>>>> Rob
>>>>> Hi Rob,
>>>>>
>>>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
>>>>> controller, so 'syscon' is added to avoid confusion.
>>>>
>>>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
>>>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
>>>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
>>>> of 'sys-syscon' or possibly just all one node. Please provide details on
>>>> the entire h/w block so we can provide better input on the bindings.
>>>>
>>>> Rob
>>>
>>> Hi Rob,
>>>
>>> It's my description that's problematic.'syscon' here refers to the hardware module
>>> inside our JH7110, which is different from the syscon interface in linux. The syscon
>>> I added now uses the syscon interface of linux to read and write the syscon register
>>> in our JH7110. So we decided to name it that way.
>>
>> You didn't really answer Rob's questions.
>>
>> Also, syscon is Linux term, so are you sure hardware module is called
>> like this? Hardware engineers took pure Linux name and used it?
>
> Yes, from the documentation I could find[1] there are CRG blocks
> (Clock and Reset Generator) and SYSCON blocks:
> SYS CRG
> STG CRG
> AON CRG
> SYS SYSCON
> STG SYSCON
> AON SYSCON
>
> The CRG blocks contain registers to control clocks and resets that
> follow a pattern used by the clock and reset drivers. The SYSCON
> blocks just seem to contain registers to control whatever didn't fit
> in any other blocks, but might be vaguely related to the peripherals
> that run off clocks controlled by the corresponding CRG block.
The memory map [1] suggests these are indeed separate address spaces,
e.g. AON CRG, AON SYSCON and AON GPIO, but now I would argue that this
might be still one device - AON (or STG, SYS). Just like PCIE0 has four
address spaces, it does not mean you have four separate PCIE0 devices.
You have only one PCIE0, just like you have only one AON, one STG and
one SYS (System).
[1] https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/system_memory_map.html
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-28 11:28 ` Krzysztof Kozlowski
0 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-28 11:28 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 28/02/2023 12:02, Emil Renner Berthing wrote:
> On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 28/02/2023 10:05, William Qiu wrote:
>>>
>>>
>>> On 2023/2/28 6:29, Rob Herring wrote:
>>>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>>>>>
>>>>>
>>>>> On 2023/2/21 7:43, Rob Herring wrote:
>>>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>>>>>>> Add documentation to describe StarFive System Controller Registers.
>>>>>>>
>>>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>>>>> ---
>>>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>>>>>>> MAINTAINERS | 5 ++
>>>>>>> 2 files changed, 56 insertions(+)
>>>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..fa4d8522a454
>>>>>>> --- /dev/null
>>>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>> @@ -0,0 +1,51 @@
>>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>>>>> +%YAML 1.2
>>>>>>> +---
>>>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>>> +
>>>>>>> +title: StarFive JH7110 SoC system controller
>>>>>>> +
>>>>>>> +maintainers:
>>>>>>> + - William Qiu <william.qiu@starfivetech.com>
>>>>>>> +
>>>>>>> +description: |
>>>>>>> + The StarFive JH7110 SoC system controller provides register information such
>>>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>>>>> +
>>>>>>> +properties:
>>>>>>> + compatible:
>>>>>>> + items:
>>>>>>> + - enum:
>>>>>>> + - starfive,jh7110-stg-syscon
>>>>>>> + - starfive,jh7110-sys-syscon
>>>>>>> + - starfive,jh7110-aon-syscon
>>>>>>
>>>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
>>>>>> 'sys' and 'aon' not unique enough?
>>>>>>
>>>>>> Rob
>>>>> Hi Rob,
>>>>>
>>>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
>>>>> controller, so 'syscon' is added to avoid confusion.
>>>>
>>>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
>>>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
>>>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
>>>> of 'sys-syscon' or possibly just all one node. Please provide details on
>>>> the entire h/w block so we can provide better input on the bindings.
>>>>
>>>> Rob
>>>
>>> Hi Rob,
>>>
>>> It's my description that's problematic.'syscon' here refers to the hardware module
>>> inside our JH7110, which is different from the syscon interface in linux. The syscon
>>> I added now uses the syscon interface of linux to read and write the syscon register
>>> in our JH7110. So we decided to name it that way.
>>
>> You didn't really answer Rob's questions.
>>
>> Also, syscon is Linux term, so are you sure hardware module is called
>> like this? Hardware engineers took pure Linux name and used it?
>
> Yes, from the documentation I could find[1] there are CRG blocks
> (Clock and Reset Generator) and SYSCON blocks:
> SYS CRG
> STG CRG
> AON CRG
> SYS SYSCON
> STG SYSCON
> AON SYSCON
>
> The CRG blocks contain registers to control clocks and resets that
> follow a pattern used by the clock and reset drivers. The SYSCON
> blocks just seem to contain registers to control whatever didn't fit
> in any other blocks, but might be vaguely related to the peripherals
> that run off clocks controlled by the corresponding CRG block.
The memory map [1] suggests these are indeed separate address spaces,
e.g. AON CRG, AON SYSCON and AON GPIO, but now I would argue that this
might be still one device - AON (or STG, SYS). Just like PCIE0 has four
address spaces, it does not mean you have four separate PCIE0 devices.
You have only one PCIE0, just like you have only one AON, one STG and
one SYS (System).
[1] https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/system_memory_map.html
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-28 11:28 ` Krzysztof Kozlowski
@ 2023-02-28 14:59 ` Emil Renner Berthing
-1 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-28 14:59 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Tue, 28 Feb 2023 at 12:28, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 28/02/2023 12:02, Emil Renner Berthing wrote:
> > On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 28/02/2023 10:05, William Qiu wrote:
> >>>
> >>>
> >>> On 2023/2/28 6:29, Rob Herring wrote:
> >>>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
> >>>>>
> >>>>>
> >>>>> On 2023/2/21 7:43, Rob Herring wrote:
> >>>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >>>>>>> Add documentation to describe StarFive System Controller Registers.
> >>>>>>>
> >>>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>>>>>> ---
> >>>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >>>>>>> MAINTAINERS | 5 ++
> >>>>>>> 2 files changed, 56 insertions(+)
> >>>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>>
> >>>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>> new file mode 100644
> >>>>>>> index 000000000000..fa4d8522a454
> >>>>>>> --- /dev/null
> >>>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>> @@ -0,0 +1,51 @@
> >>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>>>>>> +%YAML 1.2
> >>>>>>> +---
> >>>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>>>> +
> >>>>>>> +title: StarFive JH7110 SoC system controller
> >>>>>>> +
> >>>>>>> +maintainers:
> >>>>>>> + - William Qiu <william.qiu@starfivetech.com>
> >>>>>>> +
> >>>>>>> +description: |
> >>>>>>> + The StarFive JH7110 SoC system controller provides register information such
> >>>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >>>>>>> +
> >>>>>>> +properties:
> >>>>>>> + compatible:
> >>>>>>> + items:
> >>>>>>> + - enum:
> >>>>>>> + - starfive,jh7110-stg-syscon
> >>>>>>> + - starfive,jh7110-sys-syscon
> >>>>>>> + - starfive,jh7110-aon-syscon
> >>>>>>
> >>>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> >>>>>> 'sys' and 'aon' not unique enough?
> >>>>>>
> >>>>>> Rob
> >>>>> Hi Rob,
> >>>>>
> >>>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> >>>>> controller, so 'syscon' is added to avoid confusion.
> >>>>
> >>>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> >>>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> >>>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> >>>> of 'sys-syscon' or possibly just all one node. Please provide details on
> >>>> the entire h/w block so we can provide better input on the bindings.
> >>>>
> >>>> Rob
> >>>
> >>> Hi Rob,
> >>>
> >>> It's my description that's problematic.'syscon' here refers to the hardware module
> >>> inside our JH7110, which is different from the syscon interface in linux. The syscon
> >>> I added now uses the syscon interface of linux to read and write the syscon register
> >>> in our JH7110. So we decided to name it that way.
> >>
> >> You didn't really answer Rob's questions.
> >>
> >> Also, syscon is Linux term, so are you sure hardware module is called
> >> like this? Hardware engineers took pure Linux name and used it?
> >
> > Yes, from the documentation I could find[1] there are CRG blocks
> > (Clock and Reset Generator) and SYSCON blocks:
> > SYS CRG
> > STG CRG
> > AON CRG
> > SYS SYSCON
> > STG SYSCON
> > AON SYSCON
> >
> > The CRG blocks contain registers to control clocks and resets that
> > follow a pattern used by the clock and reset drivers. The SYSCON
> > blocks just seem to contain registers to control whatever didn't fit
> > in any other blocks, but might be vaguely related to the peripherals
> > that run off clocks controlled by the corresponding CRG block.
>
> The memory map [1] suggests these are indeed separate address spaces,
> e.g. AON CRG, AON SYSCON and AON GPIO, but now I would argue that this
> might be still one device - AON (or STG, SYS). Just like PCIE0 has four
> address spaces, it does not mean you have four separate PCIE0 devices.
> You have only one PCIE0, just like you have only one AON, one STG and
> one SYS (System).
I see what you mean, but if you look into what the registers in the
SYSCON blocks actually do it's not clear to me that they should be
grouped with the clocks/resets any more than say the pinctrl/GPIO
node. Maybe it's my fault for not giving you the full picture. Eg. for
"system" and "always-on" there are blocks:
SYS CRG
SYS SYSCON
SYS IOMUX
AON CRG
AON SYSCON
AON IOMUX
..and it really don't see why eg. SYS CRG and SYS SYSCON should be
thought of as one device, but not include SYS IOMUX then.
As an examly the SYS SYSCON includes registers to control:
- remapping of different peripherals from SD controller to video encoders
- voltage select for certain GPIO pins
- phy interface selection for ethernet and CAN
- QuadSPI delay chain and SRAM configuration
- PLL configuration
- endian selection for the SD controller
To me this is pretty much exactly described by the syscon device tree binding:
"System controller node represents a register region containing a set
of miscellaneous registers. The registers are not cohesive enough to
represent as any specific type of device. [..]"
In any case it's clear that however the SYSCON blocks are represented
in the device tree, a driver for it would need to export registers in
the SYSCON block for other drivers to use.
/Emil
> [1] https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/system_memory_map.html
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-28 14:59 ` Emil Renner Berthing
0 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-28 14:59 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Tue, 28 Feb 2023 at 12:28, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 28/02/2023 12:02, Emil Renner Berthing wrote:
> > On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 28/02/2023 10:05, William Qiu wrote:
> >>>
> >>>
> >>> On 2023/2/28 6:29, Rob Herring wrote:
> >>>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
> >>>>>
> >>>>>
> >>>>> On 2023/2/21 7:43, Rob Herring wrote:
> >>>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >>>>>>> Add documentation to describe StarFive System Controller Registers.
> >>>>>>>
> >>>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>>>>>> ---
> >>>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >>>>>>> MAINTAINERS | 5 ++
> >>>>>>> 2 files changed, 56 insertions(+)
> >>>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>>
> >>>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>> new file mode 100644
> >>>>>>> index 000000000000..fa4d8522a454
> >>>>>>> --- /dev/null
> >>>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>> @@ -0,0 +1,51 @@
> >>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>>>>>> +%YAML 1.2
> >>>>>>> +---
> >>>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>>>> +
> >>>>>>> +title: StarFive JH7110 SoC system controller
> >>>>>>> +
> >>>>>>> +maintainers:
> >>>>>>> + - William Qiu <william.qiu@starfivetech.com>
> >>>>>>> +
> >>>>>>> +description: |
> >>>>>>> + The StarFive JH7110 SoC system controller provides register information such
> >>>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >>>>>>> +
> >>>>>>> +properties:
> >>>>>>> + compatible:
> >>>>>>> + items:
> >>>>>>> + - enum:
> >>>>>>> + - starfive,jh7110-stg-syscon
> >>>>>>> + - starfive,jh7110-sys-syscon
> >>>>>>> + - starfive,jh7110-aon-syscon
> >>>>>>
> >>>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> >>>>>> 'sys' and 'aon' not unique enough?
> >>>>>>
> >>>>>> Rob
> >>>>> Hi Rob,
> >>>>>
> >>>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> >>>>> controller, so 'syscon' is added to avoid confusion.
> >>>>
> >>>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> >>>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> >>>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> >>>> of 'sys-syscon' or possibly just all one node. Please provide details on
> >>>> the entire h/w block so we can provide better input on the bindings.
> >>>>
> >>>> Rob
> >>>
> >>> Hi Rob,
> >>>
> >>> It's my description that's problematic.'syscon' here refers to the hardware module
> >>> inside our JH7110, which is different from the syscon interface in linux. The syscon
> >>> I added now uses the syscon interface of linux to read and write the syscon register
> >>> in our JH7110. So we decided to name it that way.
> >>
> >> You didn't really answer Rob's questions.
> >>
> >> Also, syscon is Linux term, so are you sure hardware module is called
> >> like this? Hardware engineers took pure Linux name and used it?
> >
> > Yes, from the documentation I could find[1] there are CRG blocks
> > (Clock and Reset Generator) and SYSCON blocks:
> > SYS CRG
> > STG CRG
> > AON CRG
> > SYS SYSCON
> > STG SYSCON
> > AON SYSCON
> >
> > The CRG blocks contain registers to control clocks and resets that
> > follow a pattern used by the clock and reset drivers. The SYSCON
> > blocks just seem to contain registers to control whatever didn't fit
> > in any other blocks, but might be vaguely related to the peripherals
> > that run off clocks controlled by the corresponding CRG block.
>
> The memory map [1] suggests these are indeed separate address spaces,
> e.g. AON CRG, AON SYSCON and AON GPIO, but now I would argue that this
> might be still one device - AON (or STG, SYS). Just like PCIE0 has four
> address spaces, it does not mean you have four separate PCIE0 devices.
> You have only one PCIE0, just like you have only one AON, one STG and
> one SYS (System).
I see what you mean, but if you look into what the registers in the
SYSCON blocks actually do it's not clear to me that they should be
grouped with the clocks/resets any more than say the pinctrl/GPIO
node. Maybe it's my fault for not giving you the full picture. Eg. for
"system" and "always-on" there are blocks:
SYS CRG
SYS SYSCON
SYS IOMUX
AON CRG
AON SYSCON
AON IOMUX
..and it really don't see why eg. SYS CRG and SYS SYSCON should be
thought of as one device, but not include SYS IOMUX then.
As an examly the SYS SYSCON includes registers to control:
- remapping of different peripherals from SD controller to video encoders
- voltage select for certain GPIO pins
- phy interface selection for ethernet and CAN
- QuadSPI delay chain and SRAM configuration
- PLL configuration
- endian selection for the SD controller
To me this is pretty much exactly described by the syscon device tree binding:
"System controller node represents a register region containing a set
of miscellaneous registers. The registers are not cohesive enough to
represent as any specific type of device. [..]"
In any case it's clear that however the SYSCON blocks are represented
in the device tree, a driver for it would need to export registers in
the SYSCON block for other drivers to use.
/Emil
> [1] https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/system_memory_map.html
>
>
> Best regards,
> Krzysztof
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-28 14:59 ` Emil Renner Berthing
@ 2023-02-28 16:59 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-28 16:59 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 28/02/2023 15:59, Emil Renner Berthing wrote:
> On Tue, 28 Feb 2023 at 12:28, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 28/02/2023 12:02, Emil Renner Berthing wrote:
>>> On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 28/02/2023 10:05, William Qiu wrote:
>>>>>
>>>>>
>>>>> On 2023/2/28 6:29, Rob Herring wrote:
>>>>>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 2023/2/21 7:43, Rob Herring wrote:
>>>>>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>>>>>>>>> Add documentation to describe StarFive System Controller Registers.
>>>>>>>>>
>>>>>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>>>>>>> ---
>>>>>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>>>>>>>>> MAINTAINERS | 5 ++
>>>>>>>>> 2 files changed, 56 insertions(+)
>>>>>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>>>>
>>>>>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>>>> new file mode 100644
>>>>>>>>> index 000000000000..fa4d8522a454
>>>>>>>>> --- /dev/null
>>>>>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>>>> @@ -0,0 +1,51 @@
>>>>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>>>>>>> +%YAML 1.2
>>>>>>>>> +---
>>>>>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>>>>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>>>>> +
>>>>>>>>> +title: StarFive JH7110 SoC system controller
>>>>>>>>> +
>>>>>>>>> +maintainers:
>>>>>>>>> + - William Qiu <william.qiu@starfivetech.com>
>>>>>>>>> +
>>>>>>>>> +description: |
>>>>>>>>> + The StarFive JH7110 SoC system controller provides register information such
>>>>>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>>>>>>> +
>>>>>>>>> +properties:
>>>>>>>>> + compatible:
>>>>>>>>> + items:
>>>>>>>>> + - enum:
>>>>>>>>> + - starfive,jh7110-stg-syscon
>>>>>>>>> + - starfive,jh7110-sys-syscon
>>>>>>>>> + - starfive,jh7110-aon-syscon
>>>>>>>>
>>>>>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
>>>>>>>> 'sys' and 'aon' not unique enough?
>>>>>>>>
>>>>>>>> Rob
>>>>>>> Hi Rob,
>>>>>>>
>>>>>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
>>>>>>> controller, so 'syscon' is added to avoid confusion.
>>>>>>
>>>>>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
>>>>>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
>>>>>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
>>>>>> of 'sys-syscon' or possibly just all one node. Please provide details on
>>>>>> the entire h/w block so we can provide better input on the bindings.
>>>>>>
>>>>>> Rob
>>>>>
>>>>> Hi Rob,
>>>>>
>>>>> It's my description that's problematic.'syscon' here refers to the hardware module
>>>>> inside our JH7110, which is different from the syscon interface in linux. The syscon
>>>>> I added now uses the syscon interface of linux to read and write the syscon register
>>>>> in our JH7110. So we decided to name it that way.
>>>>
>>>> You didn't really answer Rob's questions.
>>>>
>>>> Also, syscon is Linux term, so are you sure hardware module is called
>>>> like this? Hardware engineers took pure Linux name and used it?
>>>
>>> Yes, from the documentation I could find[1] there are CRG blocks
>>> (Clock and Reset Generator) and SYSCON blocks:
>>> SYS CRG
>>> STG CRG
>>> AON CRG
>>> SYS SYSCON
>>> STG SYSCON
>>> AON SYSCON
>>>
>>> The CRG blocks contain registers to control clocks and resets that
>>> follow a pattern used by the clock and reset drivers. The SYSCON
>>> blocks just seem to contain registers to control whatever didn't fit
>>> in any other blocks, but might be vaguely related to the peripherals
>>> that run off clocks controlled by the corresponding CRG block.
>>
>> The memory map [1] suggests these are indeed separate address spaces,
>> e.g. AON CRG, AON SYSCON and AON GPIO, but now I would argue that this
>> might be still one device - AON (or STG, SYS). Just like PCIE0 has four
>> address spaces, it does not mean you have four separate PCIE0 devices.
>> You have only one PCIE0, just like you have only one AON, one STG and
>> one SYS (System).
>
> I see what you mean, but if you look into what the registers in the
> SYSCON blocks actually do it's not clear to me that they should be
> grouped with the clocks/resets any more than say the pinctrl/GPIO
> node. Maybe it's my fault for not giving you the full picture. Eg. for
> "system" and "always-on" there are blocks:
>
> SYS CRG
> SYS SYSCON
> SYS IOMUX
> AON CRG
> AON SYSCON
> AON IOMUX
>
> ..and it really don't see why eg. SYS CRG and SYS SYSCON should be
> thought of as one device, but not include SYS IOMUX then.
... include sys iomux as well, just like GPIO is included for AON.
>
> As an examly the SYS SYSCON includes registers to control:
> - remapping of different peripherals from SD controller to video encoders
> - voltage select for certain GPIO pins
> - phy interface selection for ethernet and CAN
> - QuadSPI delay chain and SRAM configuration
> - PLL configuration
> - endian selection for the SD controller
>
> To me this is pretty much exactly described by the syscon device tree binding:
> "System controller node represents a register region containing a set
> of miscellaneous registers. The registers are not cohesive enough to
> represent as any specific type of device. [..]"
> In any case it's clear that however the SYSCON blocks are represented
> in the device tree, a driver for it would need to export registers in
> the SYSCON block for other drivers to use.
You started entire sentence with "but" so you disagree but with what
exactly? The naming? But syscon is fine - hardware manual calls it like
that.
The point was that AON is one device (consisting of multiple blocks).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-28 16:59 ` Krzysztof Kozlowski
0 siblings, 0 replies; 94+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-28 16:59 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On 28/02/2023 15:59, Emil Renner Berthing wrote:
> On Tue, 28 Feb 2023 at 12:28, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 28/02/2023 12:02, Emil Renner Berthing wrote:
>>> On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 28/02/2023 10:05, William Qiu wrote:
>>>>>
>>>>>
>>>>> On 2023/2/28 6:29, Rob Herring wrote:
>>>>>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 2023/2/21 7:43, Rob Herring wrote:
>>>>>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>>>>>>>>> Add documentation to describe StarFive System Controller Registers.
>>>>>>>>>
>>>>>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>>>>>>> ---
>>>>>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>>>>>>>>> MAINTAINERS | 5 ++
>>>>>>>>> 2 files changed, 56 insertions(+)
>>>>>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>>>>
>>>>>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>>>> new file mode 100644
>>>>>>>>> index 000000000000..fa4d8522a454
>>>>>>>>> --- /dev/null
>>>>>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>>>>>>>> @@ -0,0 +1,51 @@
>>>>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>>>>>>> +%YAML 1.2
>>>>>>>>> +---
>>>>>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>>>>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>>>>> +
>>>>>>>>> +title: StarFive JH7110 SoC system controller
>>>>>>>>> +
>>>>>>>>> +maintainers:
>>>>>>>>> + - William Qiu <william.qiu@starfivetech.com>
>>>>>>>>> +
>>>>>>>>> +description: |
>>>>>>>>> + The StarFive JH7110 SoC system controller provides register information such
>>>>>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>>>>>>> +
>>>>>>>>> +properties:
>>>>>>>>> + compatible:
>>>>>>>>> + items:
>>>>>>>>> + - enum:
>>>>>>>>> + - starfive,jh7110-stg-syscon
>>>>>>>>> + - starfive,jh7110-sys-syscon
>>>>>>>>> + - starfive,jh7110-aon-syscon
>>>>>>>>
>>>>>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
>>>>>>>> 'sys' and 'aon' not unique enough?
>>>>>>>>
>>>>>>>> Rob
>>>>>>> Hi Rob,
>>>>>>>
>>>>>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
>>>>>>> controller, so 'syscon' is added to avoid confusion.
>>>>>>
>>>>>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
>>>>>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
>>>>>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
>>>>>> of 'sys-syscon' or possibly just all one node. Please provide details on
>>>>>> the entire h/w block so we can provide better input on the bindings.
>>>>>>
>>>>>> Rob
>>>>>
>>>>> Hi Rob,
>>>>>
>>>>> It's my description that's problematic.'syscon' here refers to the hardware module
>>>>> inside our JH7110, which is different from the syscon interface in linux. The syscon
>>>>> I added now uses the syscon interface of linux to read and write the syscon register
>>>>> in our JH7110. So we decided to name it that way.
>>>>
>>>> You didn't really answer Rob's questions.
>>>>
>>>> Also, syscon is Linux term, so are you sure hardware module is called
>>>> like this? Hardware engineers took pure Linux name and used it?
>>>
>>> Yes, from the documentation I could find[1] there are CRG blocks
>>> (Clock and Reset Generator) and SYSCON blocks:
>>> SYS CRG
>>> STG CRG
>>> AON CRG
>>> SYS SYSCON
>>> STG SYSCON
>>> AON SYSCON
>>>
>>> The CRG blocks contain registers to control clocks and resets that
>>> follow a pattern used by the clock and reset drivers. The SYSCON
>>> blocks just seem to contain registers to control whatever didn't fit
>>> in any other blocks, but might be vaguely related to the peripherals
>>> that run off clocks controlled by the corresponding CRG block.
>>
>> The memory map [1] suggests these are indeed separate address spaces,
>> e.g. AON CRG, AON SYSCON and AON GPIO, but now I would argue that this
>> might be still one device - AON (or STG, SYS). Just like PCIE0 has four
>> address spaces, it does not mean you have four separate PCIE0 devices.
>> You have only one PCIE0, just like you have only one AON, one STG and
>> one SYS (System).
>
> I see what you mean, but if you look into what the registers in the
> SYSCON blocks actually do it's not clear to me that they should be
> grouped with the clocks/resets any more than say the pinctrl/GPIO
> node. Maybe it's my fault for not giving you the full picture. Eg. for
> "system" and "always-on" there are blocks:
>
> SYS CRG
> SYS SYSCON
> SYS IOMUX
> AON CRG
> AON SYSCON
> AON IOMUX
>
> ..and it really don't see why eg. SYS CRG and SYS SYSCON should be
> thought of as one device, but not include SYS IOMUX then.
... include sys iomux as well, just like GPIO is included for AON.
>
> As an examly the SYS SYSCON includes registers to control:
> - remapping of different peripherals from SD controller to video encoders
> - voltage select for certain GPIO pins
> - phy interface selection for ethernet and CAN
> - QuadSPI delay chain and SRAM configuration
> - PLL configuration
> - endian selection for the SD controller
>
> To me this is pretty much exactly described by the syscon device tree binding:
> "System controller node represents a register region containing a set
> of miscellaneous registers. The registers are not cohesive enough to
> represent as any specific type of device. [..]"
> In any case it's clear that however the SYSCON blocks are represented
> in the device tree, a driver for it would need to export registers in
> the SYSCON block for other drivers to use.
You started entire sentence with "but" so you disagree but with what
exactly? The naming? But syscon is fine - hardware manual calls it like
that.
The point was that AON is one device (consisting of multiple blocks).
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-28 16:59 ` Krzysztof Kozlowski
@ 2023-02-28 17:31 ` Emil Renner Berthing
-1 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-28 17:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Tue, 28 Feb 2023 at 17:59, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 28/02/2023 15:59, Emil Renner Berthing wrote:
> > On Tue, 28 Feb 2023 at 12:28, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >> On 28/02/2023 12:02, Emil Renner Berthing wrote:
> >>> On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 28/02/2023 10:05, William Qiu wrote:
> >>>>>
> >>>>>
> >>>>> On 2023/2/28 6:29, Rob Herring wrote:
> >>>>>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
> >>>>>>>
> >>>>>>>
> >>>>>>> On 2023/2/21 7:43, Rob Herring wrote:
> >>>>>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >>>>>>>>> Add documentation to describe StarFive System Controller Registers.
> >>>>>>>>>
> >>>>>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>>>>>>>> ---
> >>>>>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >>>>>>>>> MAINTAINERS | 5 ++
> >>>>>>>>> 2 files changed, 56 insertions(+)
> >>>>>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>>>>
> >>>>>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>>>> new file mode 100644
> >>>>>>>>> index 000000000000..fa4d8522a454
> >>>>>>>>> --- /dev/null
> >>>>>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>>>> @@ -0,0 +1,51 @@
> >>>>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>>>>>>>> +%YAML 1.2
> >>>>>>>>> +---
> >>>>>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >>>>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>>>>>> +
> >>>>>>>>> +title: StarFive JH7110 SoC system controller
> >>>>>>>>> +
> >>>>>>>>> +maintainers:
> >>>>>>>>> + - William Qiu <william.qiu@starfivetech.com>
> >>>>>>>>> +
> >>>>>>>>> +description: |
> >>>>>>>>> + The StarFive JH7110 SoC system controller provides register information such
> >>>>>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >>>>>>>>> +
> >>>>>>>>> +properties:
> >>>>>>>>> + compatible:
> >>>>>>>>> + items:
> >>>>>>>>> + - enum:
> >>>>>>>>> + - starfive,jh7110-stg-syscon
> >>>>>>>>> + - starfive,jh7110-sys-syscon
> >>>>>>>>> + - starfive,jh7110-aon-syscon
> >>>>>>>>
> >>>>>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> >>>>>>>> 'sys' and 'aon' not unique enough?
> >>>>>>>>
> >>>>>>>> Rob
> >>>>>>> Hi Rob,
> >>>>>>>
> >>>>>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> >>>>>>> controller, so 'syscon' is added to avoid confusion.
> >>>>>>
> >>>>>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> >>>>>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> >>>>>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> >>>>>> of 'sys-syscon' or possibly just all one node. Please provide details on
> >>>>>> the entire h/w block so we can provide better input on the bindings.
> >>>>>>
> >>>>>> Rob
> >>>>>
> >>>>> Hi Rob,
> >>>>>
> >>>>> It's my description that's problematic.'syscon' here refers to the hardware module
> >>>>> inside our JH7110, which is different from the syscon interface in linux. The syscon
> >>>>> I added now uses the syscon interface of linux to read and write the syscon register
> >>>>> in our JH7110. So we decided to name it that way.
> >>>>
> >>>> You didn't really answer Rob's questions.
> >>>>
> >>>> Also, syscon is Linux term, so are you sure hardware module is called
> >>>> like this? Hardware engineers took pure Linux name and used it?
> >>>
> >>> Yes, from the documentation I could find[1] there are CRG blocks
> >>> (Clock and Reset Generator) and SYSCON blocks:
> >>> SYS CRG
> >>> STG CRG
> >>> AON CRG
> >>> SYS SYSCON
> >>> STG SYSCON
> >>> AON SYSCON
> >>>
> >>> The CRG blocks contain registers to control clocks and resets that
> >>> follow a pattern used by the clock and reset drivers. The SYSCON
> >>> blocks just seem to contain registers to control whatever didn't fit
> >>> in any other blocks, but might be vaguely related to the peripherals
> >>> that run off clocks controlled by the corresponding CRG block.
> >>
> >> The memory map [1] suggests these are indeed separate address spaces,
> >> e.g. AON CRG, AON SYSCON and AON GPIO, but now I would argue that this
> >> might be still one device - AON (or STG, SYS). Just like PCIE0 has four
> >> address spaces, it does not mean you have four separate PCIE0 devices.
> >> You have only one PCIE0, just like you have only one AON, one STG and
> >> one SYS (System).
> >
> > I see what you mean, but if you look into what the registers in the
> > SYSCON blocks actually do it's not clear to me that they should be
> > grouped with the clocks/resets any more than say the pinctrl/GPIO
> > node. Maybe it's my fault for not giving you the full picture. Eg. for
> > "system" and "always-on" there are blocks:
> >
> > SYS CRG
> > SYS SYSCON
> > SYS IOMUX
> > AON CRG
> > AON SYSCON
> > AON IOMUX
> >
> > ..and it really don't see why eg. SYS CRG and SYS SYSCON should be
> > thought of as one device, but not include SYS IOMUX then.
>
> ... include sys iomux as well, just like GPIO is included for AON.
This would at least take the view that the blocks named alike should
be thought of as a single device to its logical conclusion.
Unfortunately we're a bit late for that. The pinctrl/GPiO bindings and
drivers are already merged:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d6e0a660097dcdb80e7c5c859eb12f776060b02e
> >
> > As an examly the SYS SYSCON includes registers to control:
> > - remapping of different peripherals from SD controller to video encoders
> > - voltage select for certain GPIO pins
> > - phy interface selection for ethernet and CAN
> > - QuadSPI delay chain and SRAM configuration
> > - PLL configuration
> > - endian selection for the SD controller
> >
> > To me this is pretty much exactly described by the syscon device tree binding:
> > "System controller node represents a register region containing a set
> > of miscellaneous registers. The registers are not cohesive enough to
> > represent as any specific type of device. [..]"
> > In any case it's clear that however the SYSCON blocks are represented
> > in the device tree, a driver for it would need to export registers in
> > the SYSCON block for other drivers to use.
>
> You started entire sentence with "but" so you disagree but with what
> exactly? The naming? But syscon is fine - hardware manual calls it like
> that.
>
> The point was that AON is one device (consisting of multiple blocks).
Yes, and what I'm trying to explain is that I'm not convinced that's
the right model. The CRG blocks and IOMUX blocks don't really have
anything in common other than the name StarFive gave them. You can
argue that the CRG and IOMUX blocks overlap with the corresponding
SYSCON block, but so do a lot of other peripherals as you can see from
the list above.
I think the IOMUX and SYSCON blocks are just named after the clock
domain they're under, but a lot of other peripherals are also under
the SYS and AON clock domains and we don't model them as one big
device.
/Emil
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-28 17:31 ` Emil Renner Berthing
0 siblings, 0 replies; 94+ messages in thread
From: Emil Renner Berthing @ 2023-02-28 17:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
On Tue, 28 Feb 2023 at 17:59, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 28/02/2023 15:59, Emil Renner Berthing wrote:
> > On Tue, 28 Feb 2023 at 12:28, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >> On 28/02/2023 12:02, Emil Renner Berthing wrote:
> >>> On Tue, 28 Feb 2023 at 11:40, Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 28/02/2023 10:05, William Qiu wrote:
> >>>>>
> >>>>>
> >>>>> On 2023/2/28 6:29, Rob Herring wrote:
> >>>>>> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
> >>>>>>>
> >>>>>>>
> >>>>>>> On 2023/2/21 7:43, Rob Herring wrote:
> >>>>>>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >>>>>>>>> Add documentation to describe StarFive System Controller Registers.
> >>>>>>>>>
> >>>>>>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>>>>>>>> ---
> >>>>>>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >>>>>>>>> MAINTAINERS | 5 ++
> >>>>>>>>> 2 files changed, 56 insertions(+)
> >>>>>>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>>>>
> >>>>>>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>>>> new file mode 100644
> >>>>>>>>> index 000000000000..fa4d8522a454
> >>>>>>>>> --- /dev/null
> >>>>>>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>>>>> @@ -0,0 +1,51 @@
> >>>>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>>>>>>>> +%YAML 1.2
> >>>>>>>>> +---
> >>>>>>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >>>>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>>>>>> +
> >>>>>>>>> +title: StarFive JH7110 SoC system controller
> >>>>>>>>> +
> >>>>>>>>> +maintainers:
> >>>>>>>>> + - William Qiu <william.qiu@starfivetech.com>
> >>>>>>>>> +
> >>>>>>>>> +description: |
> >>>>>>>>> + The StarFive JH7110 SoC system controller provides register information such
> >>>>>>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >>>>>>>>> +
> >>>>>>>>> +properties:
> >>>>>>>>> + compatible:
> >>>>>>>>> + items:
> >>>>>>>>> + - enum:
> >>>>>>>>> + - starfive,jh7110-stg-syscon
> >>>>>>>>> + - starfive,jh7110-sys-syscon
> >>>>>>>>> + - starfive,jh7110-aon-syscon
> >>>>>>>>
> >>>>>>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> >>>>>>>> 'sys' and 'aon' not unique enough?
> >>>>>>>>
> >>>>>>>> Rob
> >>>>>>> Hi Rob,
> >>>>>>>
> >>>>>>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> >>>>>>> controller, so 'syscon' is added to avoid confusion.
> >>>>>>
> >>>>>> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> >>>>>> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> >>>>>> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> >>>>>> of 'sys-syscon' or possibly just all one node. Please provide details on
> >>>>>> the entire h/w block so we can provide better input on the bindings.
> >>>>>>
> >>>>>> Rob
> >>>>>
> >>>>> Hi Rob,
> >>>>>
> >>>>> It's my description that's problematic.'syscon' here refers to the hardware module
> >>>>> inside our JH7110, which is different from the syscon interface in linux. The syscon
> >>>>> I added now uses the syscon interface of linux to read and write the syscon register
> >>>>> in our JH7110. So we decided to name it that way.
> >>>>
> >>>> You didn't really answer Rob's questions.
> >>>>
> >>>> Also, syscon is Linux term, so are you sure hardware module is called
> >>>> like this? Hardware engineers took pure Linux name and used it?
> >>>
> >>> Yes, from the documentation I could find[1] there are CRG blocks
> >>> (Clock and Reset Generator) and SYSCON blocks:
> >>> SYS CRG
> >>> STG CRG
> >>> AON CRG
> >>> SYS SYSCON
> >>> STG SYSCON
> >>> AON SYSCON
> >>>
> >>> The CRG blocks contain registers to control clocks and resets that
> >>> follow a pattern used by the clock and reset drivers. The SYSCON
> >>> blocks just seem to contain registers to control whatever didn't fit
> >>> in any other blocks, but might be vaguely related to the peripherals
> >>> that run off clocks controlled by the corresponding CRG block.
> >>
> >> The memory map [1] suggests these are indeed separate address spaces,
> >> e.g. AON CRG, AON SYSCON and AON GPIO, but now I would argue that this
> >> might be still one device - AON (or STG, SYS). Just like PCIE0 has four
> >> address spaces, it does not mean you have four separate PCIE0 devices.
> >> You have only one PCIE0, just like you have only one AON, one STG and
> >> one SYS (System).
> >
> > I see what you mean, but if you look into what the registers in the
> > SYSCON blocks actually do it's not clear to me that they should be
> > grouped with the clocks/resets any more than say the pinctrl/GPIO
> > node. Maybe it's my fault for not giving you the full picture. Eg. for
> > "system" and "always-on" there are blocks:
> >
> > SYS CRG
> > SYS SYSCON
> > SYS IOMUX
> > AON CRG
> > AON SYSCON
> > AON IOMUX
> >
> > ..and it really don't see why eg. SYS CRG and SYS SYSCON should be
> > thought of as one device, but not include SYS IOMUX then.
>
> ... include sys iomux as well, just like GPIO is included for AON.
This would at least take the view that the blocks named alike should
be thought of as a single device to its logical conclusion.
Unfortunately we're a bit late for that. The pinctrl/GPiO bindings and
drivers are already merged:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d6e0a660097dcdb80e7c5c859eb12f776060b02e
> >
> > As an examly the SYS SYSCON includes registers to control:
> > - remapping of different peripherals from SD controller to video encoders
> > - voltage select for certain GPIO pins
> > - phy interface selection for ethernet and CAN
> > - QuadSPI delay chain and SRAM configuration
> > - PLL configuration
> > - endian selection for the SD controller
> >
> > To me this is pretty much exactly described by the syscon device tree binding:
> > "System controller node represents a register region containing a set
> > of miscellaneous registers. The registers are not cohesive enough to
> > represent as any specific type of device. [..]"
> > In any case it's clear that however the SYSCON blocks are represented
> > in the device tree, a driver for it would need to export registers in
> > the SYSCON block for other drivers to use.
>
> You started entire sentence with "but" so you disagree but with what
> exactly? The naming? But syscon is fine - hardware manual calls it like
> that.
>
> The point was that AON is one device (consisting of multiple blocks).
Yes, and what I'm trying to explain is that I'm not convinced that's
the right model. The CRG blocks and IOMUX blocks don't really have
anything in common other than the name StarFive gave them. You can
argue that the CRG and IOMUX blocks overlap with the corresponding
SYSCON block, but so do a lot of other peripherals as you can see from
the list above.
I think the IOMUX and SYSCON blocks are just named after the clock
domain they're under, but a lot of other peripherals are also under
the SYS and AON clock domains and we don't model them as one big
device.
/Emil
>
> Best regards,
> Krzysztof
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-28 17:31 ` Emil Renner Berthing
@ 2023-02-28 18:06 ` Conor Dooley
-1 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-02-28 18:06 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: Krzysztof Kozlowski, William Qiu, Rob Herring, linux-riscv,
devicetree, linux-mmc, Krzysztof Kozlowski, Jaehoon Chung,
Ulf Hansson, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3623 bytes --]
On Tue, Feb 28, 2023 at 06:31:46PM +0100, Emil Renner Berthing wrote:
> On Tue, 28 Feb 2023 at 17:59, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> > On 28/02/2023 15:59, Emil Renner Berthing wrote:
> > > On Tue, 28 Feb 2023 at 12:28, Krzysztof Kozlowski
> > > <krzysztof.kozlowski@linaro.org> wrote:
> > > I see what you mean, but if you look into what the registers in the
> > > SYSCON blocks actually do it's not clear to me that they should be
> > > grouped with the clocks/resets any more than say the pinctrl/GPIO
> > > node. Maybe it's my fault for not giving you the full picture. Eg. for
> > > "system" and "always-on" there are blocks:
> > >
> > > SYS CRG
> > > SYS SYSCON
> > > SYS IOMUX
> > > AON CRG
> > > AON SYSCON
> > > AON IOMUX
> > >
> > > ..and it really don't see why eg. SYS CRG and SYS SYSCON should be
> > > thought of as one device, but not include SYS IOMUX then.
> >
> > ... include sys iomux as well, just like GPIO is included for AON.
>
> This would at least take the view that the blocks named alike should
> be thought of as a single device to its logical conclusion.
> Unfortunately we're a bit late for that. The pinctrl/GPiO bindings and
> drivers are already merged:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d6e0a660097dcdb80e7c5c859eb12f776060b02e
>
> > >
> > > As an examly the SYS SYSCON includes registers to control:
> > > - remapping of different peripherals from SD controller to video encoders
> > > - voltage select for certain GPIO pins
> > > - phy interface selection for ethernet and CAN
> > > - QuadSPI delay chain and SRAM configuration
> > > - PLL configuration
> > > - endian selection for the SD controller
> > >
> > > To me this is pretty much exactly described by the syscon device tree binding:
> > > "System controller node represents a register region containing a set
> > > of miscellaneous registers. The registers are not cohesive enough to
> > > represent as any specific type of device. [..]"
> > > In any case it's clear that however the SYSCON blocks are represented
> > > in the device tree, a driver for it would need to export registers in
> > > the SYSCON block for other drivers to use.
> >
> > You started entire sentence with "but" so you disagree but with what
> > exactly? The naming? But syscon is fine - hardware manual calls it like
> > that.
> >
> > The point was that AON is one device (consisting of multiple blocks).
>
> Yes, and what I'm trying to explain is that I'm not convinced that's
> the right model. The CRG blocks and IOMUX blocks don't really have
> anything in common other than the name StarFive gave them. You can
> argue that the CRG and IOMUX blocks overlap with the corresponding
> SYSCON block, but so do a lot of other peripherals as you can see from
> the list above.
>
> I think the IOMUX and SYSCON blocks are just named after the clock
> domain they're under, but a lot of other peripherals are also under
> the SYS and AON clock domains and we don't model them as one big
> device.
I went and bothered Rob/Krzysztof on IRC about this.
Not gonna speak for them, but I think they're now okay with keeping the
SYS_CRG (clock+reset block) separate from the SYS_SYSCON block ("random
collection of registers"). Possibly there was just confusion due to the
naming used here, thinking that "SYS", "STG" and "AON" were devices with
two register blocks, as opposed to being the name of a clock/power domain
on the SoC.
I'll leave it up to them to confirm that though!
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-28 18:06 ` Conor Dooley
0 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-02-28 18:06 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: Krzysztof Kozlowski, William Qiu, Rob Herring, linux-riscv,
devicetree, linux-mmc, Krzysztof Kozlowski, Jaehoon Chung,
Ulf Hansson, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 3623 bytes --]
On Tue, Feb 28, 2023 at 06:31:46PM +0100, Emil Renner Berthing wrote:
> On Tue, 28 Feb 2023 at 17:59, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> > On 28/02/2023 15:59, Emil Renner Berthing wrote:
> > > On Tue, 28 Feb 2023 at 12:28, Krzysztof Kozlowski
> > > <krzysztof.kozlowski@linaro.org> wrote:
> > > I see what you mean, but if you look into what the registers in the
> > > SYSCON blocks actually do it's not clear to me that they should be
> > > grouped with the clocks/resets any more than say the pinctrl/GPIO
> > > node. Maybe it's my fault for not giving you the full picture. Eg. for
> > > "system" and "always-on" there are blocks:
> > >
> > > SYS CRG
> > > SYS SYSCON
> > > SYS IOMUX
> > > AON CRG
> > > AON SYSCON
> > > AON IOMUX
> > >
> > > ..and it really don't see why eg. SYS CRG and SYS SYSCON should be
> > > thought of as one device, but not include SYS IOMUX then.
> >
> > ... include sys iomux as well, just like GPIO is included for AON.
>
> This would at least take the view that the blocks named alike should
> be thought of as a single device to its logical conclusion.
> Unfortunately we're a bit late for that. The pinctrl/GPiO bindings and
> drivers are already merged:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d6e0a660097dcdb80e7c5c859eb12f776060b02e
>
> > >
> > > As an examly the SYS SYSCON includes registers to control:
> > > - remapping of different peripherals from SD controller to video encoders
> > > - voltage select for certain GPIO pins
> > > - phy interface selection for ethernet and CAN
> > > - QuadSPI delay chain and SRAM configuration
> > > - PLL configuration
> > > - endian selection for the SD controller
> > >
> > > To me this is pretty much exactly described by the syscon device tree binding:
> > > "System controller node represents a register region containing a set
> > > of miscellaneous registers. The registers are not cohesive enough to
> > > represent as any specific type of device. [..]"
> > > In any case it's clear that however the SYSCON blocks are represented
> > > in the device tree, a driver for it would need to export registers in
> > > the SYSCON block for other drivers to use.
> >
> > You started entire sentence with "but" so you disagree but with what
> > exactly? The naming? But syscon is fine - hardware manual calls it like
> > that.
> >
> > The point was that AON is one device (consisting of multiple blocks).
>
> Yes, and what I'm trying to explain is that I'm not convinced that's
> the right model. The CRG blocks and IOMUX blocks don't really have
> anything in common other than the name StarFive gave them. You can
> argue that the CRG and IOMUX blocks overlap with the corresponding
> SYSCON block, but so do a lot of other peripherals as you can see from
> the list above.
>
> I think the IOMUX and SYSCON blocks are just named after the clock
> domain they're under, but a lot of other peripherals are also under
> the SYS and AON clock domains and we don't model them as one big
> device.
I went and bothered Rob/Krzysztof on IRC about this.
Not gonna speak for them, but I think they're now okay with keeping the
SYS_CRG (clock+reset block) separate from the SYS_SYSCON block ("random
collection of registers"). Possibly there was just confusion due to the
naming used here, thinking that "SYS", "STG" and "AON" were devices with
two register blocks, as opposed to being the name of a clock/power domain
on the SoC.
I'll leave it up to them to confirm that though!
Cheers,
Conor.
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
2023-02-28 10:37 ` Krzysztof Kozlowski
@ 2023-02-28 11:08 ` Conor Dooley
-1 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-02-28 11:08 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3888 bytes --]
On Tue, Feb 28, 2023 at 11:37:20AM +0100, Krzysztof Kozlowski wrote:
> On 28/02/2023 10:05, William Qiu wrote:
> > On 2023/2/28 6:29, Rob Herring wrote:
> >> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
> >>> On 2023/2/21 7:43, Rob Herring wrote:
> >>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >>>>> Add documentation to describe StarFive System Controller Registers.
> >>>>>
> >>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>>>> ---
> >>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >>>>> MAINTAINERS | 5 ++
> >>>>> 2 files changed, 56 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>> new file mode 100644
> >>>>> index 000000000000..fa4d8522a454
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>> @@ -0,0 +1,51 @@
> >>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>>>> +%YAML 1.2
> >>>>> +---
> >>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>> +
> >>>>> +title: StarFive JH7110 SoC system controller
> >>>>> +
> >>>>> +maintainers:
> >>>>> + - William Qiu <william.qiu@starfivetech.com>
> >>>>> +
> >>>>> +description: |
> >>>>> + The StarFive JH7110 SoC system controller provides register information such
> >>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >>>>> +
> >>>>> +properties:
> >>>>> + compatible:
> >>>>> + items:
> >>>>> + - enum:
> >>>>> + - starfive,jh7110-stg-syscon
> >>>>> + - starfive,jh7110-sys-syscon
> >>>>> + - starfive,jh7110-aon-syscon
> >>>>
> >>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> >>>> 'sys' and 'aon' not unique enough?
> >>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> >>> controller, so 'syscon' is added to avoid confusion.
> >>
> >> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> >> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> >> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> >> of 'sys-syscon' or possibly just all one node. Please provide details on
> >> the entire h/w block so we can provide better input on the bindings.
> > It's my description that's problematic.'syscon' here refers to the hardware module
> > inside our JH7110, which is different from the syscon interface in linux. The syscon
> > I added now uses the syscon interface of linux to read and write the syscon register
> > in our JH7110. So we decided to name it that way.
>
> You didn't really answer Rob's questions.
>
> Also, syscon is Linux term, so are you sure hardware module is called
> like this? Hardware engineers took pure Linux name and used it?
Their TRM uses the term SYSCON for these, yes.
Eg:
"The JH7110 system provides the following STG SYSCON control registers
which provides [sic] clock and reset signals to interfaces..."
In fact, the TRM I have describes the following system control register
blocks:
SYS CRG
STG CRG
AON CRG
SYS SYSCON
STG SYSCON
AON SYSCON
SYS IOMUX CFG
AON IOMUX CFG
My understanding is that the first 3 (the CRG ones) are concerned with
clocks and resets & the second 3 contain "random" configuration options,
such as their QSPI IP's configuration options, GPIO voltage settings
etc.
Each of these has a separate, 0x1000 aligned, block in the memory map.
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
@ 2023-02-28 11:08 ` Conor Dooley
0 siblings, 0 replies; 94+ messages in thread
From: Conor Dooley @ 2023-02-28 11:08 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: William Qiu, Rob Herring, linux-riscv, devicetree, linux-mmc,
Krzysztof Kozlowski, Jaehoon Chung, Ulf Hansson, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 3888 bytes --]
On Tue, Feb 28, 2023 at 11:37:20AM +0100, Krzysztof Kozlowski wrote:
> On 28/02/2023 10:05, William Qiu wrote:
> > On 2023/2/28 6:29, Rob Herring wrote:
> >> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote:
> >>> On 2023/2/21 7:43, Rob Herring wrote:
> >>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
> >>>>> Add documentation to describe StarFive System Controller Registers.
> >>>>>
> >>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >>>>> ---
> >>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
> >>>>> MAINTAINERS | 5 ++
> >>>>> 2 files changed, 56 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>> new file mode 100644
> >>>>> index 000000000000..fa4d8522a454
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >>>>> @@ -0,0 +1,51 @@
> >>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >>>>> +%YAML 1.2
> >>>>> +---
> >>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
> >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>> +
> >>>>> +title: StarFive JH7110 SoC system controller
> >>>>> +
> >>>>> +maintainers:
> >>>>> + - William Qiu <william.qiu@starfivetech.com>
> >>>>> +
> >>>>> +description: |
> >>>>> + The StarFive JH7110 SoC system controller provides register information such
> >>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >>>>> +
> >>>>> +properties:
> >>>>> + compatible:
> >>>>> + items:
> >>>>> + - enum:
> >>>>> + - starfive,jh7110-stg-syscon
> >>>>> + - starfive,jh7110-sys-syscon
> >>>>> + - starfive,jh7110-aon-syscon
> >>>>
> >>>> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> >>>> 'sys' and 'aon' not unique enough?
> >>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
> >>> controller, so 'syscon' is added to avoid confusion.
> >>
> >> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2
> >> different h/w blocks and unrelated to each other? Or 'syscrg' is the
> >> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child
> >> of 'sys-syscon' or possibly just all one node. Please provide details on
> >> the entire h/w block so we can provide better input on the bindings.
> > It's my description that's problematic.'syscon' here refers to the hardware module
> > inside our JH7110, which is different from the syscon interface in linux. The syscon
> > I added now uses the syscon interface of linux to read and write the syscon register
> > in our JH7110. So we decided to name it that way.
>
> You didn't really answer Rob's questions.
>
> Also, syscon is Linux term, so are you sure hardware module is called
> like this? Hardware engineers took pure Linux name and used it?
Their TRM uses the term SYSCON for these, yes.
Eg:
"The JH7110 system provides the following STG SYSCON control registers
which provides [sic] clock and reset signals to interfaces..."
In fact, the TRM I have describes the following system control register
blocks:
SYS CRG
STG CRG
AON CRG
SYS SYSCON
STG SYSCON
AON SYSCON
SYS IOMUX CFG
AON IOMUX CFG
My understanding is that the first 3 (the CRG ones) are concerned with
clocks and resets & the second 3 contain "random" configuration options,
such as their QSPI IP's configuration options, GPIO voltage settings
etc.
Each of these has a separate, 0x1000 aligned, block in the memory map.
Cheers,
Conor.
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 0/4] StarFive's SDIO/eMMC driver support
2023-02-15 11:32 ` William Qiu
@ 2023-02-15 12:37 ` Ulf Hansson
-1 siblings, 0 replies; 94+ messages in thread
From: Ulf Hansson @ 2023-02-15 12:37 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, linux-kernel
On Wed, 15 Feb 2023 at 12:32, William Qiu <william.qiu@starfivetech.com> wrote:
>
> Hi,
>
> This patchset adds initial rudimentary support for the StarFive
> designware mobile storage host controller driver. And this driver will
> be used in StarFive's VisionFive 2 board. The main purpose of adding
> this driver is to accommodate the ultra-high speed mode of eMMC.
>
> The last patch should be applied after the patchset [1]:
> [1] https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
>
> Changes v3->v4:
> - Added documentation to describe StarFive System Controller Registers.
> - Added aon_syscon and stg_syscon node.
> - Fixed some checkpatch errors/warnings.
>
> Changes v2->v3:
> - Wraped commit message according to Linux coding style.
> - Rephrased the description of the patches.
> - Changed the description of syscon regsiter.
> - Dropped redundant properties.
>
> Changes v1->v2:
> - Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
> - Changed the type of 'starfive,syscon' and modify its description.
> - Deleted unused head files like '#include <linux/gpio.h>'.
> - Added comment for the 'rise_point' and 'fall_point'.
> - Changed the API 'num_caps' to 'common_caps'.
> - Changed the node name 'sys_syscon' to 'syscon'.
> - Changed the node name 'sdio' to 'mmc'.
>
> The patch series is based on v6.1.
>
> William Qiu (4):
> dt-bindings: mmc: Add StarFive MMC module
> mmc: starfive: Add sdio/emmc driver support
> riscv: dts: starfive: Add mmc node
> dt-bindings: syscon: Add StarFive syscon doc
>
> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 ++++++++
> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++
> MAINTAINERS | 11 ++
> .../jh7110-starfive-visionfive-2.dtsi | 23 +++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++
> drivers/mmc/host/Kconfig | 10 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/dw_mmc-starfive.c | 186 ++++++++++++++++++
> 8 files changed, 406 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>
I have dropped the v3 patches and applied patch1 and patch2 from the
v4 series instead, for my next branch, thanks!
Kind regards
Uffe
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 0/4] StarFive's SDIO/eMMC driver support
@ 2023-02-15 12:37 ` Ulf Hansson
0 siblings, 0 replies; 94+ messages in thread
From: Ulf Hansson @ 2023-02-15 12:37 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, linux-kernel
On Wed, 15 Feb 2023 at 12:32, William Qiu <william.qiu@starfivetech.com> wrote:
>
> Hi,
>
> This patchset adds initial rudimentary support for the StarFive
> designware mobile storage host controller driver. And this driver will
> be used in StarFive's VisionFive 2 board. The main purpose of adding
> this driver is to accommodate the ultra-high speed mode of eMMC.
>
> The last patch should be applied after the patchset [1]:
> [1] https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
>
> Changes v3->v4:
> - Added documentation to describe StarFive System Controller Registers.
> - Added aon_syscon and stg_syscon node.
> - Fixed some checkpatch errors/warnings.
>
> Changes v2->v3:
> - Wraped commit message according to Linux coding style.
> - Rephrased the description of the patches.
> - Changed the description of syscon regsiter.
> - Dropped redundant properties.
>
> Changes v1->v2:
> - Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
> - Changed the type of 'starfive,syscon' and modify its description.
> - Deleted unused head files like '#include <linux/gpio.h>'.
> - Added comment for the 'rise_point' and 'fall_point'.
> - Changed the API 'num_caps' to 'common_caps'.
> - Changed the node name 'sys_syscon' to 'syscon'.
> - Changed the node name 'sdio' to 'mmc'.
>
> The patch series is based on v6.1.
>
> William Qiu (4):
> dt-bindings: mmc: Add StarFive MMC module
> mmc: starfive: Add sdio/emmc driver support
> riscv: dts: starfive: Add mmc node
> dt-bindings: syscon: Add StarFive syscon doc
>
> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 ++++++++
> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++
> MAINTAINERS | 11 ++
> .../jh7110-starfive-visionfive-2.dtsi | 23 +++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++
> drivers/mmc/host/Kconfig | 10 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/dw_mmc-starfive.c | 186 ++++++++++++++++++
> 8 files changed, 406 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>
I have dropped the v3 patches and applied patch1 and patch2 from the
v4 series instead, for my next branch, thanks!
Kind regards
Uffe
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread
* Re: [PATCH v4 0/4] StarFive's SDIO/eMMC driver support
2023-02-15 12:37 ` Ulf Hansson
@ 2023-02-27 7:47 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-27 7:47 UTC (permalink / raw)
To: Ulf Hansson
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, linux-kernel
On 2023/2/15 20:37, Ulf Hansson wrote:
> On Wed, 15 Feb 2023 at 12:32, William Qiu <william.qiu@starfivetech.com> wrote:
>>
>> Hi,
>>
>> This patchset adds initial rudimentary support for the StarFive
>> designware mobile storage host controller driver. And this driver will
>> be used in StarFive's VisionFive 2 board. The main purpose of adding
>> this driver is to accommodate the ultra-high speed mode of eMMC.
>>
>> The last patch should be applied after the patchset [1]:
>> [1] https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
>>
>> Changes v3->v4:
>> - Added documentation to describe StarFive System Controller Registers.
>> - Added aon_syscon and stg_syscon node.
>> - Fixed some checkpatch errors/warnings.
>>
>> Changes v2->v3:
>> - Wraped commit message according to Linux coding style.
>> - Rephrased the description of the patches.
>> - Changed the description of syscon regsiter.
>> - Dropped redundant properties.
>>
>> Changes v1->v2:
>> - Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
>> - Changed the type of 'starfive,syscon' and modify its description.
>> - Deleted unused head files like '#include <linux/gpio.h>'.
>> - Added comment for the 'rise_point' and 'fall_point'.
>> - Changed the API 'num_caps' to 'common_caps'.
>> - Changed the node name 'sys_syscon' to 'syscon'.
>> - Changed the node name 'sdio' to 'mmc'.
>>
>> The patch series is based on v6.1.
>>
>> William Qiu (4):
>> dt-bindings: mmc: Add StarFive MMC module
>> mmc: starfive: Add sdio/emmc driver support
>> riscv: dts: starfive: Add mmc node
>> dt-bindings: syscon: Add StarFive syscon doc
>>
>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 ++++++++
>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++
>> MAINTAINERS | 11 ++
>> .../jh7110-starfive-visionfive-2.dtsi | 23 +++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++
>> drivers/mmc/host/Kconfig | 10 +
>> drivers/mmc/host/Makefile | 1 +
>> drivers/mmc/host/dw_mmc-starfive.c | 186 ++++++++++++++++++
>> 8 files changed, 406 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>>
>
> I have dropped the v3 patches and applied patch1 and patch2 from the
> v4 series instead, for my next branch, thanks!
>
> Kind regards
> Uffe
Hi Uffe,
Sorry to bother you.But I found a bug that in drivers/mmc/host/dw_mmc-starfive.c:
47 static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
48 u32 opcode)
49 {
50 static const int grade = MAX_DELAY_CHAIN;
51 struct dw_mci *host = slot->host;
52 struct starfive_priv *priv = host->priv;
53 int rise_point = -1, fall_point = -1;
54 int err, prev_err;
55 int i;
56 bool found = 0;
57 u32 regval;
58
59 /*
60 * Use grade as the max delay chain, and use the rise_point and
61 * fall_point to ensure the best sampling point of a data input
62 * signals.
63 */
64 for (i = 0; i < grade; i++) {
65 regval = i << priv->syscon_shift;
66 err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
67 priv->syscon_mask, regval);
68 if (err)
69 return err;
70 mci_writel(host, RINTSTS, ALL_INT_CLR);
71
72 err = mmc_send_tuning(slot->mmc, opcode, NULL);
73 if (!err)
74 found = 1;
75
76 if (i > 0) {
--> 77 if (err && !prev_err)
prev_err was never initialized to zero.
So I'm here to ask for your suggestion, should I send a new version
to fix it or send you a patch with a fixes tag?
Best regards
William
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 0/4] StarFive's SDIO/eMMC driver support
@ 2023-02-27 7:47 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-27 7:47 UTC (permalink / raw)
To: Ulf Hansson
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, linux-kernel
On 2023/2/15 20:37, Ulf Hansson wrote:
> On Wed, 15 Feb 2023 at 12:32, William Qiu <william.qiu@starfivetech.com> wrote:
>>
>> Hi,
>>
>> This patchset adds initial rudimentary support for the StarFive
>> designware mobile storage host controller driver. And this driver will
>> be used in StarFive's VisionFive 2 board. The main purpose of adding
>> this driver is to accommodate the ultra-high speed mode of eMMC.
>>
>> The last patch should be applied after the patchset [1]:
>> [1] https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
>>
>> Changes v3->v4:
>> - Added documentation to describe StarFive System Controller Registers.
>> - Added aon_syscon and stg_syscon node.
>> - Fixed some checkpatch errors/warnings.
>>
>> Changes v2->v3:
>> - Wraped commit message according to Linux coding style.
>> - Rephrased the description of the patches.
>> - Changed the description of syscon regsiter.
>> - Dropped redundant properties.
>>
>> Changes v1->v2:
>> - Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
>> - Changed the type of 'starfive,syscon' and modify its description.
>> - Deleted unused head files like '#include <linux/gpio.h>'.
>> - Added comment for the 'rise_point' and 'fall_point'.
>> - Changed the API 'num_caps' to 'common_caps'.
>> - Changed the node name 'sys_syscon' to 'syscon'.
>> - Changed the node name 'sdio' to 'mmc'.
>>
>> The patch series is based on v6.1.
>>
>> William Qiu (4):
>> dt-bindings: mmc: Add StarFive MMC module
>> mmc: starfive: Add sdio/emmc driver support
>> riscv: dts: starfive: Add mmc node
>> dt-bindings: syscon: Add StarFive syscon doc
>>
>> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 ++++++++
>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++
>> MAINTAINERS | 11 ++
>> .../jh7110-starfive-visionfive-2.dtsi | 23 +++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++
>> drivers/mmc/host/Kconfig | 10 +
>> drivers/mmc/host/Makefile | 1 +
>> drivers/mmc/host/dw_mmc-starfive.c | 186 ++++++++++++++++++
>> 8 files changed, 406 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>>
>
> I have dropped the v3 patches and applied patch1 and patch2 from the
> v4 series instead, for my next branch, thanks!
>
> Kind regards
> Uffe
Hi Uffe,
Sorry to bother you.But I found a bug that in drivers/mmc/host/dw_mmc-starfive.c:
47 static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
48 u32 opcode)
49 {
50 static const int grade = MAX_DELAY_CHAIN;
51 struct dw_mci *host = slot->host;
52 struct starfive_priv *priv = host->priv;
53 int rise_point = -1, fall_point = -1;
54 int err, prev_err;
55 int i;
56 bool found = 0;
57 u32 regval;
58
59 /*
60 * Use grade as the max delay chain, and use the rise_point and
61 * fall_point to ensure the best sampling point of a data input
62 * signals.
63 */
64 for (i = 0; i < grade; i++) {
65 regval = i << priv->syscon_shift;
66 err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
67 priv->syscon_mask, regval);
68 if (err)
69 return err;
70 mci_writel(host, RINTSTS, ALL_INT_CLR);
71
72 err = mmc_send_tuning(slot->mmc, opcode, NULL);
73 if (!err)
74 found = 1;
75
76 if (i > 0) {
--> 77 if (err && !prev_err)
prev_err was never initialized to zero.
So I'm here to ask for your suggestion, should I send a new version
to fix it or send you a patch with a fixes tag?
Best regards
William
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 0/4] StarFive's SDIO/eMMC driver support
2023-02-27 7:47 ` William Qiu
@ 2023-02-27 14:53 ` Ulf Hansson
-1 siblings, 0 replies; 94+ messages in thread
From: Ulf Hansson @ 2023-02-27 14:53 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, linux-kernel
On Mon, 27 Feb 2023 at 08:47, William Qiu <william.qiu@starfivetech.com> wrote:
>
>
>
> On 2023/2/15 20:37, Ulf Hansson wrote:
> > On Wed, 15 Feb 2023 at 12:32, William Qiu <william.qiu@starfivetech.com> wrote:
> >>
> >> Hi,
> >>
> >> This patchset adds initial rudimentary support for the StarFive
> >> designware mobile storage host controller driver. And this driver will
> >> be used in StarFive's VisionFive 2 board. The main purpose of adding
> >> this driver is to accommodate the ultra-high speed mode of eMMC.
> >>
> >> The last patch should be applied after the patchset [1]:
> >> [1] https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
> >>
> >> Changes v3->v4:
> >> - Added documentation to describe StarFive System Controller Registers.
> >> - Added aon_syscon and stg_syscon node.
> >> - Fixed some checkpatch errors/warnings.
> >>
> >> Changes v2->v3:
> >> - Wraped commit message according to Linux coding style.
> >> - Rephrased the description of the patches.
> >> - Changed the description of syscon regsiter.
> >> - Dropped redundant properties.
> >>
> >> Changes v1->v2:
> >> - Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
> >> - Changed the type of 'starfive,syscon' and modify its description.
> >> - Deleted unused head files like '#include <linux/gpio.h>'.
> >> - Added comment for the 'rise_point' and 'fall_point'.
> >> - Changed the API 'num_caps' to 'common_caps'.
> >> - Changed the node name 'sys_syscon' to 'syscon'.
> >> - Changed the node name 'sdio' to 'mmc'.
> >>
> >> The patch series is based on v6.1.
> >>
> >> William Qiu (4):
> >> dt-bindings: mmc: Add StarFive MMC module
> >> mmc: starfive: Add sdio/emmc driver support
> >> riscv: dts: starfive: Add mmc node
> >> dt-bindings: syscon: Add StarFive syscon doc
> >>
> >> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 ++++++++
> >> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++
> >> MAINTAINERS | 11 ++
> >> .../jh7110-starfive-visionfive-2.dtsi | 23 +++
> >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++
> >> drivers/mmc/host/Kconfig | 10 +
> >> drivers/mmc/host/Makefile | 1 +
> >> drivers/mmc/host/dw_mmc-starfive.c | 186 ++++++++++++++++++
> >> 8 files changed, 406 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
> >>
> >
> > I have dropped the v3 patches and applied patch1 and patch2 from the
> > v4 series instead, for my next branch, thanks!
> >
> > Kind regards
> > Uffe
>
> Hi Uffe,
>
> Sorry to bother you.But I found a bug that in drivers/mmc/host/dw_mmc-starfive.c:
>
> 47 static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
> 48 u32 opcode)
> 49 {
> 50 static const int grade = MAX_DELAY_CHAIN;
> 51 struct dw_mci *host = slot->host;
> 52 struct starfive_priv *priv = host->priv;
> 53 int rise_point = -1, fall_point = -1;
> 54 int err, prev_err;
> 55 int i;
> 56 bool found = 0;
> 57 u32 regval;
> 58
> 59 /*
> 60 * Use grade as the max delay chain, and use the rise_point and
> 61 * fall_point to ensure the best sampling point of a data input
> 62 * signals.
> 63 */
> 64 for (i = 0; i < grade; i++) {
> 65 regval = i << priv->syscon_shift;
> 66 err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
> 67 priv->syscon_mask, regval);
> 68 if (err)
> 69 return err;
> 70 mci_writel(host, RINTSTS, ALL_INT_CLR);
> 71
> 72 err = mmc_send_tuning(slot->mmc, opcode, NULL);
> 73 if (!err)
> 74 found = 1;
> 75
> 76 if (i > 0) {
> --> 77 if (err && !prev_err)
>
> prev_err was never initialized to zero.
>
> So I'm here to ask for your suggestion, should I send a new version
> to fix it or send you a patch with a fixes tag?
Please send a new incremental patch on top. I will queue it up as a
fix for v6.3-rc[n].
Kind regards
Uffe
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 0/4] StarFive's SDIO/eMMC driver support
@ 2023-02-27 14:53 ` Ulf Hansson
0 siblings, 0 replies; 94+ messages in thread
From: Ulf Hansson @ 2023-02-27 14:53 UTC (permalink / raw)
To: William Qiu
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, linux-kernel
On Mon, 27 Feb 2023 at 08:47, William Qiu <william.qiu@starfivetech.com> wrote:
>
>
>
> On 2023/2/15 20:37, Ulf Hansson wrote:
> > On Wed, 15 Feb 2023 at 12:32, William Qiu <william.qiu@starfivetech.com> wrote:
> >>
> >> Hi,
> >>
> >> This patchset adds initial rudimentary support for the StarFive
> >> designware mobile storage host controller driver. And this driver will
> >> be used in StarFive's VisionFive 2 board. The main purpose of adding
> >> this driver is to accommodate the ultra-high speed mode of eMMC.
> >>
> >> The last patch should be applied after the patchset [1]:
> >> [1] https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
> >>
> >> Changes v3->v4:
> >> - Added documentation to describe StarFive System Controller Registers.
> >> - Added aon_syscon and stg_syscon node.
> >> - Fixed some checkpatch errors/warnings.
> >>
> >> Changes v2->v3:
> >> - Wraped commit message according to Linux coding style.
> >> - Rephrased the description of the patches.
> >> - Changed the description of syscon regsiter.
> >> - Dropped redundant properties.
> >>
> >> Changes v1->v2:
> >> - Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
> >> - Changed the type of 'starfive,syscon' and modify its description.
> >> - Deleted unused head files like '#include <linux/gpio.h>'.
> >> - Added comment for the 'rise_point' and 'fall_point'.
> >> - Changed the API 'num_caps' to 'common_caps'.
> >> - Changed the node name 'sys_syscon' to 'syscon'.
> >> - Changed the node name 'sdio' to 'mmc'.
> >>
> >> The patch series is based on v6.1.
> >>
> >> William Qiu (4):
> >> dt-bindings: mmc: Add StarFive MMC module
> >> mmc: starfive: Add sdio/emmc driver support
> >> riscv: dts: starfive: Add mmc node
> >> dt-bindings: syscon: Add StarFive syscon doc
> >>
> >> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 ++++++++
> >> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++
> >> MAINTAINERS | 11 ++
> >> .../jh7110-starfive-visionfive-2.dtsi | 23 +++
> >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++
> >> drivers/mmc/host/Kconfig | 10 +
> >> drivers/mmc/host/Makefile | 1 +
> >> drivers/mmc/host/dw_mmc-starfive.c | 186 ++++++++++++++++++
> >> 8 files changed, 406 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
> >> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
> >>
> >
> > I have dropped the v3 patches and applied patch1 and patch2 from the
> > v4 series instead, for my next branch, thanks!
> >
> > Kind regards
> > Uffe
>
> Hi Uffe,
>
> Sorry to bother you.But I found a bug that in drivers/mmc/host/dw_mmc-starfive.c:
>
> 47 static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
> 48 u32 opcode)
> 49 {
> 50 static const int grade = MAX_DELAY_CHAIN;
> 51 struct dw_mci *host = slot->host;
> 52 struct starfive_priv *priv = host->priv;
> 53 int rise_point = -1, fall_point = -1;
> 54 int err, prev_err;
> 55 int i;
> 56 bool found = 0;
> 57 u32 regval;
> 58
> 59 /*
> 60 * Use grade as the max delay chain, and use the rise_point and
> 61 * fall_point to ensure the best sampling point of a data input
> 62 * signals.
> 63 */
> 64 for (i = 0; i < grade; i++) {
> 65 regval = i << priv->syscon_shift;
> 66 err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
> 67 priv->syscon_mask, regval);
> 68 if (err)
> 69 return err;
> 70 mci_writel(host, RINTSTS, ALL_INT_CLR);
> 71
> 72 err = mmc_send_tuning(slot->mmc, opcode, NULL);
> 73 if (!err)
> 74 found = 1;
> 75
> 76 if (i > 0) {
> --> 77 if (err && !prev_err)
>
> prev_err was never initialized to zero.
>
> So I'm here to ask for your suggestion, should I send a new version
> to fix it or send you a patch with a fixes tag?
Please send a new incremental patch on top. I will queue it up as a
fix for v6.3-rc[n].
Kind regards
Uffe
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 0/4] StarFive's SDIO/eMMC driver support
2023-02-27 14:53 ` Ulf Hansson
@ 2023-02-28 5:56 ` William Qiu
-1 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-28 5:56 UTC (permalink / raw)
To: Ulf Hansson
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, linux-kernel
On 2023/2/27 22:53, Ulf Hansson wrote:
> On Mon, 27 Feb 2023 at 08:47, William Qiu <william.qiu@starfivetech.com> wrote:
>>
>>
>>
>> On 2023/2/15 20:37, Ulf Hansson wrote:
>> > On Wed, 15 Feb 2023 at 12:32, William Qiu <william.qiu@starfivetech.com> wrote:
>> >>
>> >> Hi,
>> >>
>> >> This patchset adds initial rudimentary support for the StarFive
>> >> designware mobile storage host controller driver. And this driver will
>> >> be used in StarFive's VisionFive 2 board. The main purpose of adding
>> >> this driver is to accommodate the ultra-high speed mode of eMMC.
>> >>
>> >> The last patch should be applied after the patchset [1]:
>> >> [1] https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
>> >>
>> >> Changes v3->v4:
>> >> - Added documentation to describe StarFive System Controller Registers.
>> >> - Added aon_syscon and stg_syscon node.
>> >> - Fixed some checkpatch errors/warnings.
>> >>
>> >> Changes v2->v3:
>> >> - Wraped commit message according to Linux coding style.
>> >> - Rephrased the description of the patches.
>> >> - Changed the description of syscon regsiter.
>> >> - Dropped redundant properties.
>> >>
>> >> Changes v1->v2:
>> >> - Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
>> >> - Changed the type of 'starfive,syscon' and modify its description.
>> >> - Deleted unused head files like '#include <linux/gpio.h>'.
>> >> - Added comment for the 'rise_point' and 'fall_point'.
>> >> - Changed the API 'num_caps' to 'common_caps'.
>> >> - Changed the node name 'sys_syscon' to 'syscon'.
>> >> - Changed the node name 'sdio' to 'mmc'.
>> >>
>> >> The patch series is based on v6.1.
>> >>
>> >> William Qiu (4):
>> >> dt-bindings: mmc: Add StarFive MMC module
>> >> mmc: starfive: Add sdio/emmc driver support
>> >> riscv: dts: starfive: Add mmc node
>> >> dt-bindings: syscon: Add StarFive syscon doc
>> >>
>> >> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 ++++++++
>> >> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++
>> >> MAINTAINERS | 11 ++
>> >> .../jh7110-starfive-visionfive-2.dtsi | 23 +++
>> >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++
>> >> drivers/mmc/host/Kconfig | 10 +
>> >> drivers/mmc/host/Makefile | 1 +
>> >> drivers/mmc/host/dw_mmc-starfive.c | 186 ++++++++++++++++++
>> >> 8 files changed, 406 insertions(+)
>> >> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> >> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>> >>
>> >
>> > I have dropped the v3 patches and applied patch1 and patch2 from the
>> > v4 series instead, for my next branch, thanks!
>> >
>> > Kind regards
>> > Uffe
>>
>> Hi Uffe,
>>
>> Sorry to bother you.But I found a bug that in drivers/mmc/host/dw_mmc-starfive.c:
>>
>> 47 static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
>> 48 u32 opcode)
>> 49 {
>> 50 static const int grade = MAX_DELAY_CHAIN;
>> 51 struct dw_mci *host = slot->host;
>> 52 struct starfive_priv *priv = host->priv;
>> 53 int rise_point = -1, fall_point = -1;
>> 54 int err, prev_err;
>> 55 int i;
>> 56 bool found = 0;
>> 57 u32 regval;
>> 58
>> 59 /*
>> 60 * Use grade as the max delay chain, and use the rise_point and
>> 61 * fall_point to ensure the best sampling point of a data input
>> 62 * signals.
>> 63 */
>> 64 for (i = 0; i < grade; i++) {
>> 65 regval = i << priv->syscon_shift;
>> 66 err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>> 67 priv->syscon_mask, regval);
>> 68 if (err)
>> 69 return err;
>> 70 mci_writel(host, RINTSTS, ALL_INT_CLR);
>> 71
>> 72 err = mmc_send_tuning(slot->mmc, opcode, NULL);
>> 73 if (!err)
>> 74 found = 1;
>> 75
>> 76 if (i > 0) {
>> --> 77 if (err && !prev_err)
>>
>> prev_err was never initialized to zero.
>>
>> So I'm here to ask for your suggestion, should I send a new version
>> to fix it or send you a patch with a fixes tag?
>
> Please send a new incremental patch on top. I will queue it up as a
> fix for v6.3-rc[n].
>
> Kind regards
> Uffe
Fine, I'll do it in my next version. Thanks for your apply.
Best regards
William
^ permalink raw reply [flat|nested] 94+ messages in thread* Re: [PATCH v4 0/4] StarFive's SDIO/eMMC driver support
@ 2023-02-28 5:56 ` William Qiu
0 siblings, 0 replies; 94+ messages in thread
From: William Qiu @ 2023-02-28 5:56 UTC (permalink / raw)
To: Ulf Hansson
Cc: linux-riscv, devicetree, linux-mmc, Rob Herring,
Krzysztof Kozlowski, Jaehoon Chung, linux-kernel
On 2023/2/27 22:53, Ulf Hansson wrote:
> On Mon, 27 Feb 2023 at 08:47, William Qiu <william.qiu@starfivetech.com> wrote:
>>
>>
>>
>> On 2023/2/15 20:37, Ulf Hansson wrote:
>> > On Wed, 15 Feb 2023 at 12:32, William Qiu <william.qiu@starfivetech.com> wrote:
>> >>
>> >> Hi,
>> >>
>> >> This patchset adds initial rudimentary support for the StarFive
>> >> designware mobile storage host controller driver. And this driver will
>> >> be used in StarFive's VisionFive 2 board. The main purpose of adding
>> >> this driver is to accommodate the ultra-high speed mode of eMMC.
>> >>
>> >> The last patch should be applied after the patchset [1]:
>> >> [1] https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
>> >>
>> >> Changes v3->v4:
>> >> - Added documentation to describe StarFive System Controller Registers.
>> >> - Added aon_syscon and stg_syscon node.
>> >> - Fixed some checkpatch errors/warnings.
>> >>
>> >> Changes v2->v3:
>> >> - Wraped commit message according to Linux coding style.
>> >> - Rephrased the description of the patches.
>> >> - Changed the description of syscon regsiter.
>> >> - Dropped redundant properties.
>> >>
>> >> Changes v1->v2:
>> >> - Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
>> >> - Changed the type of 'starfive,syscon' and modify its description.
>> >> - Deleted unused head files like '#include <linux/gpio.h>'.
>> >> - Added comment for the 'rise_point' and 'fall_point'.
>> >> - Changed the API 'num_caps' to 'common_caps'.
>> >> - Changed the node name 'sys_syscon' to 'syscon'.
>> >> - Changed the node name 'sdio' to 'mmc'.
>> >>
>> >> The patch series is based on v6.1.
>> >>
>> >> William Qiu (4):
>> >> dt-bindings: mmc: Add StarFive MMC module
>> >> mmc: starfive: Add sdio/emmc driver support
>> >> riscv: dts: starfive: Add mmc node
>> >> dt-bindings: syscon: Add StarFive syscon doc
>> >>
>> >> .../bindings/mmc/starfive,jh7110-mmc.yaml | 77 ++++++++
>> >> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++
>> >> MAINTAINERS | 11 ++
>> >> .../jh7110-starfive-visionfive-2.dtsi | 23 +++
>> >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++
>> >> drivers/mmc/host/Kconfig | 10 +
>> >> drivers/mmc/host/Makefile | 1 +
>> >> drivers/mmc/host/dw_mmc-starfive.c | 186 ++++++++++++++++++
>> >> 8 files changed, 406 insertions(+)
>> >> create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml
>> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> >> create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
>> >>
>> >
>> > I have dropped the v3 patches and applied patch1 and patch2 from the
>> > v4 series instead, for my next branch, thanks!
>> >
>> > Kind regards
>> > Uffe
>>
>> Hi Uffe,
>>
>> Sorry to bother you.But I found a bug that in drivers/mmc/host/dw_mmc-starfive.c:
>>
>> 47 static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
>> 48 u32 opcode)
>> 49 {
>> 50 static const int grade = MAX_DELAY_CHAIN;
>> 51 struct dw_mci *host = slot->host;
>> 52 struct starfive_priv *priv = host->priv;
>> 53 int rise_point = -1, fall_point = -1;
>> 54 int err, prev_err;
>> 55 int i;
>> 56 bool found = 0;
>> 57 u32 regval;
>> 58
>> 59 /*
>> 60 * Use grade as the max delay chain, and use the rise_point and
>> 61 * fall_point to ensure the best sampling point of a data input
>> 62 * signals.
>> 63 */
>> 64 for (i = 0; i < grade; i++) {
>> 65 regval = i << priv->syscon_shift;
>> 66 err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
>> 67 priv->syscon_mask, regval);
>> 68 if (err)
>> 69 return err;
>> 70 mci_writel(host, RINTSTS, ALL_INT_CLR);
>> 71
>> 72 err = mmc_send_tuning(slot->mmc, opcode, NULL);
>> 73 if (!err)
>> 74 found = 1;
>> 75
>> 76 if (i > 0) {
>> --> 77 if (err && !prev_err)
>>
>> prev_err was never initialized to zero.
>>
>> So I'm here to ask for your suggestion, should I send a new version
>> to fix it or send you a patch with a fixes tag?
>
> Please send a new incremental patch on top. I will queue it up as a
> fix for v6.3-rc[n].
>
> Kind regards
> Uffe
Fine, I'll do it in my next version. Thanks for your apply.
Best regards
William
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 94+ messages in thread