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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com>
Cc: "Ben Widawsky" <bwidawsk@kernel.org>,
	linux-cxl@vger.kernel.org, linuxarm@huawei.com,
	"Ira Weiny" <ira.weiny@intel.com>,
	"Gregory Price" <gourry.memverge@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Mike Maslenkin" <mike.maslenkin@gmail.com>,
	"Dave Jiang" <dave.jiang@intel.com>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Thomas Huth" <thuth@redhat.com>
Subject: [PATCH v6 2/8] hw/pci/aer: Add missing routing for AER errors
Date: Mon, 27 Feb 2023 11:27:45 +0000	[thread overview]
Message-ID: <20230227112751.6101-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20230227112751.6101-1-Jonathan.Cameron@huawei.com>

PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
Device Control Register is set.

Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
 hw/pci/pcie_aer.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index 909e027d99..103667c368 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -192,8 +192,16 @@ static void pcie_aer_update_uncor_status(PCIDevice *dev)
 static bool
 pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
 {
+    uint16_t devctl = pci_get_word(dev->config + dev->exp.exp_cap +
+                                   PCI_EXP_DEVCTL);
     if (!(pcie_aer_msg_is_uncor(msg) &&
-          (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) {
+          (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR)) &&
+        !((msg->severity == PCI_ERR_ROOT_CMD_NONFATAL_EN) &&
+          (devctl & PCI_EXP_DEVCTL_NFERE)) &&
+        !((msg->severity == PCI_ERR_ROOT_CMD_COR_EN) &&
+          (devctl & PCI_EXP_DEVCTL_CERE)) &&
+        !((msg->severity == PCI_ERR_ROOT_CMD_FATAL_EN) &&
+          (devctl & PCI_EXP_DEVCTL_FERE))) {
         return false;
     }
 
-- 
2.37.2


WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com>
Cc: "Ben Widawsky" <bwidawsk@kernel.org>,
	linux-cxl@vger.kernel.org, linuxarm@huawei.com,
	"Ira Weiny" <ira.weiny@intel.com>,
	"Gregory Price" <gourry.memverge@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Mike Maslenkin" <mike.maslenkin@gmail.com>,
	"Dave Jiang" <dave.jiang@intel.com>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Thomas Huth" <thuth@redhat.com>
Subject: [PATCH v6 2/8] hw/pci/aer: Add missing routing for AER errors
Date: Mon, 27 Feb 2023 11:27:45 +0000	[thread overview]
Message-ID: <20230227112751.6101-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20230227112751.6101-1-Jonathan.Cameron@huawei.com>

PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
Device Control Register is set.

Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
 hw/pci/pcie_aer.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index 909e027d99..103667c368 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -192,8 +192,16 @@ static void pcie_aer_update_uncor_status(PCIDevice *dev)
 static bool
 pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
 {
+    uint16_t devctl = pci_get_word(dev->config + dev->exp.exp_cap +
+                                   PCI_EXP_DEVCTL);
     if (!(pcie_aer_msg_is_uncor(msg) &&
-          (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) {
+          (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR)) &&
+        !((msg->severity == PCI_ERR_ROOT_CMD_NONFATAL_EN) &&
+          (devctl & PCI_EXP_DEVCTL_NFERE)) &&
+        !((msg->severity == PCI_ERR_ROOT_CMD_COR_EN) &&
+          (devctl & PCI_EXP_DEVCTL_CERE)) &&
+        !((msg->severity == PCI_ERR_ROOT_CMD_FATAL_EN) &&
+          (devctl & PCI_EXP_DEVCTL_FERE))) {
         return false;
     }
 
-- 
2.37.2



  parent reply	other threads:[~2023-02-27 11:29 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-27 11:27 [PATCH v6 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
2023-02-27 11:27 ` Jonathan Cameron via
2023-02-27 11:27 ` [PATCH v6 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron
2023-02-27 11:27   ` Jonathan Cameron via
2023-02-27 11:27 ` Jonathan Cameron [this message]
2023-02-27 11:27   ` [PATCH v6 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron via
2023-02-27 11:27 ` [PATCH v6 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron
2023-02-27 11:27   ` Jonathan Cameron via
2023-02-27 11:27 ` [PATCH v6 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron
2023-02-27 11:27   ` Jonathan Cameron via
2023-02-27 11:27 ` [PATCH v6 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron
2023-02-27 11:27   ` Jonathan Cameron via
2023-02-27 11:27 ` [PATCH v6 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron
2023-02-27 11:27   ` Jonathan Cameron via
2023-02-27 11:27 ` [PATCH v6 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron
2023-02-27 11:27   ` Jonathan Cameron via
2023-02-27 11:27 ` [PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron
2023-02-27 11:27   ` Jonathan Cameron via
2023-03-02 10:06   ` Jonathan Cameron via
2023-03-02 10:06     ` Jonathan Cameron
2023-03-02 10:49     ` Philippe Mathieu-Daudé
2023-03-02 10:55       ` Michael S. Tsirkin
2023-03-02 17:22         ` Jonathan Cameron
2023-03-02 17:22           ` Jonathan Cameron via

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