From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com> Cc: "Ben Widawsky" <bwidawsk@kernel.org>, linux-cxl@vger.kernel.org, linuxarm@huawei.com, "Ira Weiny" <ira.weiny@intel.com>, "Gregory Price" <gourry.memverge@gmail.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, "Mike Maslenkin" <mike.maslenkin@gmail.com>, "Dave Jiang" <dave.jiang@intel.com>, "Markus Armbruster" <armbru@redhat.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, "Thomas Huth" <thuth@redhat.com> Subject: [PATCH v6 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Date: Mon, 27 Feb 2023 11:27:49 +0000 [thread overview] Message-ID: <20230227112751.6101-7-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20230227112751.6101-1-Jonathan.Cameron@huawei.com> As these are about to be modified, fix the endian handle for this set of registers rather than making it worse. Note that CXL is currently only supported in QEMU on x86 (arm64 patches out of tree) so we aren't going to yet hit an problems with big endian. However it is good to avoid making things worse for that support in the future. Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/cxl/cxl-component-utils.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 3edd303a33..737b4764b9 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -141,17 +141,17 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) * Error status is RW1C but given bits are not yet set, it can * be handled as RO. */ - reg_state[R_CXL_RAS_UNC_ERR_STATUS] = 0; + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ - reg_state[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; - write_msk[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; - reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; - write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; - reg_state[R_CXL_RAS_COR_ERR_STATUS] = 0; - reg_state[R_CXL_RAS_COR_ERR_MASK] = 0x7f; - write_msk[R_CXL_RAS_COR_ERR_MASK] = 0x7f; + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); + stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); /* CXL switches and devices must set */ - reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; + stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00); } static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org> To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com> Cc: "Ben Widawsky" <bwidawsk@kernel.org>, linux-cxl@vger.kernel.org, linuxarm@huawei.com, "Ira Weiny" <ira.weiny@intel.com>, "Gregory Price" <gourry.memverge@gmail.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, "Mike Maslenkin" <mike.maslenkin@gmail.com>, "Dave Jiang" <dave.jiang@intel.com>, "Markus Armbruster" <armbru@redhat.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, "Thomas Huth" <thuth@redhat.com> Subject: [PATCH v6 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Date: Mon, 27 Feb 2023 11:27:49 +0000 [thread overview] Message-ID: <20230227112751.6101-7-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20230227112751.6101-1-Jonathan.Cameron@huawei.com> As these are about to be modified, fix the endian handle for this set of registers rather than making it worse. Note that CXL is currently only supported in QEMU on x86 (arm64 patches out of tree) so we aren't going to yet hit an problems with big endian. However it is good to avoid making things worse for that support in the future. Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/cxl/cxl-component-utils.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 3edd303a33..737b4764b9 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -141,17 +141,17 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) * Error status is RW1C but given bits are not yet set, it can * be handled as RO. */ - reg_state[R_CXL_RAS_UNC_ERR_STATUS] = 0; + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ - reg_state[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; - write_msk[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff; - reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; - write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff; - reg_state[R_CXL_RAS_COR_ERR_STATUS] = 0; - reg_state[R_CXL_RAS_COR_ERR_MASK] = 0x7f; - write_msk[R_CXL_RAS_COR_ERR_MASK] = 0x7f; + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); + stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); /* CXL switches and devices must set */ - reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; + stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00); } static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, -- 2.37.2
next prev parent reply other threads:[~2023-02-27 11:30 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-27 11:27 [PATCH v6 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron 2023-02-27 11:27 ` Jonathan Cameron via 2023-02-27 11:27 ` [PATCH v6 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron 2023-02-27 11:27 ` Jonathan Cameron via 2023-02-27 11:27 ` [PATCH v6 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron 2023-02-27 11:27 ` Jonathan Cameron via 2023-02-27 11:27 ` [PATCH v6 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron 2023-02-27 11:27 ` Jonathan Cameron via 2023-02-27 11:27 ` [PATCH v6 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron 2023-02-27 11:27 ` Jonathan Cameron via 2023-02-27 11:27 ` [PATCH v6 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron 2023-02-27 11:27 ` Jonathan Cameron via 2023-02-27 11:27 ` Jonathan Cameron [this message] 2023-02-27 11:27 ` [PATCH v6 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron via 2023-02-27 11:27 ` [PATCH v6 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron 2023-02-27 11:27 ` Jonathan Cameron via 2023-02-27 11:27 ` [PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron 2023-02-27 11:27 ` Jonathan Cameron via 2023-03-02 10:06 ` Jonathan Cameron via 2023-03-02 10:06 ` Jonathan Cameron 2023-03-02 10:49 ` Philippe Mathieu-Daudé 2023-03-02 10:55 ` Michael S. Tsirkin 2023-03-02 17:22 ` Jonathan Cameron 2023-03-02 17:22 ` Jonathan Cameron via
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