From: Bartosz Golaszewski <brgl@bgdev.pl> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Subject: [PATCH 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Date: Tue, 28 Mar 2023 21:36:32 +0200 [thread overview] Message-ID: <20230328193632.226095-8-brgl@bgdev.pl> (raw) In-Reply-To: <20230328193632.226095-1-brgl@bgdev.pl> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add the GPU IOMMU for sa8775p-based platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 4c45ad1cc7ff..de5e8449397c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -603,6 +604,34 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + kgsl_smmu: iommu@3da0000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Bartosz Golaszewski <brgl@bgdev.pl> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Subject: [PATCH 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Date: Tue, 28 Mar 2023 21:36:32 +0200 [thread overview] Message-ID: <20230328193632.226095-8-brgl@bgdev.pl> (raw) In-Reply-To: <20230328193632.226095-1-brgl@bgdev.pl> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add the GPU IOMMU for sa8775p-based platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 4c45ad1cc7ff..de5e8449397c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -603,6 +604,34 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + kgsl_smmu: iommu@3da0000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-03-28 19:36 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-28 19:36 [PATCH 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-28 19:36 ` [PATCH 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 8:30 ` Krzysztof Kozlowski 2023-03-29 8:30 ` Krzysztof Kozlowski 2023-03-28 19:36 ` [PATCH 2/7] clk: qcom: add the GPUCC driver for sa8775p Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 2:15 ` Stephen Boyd 2023-03-29 2:15 ` Stephen Boyd 2023-04-06 11:20 ` Bartosz Golaszewski 2023-04-06 11:20 ` Bartosz Golaszewski 2023-04-10 19:09 ` Stephen Boyd 2023-04-10 19:09 ` Stephen Boyd 2023-03-29 11:30 ` Konrad Dybcio 2023-03-29 11:30 ` Konrad Dybcio 2023-03-28 19:36 ` [PATCH 3/7] arm64: defconfig: enable the SA8775P GPUCC driver Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 8:33 ` Krzysztof Kozlowski 2023-03-29 8:33 ` Krzysztof Kozlowski 2023-04-06 13:28 ` Dmitry Baryshkov 2023-04-06 13:28 ` Dmitry Baryshkov 2023-03-28 19:36 ` [PATCH 4/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 8:31 ` Krzysztof Kozlowski 2023-03-29 8:31 ` Krzysztof Kozlowski 2023-04-03 20:41 ` Rob Herring 2023-04-03 20:41 ` Rob Herring 2023-04-03 22:38 ` Konrad Dybcio 2023-04-03 22:38 ` Konrad Dybcio 2023-03-28 19:36 ` [PATCH 5/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 11:33 ` Konrad Dybcio 2023-03-29 11:33 ` Konrad Dybcio 2023-03-28 19:36 ` [PATCH 6/7] arm64: dts: qcom: sa8775p: add the GPU clock controller node Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 11:31 ` Konrad Dybcio 2023-03-29 11:31 ` Konrad Dybcio 2023-03-28 19:36 ` Bartosz Golaszewski [this message] 2023-03-28 19:36 ` [PATCH 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Bartosz Golaszewski
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