[Patch 4/6] cpufreq: CPPC: update sampling window for Tegra241

From: Sumit Gupta <sumitg@nvidia.com>
To: <viresh.kumar@linaro.org>, <rafael@kernel.org>,
	<ionela.voinescu@arm.com>, <mark.rutland@arm.com>,
	<sudeep.holla@arm.com>, <lpieralisi@kernel.org>,
	<catalin.marinas@arm.com>, <will@kernel.org>
Cc: <linux-pm@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<treding@nvidia.com>, <jonathanh@nvidia.com>, <vsethi@nvidia.com>,
	<sdonthineni@nvidia.com>, <sanjayc@nvidia.com>,
	<ksitaraman@nvidia.com>, <bbasu@nvidia.com>, <sumitg@nvidia.com>
Subject: [Patch 4/6] cpufreq: CPPC: update sampling window for Tegra241
Date: Tue, 18 Apr 2023 17:04:57 +0530	[thread overview]
Message-ID: <20230418113459.12860-5-sumitg@nvidia.com> (raw)
In-Reply-To: <20230418113459.12860-1-sumitg@nvidia.com>

In Tegra241, the Activity Monitor Unit's (AMU) constant counter
(i.e. reference clock counter) increment happens in bursts and
not incremented in the steps of one. For example reference counter
may increment by '0x20' every '32' periods of ARM periphclk. This
quantization of the reference counter is a source of error when
reconstructing the frequency from the AMU counter data. To fix,
increase the observation time interval so the error percentage
becomes less.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
 drivers/cpufreq/cppc_cpufreq.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c
index 15c2cbb7a50e..5e6a132a525e 100644
--- a/drivers/cpufreq/cppc_cpufreq.c
+++ b/drivers/cpufreq/cppc_cpufreq.c
@@ -43,12 +43,17 @@ static LIST_HEAD(cpu_data_list);
 
 static bool boost_supported;
 
+/* default 2usec delay between sampling */
+static unsigned int sampling_delay_us = 2;
+
 static void cppc_check_hisi_workaround(void);
+static void cppc_nvidia_workaround(void);
 
 struct cppc_workaround_oem_info {
 	char oem_id[ACPI_OEM_ID_SIZE + 1];
 	char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
 	u32 oem_revision;
+	u32 smcc_soc_id;
 	void (*apply_wa_func)(void);
 };
 
@@ -63,6 +68,10 @@ static struct cppc_workaround_oem_info wa_info[] = {
 		.oem_table_id	= "HIP08   ",
 		.oem_revision	= 0,
 		.apply_wa_func	= cppc_check_hisi_workaround,
+	}, {
+		.oem_id         = "NVIDIA",
+		.smcc_soc_id	= 0x036b0241, /* JEP106 code for NVIDIA T241 chip (036b:0241) */
+		.apply_wa_func	= cppc_nvidia_workaround,
 	}
 };
 
@@ -856,7 +865,7 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int cpu)
 	if (ret)
 		return ret;
 
-	udelay(2); /* 2usec delay between sampling */
+	udelay(sampling_delay_us);
 
 	ret = cppc_get_perf_ctrs(cpu, &fb_ctrs_t1);
 	if (ret)
@@ -942,6 +951,11 @@ static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu)
 	return cppc_cpufreq_perf_to_khz(cpu_data, desired_perf);
 }
 
+static void cppc_nvidia_workaround(void)
+{
+	sampling_delay_us = 25;
+}
+
 static void cppc_check_hisi_workaround(void)
 {
 	/* Overwrite the get() callback */
@@ -953,8 +967,21 @@ static void cppc_apply_workarounds(void)
 {
 	struct acpi_table_header *tbl;
 	acpi_status status = AE_OK;
+	s32 soc_id;
 	int i;
 
+#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
+	for (i = 0; i < ARRAY_SIZE(wa_info); i++) {
+		if (wa_info[i].smcc_soc_id) {
+			soc_id = arm_smccc_get_soc_id_version();
+			if (wa_info[i].smcc_soc_id == soc_id) {
+				wa_info[i].apply_wa_func();
+				return;
+			}
+		}
+	}
+#endif
+
 	status = acpi_get_table(ACPI_SIG_PCCT, 0, &tbl);
 	if (ACPI_FAILURE(status) || !tbl)
 		return;
-- 
2.17.1

