From: Jim Quinlan <jim2101024@gmail.com> To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne <nsaenz@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Cyril Brulebois <kibi@debian.org>, Phil Elwell <phil@raspberrypi.com>, bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: "Florian Fainelli" <f.fainelli@gmail.com>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 1/5] dt-bindings: PCI: brcmstb: brcm,{enable-l1ss,completion-timeout-us} props Date: Fri, 28 Apr 2023 18:34:55 -0400 [thread overview] Message-ID: <20230428223500.23337-2-jim2101024@gmail.com> (raw) In-Reply-To: <20230428223500.23337-1-jim2101024@gmail.com> This commit introduces two new properties: brcm,enable-l1ss (bool): The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- requires the driver probe() to deliberately place the HW one of three CLKREQ# modes: (a) CLKREQ# driven by the RC unconditionally (b) CLKREQ# driven by the EP for ASPM L0s, L1 (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS). The HW+driver can tell the difference between downstream devices that need (a) and (b), but does not know when to configure (c). All devices should work fine when the driver chooses (a) or (b), but (c) may be desired to realize the extra power savings that L1SS offers. So we introduce the boolean "brcm,enable-l1ss" property to inform the driver that (c) is desired. Setting this property only makes sense when the downstream device is L1SS-capable and the OS is configured to activate this mode (e.g. policy==superpowersave). This property is already present in the Raspian version of Linux, but the upstream driver implementaion that follows adds more details and discerns between (a) and (b). brcm,completion-timeout-us (u32): Our HW will cause a CPU abort on any PCI transaction completion abort error. It makes sense then to increase the timeout value for this type of error in hopes that the response is merely delayed. Further, L1SS-capable devices may have a long L1SS exit time and may require a custom timeout value: we've been asked by our customers to make this configurable for just this reason. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e..239cc95545bd 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,22 @@ properties: aspm-no-l0s: true + brcm,enable-l1ss: + description: Indicates that PCIe L1SS power savings + are desired, the downstream device is L1SS-capable, and the + OS has been configured to enable this mode. For boards + using a mini-card connector, this mode may not meet the + TCRLon maximum time of 400ns, as specified in 3.2.5.2.5 + of the PCI Express Mini CEM 2.0 specification. + type: boolean + + brcm,completion-timeout-us: + description: Number of microseconds before PCI transaction + completion timeout abort is signalled. + minimum: 16 + default: 1000000 + maximum: 19884107 + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Jim Quinlan <jim2101024@gmail.com> To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne <nsaenz@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Cyril Brulebois <kibi@debian.org>, Phil Elwell <phil@raspberrypi.com>, bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: "Florian Fainelli" <f.fainelli@gmail.com>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 1/5] dt-bindings: PCI: brcmstb: brcm,{enable-l1ss,completion-timeout-us} props Date: Fri, 28 Apr 2023 18:34:55 -0400 [thread overview] Message-ID: <20230428223500.23337-2-jim2101024@gmail.com> (raw) In-Reply-To: <20230428223500.23337-1-jim2101024@gmail.com> This commit introduces two new properties: brcm,enable-l1ss (bool): The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- requires the driver probe() to deliberately place the HW one of three CLKREQ# modes: (a) CLKREQ# driven by the RC unconditionally (b) CLKREQ# driven by the EP for ASPM L0s, L1 (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS). The HW+driver can tell the difference between downstream devices that need (a) and (b), but does not know when to configure (c). All devices should work fine when the driver chooses (a) or (b), but (c) may be desired to realize the extra power savings that L1SS offers. So we introduce the boolean "brcm,enable-l1ss" property to inform the driver that (c) is desired. Setting this property only makes sense when the downstream device is L1SS-capable and the OS is configured to activate this mode (e.g. policy==superpowersave). This property is already present in the Raspian version of Linux, but the upstream driver implementaion that follows adds more details and discerns between (a) and (b). brcm,completion-timeout-us (u32): Our HW will cause a CPU abort on any PCI transaction completion abort error. It makes sense then to increase the timeout value for this type of error in hopes that the response is merely delayed. Further, L1SS-capable devices may have a long L1SS exit time and may require a custom timeout value: we've been asked by our customers to make this configurable for just this reason. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e..239cc95545bd 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,22 @@ properties: aspm-no-l0s: true + brcm,enable-l1ss: + description: Indicates that PCIe L1SS power savings + are desired, the downstream device is L1SS-capable, and the + OS has been configured to enable this mode. For boards + using a mini-card connector, this mode may not meet the + TCRLon maximum time of 400ns, as specified in 3.2.5.2.5 + of the PCI Express Mini CEM 2.0 specification. + type: boolean + + brcm,completion-timeout-us: + description: Number of microseconds before PCI transaction + completion timeout abort is signalled. + minimum: 16 + default: 1000000 + maximum: 19884107 + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-04-28 22:35 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-28 22:34 [PATCH v4 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode Jim Quinlan 2023-04-28 22:34 ` Jim Quinlan 2023-04-28 22:34 ` Jim Quinlan [this message] 2023-04-28 22:34 ` [PATCH v4 1/5] dt-bindings: PCI: brcmstb: brcm,{enable-l1ss,completion-timeout-us} props Jim Quinlan 2023-04-30 19:10 ` Bjorn Helgaas 2023-04-30 19:10 ` Bjorn Helgaas 2023-05-03 14:38 ` Jim Quinlan 2023-05-03 14:38 ` Jim Quinlan 2023-05-03 18:07 ` Bjorn Helgaas 2023-05-03 18:07 ` Bjorn Helgaas 2023-05-03 21:38 ` Jim Quinlan 2023-05-03 21:38 ` Jim Quinlan 2023-05-03 22:18 ` Bjorn Helgaas 2023-05-03 22:18 ` Bjorn Helgaas 2023-05-05 12:39 ` Jim Quinlan 2023-05-05 12:39 ` Jim Quinlan 2023-05-05 13:34 ` Bjorn Helgaas 2023-05-05 13:34 ` Bjorn Helgaas 2023-05-05 14:40 ` Jim Quinlan 2023-05-05 14:40 ` Jim Quinlan 2023-05-05 14:54 ` Bjorn Helgaas 2023-05-05 14:54 ` Bjorn Helgaas 2023-04-28 22:34 ` [PATCH v4 2/5] PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device Jim Quinlan 2023-04-28 22:34 ` Jim Quinlan 2023-05-03 6:09 ` Stefan Wahren 2023-05-03 6:09 ` Stefan Wahren 2023-04-28 22:34 ` [PATCH v4 3/5] PCI: brcmstb: Set PCIe transaction completion timeout Jim Quinlan 2023-04-28 22:34 ` Jim Quinlan 2023-04-30 19:13 ` Bjorn Helgaas 2023-04-30 19:13 ` Bjorn Helgaas 2023-04-30 21:24 ` Jim Quinlan 2023-04-30 21:24 ` Jim Quinlan 2023-04-30 22:38 ` Bjorn Helgaas 2023-04-30 22:38 ` Bjorn Helgaas 2023-05-01 20:55 ` Lukas Wunner 2023-05-03 14:06 ` Jim Quinlan 2023-05-03 14:06 ` Jim Quinlan 2023-05-03 6:06 ` Stefan Wahren 2023-05-03 6:06 ` Stefan Wahren 2023-04-28 22:34 ` [PATCH v4 4/5] PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted Jim Quinlan 2023-04-28 22:34 ` Jim Quinlan 2023-04-28 22:34 ` [PATCH v4 5/5] PCI: brcmstb: Remove stale comment Jim Quinlan 2023-04-28 22:34 ` Jim Quinlan 2023-05-02 23:15 ` [PATCH v4 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode Cyril Brulebois 2023-05-02 23:15 ` Cyril Brulebois 2023-05-03 18:10 ` Jim Quinlan 2023-05-03 18:10 ` Jim Quinlan 2023-05-03 19:10 ` Cyril Brulebois 2023-05-03 19:10 ` Cyril Brulebois
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230428223500.23337-2-jim2101024@gmail.com \ --to=jim2101024@gmail.com \ --cc=bcm-kernel-feedback-list@broadcom.com \ --cc=bhelgaas@google.com \ --cc=devicetree@vger.kernel.org \ --cc=f.fainelli@gmail.com \ --cc=james.quinlan@broadcom.com \ --cc=kibi@debian.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=kw@linux.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=linux-rpi-kernel@lists.infradead.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=lpieralisi@kernel.org \ --cc=nsaenz@kernel.org \ --cc=phil@raspberrypi.com \ --cc=robh@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.