* [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support
@ 2023-06-01 14:40 Frank Li
2023-06-01 14:40 ` [PATCH v3 01/12] dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c Frank Li
` (11 more replies)
0 siblings, 12 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:40 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
This patch series introduces support for the eDMA version 3 from
Freescale. The eDMA v3 brings alterations in the register layout,
particularly, the separation of channel control registers into
different channels. The Transfer Control Descriptor (TCD) layout,
however, remains identical with only the offset being changed.
The first ten patches aim at tidying up the existing Freescale
eDMA code and laying the groundwork for the integration of eDMA v3
support.
Patch 1-10:
These patches primarily focus on cleaning up and refactoring the existing
fsl_edma driver code. This is to accommodate the upcoming changes and new
features introduced with the eDMA v3.
Patch 11:
This patch introduces support for eDMA v3. In addition, this patch has
been designed with an eye towards future upgradability, specifically for
transitioning to eDMA v5. The latter involves a significant upgrade
where the TCD address would need to support 64 bits.
Patch 12:
This patch focuses on the device tree bindings and their modifications
to properly handle and integrate the changes brought about by eDMA v3
Change from v2 to v3
- dt-binding: add interrupt-names
- dt-binding: add minItems
- dt-binding: add missed property: fsl,channel-mask
- rework patch 4, removed edma_version to avoid confuse with hardware
IP version.
Change from v1 to v2
- fixed issue found by make DT_CHECKER_FLAGS=-m dt_binding_check
- fixed warning found by kernel test robot
Frank Li (12):
1 dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c
2 dmaengine: fsl-edma: clean up fsl_edma_irq_exit()
3 dmaengine: fsl-edma: transition from bool fields to bitmask flags in
drvdata
4 dmaengine: fsl-edma: remove v3 from enum edma_version
5 dmaengine: fsl-edma: move common IRQ handler to common.c
6 dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs()
7 dmaengine: fsl-edma: refactor using devm_clk_get_enabled
8 dmaengine: fsl-edma: move clearing of register interrupt into
setup_irq function
9 dmaengine: fsl-edma: refactor chan_name setup and safety
10 dmaengine: fsl-edma: move tcd into struct fsl_dma_chan
11 dmaengine: fsl-edma: integrate v3 support
12 dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string
.../devicetree/bindings/dma/fsl,edma.yaml | 19 ++
drivers/dma/Makefile | 6 +-
drivers/dma/fsl-edma-common.c | 267 +++++++++++----
drivers/dma/fsl-edma-common.h | 119 ++++++-
drivers/dma/{fsl-edma.c => fsl-edma-main.c} | 323 ++++++++++++++----
drivers/dma/{mcf-edma.c => mcf-edma-main.c} | 34 +-
6 files changed, 578 insertions(+), 190 deletions(-)
rename drivers/dma/{fsl-edma.c => fsl-edma-main.c} (62%)
rename drivers/dma/{mcf-edma.c => mcf-edma-main.c} (91%)
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 01/12] dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
@ 2023-06-01 14:40 ` Frank Li
2023-06-01 14:40 ` [PATCH v3 02/12] dmaengine: fsl-edma: clean up fsl_edma_irq_exit() Frank Li
` (10 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:40 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
Exported functions in fsl-edma-common.c are only used within
fsl-edma.c and mcf-edma.c. Global export is unnecessary.
This commit removes all EXPORT_SYMBOL_GPL in fsl-edma-common.c,
and renames fsl-edma.c and mcf-edma.c to maintain the same
final module names as before, thereby simplifying the codebase.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
drivers/dma/Makefile | 6 ++++--
drivers/dma/fsl-edma-common.c | 18 ------------------
drivers/dma/{fsl-edma.c => fsl-edma-main.c} | 0
drivers/dma/{mcf-edma.c => mcf-edma-main.c} | 0
4 files changed, 4 insertions(+), 20 deletions(-)
rename drivers/dma/{fsl-edma.c => fsl-edma-main.c} (100%)
rename drivers/dma/{mcf-edma.c => mcf-edma-main.c} (100%)
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index a4fd1ce29510..7f3d62c9dee2 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,8 +32,10 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_DW_EDMA) += dw-edma/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
-obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
-obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
+fsl-edma-objs := fsl-edma-main.o fsl-edma-common.o
+obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+mcf-edma-objs := mcf-edma-main.o fsl-edma-common.o
+obj-$(CONFIG_MCF_EDMA) += mcf-edma.o
obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HISI_DMA) += hisi_dma.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index a06a1575a2a5..ce8d7c9eaf77 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -75,7 +75,6 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei);
}
}
-EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
u32 off, u32 slot, bool enable)
@@ -126,7 +125,6 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
else
mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
}
-EXPORT_SYMBOL_GPL(fsl_edma_chan_mux);
static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
{
@@ -155,7 +153,6 @@ void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
fsl_desc->tcd[i].ptcd);
kfree(fsl_desc);
}
-EXPORT_SYMBOL_GPL(fsl_edma_free_desc);
int fsl_edma_terminate_all(struct dma_chan *chan)
{
@@ -172,7 +169,6 @@ int fsl_edma_terminate_all(struct dma_chan *chan)
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
return 0;
}
-EXPORT_SYMBOL_GPL(fsl_edma_terminate_all);
int fsl_edma_pause(struct dma_chan *chan)
{
@@ -188,7 +184,6 @@ int fsl_edma_pause(struct dma_chan *chan)
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
return 0;
}
-EXPORT_SYMBOL_GPL(fsl_edma_pause);
int fsl_edma_resume(struct dma_chan *chan)
{
@@ -204,7 +199,6 @@ int fsl_edma_resume(struct dma_chan *chan)
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
return 0;
}
-EXPORT_SYMBOL_GPL(fsl_edma_resume);
static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan)
{
@@ -265,7 +259,6 @@ int fsl_edma_slave_config(struct dma_chan *chan,
return 0;
}
-EXPORT_SYMBOL_GPL(fsl_edma_slave_config);
static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
struct virt_dma_desc *vdesc, bool in_progress)
@@ -340,7 +333,6 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
return fsl_chan->status;
}
-EXPORT_SYMBOL_GPL(fsl_edma_tx_status);
static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
struct fsl_edma_hw_tcd *tcd)
@@ -520,7 +512,6 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
}
-EXPORT_SYMBOL_GPL(fsl_edma_prep_dma_cyclic);
struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
struct dma_chan *chan, struct scatterlist *sgl,
@@ -589,7 +580,6 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
}
-EXPORT_SYMBOL_GPL(fsl_edma_prep_slave_sg);
struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan,
dma_addr_t dma_dst, dma_addr_t dma_src,
@@ -612,7 +602,6 @@ struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan,
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
}
-EXPORT_SYMBOL_GPL(fsl_edma_prep_memcpy);
void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
{
@@ -629,7 +618,6 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
fsl_chan->status = DMA_IN_PROGRESS;
fsl_chan->idle = false;
}
-EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc);
void fsl_edma_issue_pending(struct dma_chan *chan)
{
@@ -649,7 +637,6 @@ void fsl_edma_issue_pending(struct dma_chan *chan)
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
}
-EXPORT_SYMBOL_GPL(fsl_edma_issue_pending);
int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
{
@@ -660,7 +647,6 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
32, 0);
return 0;
}
-EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources);
void fsl_edma_free_chan_resources(struct dma_chan *chan)
{
@@ -683,7 +669,6 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan)
fsl_chan->tcd_pool = NULL;
fsl_chan->is_sw = false;
}
-EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources);
void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
{
@@ -695,7 +680,6 @@ void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
tasklet_kill(&chan->vchan.task);
}
}
-EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan);
/*
* On the 32 channels Vybrid/mpc577x edma version (here called "v1"),
@@ -743,6 +727,4 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
edma->regs.tcd = edma->membase + EDMA_TCD;
}
-EXPORT_SYMBOL_GPL(fsl_edma_setup_regs);
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma-main.c
similarity index 100%
rename from drivers/dma/fsl-edma.c
rename to drivers/dma/fsl-edma-main.c
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma-main.c
similarity index 100%
rename from drivers/dma/mcf-edma.c
rename to drivers/dma/mcf-edma-main.c
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 02/12] dmaengine: fsl-edma: clean up fsl_edma_irq_exit()
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
2023-06-01 14:40 ` [PATCH v3 01/12] dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c Frank Li
@ 2023-06-01 14:40 ` Frank Li
2023-06-01 14:40 ` [PATCH v3 03/12] dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdata Frank Li
` (9 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:40 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
In the probe function, devm_request_irq is now being used to automatically
manage IRQ. It eliminates the need for manual IRQ freeing during removal.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
drivers/dma/fsl-edma-main.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index e40769666e39..16305bb9a2ef 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -216,17 +216,6 @@ fsl_edma2_irq_init(struct platform_device *pdev,
return 0;
}
-static void fsl_edma_irq_exit(
- struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
-{
- if (fsl_edma->txirq == fsl_edma->errirq) {
- devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
- } else {
- devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
- devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
- }
-}
-
static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
{
int i;
@@ -427,7 +416,6 @@ static int fsl_edma_remove(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node;
struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
- fsl_edma_irq_exit(pdev, fsl_edma);
fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
of_dma_controller_free(np);
dma_async_device_unregister(&fsl_edma->dma_dev);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 03/12] dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdata
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
2023-06-01 14:40 ` [PATCH v3 01/12] dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c Frank Li
2023-06-01 14:40 ` [PATCH v3 02/12] dmaengine: fsl-edma: clean up fsl_edma_irq_exit() Frank Li
@ 2023-06-01 14:40 ` Frank Li
2023-06-01 14:40 ` [PATCH v3 04/12] dmaengine: fsl-edma: Remove enum edma_version Frank Li
` (8 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:40 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
Replace individual bool fields with bitmask flags within drvdata. This
will facilitate future extensions, making it easier to add more flags to
accommodate new versions of the edma IP.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
drivers/dma/fsl-edma-common.c | 2 +-
drivers/dma/fsl-edma-common.h | 5 +++--
drivers/dma/fsl-edma-main.c | 6 +++---
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index ce8d7c9eaf77..10dcc1435d37 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -114,7 +114,7 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr;
ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
- if (fsl_chan->edma->drvdata->mux_swap)
+ if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_MUX_SWAP)
ch_off += endian_diff[ch_off % 4];
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 004ec4a6bc86..db137a8c558d 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -144,11 +144,12 @@ enum edma_version {
v3, /* 32ch, i.mx7ulp */
};
+#define FSL_EDMA_DRV_HAS_DMACLK BIT(0)
+#define FSL_EDMA_DRV_MUX_SWAP BIT(1)
struct fsl_edma_drvdata {
enum edma_version version;
u32 dmamuxs;
- bool has_dmaclk;
- bool mux_swap;
+ u32 flags;
int (*setup_irq)(struct platform_device *pdev,
struct fsl_edma_engine *fsl_edma);
};
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 16305bb9a2ef..f5cf95d185f8 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -233,14 +233,14 @@ static struct fsl_edma_drvdata vf610_data = {
static struct fsl_edma_drvdata ls1028a_data = {
.version = v1,
.dmamuxs = DMAMUX_NR,
- .mux_swap = true,
+ .flags = FSL_EDMA_DRV_MUX_SWAP,
.setup_irq = fsl_edma_irq_init,
};
static struct fsl_edma_drvdata imx7ulp_data = {
.version = v3,
.dmamuxs = 1,
- .has_dmaclk = true,
+ .flags = FSL_EDMA_DRV_HAS_DMACLK,
.setup_irq = fsl_edma2_irq_init,
};
@@ -293,7 +293,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
fsl_edma_setup_regs(fsl_edma);
regs = &fsl_edma->regs;
- if (drvdata->has_dmaclk) {
+ if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
if (IS_ERR(fsl_edma->dmaclk)) {
dev_err(&pdev->dev, "Missing DMA block clock.\n");
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 04/12] dmaengine: fsl-edma: Remove enum edma_version
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
` (2 preceding siblings ...)
2023-06-01 14:40 ` [PATCH v3 03/12] dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdata Frank Li
@ 2023-06-01 14:40 ` Frank Li
2023-06-01 14:41 ` [PATCH v3 05/12] dmaengine: fsl-edma: move common IRQ handler to common.c Frank Li
` (7 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:40 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
The enum edma_version, which defines v1, v2, and v3, is a software concept
used to distinguish IP differences. However, it is not aligned with the
chip reference manual. According to the 7ulp reference manual, it should
be edma2. In the future, there will be edma3, edma4, and edma5, which
could cause confusion. To avoid this confusion, remove the edma_version
and instead use drvdata->flags to distinguish the IP difference.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/fsl-edma-common.c | 47 ++++++++++++++---------------------
drivers/dma/fsl-edma-common.h | 10 +++-----
drivers/dma/fsl-edma-main.c | 9 +++----
drivers/dma/mcf-edma-main.c | 2 +-
4 files changed, 26 insertions(+), 42 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 10dcc1435d37..9948babcadf6 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -47,7 +47,7 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
struct edma_regs *regs = &fsl_chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- if (fsl_chan->edma->drvdata->version == v1) {
+ if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {
edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
edma_writeb(fsl_chan->edma, ch, regs->serq);
} else {
@@ -64,7 +64,7 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
struct edma_regs *regs = &fsl_chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- if (fsl_chan->edma->drvdata->version == v1) {
+ if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {
edma_writeb(fsl_chan->edma, ch, regs->cerq);
edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
} else {
@@ -120,7 +120,7 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
slot = EDMAMUX_CHCFG_SOURCE(slot);
- if (fsl_chan->edma->drvdata->version == v3)
+ if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_CONFIG32)
mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable);
else
mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
@@ -682,9 +682,8 @@ void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
}
/*
- * On the 32 channels Vybrid/mpc577x edma version (here called "v1"),
- * register offsets are different compared to ColdFire mcf5441x 64 channels
- * edma (here called "v2").
+ * On the 32 channels Vybrid/mpc577x edma version, register offsets are
+ * different compared to ColdFire mcf5441x 64 channels edma.
*
* This function sets up register offsets as per proper declared version
* so must be called in xxx_edma_probe() just after setting the
@@ -692,33 +691,25 @@ void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
*/
void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
{
+ bool is64 = !!(edma->drvdata->flags & FSL_EDMA_DRV_EDMA64);
+
edma->regs.cr = edma->membase + EDMA_CR;
edma->regs.es = edma->membase + EDMA_ES;
edma->regs.erql = edma->membase + EDMA_ERQ;
edma->regs.eeil = edma->membase + EDMA_EEI;
- edma->regs.serq = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_SERQ : EDMA_SERQ);
- edma->regs.cerq = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_CERQ : EDMA_CERQ);
- edma->regs.seei = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_SEEI : EDMA_SEEI);
- edma->regs.ceei = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_CEEI : EDMA_CEEI);
- edma->regs.cint = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_CINT : EDMA_CINT);
- edma->regs.cerr = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_CERR : EDMA_CERR);
- edma->regs.ssrt = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_SSRT : EDMA_SSRT);
- edma->regs.cdne = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_CDNE : EDMA_CDNE);
- edma->regs.intl = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_INTL : EDMA_INTR);
- edma->regs.errl = edma->membase + ((edma->drvdata->version == v2) ?
- EDMA64_ERRL : EDMA_ERR);
-
- if (edma->drvdata->version == v2) {
+ edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ);
+ edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ);
+ edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI);
+ edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI);
+ edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT);
+ edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR);
+ edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT);
+ edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE);
+ edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR);
+ edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR);
+
+ if (is64) {
edma->regs.erqh = edma->membase + EDMA64_ERQH;
edma->regs.eeih = edma->membase + EDMA64_EEIH;
edma->regs.errh = edma->membase + EDMA64_ERRH;
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index db137a8c558d..5f3fcb991b5e 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -138,16 +138,12 @@ struct fsl_edma_desc {
struct fsl_edma_sw_tcd tcd[];
};
-enum edma_version {
- v1, /* 32ch, Vybrid, mpc57x, etc */
- v2, /* 64ch Coldfire */
- v3, /* 32ch, i.mx7ulp */
-};
-
#define FSL_EDMA_DRV_HAS_DMACLK BIT(0)
#define FSL_EDMA_DRV_MUX_SWAP BIT(1)
+#define FSL_EDMA_DRV_CONFIG32 BIT(2)
+#define FSL_EDMA_DRV_WRAP_IO BIT(3)
+#define FSL_EDMA_DRV_EDMA64 BIT(4)
struct fsl_edma_drvdata {
- enum edma_version version;
u32 dmamuxs;
u32 flags;
int (*setup_irq)(struct platform_device *pdev,
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index f5cf95d185f8..c7f57edd2bb6 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -225,22 +225,19 @@ static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
}
static struct fsl_edma_drvdata vf610_data = {
- .version = v1,
- .dmamuxs = DMAMUX_NR,
+ .dmamuxs = DMAMUX_NR | FSL_EDMA_DRV_WRAP_IO,
.setup_irq = fsl_edma_irq_init,
};
static struct fsl_edma_drvdata ls1028a_data = {
- .version = v1,
.dmamuxs = DMAMUX_NR,
- .flags = FSL_EDMA_DRV_MUX_SWAP,
+ .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
.setup_irq = fsl_edma_irq_init,
};
static struct fsl_edma_drvdata imx7ulp_data = {
- .version = v3,
.dmamuxs = 1,
- .flags = FSL_EDMA_DRV_HAS_DMACLK,
+ .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
.setup_irq = fsl_edma2_irq_init,
};
diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
index ebd8733f72ad..7b05e303ba51 100644
--- a/drivers/dma/mcf-edma-main.c
+++ b/drivers/dma/mcf-edma-main.c
@@ -172,7 +172,7 @@ static void mcf_edma_irq_free(struct platform_device *pdev,
}
static struct fsl_edma_drvdata mcf_data = {
- .version = v2,
+ .flags = FSL_EDMA_DRV_EDMA64,
.setup_irq = mcf_edma_irq_init,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 05/12] dmaengine: fsl-edma: move common IRQ handler to common.c
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
` (3 preceding siblings ...)
2023-06-01 14:40 ` [PATCH v3 04/12] dmaengine: fsl-edma: Remove enum edma_version Frank Li
@ 2023-06-01 14:41 ` Frank Li
2023-06-01 14:41 ` [PATCH v3 06/12] dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs() Frank Li
` (6 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:41 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
Move the common part of IRQ handler from fsl-edma-main.c and
mcf-edma-main.c to fsl-edma-common.c. This eliminates redundant code, as
the both files contains mostly identical code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/fsl-edma-common.c | 26 ++++++++++++++++++++++++++
drivers/dma/fsl-edma-common.h | 7 +++++++
drivers/dma/fsl-edma-main.c | 30 ++----------------------------
drivers/dma/mcf-edma-main.c | 30 ++----------------------------
4 files changed, 37 insertions(+), 56 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 9948babcadf6..a9d17cf142fc 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -42,6 +42,32 @@
#define EDMA_TCD 0x1000
+void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan)
+{
+ spin_lock(&fsl_chan->vchan.lock);
+
+ if (!fsl_chan->edesc) {
+ /* terminate_all called before */
+ spin_unlock(&fsl_chan->vchan.lock);
+ return;
+ }
+
+ if (!fsl_chan->edesc->iscyclic) {
+ list_del(&fsl_chan->edesc->vdesc.node);
+ vchan_cookie_complete(&fsl_chan->edesc->vdesc);
+ fsl_chan->edesc = NULL;
+ fsl_chan->status = DMA_COMPLETE;
+ fsl_chan->idle = true;
+ } else {
+ vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
+ }
+
+ if (!fsl_chan->edesc)
+ fsl_edma_xfer_desc(fsl_chan);
+
+ spin_unlock(&fsl_chan->vchan.lock);
+}
+
static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
{
struct edma_regs *regs = &fsl_chan->edma->regs;
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 5f3fcb991b5e..242ab7df8993 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -219,6 +219,13 @@ static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
return container_of(vd, struct fsl_edma_desc, vdesc);
}
+static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
+{
+ fsl_chan->status = DMA_ERROR;
+ fsl_chan->idle = true;
+}
+
+void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
unsigned int slot, bool enable);
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index c7f57edd2bb6..73178f250d0a 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -33,7 +33,6 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
struct fsl_edma_engine *fsl_edma = dev_id;
unsigned int intr, ch;
struct edma_regs *regs = &fsl_edma->regs;
- struct fsl_edma_chan *fsl_chan;
intr = edma_readl(fsl_edma, regs->intl);
if (!intr)
@@ -42,31 +41,7 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
for (ch = 0; ch < fsl_edma->n_chans; ch++) {
if (intr & (0x1 << ch)) {
edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
-
- fsl_chan = &fsl_edma->chans[ch];
-
- spin_lock(&fsl_chan->vchan.lock);
-
- if (!fsl_chan->edesc) {
- /* terminate_all called before */
- spin_unlock(&fsl_chan->vchan.lock);
- continue;
- }
-
- if (!fsl_chan->edesc->iscyclic) {
- list_del(&fsl_chan->edesc->vdesc.node);
- vchan_cookie_complete(&fsl_chan->edesc->vdesc);
- fsl_chan->edesc = NULL;
- fsl_chan->status = DMA_COMPLETE;
- fsl_chan->idle = true;
- } else {
- vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
- }
-
- if (!fsl_chan->edesc)
- fsl_edma_xfer_desc(fsl_chan);
-
- spin_unlock(&fsl_chan->vchan.lock);
+ fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]);
}
}
return IRQ_HANDLED;
@@ -86,8 +61,7 @@ static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
if (err & (0x1 << ch)) {
fsl_edma_disable_request(&fsl_edma->chans[ch]);
edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
- fsl_edma->chans[ch].status = DMA_ERROR;
- fsl_edma->chans[ch].idle = true;
+ fsl_edma_err_chan_handler(&fsl_edma->chans[ch]);
}
}
return IRQ_HANDLED;
diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
index 7b05e303ba51..316e637b00c4 100644
--- a/drivers/dma/mcf-edma-main.c
+++ b/drivers/dma/mcf-edma-main.c
@@ -19,7 +19,6 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
struct fsl_edma_engine *mcf_edma = dev_id;
struct edma_regs *regs = &mcf_edma->regs;
unsigned int ch;
- struct fsl_edma_chan *mcf_chan;
u64 intmap;
intmap = ioread32(regs->inth);
@@ -31,31 +30,7 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
for (ch = 0; ch < mcf_edma->n_chans; ch++) {
if (intmap & BIT(ch)) {
iowrite8(EDMA_MASK_CH(ch), regs->cint);
-
- mcf_chan = &mcf_edma->chans[ch];
-
- spin_lock(&mcf_chan->vchan.lock);
-
- if (!mcf_chan->edesc) {
- /* terminate_all called before */
- spin_unlock(&mcf_chan->vchan.lock);
- continue;
- }
-
- if (!mcf_chan->edesc->iscyclic) {
- list_del(&mcf_chan->edesc->vdesc.node);
- vchan_cookie_complete(&mcf_chan->edesc->vdesc);
- mcf_chan->edesc = NULL;
- mcf_chan->status = DMA_COMPLETE;
- mcf_chan->idle = true;
- } else {
- vchan_cyclic_callback(&mcf_chan->edesc->vdesc);
- }
-
- if (!mcf_chan->edesc)
- fsl_edma_xfer_desc(mcf_chan);
-
- spin_unlock(&mcf_chan->vchan.lock);
+ fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
}
}
@@ -76,8 +51,7 @@ static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
if (err & BIT(ch)) {
fsl_edma_disable_request(&mcf_edma->chans[ch]);
iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
- mcf_edma->chans[ch].status = DMA_ERROR;
- mcf_edma->chans[ch].idle = true;
+ fsl_edma_err_chan_handler(&mcf_edma->chans[ch]);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 06/12] dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs()
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
` (4 preceding siblings ...)
2023-06-01 14:41 ` [PATCH v3 05/12] dmaengine: fsl-edma: move common IRQ handler to common.c Frank Li
@ 2023-06-01 14:41 ` Frank Li
2023-06-01 14:41 ` [PATCH v3 07/12] dmaengine: fsl-edma: refactor using devm_clk_get_enabled Frank Li
` (5 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:41 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
Removes all ATTR_DSIZE_*BIT(BYTE) and ATTR_SSIZE_*BIT(BYTE) definitions
in edma. Uses ffs() instead, as it gives identical results. This simplifies
the code and avoids adding more similar definitions in future V3 version.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/fsl-edma-common.c | 21 ++++++++-------------
drivers/dma/fsl-edma-common.h | 10 ----------
2 files changed, 8 insertions(+), 23 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index a9d17cf142fc..51fbd7531c74 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -154,18 +154,13 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
{
- switch (addr_width) {
- case 1:
- return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT;
- case 2:
- return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT;
- case 4:
- return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
- case 8:
- return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT;
- default:
- return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
- }
+ u32 val;
+
+ if (addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
+ addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+
+ val = ffs(addr_width) - 1;
+ return val | (val << 8);
}
void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
@@ -623,7 +618,7 @@ struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan,
/* To match with copy_align and max_seg_size so 1 tcd is enough */
fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
- EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE,
+ fsl_edma_get_tcd_attr(DMA_SLAVE_BUSWIDTH_32_BYTES),
32, len, 0, 1, 1, 32, 0, true, true, false);
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 242ab7df8993..521b79fc3828 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -29,16 +29,6 @@
#define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
-#define EDMA_TCD_ATTR_DSIZE_8BIT 0
-#define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0)
-#define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1)
-#define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1))
-#define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(2) | BIT(0))
-#define EDMA_TCD_ATTR_SSIZE_8BIT 0
-#define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8)
-#define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8)
-#define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8)
-#define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8)
#define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0))
#define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0))
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 07/12] dmaengine: fsl-edma: refactor using devm_clk_get_enabled
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
` (5 preceding siblings ...)
2023-06-01 14:41 ` [PATCH v3 06/12] dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs() Frank Li
@ 2023-06-01 14:41 ` Frank Li
2023-06-01 14:41 ` [PATCH v3 08/12] dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function Frank Li
` (4 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:41 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
Use devm_clk_get_enabled in probe code to reduce error checks,
thereby enhancing readability
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/fsl-edma-main.c | 19 ++-----------------
1 file changed, 2 insertions(+), 17 deletions(-)
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 73178f250d0a..70e1a0605025 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -265,17 +265,11 @@ static int fsl_edma_probe(struct platform_device *pdev)
regs = &fsl_edma->regs;
if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
- fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
+ fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
if (IS_ERR(fsl_edma->dmaclk)) {
dev_err(&pdev->dev, "Missing DMA block clock.\n");
return PTR_ERR(fsl_edma->dmaclk);
}
-
- ret = clk_prepare_enable(fsl_edma->dmaclk);
- if (ret) {
- dev_err(&pdev->dev, "DMA clk block failed.\n");
- return ret;
- }
}
for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
@@ -290,19 +284,12 @@ static int fsl_edma_probe(struct platform_device *pdev)
}
sprintf(clkname, "dmamux%d", i);
- fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
+ fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname);
if (IS_ERR(fsl_edma->muxclk[i])) {
dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
/* on error: disable all previously enabled clks */
- fsl_disable_clocks(fsl_edma, i);
return PTR_ERR(fsl_edma->muxclk[i]);
}
-
- ret = clk_prepare_enable(fsl_edma->muxclk[i]);
- if (ret)
- /* on error: disable all previously enabled clks */
- fsl_disable_clocks(fsl_edma, i);
-
}
fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
@@ -363,7 +350,6 @@ static int fsl_edma_probe(struct platform_device *pdev)
if (ret) {
dev_err(&pdev->dev,
"Can't register Freescale eDMA engine. (%d)\n", ret);
- fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
return ret;
}
@@ -372,7 +358,6 @@ static int fsl_edma_probe(struct platform_device *pdev)
dev_err(&pdev->dev,
"Can't register Freescale eDMA of_dma. (%d)\n", ret);
dma_async_device_unregister(&fsl_edma->dma_dev);
- fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 08/12] dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
` (6 preceding siblings ...)
2023-06-01 14:41 ` [PATCH v3 07/12] dmaengine: fsl-edma: refactor using devm_clk_get_enabled Frank Li
@ 2023-06-01 14:41 ` Frank Li
2023-06-01 14:41 ` [PATCH v3 09/12] dmaengine: fsl-edma: refactor chan_name setup and safety Frank Li
` (3 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:41 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
This accommodates differences in the register layout of EDMA v3 by moving
the clearing of register interrupts into the platform-specific set_irq
function. This should ensure better compatibility with EDMA v3.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/fsl-edma-main.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 70e1a0605025..f7f3373989f8 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -113,6 +113,8 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma
{
int ret;
+ edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
+
fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
if (fsl_edma->txirq < 0)
return fsl_edma->txirq;
@@ -154,6 +156,8 @@ fsl_edma2_irq_init(struct platform_device *pdev,
int i, ret, irq;
int count;
+ edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
+
count = platform_irq_count(pdev);
dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
if (count <= 2) {
@@ -310,7 +314,6 @@ static int fsl_edma_probe(struct platform_device *pdev)
fsl_edma_chan_mux(fsl_chan, 0, false);
}
- edma_writel(fsl_edma, ~0, regs->intl);
ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
if (ret)
return ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 09/12] dmaengine: fsl-edma: refactor chan_name setup and safety
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
` (7 preceding siblings ...)
2023-06-01 14:41 ` [PATCH v3 08/12] dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function Frank Li
@ 2023-06-01 14:41 ` Frank Li
2023-06-01 14:41 ` [PATCH v3 10/12] dmaengine: fsl-edma: move tcd into struct fsl_dma_chan Frank Li
` (2 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:41 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
Relocated the setup of chan_name from setup_irq() to fsl_chan init. This
change anticipates its future use in various locations.
For increased safety, sprintf has been replaced with snprintf. In addition,
The size of the fsl_chan->name[] array was expanded from 16 to 32.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/fsl-edma-common.h | 2 +-
drivers/dma/fsl-edma-main.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 521b79fc3828..316df42ae5cb 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -116,7 +116,7 @@ struct fsl_edma_chan {
dma_addr_t dma_dev_addr;
u32 dma_dev_size;
enum dma_data_direction dma_dir;
- char chan_name[16];
+ char chan_name[32];
};
struct fsl_edma_desc {
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index f7f3373989f8..6bbf9c2cea2f 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -175,8 +175,6 @@ fsl_edma2_irq_init(struct platform_device *pdev,
if (irq < 0)
return -ENXIO;
- sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
-
/* The last IRQ is for eDMA err */
if (i == count - 1)
ret = devm_request_irq(&pdev->dev, irq,
@@ -302,6 +300,9 @@ static int fsl_edma_probe(struct platform_device *pdev)
for (i = 0; i < fsl_edma->n_chans; i++) {
struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
+ snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d",
+ dev_name(&pdev->dev), i);
+
fsl_chan->edma = fsl_edma;
fsl_chan->pm_state = RUNNING;
fsl_chan->slave_id = 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 10/12] dmaengine: fsl-edma: move tcd into struct fsl_dma_chan
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
` (8 preceding siblings ...)
2023-06-01 14:41 ` [PATCH v3 09/12] dmaengine: fsl-edma: refactor chan_name setup and safety Frank Li
@ 2023-06-01 14:41 ` Frank Li
2023-06-01 14:41 ` [PATCH v3 11/12] dmaengine: fsl-edma: integrate v3 support Frank Li
2023-06-01 14:41 ` [PATCH v3 12/12] dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string Frank Li
11 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:41 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
Relocates the tcd into the fsl_dma_chan structure. This adjustment reduces
the need to reference back to fsl_edma_engine, paving the way for EDMA V3
support.
Unified the edma_writel and edma_writew functions for accessing TCD
(Transfer Control Descriptor) registers. A new macro is added that can
automatically detect whether a 32-bit or 16-bit access should be used
based on the structure field definition. This provide better support
64-bit TCD with future v5 version.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202305271951.gmRobs3a-lkp@intel.com/
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/fsl-edma-common.c | 38 +++++++++++++----------------------
drivers/dma/fsl-edma-common.h | 22 +++++++++++++++++++-
drivers/dma/fsl-edma-main.c | 6 ++++--
drivers/dma/mcf-edma-main.c | 4 +++-
4 files changed, 42 insertions(+), 28 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 51fbd7531c74..eead6a4765f7 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -40,8 +40,6 @@
#define EDMA64_ERRH 0x28
#define EDMA64_ERRL 0x2c
-#define EDMA_TCD 0x1000
-
void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan)
{
spin_lock(&fsl_chan->vchan.lock);
@@ -285,8 +283,6 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
struct virt_dma_desc *vdesc, bool in_progress)
{
struct fsl_edma_desc *edesc = fsl_chan->edesc;
- struct edma_regs *regs = &fsl_chan->edma->regs;
- u32 ch = fsl_chan->vchan.chan.chan_id;
enum dma_transfer_direction dir = edesc->dirn;
dma_addr_t cur_addr, dma_addr;
size_t len, size;
@@ -301,9 +297,9 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
return len;
if (dir == DMA_MEM_TO_DEV)
- cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].saddr);
+ cur_addr = edma_read_tcdreg(fsl_chan, saddr);
else
- cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].daddr);
+ cur_addr = edma_read_tcdreg(fsl_chan, daddr);
/* figure out the finished and calculate the residue */
for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
@@ -358,9 +354,6 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
struct fsl_edma_hw_tcd *tcd)
{
- struct fsl_edma_engine *edma = fsl_chan->edma;
- struct edma_regs *regs = &fsl_chan->edma->regs;
- u32 ch = fsl_chan->vchan.chan.chan_id;
u16 csr = 0;
/*
@@ -369,23 +362,22 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
* big- or little-endian obeying the eDMA engine model endian,
* and this is performed from specific edma_write functions
*/
- edma_writew(edma, 0, ®s->tcd[ch].csr);
+ edma_write_tcdreg(fsl_chan, 0, csr);
- edma_writel(edma, (s32)tcd->saddr, ®s->tcd[ch].saddr);
- edma_writel(edma, (s32)tcd->daddr, ®s->tcd[ch].daddr);
+ edma_write_tcdreg(fsl_chan, tcd->saddr, saddr);
+ edma_write_tcdreg(fsl_chan, tcd->daddr, daddr);
- edma_writew(edma, (s16)tcd->attr, ®s->tcd[ch].attr);
- edma_writew(edma, tcd->soff, ®s->tcd[ch].soff);
+ edma_write_tcdreg(fsl_chan, tcd->attr, attr);
+ edma_write_tcdreg(fsl_chan, tcd->soff, soff);
- edma_writel(edma, (s32)tcd->nbytes, ®s->tcd[ch].nbytes);
- edma_writel(edma, (s32)tcd->slast, ®s->tcd[ch].slast);
+ edma_write_tcdreg(fsl_chan, tcd->nbytes, nbytes);
+ edma_write_tcdreg(fsl_chan, tcd->slast, slast);
- edma_writew(edma, (s16)tcd->citer, ®s->tcd[ch].citer);
- edma_writew(edma, (s16)tcd->biter, ®s->tcd[ch].biter);
- edma_writew(edma, (s16)tcd->doff, ®s->tcd[ch].doff);
+ edma_write_tcdreg(fsl_chan, tcd->citer, citer);
+ edma_write_tcdreg(fsl_chan, tcd->biter, biter);
+ edma_write_tcdreg(fsl_chan, tcd->doff, doff);
- edma_writel(edma, (s32)tcd->dlast_sga,
- ®s->tcd[ch].dlast_sga);
+ edma_write_tcdreg(fsl_chan, tcd->dlast_sga, dlast_sga);
if (fsl_chan->is_sw) {
csr = le16_to_cpu(tcd->csr);
@@ -393,7 +385,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
tcd->csr = cpu_to_le16(csr);
}
- edma_writew(edma, (s16)tcd->csr, ®s->tcd[ch].csr);
+ edma_write_tcdreg(fsl_chan, tcd->csr, csr);
}
static inline
@@ -736,7 +728,5 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
edma->regs.errh = edma->membase + EDMA64_ERRH;
edma->regs.inth = edma->membase + EDMA64_INTH;
}
-
- edma->regs.tcd = edma->membase + EDMA_TCD;
}
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 316df42ae5cb..cfc41915eaa1 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -48,6 +48,8 @@
#define DMAMUX_NR 2
+#define EDMA_TCD 0x1000
+
#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
@@ -93,7 +95,6 @@ struct edma_regs {
void __iomem *intl;
void __iomem *errh;
void __iomem *errl;
- struct fsl_edma_hw_tcd __iomem *tcd;
};
struct fsl_edma_sw_tcd {
@@ -117,6 +118,7 @@ struct fsl_edma_chan {
u32 dma_dev_size;
enum dma_data_direction dma_dir;
char chan_name[32];
+ struct fsl_edma_hw_tcd __iomem *tcd;
};
struct fsl_edma_desc {
@@ -156,6 +158,16 @@ struct fsl_edma_engine {
struct fsl_edma_chan chans[];
};
+#define edma_read_tcdreg(chan, __name) \
+(sizeof(chan->tcd->__name) == sizeof(u32) ? \
+ edma_readl(chan->edma, &chan->tcd->__name) : \
+ edma_readw(chan->edma, &chan->tcd->__name))
+
+#define edma_write_tcdreg(chan, val, __name) \
+(sizeof(chan->tcd->__name) == sizeof(u32) ? \
+ edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \
+ edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name))
+
/*
* R/W functions for big- or little-endian registers:
* The eDMA controller's endian is independent of the CPU core's endian.
@@ -170,6 +182,14 @@ static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
return ioread32(addr);
}
+static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
+{
+ if (edma->big_endian)
+ return ioread16be(addr);
+ else
+ return ioread16(addr);
+}
+
static inline void edma_writeb(struct fsl_edma_engine *edma,
u8 val, void __iomem *addr)
{
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 6bbf9c2cea2f..e5f42dd974e8 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -309,9 +309,11 @@ static int fsl_edma_probe(struct platform_device *pdev)
fsl_chan->idle = true;
fsl_chan->dma_dir = DMA_NONE;
fsl_chan->vchan.desc_free = fsl_edma_free_desc;
+ fsl_chan->tcd = fsl_edma->membase + EDMA_TCD
+ + i * sizeof(struct fsl_edma_hw_tcd);
vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
- edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
+ edma_write_tcdreg(fsl_chan, 0, csr);
fsl_edma_chan_mux(fsl_chan, 0, false);
}
@@ -418,7 +420,7 @@ static int fsl_edma_resume_early(struct device *dev)
for (i = 0; i < fsl_edma->n_chans; i++) {
fsl_chan = &fsl_edma->chans[i];
fsl_chan->pm_state = RUNNING;
- edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
+ edma_write_tcdreg(fsl_chan, 0, csr);
if (fsl_chan->slave_id != 0)
fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
}
diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
index 316e637b00c4..bccb5448e492 100644
--- a/drivers/dma/mcf-edma-main.c
+++ b/drivers/dma/mcf-edma-main.c
@@ -200,7 +200,9 @@ static int mcf_edma_probe(struct platform_device *pdev)
mcf_chan->dma_dir = DMA_NONE;
mcf_chan->vchan.desc_free = fsl_edma_free_desc;
vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
- iowrite32(0x0, ®s->tcd[i].csr);
+ mcf_chan->tcd = mcf_edma->membase + EDMA_TCD
+ + i * sizeof(struct fsl_edma_hw_tcd);
+ iowrite32(0x0, &mcf_chan->tcd->csr);
}
iowrite32(~0, regs->inth);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 11/12] dmaengine: fsl-edma: integrate v3 support
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
` (9 preceding siblings ...)
2023-06-01 14:41 ` [PATCH v3 10/12] dmaengine: fsl-edma: move tcd into struct fsl_dma_chan Frank Li
@ 2023-06-01 14:41 ` Frank Li
2023-06-02 9:41 ` Joy Zou
2023-06-01 14:41 ` [PATCH v3 12/12] dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string Frank Li
11 siblings, 1 reply; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:41 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
Significant alterations have been made to the EDMA v3's register layout.
Now, each channel possesses a separate address space, encapsulating all
channel-related controls and statuses, including IRQs. There are changes
in bit position definitions as well. However, the fundamental control flow
remains analogous to the previous versions.
EDMA v3 was utilized in imx8qm, imx93, and will be in forthcoming chips.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/fsl-edma-common.c | 158 +++++++++++++++++++---
drivers/dma/fsl-edma-common.h | 75 ++++++++++
drivers/dma/fsl-edma-main.c | 248 ++++++++++++++++++++++++++++++++--
3 files changed, 456 insertions(+), 25 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index eead6a4765f7..dbfc9d80e2ed 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -7,6 +7,8 @@
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_domain.h>
#include "fsl-edma-common.h"
@@ -66,11 +68,47 @@ void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan)
spin_unlock(&fsl_chan->vchan.lock);
}
+static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan)
+{
+ u32 val, flags;
+
+ flags = fsl_edma_drvflags(fsl_chan);
+ val = edma_readl_chreg(fsl_chan, ch_sbr);
+ /* Remote/local swapped wrongly on iMX8 QM Audio edma */
+ if (flags & FSL_EDMA_DRV_QUIRK_SWAPPED) {
+ if (!fsl_chan->is_rxchan)
+ val |= EDMA_V3_CH_SBR_RD;
+ else
+ val |= EDMA_V3_CH_SBR_WR;
+ } else {
+ if (fsl_chan->is_rxchan)
+ val |= EDMA_V3_CH_SBR_RD;
+ else
+ val |= EDMA_V3_CH_SBR_WR;
+ }
+
+ if (fsl_chan->is_remote)
+ val &= ~(EDMA_V3_CH_SBR_RD | EDMA_V3_CH_SBR_WR);
+
+ edma_writel_chreg(fsl_chan, val, ch_sbr);
+
+ if ((flags & (FSL_EDMA_DRV_AXI | FSL_EDMA_DRV_HAS_CHMUX)) &&
+ fsl_chan->srcid && !edma_readl_chreg(fsl_chan, ch_mux))
+ edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
+
+ val = edma_readl_chreg(fsl_chan, ch_csr);
+ val |= EDMA_V3_CH_CSR_ERQ;
+ edma_writel_chreg(fsl_chan, val, ch_csr);
+}
+
static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
{
struct edma_regs *regs = &fsl_chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
+ if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG)
+ return fsl_edma3_enable_request(fsl_chan);
+
if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {
edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
edma_writeb(fsl_chan->edma, ch, regs->serq);
@@ -83,11 +121,29 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
}
}
+static void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan)
+{
+ u32 val = edma_readl_chreg(fsl_chan, ch_csr);
+ u32 flags;
+
+ flags = fsl_edma_drvflags(fsl_chan);
+
+ if ((flags & (FSL_EDMA_DRV_AXI | FSL_EDMA_DRV_HAS_CHMUX)) &&
+ fsl_chan->srcid)
+ edma_writel_chreg(fsl_chan, 0, ch_mux);
+
+ val &= ~EDMA_V3_CH_CSR_ERQ;
+ edma_writel_chreg(fsl_chan, val, ch_csr);
+}
+
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
{
struct edma_regs *regs = &fsl_chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
+ if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG)
+ return fsl_edma3_disable_request(fsl_chan);
+
if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {
edma_writeb(fsl_chan->edma, ch, regs->cerq);
edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
@@ -186,6 +242,10 @@ int fsl_edma_terminate_all(struct dma_chan *chan)
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
+
+ if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_PD)
+ pm_runtime_allow(fsl_chan->pd_dev);
+
return 0;
}
@@ -286,12 +346,16 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
enum dma_transfer_direction dir = edesc->dirn;
dma_addr_t cur_addr, dma_addr;
size_t len, size;
+ u32 nbytes = 0;
int i;
/* calculate the total size in this desc */
- for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++)
- len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
- * le16_to_cpu(edesc->tcd[i].vtcd->biter);
+ for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) {
+ nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes);
+ if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE))
+ nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes);
+ len += nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter);
+ }
if (!in_progress)
return len;
@@ -303,8 +367,12 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
/* figure out the finished and calculate the residue */
for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
- size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
- * le16_to_cpu(edesc->tcd[i].vtcd->biter);
+ nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes);
+ if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE))
+ nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes);
+
+ size = nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter);
+
if (dir == DMA_MEM_TO_DEV)
dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr);
else
@@ -389,13 +457,15 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
}
static inline
-void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
+void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
+ struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
u16 biter, u16 doff, u32 dlast_sga, bool major_int,
bool disable_req, bool enable_sg)
{
+ struct dma_slave_config *cfg = &fsl_chan->cfg;
u16 csr = 0;
-
+ u32 burst;
/*
* eDMA hardware SGs require the TCDs to be stored in little
* endian format irrespective of the register endian model.
@@ -409,6 +479,21 @@ void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
tcd->soff = cpu_to_le16(soff);
+ if (fsl_chan->is_multi_fifo) {
+ /* set mloff to support multiple fifo */
+ burst = cfg->direction == DMA_DEV_TO_MEM ?
+ cfg->src_addr_width : cfg->dst_addr_width;
+ nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-(burst * 4));
+ /* enable DMLOE/SMLOE */
+ if (cfg->direction == DMA_MEM_TO_DEV) {
+ nbytes |= EDMA_V3_TCD_NBYTES_DMLOE;
+ nbytes &= ~EDMA_V3_TCD_NBYTES_SMLOE;
+ } else {
+ nbytes |= EDMA_V3_TCD_NBYTES_SMLOE;
+ nbytes &= ~EDMA_V3_TCD_NBYTES_DMLOE;
+ }
+ }
+
tcd->nbytes = cpu_to_le32(nbytes);
tcd->slast = cpu_to_le32(slast);
@@ -427,6 +512,12 @@ void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
if (enable_sg)
csr |= EDMA_TCD_CSR_E_SG;
+ if (fsl_chan->is_rxchan)
+ csr |= EDMA_TCD_CSR_ACTIVE;
+
+ if (fsl_chan->is_sw)
+ csr |= EDMA_TCD_CSR_START;
+
tcd->csr = cpu_to_le16(csr);
}
@@ -466,6 +557,7 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
struct fsl_edma_desc *fsl_desc;
dma_addr_t dma_buf_next;
+ bool major_int = true;
int sg_len, i;
u32 src_addr, dst_addr, last_sg, nbytes;
u16 soff, doff, iter;
@@ -509,17 +601,23 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
src_addr = dma_buf_next;
dst_addr = fsl_chan->dma_dev_addr;
soff = fsl_chan->cfg.dst_addr_width;
- doff = 0;
- } else {
+ doff = fsl_chan->is_multi_fifo ? 4 : 0;
+ } else if (direction == DMA_DEV_TO_MEM) {
src_addr = fsl_chan->dma_dev_addr;
dst_addr = dma_buf_next;
- soff = 0;
+ soff = fsl_chan->is_multi_fifo ? 4 : 0;
doff = fsl_chan->cfg.src_addr_width;
+ } else {
+ /* DMA_DEV_TO_DEV */
+ src_addr = fsl_chan->cfg.src_addr;
+ dst_addr = fsl_chan->cfg.dst_addr;
+ soff = doff = 0;
+ major_int = false;
}
- fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
+ fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
fsl_chan->attr, soff, nbytes, 0, iter,
- iter, doff, last_sg, true, false, true);
+ iter, doff, last_sg, major_int, false, true);
dma_buf_next += period_len;
}
@@ -568,23 +666,51 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
dst_addr = fsl_chan->dma_dev_addr;
soff = fsl_chan->cfg.dst_addr_width;
doff = 0;
- } else {
+ } else if (direction == DMA_DEV_TO_MEM) {
src_addr = fsl_chan->dma_dev_addr;
dst_addr = sg_dma_address(sg);
soff = 0;
doff = fsl_chan->cfg.src_addr_width;
+ } else {
+ /* DMA_DEV_TO_DEV */
+ src_addr = fsl_chan->cfg.src_addr;
+ dst_addr = fsl_chan->cfg.dst_addr;
+ soff = 0;
+ doff = 0;
}
+ /*
+ * Choose the suitable burst length if sg_dma_len is not
+ * multiple of burst length so that the whole transfer length is
+ * multiple of minor loop(burst length).
+ */
+ if (sg_dma_len(sg) % nbytes) {
+ u32 width = (direction == DMA_DEV_TO_MEM) ? doff : soff;
+ u32 burst = (direction == DMA_DEV_TO_MEM) ?
+ fsl_chan->cfg.src_maxburst :
+ fsl_chan->cfg.dst_maxburst;
+ int j;
+
+ for (j = burst; j > 1; j--) {
+ if (!(sg_dma_len(sg) % (j * width))) {
+ nbytes = j * width;
+ break;
+ }
+ }
+ /* Set burst size as 1 if there's no suitable one */
+ if (j == 1)
+ nbytes = width;
+ }
iter = sg_dma_len(sg) / nbytes;
if (i < sg_len - 1) {
last_sg = fsl_desc->tcd[(i + 1)].ptcd;
- fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
+ fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr,
dst_addr, fsl_chan->attr, soff,
nbytes, 0, iter, iter, doff, last_sg,
false, false, true);
} else {
last_sg = 0;
- fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
+ fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr,
dst_addr, fsl_chan->attr, soff,
nbytes, 0, iter, iter, doff, last_sg,
true, true, false);
@@ -609,7 +735,7 @@ struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan,
fsl_chan->is_sw = true;
/* To match with copy_align and max_seg_size so 1 tcd is enough */
- fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
+ fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
fsl_edma_get_tcd_attr(DMA_SLAVE_BUSWIDTH_32_BYTES),
32, len, 0, 1, 1, 32, 0, true, true, false);
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index cfc41915eaa1..d4ac2644654e 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -42,6 +42,11 @@
#define EDMA_TCD_CSR_ACTIVE BIT(6)
#define EDMA_TCD_CSR_DONE BIT(7)
+#define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))
+#define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10)
+#define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30)
+#define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31)
+
#define EDMAMUX_CHCFG_DIS 0x0
#define EDMAMUX_CHCFG_ENBL 0x80
#define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
@@ -54,6 +59,15 @@
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
+
+#define EDMA_V3_CH_SBR_RD BIT(22)
+#define EDMA_V3_CH_SBR_WR BIT(21)
+#define EDMA_V3_CH_CSR_ERQ BIT(0)
+#define EDMA_V3_CH_CSR_EARQ BIT(1)
+#define EDMA_V3_CH_CSR_EEI BIT(2)
+#define EDMA_V3_CH_CSR_DONE BIT(30)
+#define EDMA_V3_CH_CSR_ACTIVE BIT(31)
+
enum fsl_edma_pm_state {
RUNNING = 0,
SUSPENDED,
@@ -73,6 +87,18 @@ struct fsl_edma_hw_tcd {
__le16 biter;
};
+struct fsl_edma3_ch_reg {
+ __le32 ch_csr;
+ __le32 ch_es;
+ __le32 ch_int;
+ __le32 ch_sbr;
+ __le32 ch_pri;
+ __le32 ch_mux;
+ __le32 ch_mattr; /* edma4, reserved for edma3 */
+ __le32 ch_reserved;
+ struct fsl_edma_hw_tcd tcd;
+} __packed;
+
/*
* These are iomem pointers, for both v32 and v64.
*/
@@ -119,6 +145,18 @@ struct fsl_edma_chan {
enum dma_data_direction dma_dir;
char chan_name[32];
struct fsl_edma_hw_tcd __iomem *tcd;
+ u32 real_count;
+ struct work_struct issue_worker;
+ struct platform_device *pdev;
+ struct device *pd_dev;
+ u32 srcid;
+ struct clk *clk;
+ int priority;
+ int hw_chanid;
+ int txirq;
+ bool is_rxchan;
+ bool is_remote;
+ bool is_multi_fifo;
};
struct fsl_edma_desc {
@@ -135,8 +173,30 @@ struct fsl_edma_desc {
#define FSL_EDMA_DRV_CONFIG32 BIT(2)
#define FSL_EDMA_DRV_WRAP_IO BIT(3)
#define FSL_EDMA_DRV_EDMA64 BIT(4)
+#define FSL_EDMA_DRV_HAS_PD BIT(5)
+#define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
+#define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
+/* imx8 QM audio edma remote local swapped */
+#define FSL_EDMA_DRV_QUIRK_SWAPPED BIT(8)
+/* imx93 edma4 is AXI master */
+#define FSL_EDMA_DRV_AXI BIT(9)
+/* control and status register is in tcd address space, edma3 reg layout */
+#define FSL_EDMA_DRV_SPLIT_REG BIT(10)
+#define FSL_EDMA_DRV_BUS_8BYTE BIT(11)
+#define FSL_EDMA_DRV_DEV_TO_DEV BIT(12)
+#define FSL_EDMA_DRV_ALIGN_64BYTE BIT(13)
+
+#define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \
+ FSL_EDMA_DRV_BUS_8BYTE | \
+ FSL_EDMA_DRV_DEV_TO_DEV | \
+ FSL_EDMA_DRV_ALIGN_64BYTE)
+
+#define FSL_EDMA_DRV_EDMA4 (FSL_EDMA_DRV_EDMA3 | \
+ FSL_EDMA_DRV_AXI)
struct fsl_edma_drvdata {
u32 dmamuxs;
+ u32 chreg_off;
+ u32 chreg_space_sz;
u32 flags;
int (*setup_irq)(struct platform_device *pdev,
struct fsl_edma_engine *fsl_edma);
@@ -148,6 +208,7 @@ struct fsl_edma_engine {
void __iomem *muxbase[DMAMUX_NR];
struct clk *muxclk[DMAMUX_NR];
struct clk *dmaclk;
+ struct clk *chclk;
struct mutex fsl_edma_mutex;
const struct fsl_edma_drvdata *drvdata;
u32 n_chans;
@@ -155,6 +216,7 @@ struct fsl_edma_engine {
int errirq;
bool big_endian;
struct edma_regs regs;
+ u64 chan_masked;
struct fsl_edma_chan chans[];
};
@@ -168,6 +230,14 @@ struct fsl_edma_engine {
edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \
edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name))
+#define edma_readl_chreg(chan, __name) \
+ edma_readl(chan->edma, \
+ (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
+
+#define edma_writel_chreg(chan, val, __name) \
+ edma_writel(chan->edma, val, \
+ (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
+
/*
* R/W functions for big- or little-endian registers:
* The eDMA controller's endian is independent of the CPU core's endian.
@@ -224,6 +294,11 @@ static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
return container_of(chan, struct fsl_edma_chan, vchan.chan);
}
+static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan)
+{
+ return fsl_chan->edma->drvdata->flags;
+}
+
static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
{
return container_of(vd, struct fsl_edma_desc, vdesc);
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index e5f42dd974e8..33339ade79a4 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -18,9 +18,15 @@
#include <linux/of_irq.h>
#include <linux/of_dma.h>
#include <linux/dma-mapping.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_domain.h>
#include "fsl-edma-common.h"
+#define ARGS_RX BIT(0)
+#define ARGS_REMOTE BIT(1)
+#define ARGS_MULTI_FIFO BIT(2)
+
static void fsl_edma_synchronize(struct dma_chan *chan)
{
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
@@ -47,6 +53,22 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_chan *fsl_chan = dev_id;
+ unsigned int intr;
+
+ intr = edma_readl_chreg(fsl_chan, ch_int);
+ if (!intr)
+ return IRQ_HANDLED;
+
+ edma_writel_chreg(fsl_chan, 1, ch_int);
+
+ fsl_edma_tx_chan_handler(fsl_chan);
+
+ return IRQ_HANDLED;
+}
+
static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
{
struct fsl_edma_engine *fsl_edma = dev_id;
@@ -108,6 +130,52 @@ static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
return NULL;
}
+static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
+ struct dma_chan *chan, *_chan;
+ struct fsl_edma_chan *fsl_chan;
+ int i;
+
+ if (dma_spec->args_count != 3)
+ return NULL;
+
+ mutex_lock(&fsl_edma->fsl_edma_mutex);
+ list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
+ device_node) {
+
+ if (chan->client_count)
+ continue;
+
+ fsl_chan = to_fsl_edma_chan(chan);
+ i = fsl_chan - fsl_edma->chans;
+ if (fsl_edma->drvdata->dmamuxs == 0 && i == dma_spec->args[0]) {
+ chan = dma_get_slave_channel(chan);
+ chan->device->privatecnt++;
+ fsl_chan->priority = dma_spec->args[1];
+ fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
+ fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
+ fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO;
+ mutex_unlock(&fsl_edma->fsl_edma_mutex);
+ return chan;
+ } else if ((fsl_edma->drvdata->dmamuxs ||
+ (fsl_edma->drvdata->flags & FSL_EDMA_DRV_AXI)) && !fsl_chan->srcid) {
+ chan = dma_get_slave_channel(chan);
+ chan->device->privatecnt++;
+ fsl_chan->priority = dma_spec->args[1];
+ fsl_chan->srcid = dma_spec->args[0];
+ fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
+ fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
+ fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO;
+ mutex_unlock(&fsl_edma->fsl_edma_mutex);
+ return chan;
+ }
+ }
+ mutex_unlock(&fsl_edma->fsl_edma_mutex);
+ return NULL;
+}
+
static int
fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
{
@@ -149,6 +217,37 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma
return 0;
}
+static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < fsl_edma->n_chans; i++) {
+
+ struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
+
+ if (fsl_edma->chan_masked & BIT(i))
+ continue;
+
+ /* request channel irq */
+ fsl_chan->txirq = platform_get_irq(pdev, i);
+ if (fsl_chan->txirq < 0) {
+ dev_err(&pdev->dev, "Can't get chan %d's irq.\n", i);
+ return -EINVAL;
+ }
+
+ ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
+ fsl_edma3_tx_handler, IRQF_SHARED,
+ fsl_chan->chan_name, fsl_chan);
+ if (ret) {
+ dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
static int
fsl_edma2_irq_init(struct platform_device *pdev,
struct fsl_edma_engine *fsl_edma)
@@ -202,29 +301,115 @@ static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
static struct fsl_edma_drvdata vf610_data = {
.dmamuxs = DMAMUX_NR | FSL_EDMA_DRV_WRAP_IO,
+ .dmamuxs = DMAMUX_NR,
+ .chreg_off = EDMA_TCD,
+ .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
.setup_irq = fsl_edma_irq_init,
};
static struct fsl_edma_drvdata ls1028a_data = {
.dmamuxs = DMAMUX_NR,
.flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
+ .chreg_off = EDMA_TCD,
+ .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
.setup_irq = fsl_edma_irq_init,
};
static struct fsl_edma_drvdata imx7ulp_data = {
.dmamuxs = 1,
+ .chreg_off = EDMA_TCD,
+ .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
.flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
.setup_irq = fsl_edma2_irq_init,
};
+static struct fsl_edma_drvdata imx8qm_data = {
+ .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_PD
+ | FSL_EDMA_DRV_EDMA3,
+ .chreg_space_sz = 0x10000,
+ .chreg_off = 0x10000,
+ .setup_irq = fsl_edma3_irq_init,
+};
+
+static struct fsl_edma_drvdata imx8qm_audio_data = {
+ .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_QUIRK_SWAPPED |
+ FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
+ .chreg_space_sz = 0x10000,
+ .chreg_off = 0x10000,
+ .setup_irq = fsl_edma3_irq_init,
+};
+
+static struct fsl_edma_drvdata imx93_data3 = {
+ .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK
+ | FSL_EDMA_DRV_EDMA3,
+ .chreg_space_sz = 0x10000,
+ .chreg_off = 0x10000,
+ .setup_irq = fsl_edma3_irq_init,
+};
+
+static struct fsl_edma_drvdata imx93_data4 = {
+ .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK
+ | FSL_EDMA_DRV_EDMA4,
+ .chreg_space_sz = 0x8000,
+ .chreg_off = 0x10000,
+ .setup_irq = fsl_edma3_irq_init,
+};
+
static const struct of_device_id fsl_edma_dt_ids[] = {
{ .compatible = "fsl,vf610-edma", .data = &vf610_data},
{ .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
{ .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
+ { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
+ { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data},
+ { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
+ { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
{ /* sentinel */ }
};
+
MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
+static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
+{
+ struct fsl_edma_chan *fsl_chan;
+ struct device_link *link;
+ struct device *pd_chan;
+ struct device *dev;
+ int i;
+
+ dev = &pdev->dev;
+
+ for (i = 0; i < fsl_edma->n_chans; i++) {
+ if (fsl_edma->chan_masked & BIT(i))
+ continue;
+
+ fsl_chan = &fsl_edma->chans[i];
+
+ pd_chan = dev_pm_domain_attach_by_id(dev, i);
+ if (IS_ERR_OR_NULL(pd_chan)) {
+ dev_err(dev, "Failed attach pd %d\n", i);
+ return -EINVAL;
+ }
+
+ link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
+ DL_FLAG_PM_RUNTIME |
+ DL_FLAG_RPM_ACTIVE);
+ if (IS_ERR(link)) {
+ dev_err(dev, "Failed to add device_link to %d: %ld\n", i,
+ PTR_ERR(link));
+ return -EINVAL;
+ }
+
+ fsl_chan->pd_dev = pd_chan;
+
+ pm_runtime_use_autosuspend(fsl_chan->pd_dev);
+ pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200);
+ pm_runtime_set_active(fsl_chan->pd_dev);
+ //pm_runtime_put_sync_suspend(fsl_chan->pd_dev);
+ }
+
+ return 0;
+}
+
static int fsl_edma_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id =
@@ -263,8 +448,10 @@ static int fsl_edma_probe(struct platform_device *pdev)
if (IS_ERR(fsl_edma->membase))
return PTR_ERR(fsl_edma->membase);
- fsl_edma_setup_regs(fsl_edma);
- regs = &fsl_edma->regs;
+ if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) {
+ fsl_edma_setup_regs(fsl_edma);
+ regs = &fsl_edma->regs;
+ }
if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
@@ -274,6 +461,17 @@ static int fsl_edma_probe(struct platform_device *pdev)
}
}
+ if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
+ fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp");
+ if (IS_ERR(fsl_edma->chclk)) {
+ dev_err(&pdev->dev, "Missing MP block clock.\n");
+ return PTR_ERR(fsl_edma->chclk);
+ }
+ }
+
+ if (of_property_read_u64(np, "fsl,channel-mask", &fsl_edma->chan_masked))
+ fsl_edma->chan_masked = 0;
+
for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
char clkname[32];
@@ -296,9 +494,18 @@ static int fsl_edma_probe(struct platform_device *pdev)
fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
+ if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) {
+ ret = fsl_edma3_attach_pd(pdev, fsl_edma);
+ if (ret)
+ return ret;
+ }
+
INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
for (i = 0; i < fsl_edma->n_chans; i++) {
- struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
+ fsl_chan = &fsl_edma->chans[i];
+
+ if (fsl_edma->chan_masked & BIT(i))
+ continue;
snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d",
dev_name(&pdev->dev), i);
@@ -309,12 +516,19 @@ static int fsl_edma_probe(struct platform_device *pdev)
fsl_chan->idle = true;
fsl_chan->dma_dir = DMA_NONE;
fsl_chan->vchan.desc_free = fsl_edma_free_desc;
- fsl_chan->tcd = fsl_edma->membase + EDMA_TCD
- + i * sizeof(struct fsl_edma_hw_tcd);
+
+ len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ?
+ offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
+ fsl_chan->tcd = fsl_edma->membase
+ + i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
+
+ fsl_chan->pdev = pdev;
vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
edma_write_tcdreg(fsl_chan, 0, csr);
- fsl_edma_chan_mux(fsl_chan, 0, false);
+
+ if (drvdata->dmamuxs)
+ fsl_edma_chan_mux(fsl_chan, 0, false);
}
ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
@@ -344,12 +558,25 @@ static int fsl_edma_probe(struct platform_device *pdev)
fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
+
+ if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) {
+ fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+ fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
+ }
+
fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV)
+ fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV);
+
+ fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ?
+ DMAENGINE_ALIGN_64_BYTES :
+ DMAENGINE_ALIGN_32_BYTES;
- fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES;
/* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff);
+ fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+
platform_set_drvdata(pdev, fsl_edma);
ret = dma_async_device_register(&fsl_edma->dma_dev);
@@ -359,7 +586,9 @@ static int fsl_edma_probe(struct platform_device *pdev)
return ret;
}
- ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
+ ret = of_dma_controller_register(np,
+ drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate,
+ fsl_edma);
if (ret) {
dev_err(&pdev->dev,
"Can't register Freescale eDMA of_dma. (%d)\n", ret);
@@ -368,7 +597,8 @@ static int fsl_edma_probe(struct platform_device *pdev)
}
/* enable round robin arbitration */
- edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
+ if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
+ edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 12/12] dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
` (10 preceding siblings ...)
2023-06-01 14:41 ` [PATCH v3 11/12] dmaengine: fsl-edma: integrate v3 support Frank Li
@ 2023-06-01 14:41 ` Frank Li
2023-06-02 8:30 ` Krzysztof Kozlowski
11 siblings, 1 reply; 16+ messages in thread
From: Frank Li @ 2023-06-01 14:41 UTC (permalink / raw)
To: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
Extend Freescale eDMA driver bindings to support eDMA3 IP blocks in
i.MX8QM and i.MX8QXP SoCs. In i.MX93, both eDMA3 and eDMA4 are now.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../devicetree/bindings/dma/fsl,edma.yaml | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
index 5fd8fc604261..ec0fe8735ec7 100644
--- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml
+++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
@@ -21,6 +21,10 @@ properties:
- enum:
- fsl,vf610-edma
- fsl,imx7ulp-edma
+ - fsl,imx8qm-edma
+ - fsl,imx8qm-adma
+ - fsl,imx93-edma3
+ - fsl,imx93-edma4
- items:
- const: fsl,ls1028a-edma
- const: fsl,vf610-edma
@@ -49,6 +53,10 @@ properties:
clock-names:
maxItems: 2
+ fsl,channel-mask:
+ $ref: /schemas/types.yaml#/definitions/uint64
+ description: A bitmask lets you skip certain channel.
+
big-endian:
description: |
If present registers and hardware scatter/gather descriptors of the
@@ -101,6 +109,26 @@ allOf:
reg:
maxItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ anyOf:
+ - const: fsl,imx8qm-edma
+ - const: fsl,imx8qm-adma
+ - const: fsl,imx93-edma3
+ - const: fsl,imx93-edma4
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ interrupts:
+ minItems: 1
+ maxItems: 64
+ interrupt-names:
+ minItems: 1
+ maxItems: 64
+
unevaluatedProperties: false
examples:
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 12/12] dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string
2023-06-01 14:41 ` [PATCH v3 12/12] dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string Frank Li
@ 2023-06-02 8:30 ` Krzysztof Kozlowski
0 siblings, 0 replies; 16+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-02 8:30 UTC (permalink / raw)
To: Frank Li, vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine,
devicetree, linux-kernel, peng.fan, joy.zou, shenwei.wang, imx
On 01/06/2023 16:41, Frank Li wrote:
> Extend Freescale eDMA driver bindings to support eDMA3 IP blocks in
> i.MX8QM and i.MX8QXP SoCs. In i.MX93, both eDMA3 and eDMA4 are now.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../devicetree/bindings/dma/fsl,edma.yaml | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> index 5fd8fc604261..ec0fe8735ec7 100644
> --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> @@ -21,6 +21,10 @@ properties:
> - enum:
> - fsl,vf610-edma
> - fsl,imx7ulp-edma
> + - fsl,imx8qm-edma
> + - fsl,imx8qm-adma
> + - fsl,imx93-edma3
> + - fsl,imx93-edma4
> - items:
> - const: fsl,ls1028a-edma
> - const: fsl,vf610-edma
> @@ -49,6 +53,10 @@ properties:
> clock-names:
> maxItems: 2
>
> + fsl,channel-mask:
> + $ref: /schemas/types.yaml#/definitions/uint64
> + description: A bitmask lets you skip certain channel.
There is already a property for this - included in your binding:
dma-channel-mask. Use this one.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v3 11/12] dmaengine: fsl-edma: integrate v3 support
2023-06-01 14:41 ` [PATCH v3 11/12] dmaengine: fsl-edma: integrate v3 support Frank Li
@ 2023-06-02 9:41 ` Joy Zou
2023-06-02 21:39 ` Frank Li
0 siblings, 1 reply; 16+ messages in thread
From: Joy Zou @ 2023-06-02 9:41 UTC (permalink / raw)
To: Frank Li, vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine,
devicetree, linux-kernel, Peng Fan, Shenwei Wang, imx
Cc: Peng Fan, Aisheng Dong
> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: 2023年6月1日 22:41
> To: vkoul@kernel.org; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> dmaengine@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; Peng Fan <peng.fan@nxp.com>; Joy Zou
> <joy.zou@nxp.com>; Shenwei Wang <shenwei.wang@nxp.com>;
> imx@lists.linux.dev
> Subject: [PATCH v3 11/12] dmaengine: fsl-edma: integrate v3 support
>
> Significant alterations have been made to the EDMA v3's register layout.
> Now, each channel possesses a separate address space, encapsulating all
> channel-related controls and statuses, including IRQs. There are changes in bit
> position definitions as well. However, the fundamental control flow remains
> analogous to the previous versions.
>
> EDMA v3 was utilized in imx8qm, imx93, and will be in forthcoming chips.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/dma/fsl-edma-common.c | 158 +++++++++++++++++++---
> drivers/dma/fsl-edma-common.h | 75 ++++++++++
> drivers/dma/fsl-edma-main.c | 248
> ++++++++++++++++++++++++++++++++--
> 3 files changed, 456 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/dma/fsl-edma-common.c
> b/drivers/dma/fsl-edma-common.c index eead6a4765f7..dbfc9d80e2ed
> 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -7,6 +7,8 @@
> #include <linux/module.h>
> #include <linux/slab.h>
> #include <linux/dma-mapping.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/pm_domain.h>
>
> #include "fsl-edma-common.h"
>
> @@ -66,11 +68,47 @@ void fsl_edma_tx_chan_handler(struct fsl_edma_chan
> *fsl_chan)
> spin_unlock(&fsl_chan->vchan.lock);
> }
>
> +static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan) {
> + u32 val, flags;
> +
> + flags = fsl_edma_drvflags(fsl_chan);
> + val = edma_readl_chreg(fsl_chan, ch_sbr);
> + /* Remote/local swapped wrongly on iMX8 QM Audio edma */
> + if (flags & FSL_EDMA_DRV_QUIRK_SWAPPED) {
> + if (!fsl_chan->is_rxchan)
> + val |= EDMA_V3_CH_SBR_RD;
> + else
> + val |= EDMA_V3_CH_SBR_WR;
> + } else {
> + if (fsl_chan->is_rxchan)
> + val |= EDMA_V3_CH_SBR_RD;
> + else
> + val |= EDMA_V3_CH_SBR_WR;
> + }
> +
> + if (fsl_chan->is_remote)
> + val &= ~(EDMA_V3_CH_SBR_RD | EDMA_V3_CH_SBR_WR);
> +
> + edma_writel_chreg(fsl_chan, val, ch_sbr);
> +
> + if ((flags & (FSL_EDMA_DRV_AXI | FSL_EDMA_DRV_HAS_CHMUX)) &&
> + fsl_chan->srcid && !edma_readl_chreg(fsl_chan, ch_mux))
> + edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
> +
> + val = edma_readl_chreg(fsl_chan, ch_csr);
> + val |= EDMA_V3_CH_CSR_ERQ;
> + edma_writel_chreg(fsl_chan, val, ch_csr); }
> +
> static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) {
> struct edma_regs *regs = &fsl_chan->edma->regs;
> u32 ch = fsl_chan->vchan.chan.chan_id;
>
> + if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG)
> + return fsl_edma3_enable_request(fsl_chan);
> +
> if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {
> edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
> edma_writeb(fsl_chan->edma, ch, regs->serq); @@ -83,11 +121,29
> @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
> }
> }
>
> +static void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan) {
> + u32 val = edma_readl_chreg(fsl_chan, ch_csr);
> + u32 flags;
> +
> + flags = fsl_edma_drvflags(fsl_chan);
> +
> + if ((flags & (FSL_EDMA_DRV_AXI | FSL_EDMA_DRV_HAS_CHMUX)) &&
> + fsl_chan->srcid)
> + edma_writel_chreg(fsl_chan, 0, ch_mux);
> +
> + val &= ~EDMA_V3_CH_CSR_ERQ;
> + edma_writel_chreg(fsl_chan, val, ch_csr); }
> +
> void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan) {
> struct edma_regs *regs = &fsl_chan->edma->regs;
> u32 ch = fsl_chan->vchan.chan.chan_id;
>
> + if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG)
> + return fsl_edma3_disable_request(fsl_chan);
> +
> if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {
> edma_writeb(fsl_chan->edma, ch, regs->cerq);
> edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
> @@ -186,6 +242,10 @@ int fsl_edma_terminate_all(struct dma_chan *chan)
> vchan_get_all_descriptors(&fsl_chan->vchan, &head);
> spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
> vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
> +
> + if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_PD)
> + pm_runtime_allow(fsl_chan->pd_dev);
> +
> return 0;
> }
>
> @@ -286,12 +346,16 @@ static size_t fsl_edma_desc_residue(struct
> fsl_edma_chan *fsl_chan,
> enum dma_transfer_direction dir = edesc->dirn;
> dma_addr_t cur_addr, dma_addr;
> size_t len, size;
> + u32 nbytes = 0;
> int i;
>
> /* calculate the total size in this desc */
> - for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++)
> - len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
> - * le16_to_cpu(edesc->tcd[i].vtcd->biter);
> + for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) {
> + nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes);
> + if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE |
> EDMA_V3_TCD_NBYTES_SMLOE))
> + nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes);
> + len += nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter);
> + }
>
> if (!in_progress)
> return len;
> @@ -303,8 +367,12 @@ static size_t fsl_edma_desc_residue(struct
> fsl_edma_chan *fsl_chan,
>
> /* figure out the finished and calculate the residue */
> for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
> - size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
> - * le16_to_cpu(edesc->tcd[i].vtcd->biter);
> + nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes);
> + if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE |
> EDMA_V3_TCD_NBYTES_SMLOE))
> + nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes);
> +
> + size = nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter);
> +
> if (dir == DMA_MEM_TO_DEV)
> dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr);
> else
> @@ -389,13 +457,15 @@ static void fsl_edma_set_tcd_regs(struct
> fsl_edma_chan *fsl_chan, }
>
> static inline
> -void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
> +void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
> + struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
> u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
> u16 biter, u16 doff, u32 dlast_sga, bool major_int,
> bool disable_req, bool enable_sg) {
> + struct dma_slave_config *cfg = &fsl_chan->cfg;
> u16 csr = 0;
> -
> + u32 burst;
> /*
> * eDMA hardware SGs require the TCDs to be stored in little
> * endian format irrespective of the register endian model.
> @@ -409,6 +479,21 @@ void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd,
> u32 src, u32 dst,
>
> tcd->soff = cpu_to_le16(soff);
>
> + if (fsl_chan->is_multi_fifo) {
> + /* set mloff to support multiple fifo */
> + burst = cfg->direction == DMA_DEV_TO_MEM ?
> + cfg->src_addr_width : cfg->dst_addr_width;
> + nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-(burst * 4));
> + /* enable DMLOE/SMLOE */
> + if (cfg->direction == DMA_MEM_TO_DEV) {
> + nbytes |= EDMA_V3_TCD_NBYTES_DMLOE;
> + nbytes &= ~EDMA_V3_TCD_NBYTES_SMLOE;
> + } else {
> + nbytes |= EDMA_V3_TCD_NBYTES_SMLOE;
> + nbytes &= ~EDMA_V3_TCD_NBYTES_DMLOE;
> + }
> + }
> +
> tcd->nbytes = cpu_to_le32(nbytes);
> tcd->slast = cpu_to_le32(slast);
>
> @@ -427,6 +512,12 @@ void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd,
> u32 src, u32 dst,
> if (enable_sg)
> csr |= EDMA_TCD_CSR_E_SG;
>
> + if (fsl_chan->is_rxchan)
> + csr |= EDMA_TCD_CSR_ACTIVE;
> +
> + if (fsl_chan->is_sw)
> + csr |= EDMA_TCD_CSR_START;
> +
> tcd->csr = cpu_to_le16(csr);
> }
>
> @@ -466,6 +557,7 @@ struct dma_async_tx_descriptor
> *fsl_edma_prep_dma_cyclic(
> struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
> struct fsl_edma_desc *fsl_desc;
> dma_addr_t dma_buf_next;
> + bool major_int = true;
> int sg_len, i;
> u32 src_addr, dst_addr, last_sg, nbytes;
> u16 soff, doff, iter;
> @@ -509,17 +601,23 @@ struct dma_async_tx_descriptor
> *fsl_edma_prep_dma_cyclic(
> src_addr = dma_buf_next;
> dst_addr = fsl_chan->dma_dev_addr;
> soff = fsl_chan->cfg.dst_addr_width;
> - doff = 0;
> - } else {
> + doff = fsl_chan->is_multi_fifo ? 4 : 0;
> + } else if (direction == DMA_DEV_TO_MEM) {
> src_addr = fsl_chan->dma_dev_addr;
> dst_addr = dma_buf_next;
> - soff = 0;
> + soff = fsl_chan->is_multi_fifo ? 4 : 0;
> doff = fsl_chan->cfg.src_addr_width;
> + } else {
> + /* DMA_DEV_TO_DEV */
> + src_addr = fsl_chan->cfg.src_addr;
> + dst_addr = fsl_chan->cfg.dst_addr;
> + soff = doff = 0;
> + major_int = false;
> }
>
> - fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
> + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr,
> +dst_addr,
> fsl_chan->attr, soff, nbytes, 0, iter,
> - iter, doff, last_sg, true, false, true);
> + iter, doff, last_sg, major_int, false, true);
> dma_buf_next += period_len;
> }
>
> @@ -568,23 +666,51 @@ struct dma_async_tx_descriptor
> *fsl_edma_prep_slave_sg(
> dst_addr = fsl_chan->dma_dev_addr;
> soff = fsl_chan->cfg.dst_addr_width;
> doff = 0;
> - } else {
> + } else if (direction == DMA_DEV_TO_MEM) {
> src_addr = fsl_chan->dma_dev_addr;
> dst_addr = sg_dma_address(sg);
> soff = 0;
> doff = fsl_chan->cfg.src_addr_width;
> + } else {
> + /* DMA_DEV_TO_DEV */
> + src_addr = fsl_chan->cfg.src_addr;
> + dst_addr = fsl_chan->cfg.dst_addr;
> + soff = 0;
> + doff = 0;
> }
>
> + /*
> + * Choose the suitable burst length if sg_dma_len is not
> + * multiple of burst length so that the whole transfer length is
> + * multiple of minor loop(burst length).
> + */
> + if (sg_dma_len(sg) % nbytes) {
> + u32 width = (direction == DMA_DEV_TO_MEM) ? doff : soff;
> + u32 burst = (direction == DMA_DEV_TO_MEM) ?
> + fsl_chan->cfg.src_maxburst :
> + fsl_chan->cfg.dst_maxburst;
> + int j;
> +
> + for (j = burst; j > 1; j--) {
> + if (!(sg_dma_len(sg) % (j * width))) {
> + nbytes = j * width;
> + break;
> + }
> + }
> + /* Set burst size as 1 if there's no suitable one */
> + if (j == 1)
> + nbytes = width;
> + }
> iter = sg_dma_len(sg) / nbytes;
> if (i < sg_len - 1) {
> last_sg = fsl_desc->tcd[(i + 1)].ptcd;
> - fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
> + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr,
> dst_addr, fsl_chan->attr, soff,
> nbytes, 0, iter, iter, doff, last_sg,
> false, false, true);
> } else {
> last_sg = 0;
> - fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
> + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr,
> dst_addr, fsl_chan->attr, soff,
> nbytes, 0, iter, iter, doff, last_sg,
> true, true, false);
> @@ -609,7 +735,7 @@ struct dma_async_tx_descriptor
> *fsl_edma_prep_memcpy(struct dma_chan *chan,
> fsl_chan->is_sw = true;
>
> /* To match with copy_align and max_seg_size so 1 tcd is enough */
> - fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
> + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
> fsl_edma_get_tcd_attr(DMA_SLAVE_BUSWIDTH_32_BYTES),
> 32, len, 0, 1, 1, 32, 0, true, true, false);
>
> diff --git a/drivers/dma/fsl-edma-common.h
> b/drivers/dma/fsl-edma-common.h index cfc41915eaa1..d4ac2644654e
> 100644
> --- a/drivers/dma/fsl-edma-common.h
> +++ b/drivers/dma/fsl-edma-common.h
> @@ -42,6 +42,11 @@
> #define EDMA_TCD_CSR_ACTIVE BIT(6)
> #define EDMA_TCD_CSR_DONE BIT(7)
>
> +#define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))
> +#define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10)
> +#define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30)
> +#define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31)
> +
> #define EDMAMUX_CHCFG_DIS 0x0
> #define EDMAMUX_CHCFG_ENBL 0x80
> #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
> @@ -54,6 +59,15 @@
> BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
> BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
> BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
> +
> +#define EDMA_V3_CH_SBR_RD BIT(22)
> +#define EDMA_V3_CH_SBR_WR BIT(21)
> +#define EDMA_V3_CH_CSR_ERQ BIT(0)
> +#define EDMA_V3_CH_CSR_EARQ BIT(1)
> +#define EDMA_V3_CH_CSR_EEI BIT(2)
> +#define EDMA_V3_CH_CSR_DONE BIT(30)
> +#define EDMA_V3_CH_CSR_ACTIVE BIT(31)
> +
> enum fsl_edma_pm_state {
> RUNNING = 0,
> SUSPENDED,
> @@ -73,6 +87,18 @@ struct fsl_edma_hw_tcd {
> __le16 biter;
> };
>
> +struct fsl_edma3_ch_reg {
> + __le32 ch_csr;
> + __le32 ch_es;
> + __le32 ch_int;
> + __le32 ch_sbr;
> + __le32 ch_pri;
> + __le32 ch_mux;
> + __le32 ch_mattr; /* edma4, reserved for edma3 */
> + __le32 ch_reserved;
> + struct fsl_edma_hw_tcd tcd;
> +} __packed;
> +
> /*
> * These are iomem pointers, for both v32 and v64.
> */
> @@ -119,6 +145,18 @@ struct fsl_edma_chan {
> enum dma_data_direction dma_dir;
> char chan_name[32];
> struct fsl_edma_hw_tcd __iomem *tcd;
> + u32 real_count;
> + struct work_struct issue_worker;
> + struct platform_device *pdev;
> + struct device *pd_dev;
> + u32 srcid;
> + struct clk *clk;
> + int priority;
> + int hw_chanid;
> + int txirq;
> + bool is_rxchan;
> + bool is_remote;
> + bool is_multi_fifo;
> };
>
> struct fsl_edma_desc {
> @@ -135,8 +173,30 @@ struct fsl_edma_desc {
> #define FSL_EDMA_DRV_CONFIG32 BIT(2)
> #define FSL_EDMA_DRV_WRAP_IO BIT(3)
> #define FSL_EDMA_DRV_EDMA64 BIT(4)
> +#define FSL_EDMA_DRV_HAS_PD BIT(5)
> +#define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
> +#define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
> +/* imx8 QM audio edma remote local swapped */
> +#define FSL_EDMA_DRV_QUIRK_SWAPPED BIT(8)
> +/* imx93 edma4 is AXI master */
> +#define FSL_EDMA_DRV_AXI BIT(9)
> +/* control and status register is in tcd address space, edma3 reg layout */
> +#define FSL_EDMA_DRV_SPLIT_REG BIT(10)
> +#define FSL_EDMA_DRV_BUS_8BYTE BIT(11)
> +#define FSL_EDMA_DRV_DEV_TO_DEV BIT(12)
> +#define FSL_EDMA_DRV_ALIGN_64BYTE BIT(13)
> +
> +#define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \
> + FSL_EDMA_DRV_BUS_8BYTE | \
> + FSL_EDMA_DRV_DEV_TO_DEV | \
> + FSL_EDMA_DRV_ALIGN_64BYTE)
> +
> +#define FSL_EDMA_DRV_EDMA4 (FSL_EDMA_DRV_EDMA3 | \
> + FSL_EDMA_DRV_AXI)
> struct fsl_edma_drvdata {
> u32 dmamuxs;
> + u32 chreg_off;
> + u32 chreg_space_sz;
> u32 flags;
> int (*setup_irq)(struct platform_device *pdev,
> struct fsl_edma_engine *fsl_edma); @@ -148,6
> +208,7 @@ struct fsl_edma_engine {
> void __iomem *muxbase[DMAMUX_NR];
> struct clk *muxclk[DMAMUX_NR];
> struct clk *dmaclk;
> + struct clk *chclk;
> struct mutex fsl_edma_mutex;
> const struct fsl_edma_drvdata *drvdata;
> u32 n_chans;
> @@ -155,6 +216,7 @@ struct fsl_edma_engine {
> int errirq;
> bool big_endian;
> struct edma_regs regs;
> + u64 chan_masked;
> struct fsl_edma_chan chans[];
> };
>
> @@ -168,6 +230,14 @@ struct fsl_edma_engine {
> edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \
> edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name))
>
> +#define edma_readl_chreg(chan, __name) \
> + edma_readl(chan->edma, \
> + (void __iomem *)&(container_of(chan->tcd, struct
> fsl_edma3_ch_reg,
> +tcd)->__name))
> +
> +#define edma_writel_chreg(chan, val, __name) \
> + edma_writel(chan->edma, val, \
> + (void __iomem *)&(container_of(chan->tcd, struct
> fsl_edma3_ch_reg,
> +tcd)->__name))
> +
> /*
> * R/W functions for big- or little-endian registers:
> * The eDMA controller's endian is independent of the CPU core's endian.
> @@ -224,6 +294,11 @@ static inline struct fsl_edma_chan
> *to_fsl_edma_chan(struct dma_chan *chan)
> return container_of(chan, struct fsl_edma_chan, vchan.chan); }
>
> +static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan) {
> + return fsl_chan->edma->drvdata->flags; }
> +
> static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc
> *vd) {
> return container_of(vd, struct fsl_edma_desc, vdesc); diff --git
> a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index
> e5f42dd974e8..33339ade79a4 100644
> --- a/drivers/dma/fsl-edma-main.c
> +++ b/drivers/dma/fsl-edma-main.c
> @@ -18,9 +18,15 @@
> #include <linux/of_irq.h>
> #include <linux/of_dma.h>
> #include <linux/dma-mapping.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/pm_domain.h>
>
> #include "fsl-edma-common.h"
>
> +#define ARGS_RX BIT(0)
> +#define ARGS_REMOTE BIT(1)
> +#define ARGS_MULTI_FIFO BIT(2)
> +
> static void fsl_edma_synchronize(struct dma_chan *chan) {
> struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); @@ -47,6
> +53,22 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
> return IRQ_HANDLED;
> }
>
> +static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) {
> + struct fsl_edma_chan *fsl_chan = dev_id;
> + unsigned int intr;
> +
> + intr = edma_readl_chreg(fsl_chan, ch_int);
> + if (!intr)
> + return IRQ_HANDLED;
> +
> + edma_writel_chreg(fsl_chan, 1, ch_int);
> +
> + fsl_edma_tx_chan_handler(fsl_chan);
> +
> + return IRQ_HANDLED;
> +}
> +
> static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) {
> struct fsl_edma_engine *fsl_edma = dev_id; @@ -108,6 +130,52 @@
> static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
> return NULL;
> }
>
> +static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
> + struct of_dma *ofdma)
> +{
> + struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
> + struct dma_chan *chan, *_chan;
> + struct fsl_edma_chan *fsl_chan;
> + int i;
> +
> + if (dma_spec->args_count != 3)
> + return NULL;
> +
> + mutex_lock(&fsl_edma->fsl_edma_mutex);
> + list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
> + device_node) {
> +
> + if (chan->client_count)
> + continue;
> +
> + fsl_chan = to_fsl_edma_chan(chan);
> + i = fsl_chan - fsl_edma->chans;
> + if (fsl_edma->drvdata->dmamuxs == 0 && i == dma_spec->args[0]) {
> + chan = dma_get_slave_channel(chan);
> + chan->device->privatecnt++;
> + fsl_chan->priority = dma_spec->args[1];
> + fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
> + fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
> + fsl_chan->is_multi_fifo = dma_spec->args[2] &
> ARGS_MULTI_FIFO;
> + mutex_unlock(&fsl_edma->fsl_edma_mutex);
> + return chan;
> + } else if ((fsl_edma->drvdata->dmamuxs ||
> + (fsl_edma->drvdata->flags & FSL_EDMA_DRV_AXI))
> && !fsl_chan->srcid) {
> + chan = dma_get_slave_channel(chan);
> + chan->device->privatecnt++;
> + fsl_chan->priority = dma_spec->args[1];
> + fsl_chan->srcid = dma_spec->args[0];
> + fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
> + fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
> + fsl_chan->is_multi_fifo = dma_spec->args[2] &
> ARGS_MULTI_FIFO;
> + mutex_unlock(&fsl_edma->fsl_edma_mutex);
> + return chan;
> + }
> + }
> + mutex_unlock(&fsl_edma->fsl_edma_mutex);
> + return NULL;
> +}
> +
> static int
> fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine
> *fsl_edma) { @@ -149,6 +217,37 @@ fsl_edma_irq_init(struct
> platform_device *pdev, struct fsl_edma_engine *fsl_edma
> return 0;
> }
>
> +static int fsl_edma3_irq_init(struct platform_device *pdev, struct
> +fsl_edma_engine *fsl_edma) {
> + int ret;
> + int i;
> +
> + for (i = 0; i < fsl_edma->n_chans; i++) {
> +
> + struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
> +
> + if (fsl_edma->chan_masked & BIT(i))
> + continue;
> +
> + /* request channel irq */
> + fsl_chan->txirq = platform_get_irq(pdev, i);
> + if (fsl_chan->txirq < 0) {
> + dev_err(&pdev->dev, "Can't get chan %d's irq.\n", i);
> + return -EINVAL;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
> + fsl_edma3_tx_handler, IRQF_SHARED,
> + fsl_chan->chan_name, fsl_chan);
> + if (ret) {
> + dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i);
> + return -EINVAL;
> + }
> + }
> +
> + return 0;
> +}
> +
> static int
> fsl_edma2_irq_init(struct platform_device *pdev,
> struct fsl_edma_engine *fsl_edma)
> @@ -202,29 +301,115 @@ static void fsl_disable_clocks(struct
> fsl_edma_engine *fsl_edma, int nr_clocks)
>
> static struct fsl_edma_drvdata vf610_data = {
> .dmamuxs = DMAMUX_NR | FSL_EDMA_DRV_WRAP_IO,
> + .dmamuxs = DMAMUX_NR,
> + .chreg_off = EDMA_TCD,
> + .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
> .setup_irq = fsl_edma_irq_init,
> };
>
> static struct fsl_edma_drvdata ls1028a_data = {
> .dmamuxs = DMAMUX_NR,
> .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
> + .chreg_off = EDMA_TCD,
> + .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
> .setup_irq = fsl_edma_irq_init,
> };
>
> static struct fsl_edma_drvdata imx7ulp_data = {
> .dmamuxs = 1,
> + .chreg_off = EDMA_TCD,
> + .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
> .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
> .setup_irq = fsl_edma2_irq_init,
> };
>
> +static struct fsl_edma_drvdata imx8qm_data = {
> + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_PD
> + | FSL_EDMA_DRV_EDMA3,
> + .chreg_space_sz = 0x10000,
> + .chreg_off = 0x10000,
> + .setup_irq = fsl_edma3_irq_init,
> +};
Hi frank,
There are many dma controllers in imx8qm. But not all dma controllers support ch-mux.
In addition, Imx93 edma v3 also doesn't support ch-mux.
You can confirm with RM. Can we use the dts node property instead of drvdata flags?
BR
Joy Zou
> +
> +static struct fsl_edma_drvdata imx8qm_audio_data = {
> + .flags = FSL_EDMA_DRV_HAS_CHMUX |
> FSL_EDMA_DRV_QUIRK_SWAPPED |
> + FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
> + .chreg_space_sz = 0x10000,
> + .chreg_off = 0x10000,
> + .setup_irq = fsl_edma3_irq_init,
> +};
> +
> +static struct fsl_edma_drvdata imx93_data3 = {
> + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK
> + | FSL_EDMA_DRV_EDMA3,
> + .chreg_space_sz = 0x10000,
> + .chreg_off = 0x10000,
> + .setup_irq = fsl_edma3_irq_init,
> +};
> +
> +static struct fsl_edma_drvdata imx93_data4 = {
> + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK
> + | FSL_EDMA_DRV_EDMA4,
> + .chreg_space_sz = 0x8000,
> + .chreg_off = 0x10000,
> + .setup_irq = fsl_edma3_irq_init,
> +};
> +
> static const struct of_device_id fsl_edma_dt_ids[] = {
> { .compatible = "fsl,vf610-edma", .data = &vf610_data},
> { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
> { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
> + { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
> + { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data},
> + { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
> + { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
> { /* sentinel */ }
> };
> +
> MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
>
> +static int fsl_edma3_attach_pd(struct platform_device *pdev, struct
> +fsl_edma_engine *fsl_edma) {
> + struct fsl_edma_chan *fsl_chan;
> + struct device_link *link;
> + struct device *pd_chan;
> + struct device *dev;
> + int i;
> +
> + dev = &pdev->dev;
> +
> + for (i = 0; i < fsl_edma->n_chans; i++) {
> + if (fsl_edma->chan_masked & BIT(i))
> + continue;
> +
> + fsl_chan = &fsl_edma->chans[i];
> +
> + pd_chan = dev_pm_domain_attach_by_id(dev, i);
> + if (IS_ERR_OR_NULL(pd_chan)) {
> + dev_err(dev, "Failed attach pd %d\n", i);
> + return -EINVAL;
> + }
> +
> + link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
> + DL_FLAG_PM_RUNTIME |
> + DL_FLAG_RPM_ACTIVE);
> + if (IS_ERR(link)) {
> + dev_err(dev, "Failed to add device_link to %d: %ld\n", i,
> + PTR_ERR(link));
> + return -EINVAL;
> + }
> +
> + fsl_chan->pd_dev = pd_chan;
> +
> + pm_runtime_use_autosuspend(fsl_chan->pd_dev);
> + pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200);
> + pm_runtime_set_active(fsl_chan->pd_dev);
> + //pm_runtime_put_sync_suspend(fsl_chan->pd_dev);
> + }
> +
> + return 0;
> +}
> +
> static int fsl_edma_probe(struct platform_device *pdev) {
> const struct of_device_id *of_id =
> @@ -263,8 +448,10 @@ static int fsl_edma_probe(struct platform_device
> *pdev)
> if (IS_ERR(fsl_edma->membase))
> return PTR_ERR(fsl_edma->membase);
>
> - fsl_edma_setup_regs(fsl_edma);
> - regs = &fsl_edma->regs;
> + if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) {
> + fsl_edma_setup_regs(fsl_edma);
> + regs = &fsl_edma->regs;
> + }
>
> if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
> fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
> @@ -274,6 +461,17 @@ static int fsl_edma_probe(struct platform_device
> *pdev)
> }
> }
>
> + if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
> + fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp");
> + if (IS_ERR(fsl_edma->chclk)) {
> + dev_err(&pdev->dev, "Missing MP block clock.\n");
> + return PTR_ERR(fsl_edma->chclk);
> + }
> + }
> +
> + if (of_property_read_u64(np, "fsl,channel-mask",
> &fsl_edma->chan_masked))
> + fsl_edma->chan_masked = 0;
> +
> for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
> char clkname[32];
>
> @@ -296,9 +494,18 @@ static int fsl_edma_probe(struct platform_device
> *pdev)
>
> fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
>
> + if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) {
> + ret = fsl_edma3_attach_pd(pdev, fsl_edma);
> + if (ret)
> + return ret;
> + }
> +
> INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
> for (i = 0; i < fsl_edma->n_chans; i++) {
> - struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
> + fsl_chan = &fsl_edma->chans[i];
> +
> + if (fsl_edma->chan_masked & BIT(i))
> + continue;
>
> snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name),
> "%s-CH%02d",
> dev_name(&pdev->dev), i);
> @@ -309,12 +516,19 @@ static int fsl_edma_probe(struct platform_device
> *pdev)
> fsl_chan->idle = true;
> fsl_chan->dma_dir = DMA_NONE;
> fsl_chan->vchan.desc_free = fsl_edma_free_desc;
> - fsl_chan->tcd = fsl_edma->membase + EDMA_TCD
> - + i * sizeof(struct fsl_edma_hw_tcd);
> +
> + len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ?
> + offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
> + fsl_chan->tcd = fsl_edma->membase
> + + i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
> +
> + fsl_chan->pdev = pdev;
> vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
>
> edma_write_tcdreg(fsl_chan, 0, csr);
> - fsl_edma_chan_mux(fsl_chan, 0, false);
> +
> + if (drvdata->dmamuxs)
> + fsl_edma_chan_mux(fsl_chan, 0, false);
> }
>
> ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); @@ -344,12
> +558,25 @@ static int fsl_edma_probe(struct platform_device *pdev)
>
> fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
> fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
> +
> + if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) {
> + fsl_edma->dma_dev.src_addr_widths |=
> BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
> + fsl_edma->dma_dev.dst_addr_widths |=
> BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
> + }
> +
> fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) |
> BIT(DMA_MEM_TO_DEV);
> + if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV)
> + fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV);
> +
> + fsl_edma->dma_dev.copy_align = drvdata->flags &
> FSL_EDMA_DRV_ALIGN_64BYTE ?
> + DMAENGINE_ALIGN_64_BYTES :
> + DMAENGINE_ALIGN_32_BYTES;
>
> - fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES;
> /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
> dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff);
>
> + fsl_edma->dma_dev.residue_granularity =
> +DMA_RESIDUE_GRANULARITY_SEGMENT;
> +
> platform_set_drvdata(pdev, fsl_edma);
>
> ret = dma_async_device_register(&fsl_edma->dma_dev);
> @@ -359,7 +586,9 @@ static int fsl_edma_probe(struct platform_device
> *pdev)
> return ret;
> }
>
> - ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
> + ret = of_dma_controller_register(np,
> + drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate :
> fsl_edma_xlate,
> + fsl_edma);
> if (ret) {
> dev_err(&pdev->dev,
> "Can't register Freescale eDMA of_dma. (%d)\n", ret); @@
> -368,7 +597,8 @@ static int fsl_edma_probe(struct platform_device *pdev)
> }
>
> /* enable round robin arbitration */
> - edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
> + if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
> + edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
>
> return 0;
> }
> --
> 2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 11/12] dmaengine: fsl-edma: integrate v3 support
2023-06-02 9:41 ` Joy Zou
@ 2023-06-02 21:39 ` Frank Li
0 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2023-06-02 21:39 UTC (permalink / raw)
To: Joy Zou
Cc: vkoul, robh+dt, krzysztof.kozlowski+dt, dmaengine, devicetree,
linux-kernel, Peng Fan, Shenwei Wang, imx, Aisheng Dong
On Fri, Jun 02, 2023 at 09:41:19AM +0000, Joy Zou wrote:
> > + .chreg_off = EDMA_TCD,
> > + .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
> > .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
> > .setup_irq = fsl_edma2_irq_init,
> > };
> >
> > +static struct fsl_edma_drvdata imx8qm_data = {
> > + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_PD
> > + | FSL_EDMA_DRV_EDMA3,
> > + .chreg_space_sz = 0x10000,
> > + .chreg_off = 0x10000,
> > + .setup_irq = fsl_edma3_irq_init,
> > +};
> Hi frank,
> There are many dma controllers in imx8qm. But not all dma controllers support ch-mux.
> In addition, Imx93 edma v3 also doesn't support ch-mux.
> You can confirm with RM. Can we use the dts node property instead of drvdata flags?
> BR
> Joy Zou
> > +
I tested all i.mx8qxp have not ch-mux. did you find any one have ch-mux at imx8qm?
I will remove FSL_EDMA_DRV_HAS_CHMUX at imx8qm and imx93 at next version.
It works just because dmamuxs is 0. ch-mux register have not written at all.
we have compatible string, which are enough to distinguish the difference.
not neccesary to add property for that.
Frank Li
> > --
> > 2.34.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-06-02 21:39 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-01 14:40 [PATCH v3 00/12] dmaengine: edma: add freescale edma v3 support Frank Li
2023-06-01 14:40 ` [PATCH v3 01/12] dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c Frank Li
2023-06-01 14:40 ` [PATCH v3 02/12] dmaengine: fsl-edma: clean up fsl_edma_irq_exit() Frank Li
2023-06-01 14:40 ` [PATCH v3 03/12] dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdata Frank Li
2023-06-01 14:40 ` [PATCH v3 04/12] dmaengine: fsl-edma: Remove enum edma_version Frank Li
2023-06-01 14:41 ` [PATCH v3 05/12] dmaengine: fsl-edma: move common IRQ handler to common.c Frank Li
2023-06-01 14:41 ` [PATCH v3 06/12] dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs() Frank Li
2023-06-01 14:41 ` [PATCH v3 07/12] dmaengine: fsl-edma: refactor using devm_clk_get_enabled Frank Li
2023-06-01 14:41 ` [PATCH v3 08/12] dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function Frank Li
2023-06-01 14:41 ` [PATCH v3 09/12] dmaengine: fsl-edma: refactor chan_name setup and safety Frank Li
2023-06-01 14:41 ` [PATCH v3 10/12] dmaengine: fsl-edma: move tcd into struct fsl_dma_chan Frank Li
2023-06-01 14:41 ` [PATCH v3 11/12] dmaengine: fsl-edma: integrate v3 support Frank Li
2023-06-02 9:41 ` Joy Zou
2023-06-02 21:39 ` Frank Li
2023-06-01 14:41 ` [PATCH v3 12/12] dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string Frank Li
2023-06-02 8:30 ` Krzysztof Kozlowski
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