* [PULL 0/5] loongarch-to-apply queue
@ 2023-06-16 10:01 Song Gao
2023-06-16 10:01 ` [PULL 1/5] hw/loongarch/virt: Add cpu arch_id support Song Gao
` (5 more replies)
0 siblings, 6 replies; 18+ messages in thread
From: Song Gao @ 2023-06-16 10:01 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson
The following changes since commit 7efd65423ab22e6f5890ca08ae40c84d6660242f:
Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu into staging (2023-06-14 05:28:51 +0200)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230616
for you to fetch changes up to 505aa8d8f29b79fcef77563bb4124208badbd8d4:
target/loongarch: Fix CSR.DMW0-3.VSEG check (2023-06-16 17:58:46 +0800)
----------------------------------------------------------------
pull-loongarch-20230616
* Fix CSR.DMW0-3.VSEG check
* Add cpu arch_id support
* Set physical cpuid route for LoongArch ipi device
* Add numa support
* Supplement cpu topology arguments
----------------------------------------------------------------
Jiajie Chen (1):
target/loongarch: Fix CSR.DMW0-3.VSEG check
Tianrui Zhao (4):
hw/loongarch/virt: Add cpu arch_id support
hw/intc: Set physical cpuid route for LoongArch ipi device
hw/loongarch: Add numa support
hw/loongarch: Supplement cpu topology arguments
hw/intc/loongarch_ipi.c | 44 +++++++++++--
hw/loongarch/Kconfig | 1 +
hw/loongarch/acpi-build.c | 78 ++++++++++++++++++-----
hw/loongarch/virt.c | 144 ++++++++++++++++++++++++++++++++++++++----
target/loongarch/cpu.h | 2 +
target/loongarch/tlb_helper.c | 4 +-
6 files changed, 235 insertions(+), 38 deletions(-)
^ permalink raw reply [flat|nested] 18+ messages in thread* [PULL 1/5] hw/loongarch/virt: Add cpu arch_id support 2023-06-16 10:01 [PULL 0/5] loongarch-to-apply queue Song Gao @ 2023-06-16 10:01 ` Song Gao 2023-06-16 10:01 ` [PULL 2/5] hw/intc: Set physical cpuid route for LoongArch ipi device Song Gao ` (4 subsequent siblings) 5 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2023-06-16 10:01 UTC (permalink / raw) To: qemu-devel; +Cc: richard.henderson, Tianrui Zhao From: Tianrui Zhao <zhaotianrui@loongson.cn> With acpi madt table, there is cpu physical coreid, which may be different with logical id in qemu. This patch adds cpu arch_id support, and fill madt table with arch_id. For the present cpu arch_id is still equal to logical id. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230613120552.2471420-2-zhaotianrui@loongson.cn> --- hw/loongarch/acpi-build.c | 20 ++++++++++++++------ hw/loongarch/virt.c | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 46 insertions(+), 8 deletions(-) diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index 8e3ce07367..232344e1c7 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -107,7 +107,9 @@ static void build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) { MachineState *ms = MACHINE(lams); - int i; + MachineClass *mc = MACHINE_GET_CLASS(ms); + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); + int i, arch_id; AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id, .oem_table_id = lams->oem_table_id }; @@ -117,13 +119,15 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) build_append_int_noprefix(table_data, 0, 4); build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */ - for (i = 0; i < ms->smp.cpus; i++) { + for (i = 0; i < arch_ids->len; i++) { /* Processor Core Interrupt Controller Structure */ + arch_id = arch_ids->cpus[i].arch_id; + build_append_int_noprefix(table_data, 17, 1); /* Type */ build_append_int_noprefix(table_data, 15, 1); /* Length */ build_append_int_noprefix(table_data, 1, 1); /* Version */ build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */ - build_append_int_noprefix(table_data, i, 4); /* Core ID */ + build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */ build_append_int_noprefix(table_data, 1, 4); /* Flags */ } @@ -159,9 +163,11 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) static void build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) { - uint64_t i; + int i, arch_id; LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); MachineState *ms = MACHINE(lams); + MachineClass *mc = MACHINE_GET_CLASS(ms); + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id, .oem_table_id = lams->oem_table_id }; @@ -169,13 +175,15 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) build_append_int_noprefix(table_data, 1, 4); /* Reserved */ build_append_int_noprefix(table_data, 0, 8); /* Reserved */ - for (i = 0; i < ms->smp.cpus; ++i) { + for (i = 0; i < arch_ids->len; ++i) { + arch_id = arch_ids->cpus[i].arch_id; + /* Processor Local APIC/SAPIC Affinity Structure */ build_append_int_noprefix(table_data, 0, 1); /* Type */ build_append_int_noprefix(table_data, 16, 1); /* Length */ /* Proximity Domain [7:0] */ build_append_int_noprefix(table_data, 0, 1); - build_append_int_noprefix(table_data, i, 1); /* APIC ID */ + build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */ /* Flags, Table 5-36 */ build_append_int_noprefix(table_data, 1, 4); build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index ceddec1b23..ced5a862f8 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -771,6 +771,9 @@ static void loongarch_init(MachineState *machine) LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); int i; hwaddr fdt_base; + const CPUArchIdList *possible_cpus; + MachineClass *mc = MACHINE_GET_CLASS(machine); + CPUState *cpu; if (!cpu_model) { cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); @@ -787,8 +790,12 @@ static void loongarch_init(MachineState *machine) } create_fdt(lams); /* Init CPUs */ - for (i = 0; i < machine->smp.cpus; i++) { - cpu_create(machine->cpu_type); + + possible_cpus = mc->possible_cpu_arch_ids(machine); + for (i = 0; i < possible_cpus->len; i++) { + cpu = cpu_create(machine->cpu_type); + cpu->cpu_index = i; + machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); } fdt_add_cpu_nodes(lams); /* Add memory region */ @@ -1022,6 +1029,28 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, return NULL; } +static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) +{ + int n; + unsigned int max_cpus = ms->smp.max_cpus; + + if (ms->possible_cpus) { + assert(ms->possible_cpus->len == max_cpus); + return ms->possible_cpus; + } + + ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + + sizeof(CPUArchId) * max_cpus); + ms->possible_cpus->len = max_cpus; + for (n = 0; n < ms->possible_cpus->len; n++) { + ms->possible_cpus->cpus[n].type = ms->cpu_type; + ms->possible_cpus->cpus[n].arch_id = n; + ms->possible_cpus->cpus[n].props.has_core_id = true; + ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores; + } + return ms->possible_cpus; +} + static void loongarch_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1038,6 +1067,7 @@ static void loongarch_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_VIRTIO; mc->default_boot_order = "c"; mc->no_cdrom = 1; + mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; mc->get_hotplug_handler = virt_machine_get_hotplug_handler; mc->default_nic = "virtio-net-pci"; hc->plug = loongarch_machine_device_plug_cb; -- 2.39.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 2/5] hw/intc: Set physical cpuid route for LoongArch ipi device 2023-06-16 10:01 [PULL 0/5] loongarch-to-apply queue Song Gao 2023-06-16 10:01 ` [PULL 1/5] hw/loongarch/virt: Add cpu arch_id support Song Gao @ 2023-06-16 10:01 ` Song Gao 2023-06-16 10:01 ` [PULL 3/5] hw/loongarch: Add numa support Song Gao ` (3 subsequent siblings) 5 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2023-06-16 10:01 UTC (permalink / raw) To: qemu-devel; +Cc: richard.henderson, Tianrui Zhao From: Tianrui Zhao <zhaotianrui@loongson.cn> LoongArch ipi device uses physical cpuid to route to different vcpus rather logical cpuid, and the physical cpuid is the same with cpuid in acpi dsdt and srat table. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230613120552.2471420-3-zhaotianrui@loongson.cn> --- hw/intc/loongarch_ipi.c | 44 ++++++++++++++++++++++++++++++++++------- hw/loongarch/virt.c | 1 + target/loongarch/cpu.h | 2 ++ 3 files changed, 40 insertions(+), 7 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 3e45381652..67858b521c 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -17,6 +17,8 @@ #include "target/loongarch/internals.h" #include "trace.h" +static void loongarch_ipi_writel(void *, hwaddr, uint64_t, unsigned); + static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size) { IPICore *s = opaque; @@ -75,13 +77,42 @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr) data, MEMTXATTRS_UNSPECIFIED, NULL); } +static int archid_cmp(const void *a, const void *b) +{ + CPUArchId *archid_a = (CPUArchId *)a; + CPUArchId *archid_b = (CPUArchId *)b; + + return archid_a->arch_id - archid_b->arch_id; +} + +static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) +{ + CPUArchId apic_id, *found_cpu; + + apic_id.arch_id = id; + found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, + ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), + archid_cmp); + + return found_cpu; +} + +static CPUState *ipi_getcpu(int arch_id) +{ + MachineState *machine = MACHINE(qdev_get_machine()); + CPUArchId *archid; + + archid = find_cpu_by_archid(machine, arch_id); + return CPU(archid->cpu); +} + static void ipi_send(uint64_t val) { uint32_t cpuid; uint8_t vector; - CPULoongArchState *env; CPUState *cs; LoongArchCPU *cpu; + LoongArchIPI *s; cpuid = extract32(val, 16, 10); if (cpuid >= LOONGARCH_MAX_CPUS) { @@ -92,11 +123,10 @@ static void ipi_send(uint64_t val) /* IPI status vector */ vector = extract8(val, 0, 5); - cs = qemu_get_cpu(cpuid); + cs = ipi_getcpu(cpuid); cpu = LOONGARCH_CPU(cs); - env = &cpu->env; - address_space_stl(&env->address_space_iocsr, 0x1008, - BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL); + s = LOONGARCH_IPI(cpu->env.ipistate); + loongarch_ipi_writel(&s->ipi_core, CORE_SET_OFF, BIT(vector), 4); } static void mail_send(uint64_t val) @@ -114,7 +144,7 @@ static void mail_send(uint64_t val) } addr = 0x1020 + (val & 0x1c); - cs = qemu_get_cpu(cpuid); + cs = ipi_getcpu(cpuid); cpu = LOONGARCH_CPU(cs); env = &cpu->env; send_ipi_data(env, val, addr); @@ -135,7 +165,7 @@ static void any_send(uint64_t val) } addr = val & 0xffff; - cs = qemu_get_cpu(cpuid); + cs = ipi_getcpu(cpuid); cpu = LOONGARCH_CPU(cs); env = &cpu->env; send_ipi_data(env, val, addr); diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index ced5a862f8..17bc37bccd 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -617,6 +617,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams) memory_region_add_subregion(&env->system_iocsr, APIC_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), cpu)); + env->ipistate = ipi; } /* diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 1f37e36b7c..b23f38c3d5 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -351,6 +351,8 @@ typedef struct CPUArchState { MemoryRegion iocsr_mem; bool load_elf; uint64_t elf_address; + /* Store ipistate to access from this struct */ + DeviceState *ipistate; #endif } CPULoongArchState; -- 2.39.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 3/5] hw/loongarch: Add numa support 2023-06-16 10:01 [PULL 0/5] loongarch-to-apply queue Song Gao 2023-06-16 10:01 ` [PULL 1/5] hw/loongarch/virt: Add cpu arch_id support Song Gao 2023-06-16 10:01 ` [PULL 2/5] hw/intc: Set physical cpuid route for LoongArch ipi device Song Gao @ 2023-06-16 10:01 ` Song Gao 2024-05-03 12:50 ` Peter Maydell 2023-06-16 10:01 ` [PULL 4/5] hw/loongarch: Supplement cpu topology arguments Song Gao ` (2 subsequent siblings) 5 siblings, 1 reply; 18+ messages in thread From: Song Gao @ 2023-06-16 10:01 UTC (permalink / raw) To: qemu-devel; +Cc: richard.henderson, Tianrui Zhao From: Tianrui Zhao <zhaotianrui@loongson.cn> 1. Implement some functions for LoongArch numa support; 2. Implement fdt_add_memory_node() for fdt; 3. build_srat() fills node_id and adds build numa memory. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230613122613.2471743-1-zhaotianrui@loongson.cn> --- hw/loongarch/Kconfig | 1 + hw/loongarch/acpi-build.c | 60 +++++++++++++++++----- hw/loongarch/virt.c | 102 +++++++++++++++++++++++++++++++++----- 3 files changed, 139 insertions(+), 24 deletions(-) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index eb112af990..1e7c5b43c5 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -21,3 +21,4 @@ config LOONGARCH_VIRT select FW_CFG_DMA select DIMM select PFLASH_CFI01 + select ACPI_HMAT diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index 232344e1c7..f526f3abba 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -34,6 +34,7 @@ #include "sysemu/tpm.h" #include "hw/platform-bus.h" #include "hw/acpi/aml-build.h" +#include "hw/acpi/hmat.h" #define ACPI_BUILD_ALIGN_SIZE 0x1000 #define ACPI_BUILD_TABLE_SIZE 0x20000 @@ -163,11 +164,12 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) static void build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) { - int i, arch_id; + int i, arch_id, node_id; + uint64_t mem_len, mem_base; + int nb_numa_nodes = machine->numa_state->num_nodes; LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); - MachineState *ms = MACHINE(lams); - MachineClass *mc = MACHINE_GET_CLASS(ms); - const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); + MachineClass *mc = MACHINE_GET_CLASS(lams); + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(machine); AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id, .oem_table_id = lams->oem_table_id }; @@ -177,12 +179,13 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) for (i = 0; i < arch_ids->len; ++i) { arch_id = arch_ids->cpus[i].arch_id; + node_id = arch_ids->cpus[i].props.node_id; /* Processor Local APIC/SAPIC Affinity Structure */ build_append_int_noprefix(table_data, 0, 1); /* Type */ build_append_int_noprefix(table_data, 16, 1); /* Length */ /* Proximity Domain [7:0] */ - build_append_int_noprefix(table_data, 0, 1); + build_append_int_noprefix(table_data, node_id, 1); build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */ /* Flags, Table 5-36 */ build_append_int_noprefix(table_data, 1, 4); @@ -192,16 +195,36 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) build_append_int_noprefix(table_data, 0, 4); /* Reserved */ } + /* Node0 */ build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0, MEM_AFFINITY_ENABLED); + mem_base = VIRT_HIGHMEM_BASE; + if (!nb_numa_nodes) { + mem_len = machine->ram_size - VIRT_LOWMEM_SIZE; + } else { + mem_len = machine->numa_state->nodes[0].node_mem - VIRT_LOWMEM_SIZE; + } + if (mem_len) + build_srat_memory(table_data, mem_base, mem_len, 0, MEM_AFFINITY_ENABLED); + + /* Node1 - Nodemax */ + if (nb_numa_nodes) { + mem_base += mem_len; + for (i = 1; i < nb_numa_nodes; ++i) { + if (machine->numa_state->nodes[i].node_mem > 0) { + build_srat_memory(table_data, mem_base, + machine->numa_state->nodes[i].node_mem, i, + MEM_AFFINITY_ENABLED); + mem_base += machine->numa_state->nodes[i].node_mem; + } + } + } - build_srat_memory(table_data, VIRT_HIGHMEM_BASE, machine->ram_size - VIRT_LOWMEM_SIZE, - 0, MEM_AFFINITY_ENABLED); - - if (ms->device_memory) { - build_srat_memory(table_data, ms->device_memory->base, - memory_region_size(&ms->device_memory->mr), - 0, MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); + if (machine->device_memory) { + build_srat_memory(table_data, machine->device_memory->base, + memory_region_size(&machine->device_memory->mr), + nb_numa_nodes - 1, + MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); } acpi_table_end(linker, &table); @@ -417,6 +440,19 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine) acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, machine); + if (machine->numa_state->num_nodes) { + if (machine->numa_state->have_numa_distance) { + acpi_add_table(table_offsets, tables_blob); + build_slit(tables_blob, tables->linker, machine, lams->oem_id, + lams->oem_table_id); + } + if (machine->numa_state->hmat_enabled) { + acpi_add_table(table_offsets, tables_blob); + build_hmat(tables_blob, tables->linker, machine->numa_state, + lams->oem_id, lams->oem_table_id); + } + } + acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg = { diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 17bc37bccd..1d5c764408 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -164,11 +164,16 @@ static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) for (num = smp_cpus - 1; num >= 0; num--) { char *nodename = g_strdup_printf("/cpus/cpu@%d", num); LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); + CPUState *cs = CPU(cpu); qemu_fdt_add_subnode(ms->fdt, nodename); qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", cpu->dtb_compatible); + if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { + qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", + ms->possible_cpus->cpus[cs->cpu_index].props.node_id); + } qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", qemu_fdt_alloc_phandle(ms->fdt)); @@ -280,6 +285,22 @@ static void fdt_add_irqchip_node(LoongArchMachineState *lams) g_free(nodename); } +static void fdt_add_memory_node(MachineState *ms, + uint64_t base, uint64_t size, int node_id) +{ + char *nodename = g_strdup_printf("/memory@%" PRIx64, base); + + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size); + qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); + + if (ms->numa_state && ms->numa_state->num_nodes) { + qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); + } + + g_free(nodename); +} + #define PM_BASE 0x10080000 #define PM_SIZE 0x100 #define PM_CTRL 0x10 @@ -767,14 +788,17 @@ static void loongarch_init(MachineState *machine) const char *cpu_model = machine->cpu_type; ram_addr_t offset = 0; ram_addr_t ram_size = machine->ram_size; - uint64_t highram_size = 0; + uint64_t highram_size = 0, phyAddr = 0; MemoryRegion *address_space_mem = get_system_memory(); LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); + int nb_numa_nodes = machine->numa_state->num_nodes; + NodeInfo *numa_info = machine->numa_state->nodes; int i; hwaddr fdt_base; const CPUArchIdList *possible_cpus; MachineClass *mc = MACHINE_GET_CLASS(machine); CPUState *cpu; + char *ramName = NULL; if (!cpu_model) { cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); @@ -799,17 +823,43 @@ static void loongarch_init(MachineState *machine) machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); } fdt_add_cpu_nodes(lams); - /* Add memory region */ - memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", - machine->ram, 0, 256 * MiB); - memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); - offset += 256 * MiB; - memmap_add_entry(0, 256 * MiB, 1); - highram_size = ram_size - 256 * MiB; - memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", - machine->ram, offset, highram_size); - memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem); - memmap_add_entry(0x90000000, highram_size, 1); + + /* Node0 memory */ + memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); + fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); + memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", + machine->ram, offset, VIRT_LOWMEM_SIZE); + memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); + + offset += VIRT_LOWMEM_SIZE; + if (nb_numa_nodes > 0) { + assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); + highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; + } else { + highram_size = ram_size - VIRT_LOWMEM_SIZE; + } + phyAddr = VIRT_HIGHMEM_BASE; + memmap_add_entry(phyAddr, highram_size, 1); + fdt_add_memory_node(machine, phyAddr, highram_size, 0); + memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", + machine->ram, offset, highram_size); + memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); + + /* Node1 - Nodemax memory */ + offset += highram_size; + phyAddr += highram_size; + + for (i = 1; i < nb_numa_nodes; i++) { + MemoryRegion *nodemem = g_new(MemoryRegion, 1); + ramName = g_strdup_printf("loongarch.node%d.ram", i); + memory_region_init_alias(nodemem, NULL, ramName, machine->ram, + offset, numa_info[i].node_mem); + memory_region_add_subregion(address_space_mem, phyAddr, nodemem); + memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); + fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); + offset += numa_info[i].node_mem; + phyAddr += numa_info[i].node_mem; + } /* initialize device memory address space */ if (machine->ram_size < machine->maxram_size) { @@ -1052,6 +1102,29 @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) return ms->possible_cpus; } +static CpuInstanceProperties +virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); + + assert(cpu_index < possible_cpus->len); + return possible_cpus->cpus[cpu_index].props; +} + +static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) +{ + int64_t nidx = 0; + + if (ms->numa_state->num_nodes) { + nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); + if (ms->numa_state->num_nodes <= nidx) { + nidx = ms->numa_state->num_nodes - 1; + } + } + return nidx; +} + static void loongarch_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1069,6 +1142,11 @@ static void loongarch_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->no_cdrom = 1; mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; + mc->cpu_index_to_instance_props = virt_cpu_index_to_props; + mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; + mc->numa_mem_supported = true; + mc->auto_enable_numa_with_memhp = true; + mc->auto_enable_numa_with_memdev = true; mc->get_hotplug_handler = virt_machine_get_hotplug_handler; mc->default_nic = "virtio-net-pci"; hc->plug = loongarch_machine_device_plug_cb; -- 2.39.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PULL 3/5] hw/loongarch: Add numa support 2023-06-16 10:01 ` [PULL 3/5] hw/loongarch: Add numa support Song Gao @ 2024-05-03 12:50 ` Peter Maydell 2024-05-07 1:29 ` gaosong 0 siblings, 1 reply; 18+ messages in thread From: Peter Maydell @ 2024-05-03 12:50 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel, richard.henderson, Tianrui Zhao On Fri, 16 Jun 2023 at 11:03, Song Gao <gaosong@loongson.cn> wrote: > > From: Tianrui Zhao <zhaotianrui@loongson.cn> > > 1. Implement some functions for LoongArch numa support; > 2. Implement fdt_add_memory_node() for fdt; > 3. build_srat() fills node_id and adds build numa memory. > > Reviewed-by: Song Gao <gaosong@loongson.cn> > Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> > Signed-off-by: Song Gao <gaosong@loongson.cn> > Message-Id: <20230613122613.2471743-1-zhaotianrui@loongson.cn> Hi; Coverity has pointed out a memory leak in this commit (CID 1544773): > @@ -799,17 +823,43 @@ static void loongarch_init(MachineState *machine) > machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); > } > fdt_add_cpu_nodes(lams); > - /* Add memory region */ > - memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", > - machine->ram, 0, 256 * MiB); > - memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); > - offset += 256 * MiB; > - memmap_add_entry(0, 256 * MiB, 1); > - highram_size = ram_size - 256 * MiB; > - memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", > - machine->ram, offset, highram_size); > - memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem); > - memmap_add_entry(0x90000000, highram_size, 1); > + > + /* Node0 memory */ > + memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); > + fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); > + memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", > + machine->ram, offset, VIRT_LOWMEM_SIZE); > + memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); > + > + offset += VIRT_LOWMEM_SIZE; > + if (nb_numa_nodes > 0) { > + assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); > + highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; > + } else { > + highram_size = ram_size - VIRT_LOWMEM_SIZE; > + } > + phyAddr = VIRT_HIGHMEM_BASE; > + memmap_add_entry(phyAddr, highram_size, 1); > + fdt_add_memory_node(machine, phyAddr, highram_size, 0); > + memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", > + machine->ram, offset, highram_size); > + memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); > + > + /* Node1 - Nodemax memory */ > + offset += highram_size; > + phyAddr += highram_size; > + > + for (i = 1; i < nb_numa_nodes; i++) { > + MemoryRegion *nodemem = g_new(MemoryRegion, 1); > + ramName = g_strdup_printf("loongarch.node%d.ram", i); > + memory_region_init_alias(nodemem, NULL, ramName, machine->ram, > + offset, numa_info[i].node_mem); > + memory_region_add_subregion(address_space_mem, phyAddr, nodemem); > + memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); > + fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); > + offset += numa_info[i].node_mem; > + phyAddr += numa_info[i].node_mem; In this loop, we allocate memory via g_strdup_printf(), but never free it. The nicest fix for this is to use the g_autofree mechanism so that the memory is automatically freed when execution reaches the end of the block: g_autofree ramName = g_strdup_printf("....", ...); thanks -- PMM ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PULL 3/5] hw/loongarch: Add numa support 2024-05-03 12:50 ` Peter Maydell @ 2024-05-07 1:29 ` gaosong 0 siblings, 0 replies; 18+ messages in thread From: gaosong @ 2024-05-07 1:29 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel, richard.henderson, Tianrui Zhao 在 2024/5/3 下午8:50, Peter Maydell 写道: > On Fri, 16 Jun 2023 at 11:03, Song Gao <gaosong@loongson.cn> wrote: >> From: Tianrui Zhao <zhaotianrui@loongson.cn> >> >> 1. Implement some functions for LoongArch numa support; >> 2. Implement fdt_add_memory_node() for fdt; >> 3. build_srat() fills node_id and adds build numa memory. >> >> Reviewed-by: Song Gao <gaosong@loongson.cn> >> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> >> Signed-off-by: Song Gao <gaosong@loongson.cn> >> Message-Id: <20230613122613.2471743-1-zhaotianrui@loongson.cn> > Hi; Coverity has pointed out a memory leak in this commit > (CID 1544773): > >> @@ -799,17 +823,43 @@ static void loongarch_init(MachineState *machine) >> machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); >> } >> fdt_add_cpu_nodes(lams); >> - /* Add memory region */ >> - memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", >> - machine->ram, 0, 256 * MiB); >> - memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); >> - offset += 256 * MiB; >> - memmap_add_entry(0, 256 * MiB, 1); >> - highram_size = ram_size - 256 * MiB; >> - memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", >> - machine->ram, offset, highram_size); >> - memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem); >> - memmap_add_entry(0x90000000, highram_size, 1); >> + >> + /* Node0 memory */ >> + memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); >> + fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); >> + memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", >> + machine->ram, offset, VIRT_LOWMEM_SIZE); >> + memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); >> + >> + offset += VIRT_LOWMEM_SIZE; >> + if (nb_numa_nodes > 0) { >> + assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); >> + highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; >> + } else { >> + highram_size = ram_size - VIRT_LOWMEM_SIZE; >> + } >> + phyAddr = VIRT_HIGHMEM_BASE; >> + memmap_add_entry(phyAddr, highram_size, 1); >> + fdt_add_memory_node(machine, phyAddr, highram_size, 0); >> + memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", >> + machine->ram, offset, highram_size); >> + memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); >> + >> + /* Node1 - Nodemax memory */ >> + offset += highram_size; >> + phyAddr += highram_size; >> + >> + for (i = 1; i < nb_numa_nodes; i++) { >> + MemoryRegion *nodemem = g_new(MemoryRegion, 1); >> + ramName = g_strdup_printf("loongarch.node%d.ram", i); >> + memory_region_init_alias(nodemem, NULL, ramName, machine->ram, >> + offset, numa_info[i].node_mem); >> + memory_region_add_subregion(address_space_mem, phyAddr, nodemem); >> + memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); >> + fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); >> + offset += numa_info[i].node_mem; >> + phyAddr += numa_info[i].node_mem; > In this loop, we allocate memory via g_strdup_printf(), > but never free it. The nicest fix for this is to use the > g_autofree mechanism so that the memory is automatically > freed when execution reaches the end of the block: > g_autofree ramName = g_strdup_printf("....", ...); Thank you. I will fix it. Thanks Song Gao > thanks > -- PMM ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 4/5] hw/loongarch: Supplement cpu topology arguments 2023-06-16 10:01 [PULL 0/5] loongarch-to-apply queue Song Gao ` (2 preceding siblings ...) 2023-06-16 10:01 ` [PULL 3/5] hw/loongarch: Add numa support Song Gao @ 2023-06-16 10:01 ` Song Gao 2023-06-16 10:01 ` [PULL 5/5] target/loongarch: Fix CSR.DMW0-3.VSEG check Song Gao 2023-06-17 8:02 ` [PULL 0/5] loongarch-to-apply queue Richard Henderson 5 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2023-06-16 10:01 UTC (permalink / raw) To: qemu-devel; +Cc: richard.henderson, Tianrui Zhao, Philippe Mathieu-Daudé From: Tianrui Zhao <zhaotianrui@loongson.cn> Supplement LoongArch cpu topology arguments, including support socket and threads per core. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230613123251.2471878-1-zhaotianrui@loongson.cn> --- hw/loongarch/acpi-build.c | 4 ++++ hw/loongarch/virt.c | 9 ++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index f526f3abba..0b62c3a2f7 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -437,6 +437,10 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine) acpi_add_table(table_offsets, tables_blob); build_madt(tables_blob, tables->linker, lams); + acpi_add_table(table_offsets, tables_blob); + build_pptt(tables_blob, tables->linker, machine, + lams->oem_id, lams->oem_table_id); + acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, machine); diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1d5c764408..ca8824b6ef 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -1096,8 +1096,15 @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) for (n = 0; n < ms->possible_cpus->len; n++) { ms->possible_cpus->cpus[n].type = ms->cpu_type; ms->possible_cpus->cpus[n].arch_id = n; + + ms->possible_cpus->cpus[n].props.has_socket_id = true; + ms->possible_cpus->cpus[n].props.socket_id = + n / (ms->smp.cores * ms->smp.threads); ms->possible_cpus->cpus[n].props.has_core_id = true; - ms->possible_cpus->cpus[n].props.core_id = n % ms->smp.cores; + ms->possible_cpus->cpus[n].props.core_id = + n / ms->smp.threads % ms->smp.cores; + ms->possible_cpus->cpus[n].props.has_thread_id = true; + ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; } return ms->possible_cpus; } -- 2.39.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PULL 5/5] target/loongarch: Fix CSR.DMW0-3.VSEG check 2023-06-16 10:01 [PULL 0/5] loongarch-to-apply queue Song Gao ` (3 preceding siblings ...) 2023-06-16 10:01 ` [PULL 4/5] hw/loongarch: Supplement cpu topology arguments Song Gao @ 2023-06-16 10:01 ` Song Gao 2023-06-17 8:02 ` [PULL 0/5] loongarch-to-apply queue Richard Henderson 5 siblings, 0 replies; 18+ messages in thread From: Song Gao @ 2023-06-16 10:01 UTC (permalink / raw) To: qemu-devel; +Cc: richard.henderson, Jiajie Chen From: Jiajie Chen <c@jia.je> The previous code checks whether the highest 16 bits of virtual address equal to that of CSR.DMW0-3. This is incorrect according to the spec, and is corrected to compare only the highest four bits instead. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230614065556.2397513-1-c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn> --- target/loongarch/tlb_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c index cce1db1e0a..6e00190547 100644 --- a/target/loongarch/tlb_helper.c +++ b/target/loongarch/tlb_helper.c @@ -185,10 +185,10 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical, } plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT); - base_v = address >> TARGET_VIRT_ADDR_SPACE_BITS; + base_v = address >> R_CSR_DMW_VSEG_SHIFT; /* Check direct map window */ for (int i = 0; i < 4; i++) { - base_c = env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS; + base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG); if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) { *physical = dmw_va2pa(address); *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; -- 2.39.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PULL 0/5] loongarch-to-apply queue 2023-06-16 10:01 [PULL 0/5] loongarch-to-apply queue Song Gao ` (4 preceding siblings ...) 2023-06-16 10:01 ` [PULL 5/5] target/loongarch: Fix CSR.DMW0-3.VSEG check Song Gao @ 2023-06-17 8:02 ` Richard Henderson 5 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2023-06-17 8:02 UTC (permalink / raw) To: Song Gao, qemu-devel On 6/16/23 12:01, Song Gao wrote: > The following changes since commit 7efd65423ab22e6f5890ca08ae40c84d6660242f: > > Merge tag 'pull-riscv-to-apply-20230614' ofhttps://github.com/alistair23/qemu into staging (2023-06-14 05:28:51 +0200) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230616 > > for you to fetch changes up to 505aa8d8f29b79fcef77563bb4124208badbd8d4: > > target/loongarch: Fix CSR.DMW0-3.VSEG check (2023-06-16 17:58:46 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20230616 > > * Fix CSR.DMW0-3.VSEG check > * Add cpu arch_id support > * Set physical cpuid route for LoongArch ipi device > * Add numa support > * Supplement cpu topology arguments Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 0/5] loongarch-to-apply queue
@ 2024-05-16 9:11 Song Gao
2024-05-16 9:28 ` Peter Maydell
0 siblings, 1 reply; 18+ messages in thread
From: Song Gao @ 2024-05-16 9:11 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson
The following changes since commit 922582ace2df59572a671f5c0c5c6c5c706995e5:
Merge tag 'pull-hppa-20240515' of https://gitlab.com/rth7680/qemu into staging (2024-05-15 11:46:58 +0200)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240516
for you to fetch changes up to d55d16700a2e2b36c7e34724d4d77f4a75c5243a:
target/loongarch/kvm: fpu save the vreg registers high 192bit (2024-05-16 16:32:35 +0800)
----------------------------------------------------------------
pull-loongarch-20240516
----------------------------------------------------------------
Bibo Mao (3):
hw/loongarch: Add compat machine for 9.1
hw/loongarch: Remove minimum and default memory size
tests: Add migration test for loongarch64
Song Gao (2):
target/loongarch/kvm: Fix VM recovery from disk failures
target/loongarch/kvm: fpu save the vreg registers high 192bit
hw/loongarch/virt.c | 66 +++++++++++++++++++++++---------
target/loongarch/kvm/kvm.c | 6 +++
target/loongarch/machine.c | 6 ++-
tests/migration/Makefile | 2 +-
tests/migration/loongarch64/Makefile | 18 +++++++++
tests/migration/loongarch64/a-b-kernel.S | 49 ++++++++++++++++++++++++
tests/migration/loongarch64/a-b-kernel.h | 16 ++++++++
tests/migration/migration-test.h | 3 ++
tests/qtest/meson.build | 2 +-
tests/qtest/migration-test.c | 10 +++++
10 files changed, 156 insertions(+), 22 deletions(-)
create mode 100644 tests/migration/loongarch64/Makefile
create mode 100644 tests/migration/loongarch64/a-b-kernel.S
create mode 100644 tests/migration/loongarch64/a-b-kernel.h
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PULL 0/5] loongarch-to-apply queue 2024-05-16 9:11 Song Gao @ 2024-05-16 9:28 ` Peter Maydell 2024-05-17 1:06 ` gaosong 0 siblings, 1 reply; 18+ messages in thread From: Peter Maydell @ 2024-05-16 9:28 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel, richard.henderson On Thu, 16 May 2024 at 10:12, Song Gao <gaosong@loongson.cn> wrote: > > The following changes since commit 922582ace2df59572a671f5c0c5c6c5c706995e5: > > Merge tag 'pull-hppa-20240515' of https://gitlab.com/rth7680/qemu into staging (2024-05-15 11:46:58 +0200) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240516 > > for you to fetch changes up to d55d16700a2e2b36c7e34724d4d77f4a75c5243a: > > target/loongarch/kvm: fpu save the vreg registers high 192bit (2024-05-16 16:32:35 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20240516 > > ---------------------------------------------------------------- > Bibo Mao (3): > hw/loongarch: Add compat machine for 9.1 > hw/loongarch: Remove minimum and default memory size > tests: Add migration test for loongarch64 RTH: I had a comment about adding the versioned machine type, so we should hold off on applying this until that is resolved, I think. thanks -- PMM ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PULL 0/5] loongarch-to-apply queue 2024-05-16 9:28 ` Peter Maydell @ 2024-05-17 1:06 ` gaosong 0 siblings, 0 replies; 18+ messages in thread From: gaosong @ 2024-05-17 1:06 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel, richard.henderson 在 2024/5/16 下午5:28, Peter Maydell 写道: > On Thu, 16 May 2024 at 10:12, Song Gao <gaosong@loongson.cn> wrote: >> The following changes since commit 922582ace2df59572a671f5c0c5c6c5c706995e5: >> >> Merge tag 'pull-hppa-20240515' of https://gitlab.com/rth7680/qemu into staging (2024-05-15 11:46:58 +0200) >> >> are available in the Git repository at: >> >> https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240516 >> >> for you to fetch changes up to d55d16700a2e2b36c7e34724d4d77f4a75c5243a: >> >> target/loongarch/kvm: fpu save the vreg registers high 192bit (2024-05-16 16:32:35 +0800) >> >> ---------------------------------------------------------------- >> pull-loongarch-20240516 >> >> ---------------------------------------------------------------- >> Bibo Mao (3): >> hw/loongarch: Add compat machine for 9.1 >> hw/loongarch: Remove minimum and default memory size >> tests: Add migration test for loongarch64 > RTH: I had a comment about adding the versioned machine type, so we > should hold off on applying this until that is resolved, I think. Agreed, We will try resolved it. Thanks for your explanation. Thanks. Song Gao > thanks > -- PMM ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 0/5] loongarch-to-apply queue
@ 2023-05-15 11:19 Song Gao
2023-05-15 17:13 ` Richard Henderson
0 siblings, 1 reply; 18+ messages in thread
From: Song Gao @ 2023-05-15 11:19 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson
The following changes since commit 8844bb8d896595ee1d25d21c770e6e6f29803097:
Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu into staging (2023-05-13 11:23:14 +0100)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230515
for you to fetch changes up to 7ef0eb35a4e6961d7e40f03f16ed241c95ae93f9:
hw/intc: Add NULL pointer check on LoongArch ipi device (2023-05-15 19:09:33 +0800)
----------------------------------------------------------------
pull-loongarch-20230515
----------------------------------------------------------------
Alexander Bulekov (1):
loongarch: mark loongarch_ipi_iocsr re-entrnacy safe
Song Gao (4):
tests/avocado: Add LoongArch machine start test
hw/loongarch/virt: Modify ipi as percpu device
hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine
hw/intc: Add NULL pointer check on LoongArch ipi device
MAINTAINERS | 1 +
hw/intc/loongarch_extioi.c | 4 +-
hw/intc/loongarch_ipi.c | 86 +++++++++++++++++++++-----------------
hw/intc/trace-events | 1 +
hw/loongarch/virt.c | 25 ++++++-----
include/hw/intc/loongarch_extioi.h | 10 +++--
include/hw/intc/loongarch_ipi.h | 10 ++---
include/hw/loongarch/virt.h | 3 +-
tests/avocado/machine_loongarch.py | 58 +++++++++++++++++++++++++
9 files changed, 136 insertions(+), 62 deletions(-)
create mode 100644 tests/avocado/machine_loongarch.py
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PULL 0/5] loongarch-to-apply queue 2023-05-15 11:19 Song Gao @ 2023-05-15 17:13 ` Richard Henderson 0 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2023-05-15 17:13 UTC (permalink / raw) To: Song Gao, qemu-devel On 5/15/23 04:19, Song Gao wrote: > The following changes since commit 8844bb8d896595ee1d25d21c770e6e6f29803097: > > Merge tag 'or1k-pull-request-20230513' ofhttps://github.com/stffrdhrn/qemu into staging (2023-05-13 11:23:14 +0100) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230515 > > for you to fetch changes up to 7ef0eb35a4e6961d7e40f03f16ed241c95ae93f9: > > hw/intc: Add NULL pointer check on LoongArch ipi device (2023-05-15 19:09:33 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20230515 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 0/5] loongarch-to-apply queue
@ 2023-03-03 2:40 Song Gao
2023-03-04 13:59 ` Peter Maydell
0 siblings, 1 reply; 18+ messages in thread
From: Song Gao @ 2023-03-03 2:40 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, peter.maydell
The following changes since commit 262312d7ba6e2966acedb4f9c134fd19176b4083:
Merge tag 'pull-testing-next-010323-1' of https://gitlab.com/stsquad/qemu into staging (2023-03-02 13:02:53 +0000)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230303
for you to fetch changes up to 0d588c4f999699a430b32c563fe9ccc1710b8fd7:
hw/loongarch/virt: add system_powerdown hmp command support (2023-03-03 09:37:30 +0800)
----------------------------------------------------------------
pull-loongarch-20230303
----------------------------------------------------------------
Bibo Mao (1):
hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE
Song Gao (4):
loongarch: Add smbios command line option.
docs/system/loongarch: update loongson3.rst and rename it to virt.rst
target/loongarch: Implement Chip Configuraiton Version Register(0x0000)
hw/loongarch/virt: add system_powerdown hmp command support
docs/system/loongarch/{loongson3.rst => virt.rst} | 97 +++++++++--------------
hw/loongarch/acpi-build.c | 3 +-
hw/loongarch/virt.c | 20 ++++-
include/hw/loongarch/virt.h | 1 +
include/hw/pci-host/ls7a.h | 17 ++--
qemu-options.hx | 2 +-
target/loongarch/cpu.c | 2 +
target/loongarch/cpu.h | 1 +
8 files changed, 70 insertions(+), 73 deletions(-)
rename docs/system/loongarch/{loongson3.rst => virt.rst} (51%)
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PULL 0/5] loongarch-to-apply queue 2023-03-03 2:40 Song Gao @ 2023-03-04 13:59 ` Peter Maydell 0 siblings, 0 replies; 18+ messages in thread From: Peter Maydell @ 2023-03-04 13:59 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel, richard.henderson On Fri, 3 Mar 2023 at 02:41, Song Gao <gaosong@loongson.cn> wrote: > > The following changes since commit 262312d7ba6e2966acedb4f9c134fd19176b4083: > > Merge tag 'pull-testing-next-010323-1' of https://gitlab.com/stsquad/qemu into staging (2023-03-02 13:02:53 +0000) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230303 > > for you to fetch changes up to 0d588c4f999699a430b32c563fe9ccc1710b8fd7: > > hw/loongarch/virt: add system_powerdown hmp command support (2023-03-03 09:37:30 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20230303 > > ---------------------------------------------------------------- > Bibo Mao (1): > hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE > > Song Gao (4): > loongarch: Add smbios command line option. > docs/system/loongarch: update loongson3.rst and rename it to virt.rst > target/loongarch: Implement Chip Configuraiton Version Register(0x0000) > hw/loongarch/virt: add system_powerdown hmp command support Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PULL 0/5] loongarch-to-apply queue
@ 2022-10-17 6:39 Song Gao
2022-10-17 21:22 ` Stefan Hajnoczi
0 siblings, 1 reply; 18+ messages in thread
From: Song Gao @ 2022-10-17 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, stefanha
The following changes since commit 5c2439a92ce4a1c5a53070bd803d6f7647e702ca:
Merge tag 'pull-riscv-to-apply-20221014' of https://github.com/alistair23/qemu into staging (2022-10-16 15:53:13 -0400)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221017
for you to fetch changes up to 5ef4a4af8b41fb175374726f379a2aea79929023:
hw/intc: Fix LoongArch ipi device emulation (2022-10-17 10:28:35 +0800)
----------------------------------------------------------------
pull-loongarch-20221017
----------------------------------------------------------------
Song Gao (3):
target/loongarch: bstrins.w src register need EXT_NONE
target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags
softfloat: logB(0) should raise divideByZero exception
WANG Xuerui (1):
linux-user: Fix struct statfs ABI on loongarch64
Xiaojuan Yang (1):
hw/intc: Fix LoongArch ipi device emulation
fpu/softfloat-parts.c.inc | 1 +
hw/intc/loongarch_ipi.c | 1 -
linux-user/syscall_defs.h | 3 ++-
target/loongarch/insn_trans/trans_bit.c.inc | 36 ++++++++++++++++----------
target/loongarch/insn_trans/trans_farith.c.inc | 12 ++++-----
5 files changed, 31 insertions(+), 22 deletions(-)
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PULL 0/5] loongarch-to-apply queue 2022-10-17 6:39 Song Gao @ 2022-10-17 21:22 ` Stefan Hajnoczi 0 siblings, 0 replies; 18+ messages in thread From: Stefan Hajnoczi @ 2022-10-17 21:22 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel, richard.henderson, stefanha [-- Attachment #1: Type: text/plain, Size: 115 bytes --] Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2024-05-17 1:06 UTC | newest] Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-06-16 10:01 [PULL 0/5] loongarch-to-apply queue Song Gao 2023-06-16 10:01 ` [PULL 1/5] hw/loongarch/virt: Add cpu arch_id support Song Gao 2023-06-16 10:01 ` [PULL 2/5] hw/intc: Set physical cpuid route for LoongArch ipi device Song Gao 2023-06-16 10:01 ` [PULL 3/5] hw/loongarch: Add numa support Song Gao 2024-05-03 12:50 ` Peter Maydell 2024-05-07 1:29 ` gaosong 2023-06-16 10:01 ` [PULL 4/5] hw/loongarch: Supplement cpu topology arguments Song Gao 2023-06-16 10:01 ` [PULL 5/5] target/loongarch: Fix CSR.DMW0-3.VSEG check Song Gao 2023-06-17 8:02 ` [PULL 0/5] loongarch-to-apply queue Richard Henderson -- strict thread matches above, loose matches on Subject: below -- 2024-05-16 9:11 Song Gao 2024-05-16 9:28 ` Peter Maydell 2024-05-17 1:06 ` gaosong 2023-05-15 11:19 Song Gao 2023-05-15 17:13 ` Richard Henderson 2023-03-03 2:40 Song Gao 2023-03-04 13:59 ` Peter Maydell 2022-10-17 6:39 Song Gao 2022-10-17 21:22 ` Stefan Hajnoczi
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