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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: laurent@vivier.eu, qemu-devel@nongnu.org
Subject: [PATCH 05/21] q800: add IOSB subsystem
Date: Sun,  2 Jul 2023 16:48:22 +0100	[thread overview]
Message-ID: <20230702154838.722809-6-mark.cave-ayland@ilande.co.uk> (raw)
In-Reply-To: <20230702154838.722809-1-mark.cave-ayland@ilande.co.uk>

It is needed because it defines the BIOSConfig area.

Co-developed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 MAINTAINERS            |   2 +
 hw/m68k/Kconfig        |   1 +
 hw/m68k/q800.c         |   9 +++
 hw/misc/Kconfig        |   3 +
 hw/misc/iosb.c         | 137 +++++++++++++++++++++++++++++++++++++++++
 hw/misc/meson.build    |   1 +
 hw/misc/trace-events   |   4 ++
 include/hw/m68k/q800.h |   2 +
 include/hw/misc/iosb.h |  25 ++++++++
 9 files changed, 184 insertions(+)
 create mode 100644 hw/misc/iosb.c
 create mode 100644 include/hw/misc/iosb.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 2d85e8c28c..88db6540ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1232,6 +1232,7 @@ F: hw/nubus/*
 F: hw/display/macfb.c
 F: hw/block/swim.c
 F: hw/misc/djmemc.c
+F: hw/misc/iosb.c
 F: hw/m68k/bootinfo.h
 F: include/standard-headers/asm-m68k/bootinfo.h
 F: include/standard-headers/asm-m68k/bootinfo-mac.h
@@ -1242,6 +1243,7 @@ F: include/hw/block/swim.h
 F: include/hw/m68k/q800.h
 F: include/hw/m68k/q800-glue.h
 F: include/hw/misc/djmemc.h
+F: include/hw/misc/iosb.h
 
 virt
 M: Laurent Vivier <laurent@vivier.eu>
diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig
index 330cfdfa2d..64fa70a0db 100644
--- a/hw/m68k/Kconfig
+++ b/hw/m68k/Kconfig
@@ -24,6 +24,7 @@ config Q800
     select DP8393X
     select OR_IRQ
     select DJMEMC
+    select IOSB
 
 config M68K_VIRT
     bool
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index ac8509ba6f..081b95e9cf 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -41,6 +41,7 @@
 #include "hw/m68k/q800-glue.h"
 #include "hw/misc/mac_via.h"
 #include "hw/misc/djmemc.h"
+#include "hw/misc/iosb.h"
 #include "hw/input/adb.h"
 #include "hw/nubus/mac-nubus-bridge.h"
 #include "hw/display/macfb.h"
@@ -71,6 +72,7 @@
 #define ESP_BASE              (IO_BASE + 0x10000)
 #define ESP_PDMA              (IO_BASE + 0x10100)
 #define ASC_BASE              (IO_BASE + 0x14000)
+#define IOSB_BASE             (IO_BASE + 0x18000)
 #define SWIM_BASE             (IO_BASE + 0x1E000)
 
 #define SONIC_PROM_SIZE       0x1000
@@ -296,6 +298,13 @@ static void q800_machine_init(MachineState *machine)
     memory_region_add_subregion(&m->macio, DJMEMC_BASE - IO_BASE,
                                 sysbus_mmio_get_region(sysbus, 0));
 
+    /* IOSB subsystem */
+    object_initialize_child(OBJECT(machine), "iosb", &m->iosb, TYPE_IOSB);
+    sysbus = SYS_BUS_DEVICE(&m->iosb);
+    sysbus_realize_and_unref(sysbus, &error_fatal);
+    memory_region_add_subregion(&m->macio, IOSB_BASE - IO_BASE,
+                                sysbus_mmio_get_region(sysbus, 0));
+
     /* VIA 1 */
     object_initialize_child(OBJECT(machine), "via1", &m->via1,
                             TYPE_MOS6522_Q800_VIA1);
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 9576debc70..858742d8fc 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -186,4 +186,7 @@ config AXP2XX_PMU
 config DJMEMC
     bool
 
+config IOSB
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/iosb.c b/hw/misc/iosb.c
new file mode 100644
index 0000000000..4fc10bcf9f
--- /dev/null
+++ b/hw/misc/iosb.c
@@ -0,0 +1,137 @@
+/*
+ * QEMU IOSB emulation
+ *
+ * Copyright (c) 2019 Laurent Vivier
+ * Copyright (c) 2022 Mark Cave-Ayland
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/sysbus.h"
+#include "hw/misc/iosb.h"
+#include "trace.h"
+
+#define IOSB_SIZE          0x2000
+
+#define IOSB_CONFIG        0x0
+#define IOSB_CONFIG2       0x100
+#define IOSB_SONIC_SCSI    0x200
+#define IOSB_REVISION      0x300
+#define IOSB_SCSI_RESID    0x400
+#define IOSB_BRIGHTNESS    0x500
+#define IOSB_TIMEOUT       0x600
+
+
+static uint64_t iosb_read(void *opaque, hwaddr addr,
+                          unsigned size)
+{
+    IOSBState *s = IOSB(opaque);
+    uint64_t val = 0;
+
+    switch (addr) {
+    case IOSB_CONFIG:
+    case IOSB_CONFIG2:
+    case IOSB_SONIC_SCSI:
+    case IOSB_REVISION:
+    case IOSB_SCSI_RESID:
+    case IOSB_BRIGHTNESS:
+    case IOSB_TIMEOUT:
+        val = s->regs[addr >> 8];
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented read addr=0x%"PRIx64
+                                 " val=0x%"PRIx64 " size=%d\n",
+                                 addr, val, size);
+    }
+
+    trace_iosb_read(addr, val, size);
+    return val;
+}
+
+static void iosb_write(void *opaque, hwaddr addr, uint64_t val,
+                       unsigned size)
+{
+    IOSBState *s = IOSB(opaque);
+
+    switch (addr) {
+    case IOSB_CONFIG:
+    case IOSB_CONFIG2:
+    case IOSB_SONIC_SCSI:
+    case IOSB_REVISION:
+    case IOSB_SCSI_RESID:
+    case IOSB_BRIGHTNESS:
+    case IOSB_TIMEOUT:
+        s->regs[addr >> 8] = val;
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented write addr=0x%"PRIx64
+                                 " val=0x%"PRIx64 " size=%d\n",
+                                 addr, val, size);
+    }
+
+    trace_iosb_write(addr, val, size);
+}
+
+static const MemoryRegionOps iosb_mmio_ops = {
+    .read = iosb_read,
+    .write = iosb_write,
+    .endianness = DEVICE_BIG_ENDIAN,
+    .impl = {
+        .min_access_size = 1,
+        .max_access_size = 4,
+    },
+};
+
+static void iosb_reset_hold(Object *obj)
+{
+    IOSBState *s = IOSB(obj);
+
+    memset(s->regs, 0, sizeof(s->regs));
+
+    /* BCLK 33 MHz */
+    s->regs[IOSB_CONFIG >> 8] = 1;
+}
+
+static void iosb_init(Object *obj)
+{
+    IOSBState *s = IOSB(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+    memory_region_init_io(&s->mem_regs, obj, &iosb_mmio_ops, s, "IOSB",
+                          IOSB_SIZE);
+    sysbus_init_mmio(sbd, &s->mem_regs);
+}
+
+static const VMStateDescription vmstate_iosb = {
+    .name = "IOSB",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, IOSBState, IOSB_REGS),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void iosb_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+    dc->vmsd = &vmstate_iosb;
+    rc->phases.hold = iosb_reset_hold;
+}
+
+static const TypeInfo iosb_info_types[] = {
+    {
+        .name          = TYPE_IOSB,
+        .parent        = TYPE_SYS_BUS_DEVICE,
+        .instance_size = sizeof(IOSBState),
+        .instance_init = iosb_init,
+        .class_init    = iosb_class_init,
+    },
+};
+
+DEFINE_TYPES(iosb_info_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index c68f30e630..dc7d90ff3e 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -21,6 +21,7 @@ system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c'))
 # Mac devices
 system_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 system_ss.add(when: 'CONFIG_DJMEMC', if_true: files('djmemc.c'))
+system_ss.add(when: 'CONFIG_IOSB', if_true: files('iosb.c'))
 
 # virt devices
 system_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c'))
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 341adbf24c..d5711dcff2 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -301,3 +301,7 @@ lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
 # djmemc.c
 djmemc_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
 djmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
+
+# iosb.c
+iosb_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
+iosb_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index dd7d7a6f2c..98097165d9 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -37,6 +37,7 @@
 #include "hw/nubus/mac-nubus-bridge.h"
 #include "hw/display/macfb.h"
 #include "hw/misc/djmemc.h"
+#include "hw/misc/iosb.h"
 
 /*
  * The main Q800 machine
@@ -58,6 +59,7 @@ struct Q800MachineState {
     MacNubusBridge mac_nubus_bridge;
     MacfbNubusState macfb;
     DJMEMCState djmemc;
+    IOSBState iosb;
     MemoryRegion macio;
     MemoryRegion macio_alias;
     MemoryRegion machine_id;
diff --git a/include/hw/misc/iosb.h b/include/hw/misc/iosb.h
new file mode 100644
index 0000000000..377f8ca7e2
--- /dev/null
+++ b/include/hw/misc/iosb.h
@@ -0,0 +1,25 @@
+/*
+ * QEMU IOSB emulation
+ *
+ * Copyright (c) 2019 Laurent Vivier
+ * Copyright (c) 2022 Mark Cave-Ayland
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_MEM_IOSB_H
+#define HW_MEM_IOSB_H
+
+#define IOSB_REGS 7
+
+struct IOSBState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mem_regs;
+    uint32_t regs[IOSB_REGS];
+};
+
+#define TYPE_IOSB "IOSB"
+OBJECT_DECLARE_SIMPLE_TYPE(IOSBState, IOSB);
+
+#endif
-- 
2.30.2



  parent reply	other threads:[~2023-07-02 15:49 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-02 15:48 [PATCH 00/21] q800: add support for booting MacOS Classic - part 2 Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 01/21] q800-glue.c: convert to Resettable interface Mark Cave-Ayland
2023-07-03  7:48   ` Philippe Mathieu-Daudé
2023-07-02 15:48 ` [PATCH 02/21] q800: add djMEMC memory controller Mark Cave-Ayland
2023-07-07  8:17   ` Philippe Mathieu-Daudé
2023-07-02 15:48 ` [PATCH 03/21] q800: add machine id register Mark Cave-Ayland
2023-07-03  7:50   ` Philippe Mathieu-Daudé
2023-07-02 15:48 ` [PATCH 04/21] q800: implement additional machine id bits on VIA1 port A Mark Cave-Ayland
2023-07-07  8:19   ` Philippe Mathieu-Daudé
2023-07-02 15:48 ` Mark Cave-Ayland [this message]
2023-07-07  8:25   ` [PATCH 05/21] q800: add IOSB subsystem Philippe Mathieu-Daudé
2023-09-08  6:50     ` Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 06/21] q800: allow accesses to RAM area even if less memory is available Mark Cave-Ayland
2023-07-03  7:58   ` Philippe Mathieu-Daudé
2023-07-05  7:55   ` Laurent Vivier
2023-07-02 15:48 ` [PATCH 07/21] audio: add Apple Sound Chip (ASC) emulation Mark Cave-Ayland
2023-07-06 19:58   ` Volker Rümelin
2023-07-02 15:48 ` [PATCH 08/21] asc: generate silence if FIFO empty but engine still running Mark Cave-Ayland
2023-07-07  6:24   ` Volker Rümelin
2023-07-10  6:50     ` Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 09/21] q800: add Apple Sound Chip (ASC) audio to machine Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 10/21] q800: add easc bool machine class property to switch between ASC and EASC Mark Cave-Ayland
2023-07-07  8:29   ` Philippe Mathieu-Daudé
2023-09-08  6:54     ` Mark Cave-Ayland
2023-09-08  9:42       ` Philippe Mathieu-Daudé
2023-09-08 16:03         ` Mark Cave-Ayland
2023-09-08 16:06           ` Philippe Mathieu-Daudé
2023-09-11  5:15         ` Markus Armbruster
2023-09-20 15:41           ` Mark Cave-Ayland
2023-09-20 18:38             ` Markus Armbruster
2023-07-02 15:48 ` [PATCH 11/21] swim: add trace events for IWM and ISM registers Mark Cave-Ayland
2023-07-03  8:26   ` Philippe Mathieu-Daudé
2023-07-05 19:40     ` Mark Cave-Ayland
2023-07-06 10:05       ` Philippe Mathieu-Daudé
2023-07-02 15:48 ` [PATCH 12/21] swim: split into separate IWM and ISM register blocks Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 13/21] swim: update IWM/ISM register block decoding Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 14/21] mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEK Mark Cave-Ayland
2023-07-03  8:30   ` Philippe Mathieu-Daudé
2023-07-05 19:49     ` Mark Cave-Ayland
2023-07-06 10:10       ` Philippe Mathieu-Daudé
2023-07-06 10:34         ` Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 15/21] mac_via: workaround NetBSD ADB bus enumeration issue Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 16/21] mac_via: implement ADB_STATE_IDLE state if shift register in input mode Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 17/21] mac_via: always clear ADB interrupt when switching to A/UX mode Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 18/21] q800: add ESCC alias at 0xc000 Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 19/21] q800: add alias for MacOS toolbox ROM at 0x40000000 Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 20/21] mac_via: allow unaligned access to VIA1 registers Mark Cave-Ayland
2023-07-02 15:48 ` [PATCH 21/21] mac_via: extend timer calibration hack to work with A/UX Mark Cave-Ayland

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