* [PATCH v2 0/2] Add MAIN CPSW2G DT support for J721S2
@ 2023-07-10 9:43 ` Siddharth Vadapalli
0 siblings, 0 replies; 14+ messages in thread
From: Siddharth Vadapalli @ 2023-07-10 9:43 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Hello,
This series adds devicetree node for MAIN CPSW2G instance of CPSW
Ethernet Switch on TI's J721S2 SoC. Also, a devicetree overlay is added
in order to enable MAIN CPSW2G in RGMII-RXID mode using the GESI
Expansion Board connected to the J7 Common-Processor-Board.
Regards,
Siddharth.
---
This series is based on linux-next tagged next-20230710.
v1:
https://lore.kernel.org/r/20230529104913.560045-1-s-vadapalli@ti.com/
Changes since v1:
- Rebase series on next-20230710.
RFC:
https://lore.kernel.org/r/20230426105718.118806-1-s-vadapalli@ti.com/
Changes since RFC:
- Add GESI board product link in the device-tree overlay file.
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node
arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
arch/arm64/boot/dts/ti/Makefile | 2 +
.../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 +++++++++++++++
3 files changed, 156 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 0/2] Add MAIN CPSW2G DT support for J721S2
@ 2023-07-10 9:43 ` Siddharth Vadapalli
0 siblings, 0 replies; 14+ messages in thread
From: Siddharth Vadapalli @ 2023-07-10 9:43 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Hello,
This series adds devicetree node for MAIN CPSW2G instance of CPSW
Ethernet Switch on TI's J721S2 SoC. Also, a devicetree overlay is added
in order to enable MAIN CPSW2G in RGMII-RXID mode using the GESI
Expansion Board connected to the J7 Common-Processor-Board.
Regards,
Siddharth.
---
This series is based on linux-next tagged next-20230710.
v1:
https://lore.kernel.org/r/20230529104913.560045-1-s-vadapalli@ti.com/
Changes since v1:
- Rebase series on next-20230710.
RFC:
https://lore.kernel.org/r/20230426105718.118806-1-s-vadapalli@ti.com/
Changes since RFC:
- Add GESI board product link in the device-tree overlay file.
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node
arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
arch/arm64/boot/dts/ti/Makefile | 2 +
.../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 +++++++++++++++
3 files changed, 156 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
--
2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 1/2] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node
2023-07-10 9:43 ` Siddharth Vadapalli
@ 2023-07-10 9:43 ` Siddharth Vadapalli
-1 siblings, 0 replies; 14+ messages in thread
From: Siddharth Vadapalli @ 2023-07-10 9:43 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
From: Kishon Vijay Abraham I <kishon@ti.com>
TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch.
Add devicetree node for it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 ++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index ed79ab3a3271..4d0d27e7ca1b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -51,6 +51,12 @@ usb_serdes_mux: mux-controller@0 {
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
+ phy_gmii_sel_cpsw: phy@34 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x34 0x4>;
+ #phy-cells = <1>;
+ };
+
serdes_ln_ctrl: mux-controller@80 {
compatible = "mmio-mux";
reg = <0x80 0x10>;
@@ -1039,6 +1045,69 @@ cpts@310d0000 {
};
};
+ main_cpsw: ethernet@c200000 {
+ compatible = "ti,j721e-cpsw-nuss";
+ reg = <0x00 0xc200000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-coherent;
+ clocks = <&k3_clks 28 28>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xc640>,
+ <&main_udmap 0xc641>,
+ <&main_udmap 0xc642>,
+ <&main_udmap 0xc643>,
+ <&main_udmap 0xc644>,
+ <&main_udmap 0xc645>,
+ <&main_udmap 0xc646>,
+ <&main_udmap 0xc647>,
+ <&main_udmap 0x4640>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel_cpsw 1>;
+ status = "disabled";
+ };
+ };
+
+ main_cpsw_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 28 28>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 28 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x04104000 0x00 0x100>;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 1/2] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node
@ 2023-07-10 9:43 ` Siddharth Vadapalli
0 siblings, 0 replies; 14+ messages in thread
From: Siddharth Vadapalli @ 2023-07-10 9:43 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
From: Kishon Vijay Abraham I <kishon@ti.com>
TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch.
Add devicetree node for it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 ++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index ed79ab3a3271..4d0d27e7ca1b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -51,6 +51,12 @@ usb_serdes_mux: mux-controller@0 {
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
+ phy_gmii_sel_cpsw: phy@34 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x34 0x4>;
+ #phy-cells = <1>;
+ };
+
serdes_ln_ctrl: mux-controller@80 {
compatible = "mmio-mux";
reg = <0x80 0x10>;
@@ -1039,6 +1045,69 @@ cpts@310d0000 {
};
};
+ main_cpsw: ethernet@c200000 {
+ compatible = "ti,j721e-cpsw-nuss";
+ reg = <0x00 0xc200000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-coherent;
+ clocks = <&k3_clks 28 28>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xc640>,
+ <&main_udmap 0xc641>,
+ <&main_udmap 0xc642>,
+ <&main_udmap 0xc643>,
+ <&main_udmap 0xc644>,
+ <&main_udmap 0xc645>,
+ <&main_udmap 0xc646>,
+ <&main_udmap 0xc647>,
+ <&main_udmap 0x4640>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel_cpsw 1>;
+ status = "disabled";
+ };
+ };
+
+ main_cpsw_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 28 28>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 28 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x04104000 0x00 0x100>;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
2023-07-10 9:43 ` Siddharth Vadapalli
@ 2023-07-10 9:43 ` Siddharth Vadapalli
-1 siblings, 0 replies; 14+ messages in thread
From: Siddharth Vadapalli @ 2023-07-10 9:43 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
From: Kishon Vijay Abraham I <kishon@ti.com>
The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
to enable this.
Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address
directly from U-Boot.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 2 +
.../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++
2 files changed, 87 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 6dd7b6f1d6ab..019a8be19b93 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
# Boards with J721s2 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
@@ -58,3 +59,4 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
+DTC_FLAGS_k3-j721s2-common-proc-board += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
new file mode 100644
index 000000000000..9ababfeef904
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board.
+ *
+ * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+ };
+};
+
+&main_pmx0 {
+ main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
+ J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
+ J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
+ J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
+ J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
+ J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
+ J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
+ J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
+ J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
+ J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */
+ J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */
+ J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */
+ J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */
+ >;
+ };
+};
+
+&exp1 {
+ p15 {
+ /* P15 - EXP_MUX2 */
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "EXP_MUX2";
+ };
+};
+
+&main_cpsw {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins_default>;
+};
+
+&main_cpsw_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw_mdio_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&main_cpsw_port1 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&main_cpsw_phy0>;
+};
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
@ 2023-07-10 9:43 ` Siddharth Vadapalli
0 siblings, 0 replies; 14+ messages in thread
From: Siddharth Vadapalli @ 2023-07-10 9:43 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
From: Kishon Vijay Abraham I <kishon@ti.com>
The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
to enable this.
Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address
directly from U-Boot.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 2 +
.../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++
2 files changed, 87 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 6dd7b6f1d6ab..019a8be19b93 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
# Boards with J721s2 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
@@ -58,3 +59,4 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
+DTC_FLAGS_k3-j721s2-common-proc-board += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
new file mode 100644
index 000000000000..9ababfeef904
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board.
+ *
+ * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+ };
+};
+
+&main_pmx0 {
+ main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
+ J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
+ J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
+ J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
+ J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
+ J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
+ J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
+ J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
+ J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
+ J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */
+ J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */
+ J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */
+ J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */
+ >;
+ };
+};
+
+&exp1 {
+ p15 {
+ /* P15 - EXP_MUX2 */
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "EXP_MUX2";
+ };
+};
+
+&main_cpsw {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins_default>;
+};
+
+&main_cpsw_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw_mdio_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&main_cpsw_port1 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&main_cpsw_phy0>;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node
2023-07-10 9:43 ` Siddharth Vadapalli
@ 2023-07-19 9:42 ` Ravi Gunasekaran
-1 siblings, 0 replies; 14+ messages in thread
From: Ravi Gunasekaran @ 2023-07-19 9:42 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, kristo, robh+dt,
krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, Ravi Gunasekaran
On 7/10/23 3:13 PM, Siddharth Vadapalli wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch.
> Add devicetree node for it.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 ++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index ed79ab3a3271..4d0d27e7ca1b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -51,6 +51,12 @@ usb_serdes_mux: mux-controller@0 {
> mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
> };
>
> + phy_gmii_sel_cpsw: phy@34 {
> + compatible = "ti,am654-phy-gmii-sel";
> + reg = <0x34 0x4>;
> + #phy-cells = <1>;
> + };
> +
> serdes_ln_ctrl: mux-controller@80 {
> compatible = "mmio-mux";
> reg = <0x80 0x10>;
> @@ -1039,6 +1045,69 @@ cpts@310d0000 {
> };
> };
>
> + main_cpsw: ethernet@c200000 {
> + compatible = "ti,j721e-cpsw-nuss";
> + reg = <0x00 0xc200000 0x00 0x200000>;
> + reg-names = "cpsw_nuss";
> + ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-coherent;
> + clocks = <&k3_clks 28 28>;
> + clock-names = "fck";
> + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
> +
> + dmas = <&main_udmap 0xc640>,
> + <&main_udmap 0xc641>,
> + <&main_udmap 0xc642>,
> + <&main_udmap 0xc643>,
> + <&main_udmap 0xc644>,
> + <&main_udmap 0xc645>,
> + <&main_udmap 0xc646>,
> + <&main_udmap 0xc647>,
> + <&main_udmap 0x4640>;
> + dma-names = "tx0", "tx1", "tx2", "tx3",
> + "tx4", "tx5", "tx6", "tx7",
> + "rx";
> +
> + status = "disabled";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + main_cpsw_port1: port@1 {
> + reg = <1>;
> + ti,mac-only;
> + label = "port1";
> + phys = <&phy_gmii_sel_cpsw 1>;
> + status = "disabled";
> + };
> + };
> +
> + main_cpsw_mdio: mdio@f00 {
> + compatible = "ti,cpsw-mdio","ti,davinci_mdio";
> + reg = <0x00 0xf00 0x00 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&k3_clks 28 28>;
> + clock-names = "fck";
> + bus_freq = <1000000>;
> + status = "disabled";
> + };
> +
> + cpts@3d000 {
> + compatible = "ti,am65-cpts";
> + reg = <0x00 0x3d000 0x00 0x400>;
> + clocks = <&k3_clks 28 3>;
> + clock-names = "cpts";
> + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "cpts";
> + ti,cpts-ext-ts-inputs = <4>;
> + ti,cpts-periodic-outputs = <2>;
> + };
> + };
> +
> usbss0: cdns-usb@4104000 {
> compatible = "ti,j721e-usb";
> reg = <0x00 0x04104000 0x00 0x100>;
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
--
Regards,
Ravi
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node
@ 2023-07-19 9:42 ` Ravi Gunasekaran
0 siblings, 0 replies; 14+ messages in thread
From: Ravi Gunasekaran @ 2023-07-19 9:42 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, kristo, robh+dt,
krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, Ravi Gunasekaran
On 7/10/23 3:13 PM, Siddharth Vadapalli wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch.
> Add devicetree node for it.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 ++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index ed79ab3a3271..4d0d27e7ca1b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -51,6 +51,12 @@ usb_serdes_mux: mux-controller@0 {
> mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
> };
>
> + phy_gmii_sel_cpsw: phy@34 {
> + compatible = "ti,am654-phy-gmii-sel";
> + reg = <0x34 0x4>;
> + #phy-cells = <1>;
> + };
> +
> serdes_ln_ctrl: mux-controller@80 {
> compatible = "mmio-mux";
> reg = <0x80 0x10>;
> @@ -1039,6 +1045,69 @@ cpts@310d0000 {
> };
> };
>
> + main_cpsw: ethernet@c200000 {
> + compatible = "ti,j721e-cpsw-nuss";
> + reg = <0x00 0xc200000 0x00 0x200000>;
> + reg-names = "cpsw_nuss";
> + ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-coherent;
> + clocks = <&k3_clks 28 28>;
> + clock-names = "fck";
> + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
> +
> + dmas = <&main_udmap 0xc640>,
> + <&main_udmap 0xc641>,
> + <&main_udmap 0xc642>,
> + <&main_udmap 0xc643>,
> + <&main_udmap 0xc644>,
> + <&main_udmap 0xc645>,
> + <&main_udmap 0xc646>,
> + <&main_udmap 0xc647>,
> + <&main_udmap 0x4640>;
> + dma-names = "tx0", "tx1", "tx2", "tx3",
> + "tx4", "tx5", "tx6", "tx7",
> + "rx";
> +
> + status = "disabled";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + main_cpsw_port1: port@1 {
> + reg = <1>;
> + ti,mac-only;
> + label = "port1";
> + phys = <&phy_gmii_sel_cpsw 1>;
> + status = "disabled";
> + };
> + };
> +
> + main_cpsw_mdio: mdio@f00 {
> + compatible = "ti,cpsw-mdio","ti,davinci_mdio";
> + reg = <0x00 0xf00 0x00 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&k3_clks 28 28>;
> + clock-names = "fck";
> + bus_freq = <1000000>;
> + status = "disabled";
> + };
> +
> + cpts@3d000 {
> + compatible = "ti,am65-cpts";
> + reg = <0x00 0x3d000 0x00 0x400>;
> + clocks = <&k3_clks 28 3>;
> + clock-names = "cpts";
> + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "cpts";
> + ti,cpts-ext-ts-inputs = <4>;
> + ti,cpts-periodic-outputs = <2>;
> + };
> + };
> +
> usbss0: cdns-usb@4104000 {
> compatible = "ti,j721e-usb";
> reg = <0x00 0x04104000 0x00 0x100>;
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
--
Regards,
Ravi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
2023-07-10 9:43 ` Siddharth Vadapalli
@ 2023-07-19 9:45 ` Ravi Gunasekaran
-1 siblings, 0 replies; 14+ messages in thread
From: Ravi Gunasekaran @ 2023-07-19 9:45 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, kristo, robh+dt,
krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, Ravi Gunasekaran
On 7/10/23 3:13 PM, Siddharth Vadapalli wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
> Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
> to enable this.
>
> Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address
> directly from U-Boot.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> arch/arm64/boot/dts/ti/Makefile | 2 +
> .../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++
> 2 files changed, 87 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 6dd7b6f1d6ab..019a8be19b93 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
> # Boards with J721s2 SoC
> dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
>
> # Boards with J784s4 SoC
> dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
> @@ -58,3 +59,4 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
>
> # Enable support for device-tree overlays
> DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
> +DTC_FLAGS_k3-j721s2-common-proc-board += -@
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
> new file mode 100644
> index 000000000000..9ababfeef904
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board.
> + *
> + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
> + *
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/net/ti-dp83867.h>
> +
> +#include "k3-pinctrl.h"
> +
> +&{/} {
> + aliases {
> + ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
> + };
> +};
> +
> +&main_pmx0 {
> + main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default {
> + pinctrl-single,pins = <
> + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
> + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
> + >;
> + };
> +
> + rgmii1_pins_default: rgmii1-pins-default {
> + pinctrl-single,pins = <
> + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
> + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
> + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
> + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
> + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
> + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
> + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
> + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
> + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */
> + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */
> + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */
> + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */
> + >;
> + };
> +};
> +
> +&exp1 {
> + p15 {
> + /* P15 - EXP_MUX2 */
> + gpio-hog;
> + gpios = <13 GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "EXP_MUX2";
> + };
> +};
> +
> +&main_cpsw {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&rgmii1_pins_default>;
> +};
> +
> +&main_cpsw_mdio {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_cpsw_mdio_pins_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + main_cpsw_phy0: ethernet-phy@0 {
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,min-output-impedance;
> + };
> +};
> +
> +&main_cpsw_port1 {
> + status = "okay";
> + phy-mode = "rgmii-rxid";
> + phy-handle = <&main_cpsw_phy0>;
> +};
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
--
Regards,
Ravi
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
@ 2023-07-19 9:45 ` Ravi Gunasekaran
0 siblings, 0 replies; 14+ messages in thread
From: Ravi Gunasekaran @ 2023-07-19 9:45 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, kristo, robh+dt,
krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, Ravi Gunasekaran
On 7/10/23 3:13 PM, Siddharth Vadapalli wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
> Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
> to enable this.
>
> Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address
> directly from U-Boot.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> arch/arm64/boot/dts/ti/Makefile | 2 +
> .../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++
> 2 files changed, 87 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 6dd7b6f1d6ab..019a8be19b93 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
> # Boards with J721s2 SoC
> dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
>
> # Boards with J784s4 SoC
> dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
> @@ -58,3 +59,4 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
>
> # Enable support for device-tree overlays
> DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
> +DTC_FLAGS_k3-j721s2-common-proc-board += -@
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
> new file mode 100644
> index 000000000000..9ababfeef904
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board.
> + *
> + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
> + *
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/net/ti-dp83867.h>
> +
> +#include "k3-pinctrl.h"
> +
> +&{/} {
> + aliases {
> + ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
> + };
> +};
> +
> +&main_pmx0 {
> + main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default {
> + pinctrl-single,pins = <
> + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
> + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
> + >;
> + };
> +
> + rgmii1_pins_default: rgmii1-pins-default {
> + pinctrl-single,pins = <
> + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
> + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
> + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
> + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
> + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
> + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
> + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
> + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
> + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */
> + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */
> + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */
> + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */
> + >;
> + };
> +};
> +
> +&exp1 {
> + p15 {
> + /* P15 - EXP_MUX2 */
> + gpio-hog;
> + gpios = <13 GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "EXP_MUX2";
> + };
> +};
> +
> +&main_cpsw {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&rgmii1_pins_default>;
> +};
> +
> +&main_cpsw_mdio {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_cpsw_mdio_pins_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + main_cpsw_phy0: ethernet-phy@0 {
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,min-output-impedance;
> + };
> +};
> +
> +&main_cpsw_port1 {
> + status = "okay";
> + phy-mode = "rgmii-rxid";
> + phy-handle = <&main_cpsw_phy0>;
> +};
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
--
Regards,
Ravi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
2023-07-19 9:45 ` Ravi Gunasekaran
@ 2023-07-19 9:48 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-19 9:48 UTC (permalink / raw)
To: Ravi Gunasekaran, Siddharth Vadapalli, nm, vigneshr, kristo,
robh+dt, krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk
On 19/07/2023 11:45, Ravi Gunasekaran wrote:
>
>
> On 7/10/23 3:13 PM, Siddharth Vadapalli wrote:
>> From: Kishon Vijay Abraham I <kishon@ti.com>
>>
>> The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
>> Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
>> to enable this.
>>
Trim your replies.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
@ 2023-07-19 9:48 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-19 9:48 UTC (permalink / raw)
To: Ravi Gunasekaran, Siddharth Vadapalli, nm, vigneshr, kristo,
robh+dt, krzysztof.kozlowski+dt, conor+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk
On 19/07/2023 11:45, Ravi Gunasekaran wrote:
>
>
> On 7/10/23 3:13 PM, Siddharth Vadapalli wrote:
>> From: Kishon Vijay Abraham I <kishon@ti.com>
>>
>> The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
>> Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
>> to enable this.
>>
Trim your replies.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
2023-07-10 9:43 ` Siddharth Vadapalli
(?)
(?)
@ 2023-07-24 17:56 ` Nishanth Menon
2023-07-25 5:01 ` Siddharth Vadapalli
-1 siblings, 1 reply; 14+ messages in thread
From: Nishanth Menon @ 2023-07-24 17:56 UTC (permalink / raw)
To: Siddharth Vadapalli
Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, afd,
devicetree, linux-kernel, linux-arm-kernel, srk
On 15:13-20230710, Siddharth Vadapalli wrote:
> + rgmii1_pins_default: rgmii1-pins-default {
Could you make sure that the node names matches up with the json-schema
conversion:
https://lore.kernel.org/all/169021456020.3622493.10284534202541859578.robh@kernel.org/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
2023-07-24 17:56 ` Nishanth Menon
@ 2023-07-25 5:01 ` Siddharth Vadapalli
0 siblings, 0 replies; 14+ messages in thread
From: Siddharth Vadapalli @ 2023-07-25 5:01 UTC (permalink / raw)
To: Nishanth Menon
Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, afd,
devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
On 24/07/23 23:26, Nishanth Menon wrote:
> On 15:13-20230710, Siddharth Vadapalli wrote:
>> + rgmii1_pins_default: rgmii1-pins-default {
>
> Could you make sure that the node names matches up with the json-schema
> conversion:
> https://lore.kernel.org/all/169021456020.3622493.10284534202541859578.robh@kernel.org/
Sure. I will update the node name and post the v3 series.
--
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-07-25 5:02 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-10 9:43 [PATCH v2 0/2] Add MAIN CPSW2G DT support for J721S2 Siddharth Vadapalli
2023-07-10 9:43 ` Siddharth Vadapalli
2023-07-10 9:43 ` [PATCH v2 1/2] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node Siddharth Vadapalli
2023-07-10 9:43 ` Siddharth Vadapalli
2023-07-19 9:42 ` Ravi Gunasekaran
2023-07-19 9:42 ` Ravi Gunasekaran
2023-07-10 9:43 ` [PATCH v2 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI Siddharth Vadapalli
2023-07-10 9:43 ` Siddharth Vadapalli
2023-07-19 9:45 ` Ravi Gunasekaran
2023-07-19 9:45 ` Ravi Gunasekaran
2023-07-19 9:48 ` Krzysztof Kozlowski
2023-07-19 9:48 ` Krzysztof Kozlowski
2023-07-24 17:56 ` Nishanth Menon
2023-07-25 5:01 ` Siddharth Vadapalli
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