* [PATCH v11 00/13] Add multiport support for DWC3 controllers
@ 2023-08-28 13:30 Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 01/13] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport Krishna Kurapati
` (13 more replies)
0 siblings, 14 replies; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
Currently the DWC3 driver supports only single port controller which
requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
DWC3 controller with multiple ports that can operate in host mode.
Some of the port supports both SS+HS and other port supports only HS
mode.
This change primarily refactors the Phy logic in core driver to allow
multiport support with Generic Phy's.
Changes have been tested on QCOM SoC SA8295P which has 4 ports (2
are HS+SS capable and 2 are HS only capable).
Changes in v11:
Implemented port_count calculation by reading interrupt-names from DT.
Refactored IRQ handling in dwc3-qcom.
Moving of macros to xhci-ext-caps.h made as a separate patch.
Names of interrupts to be displayed on /proc/interrupts set to the ones
present in DT.
Changes in v10:
Refactored phy init/exit/power-on/off functions in dwc3 core
Refactored dwc3-qcom irq registration and handling
Implemented wakeup for multiport irq's
Moved few macros from xhci.h to xhci-ext-caps.h
Fixed nits pointed out in v9
Fixed Co-developed by and SOB tags in patches 5 and 11
Changes in v9:
Added IRQ support for DP/DM/SS MP Irq's of SC8280
Refactored code to read port count by accessing xhci registers
Changes in v8:
Reorganised code in patch-5
Fixed nitpicks in code according to comments received on v7
Fixed indentation in DT patches
Added drive strength for pinctrl nodes in SA8295 DT
Changes in v7:
Added power event irq's for Multiport controller.
Udpated commit text for patch-9 (adding DT changes for enabling first
port of multiport controller on sa8540-ride).
Fixed check-patch warnings for driver code.
Fixed DT binding errors for changes in snps,dwc3.yaml
Reabsed code on top of usb-next
Changes in v6:
Updated comments in code after.
Updated variables names appropriately as per review comments.
Updated commit text in patch-2 and added additional info as per review
comments.
The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected
it in this version.
Changes in v5:
Added DT support for first port of Teritiary USB controller on SA8540-Ride
Added support for reading port info from XHCI Extended Params registers.
Changes in RFC v4:
Added DT support for SA8295p.
Changes in RFC v3:
Incase any PHY init fails, then clear/exit the PHYs that
are already initialized.
Changes in RFC v2:
Changed dwc3_count_phys to return the number of PHY Phandles in the node.
This will be used now in dwc3_extract_num_phys to increment num_usb2_phy
and num_usb3_phy.
Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its
structure such that the first half is for HS-PHY and second half is for
SS-PHY.
In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is
present, pass proper SS_IDX else pass -1.
Tests done on v11:
a. ADB in device mode working on first port of SA8295P-ADP
b. Enumeration on 4 ports of SA8295 tested by connecting pendrive, mouse
and webcam
/ # lsusb -t
Bus 002 Device 004: ID 046d:085e
Bus 001 Device 001: ID 1d6b:0002
Bus 001 Device 008: ID 03f0:094a
Bus 002 Device 003: ID 0781:558b
Bus 002 Device 001: ID 1d6b:0003
Bus 001 Device 009: ID 046d:c05a
/ # dmesg | grep hub
[ 1.168337] hub 1-0:1.0: USB hub found
[ 1.168345] hub 1-0:1.0: 4 ports detected
[ 1.169059] hub 2-0:1.0: USB hub found
[ 1.169065] hub 2-0:1.0: 2 ports detected
c. Wakeup tested on 4 ports of multiport by entering system suspend and
connecting a device to each empty port and checking if it wakes up the
system or not. This method was chosen because when we enter system
suspend, power to connected peripherals was not present. So, the test was
done by connecting a peripheral to empty port and seeing if the interrupts
wake up the system or not.
d. Enumeration and wakeup tested on single port controller of SC7280 in
host mode. In this case, wakeup was initiated by a mouse click already
connected to it.
e. Interrupt registration tested on both single port and mulitport
controllers of SA8295P-ADP.
184: 0 0 0 0 0 0 0 0 PDC 127 Level dp_hs_phy_1
185: 0 0 0 0 0 0 0 0 PDC 126 Level dm_hs_phy_1
186: 0 0 0 0 0 0 0 0 PDC 129 Level dp_hs_phy_2
187: 0 0 0 0 0 0 0 0 PDC 128 Level dm_hs_phy_2
188: 0 0 0 0 0 0 0 0 PDC 131 Level dp_hs_phy_3
189: 0 0 0 0 0 0 0 0 PDC 130 Level dm_hs_phy_3
190: 0 0 0 0 0 0 0 0 PDC 133 Level dp_hs_phy_4
191: 0 0 0 0 0 0 0 0 PDC 132 Level dm_hs_phy_4
192: 0 0 0 0 0 0 0 0 PDC 16 Level ss_phy_1
193: 0 0 0 0 0 0 0 0 PDC 17 Level ss_phy_2
194: 630 0 0 0 0 0 0 0 GICv3 165 Level xhci-hcd:usb1
195: 0 0 0 0 0 0 0 0 PDC 14 Level dp_hs_phy_irq
196: 0 0 0 0 0 0 0 0 PDC 15 Level dm_hs_phy_irq
197: 0 0 0 0 0 0 0 0 PDC 138 Level ss_phy_irq
198: 31 0 0 0 0 0 0 0 GICv3 835 Level dwc3
199: 0 0 0 0 0 0 0 0 PDC 12 Level dp_hs_phy_irq
200: 0 0 0 0 0 0 0 0 PDC 13 Level dm_hs_phy_irq
201: 0 0 0 0 0 0 0 0 PDC 136 Level ss_phy_irq
Links to previous versions:
Link to v10: https://lore.kernel.org/all/20230727223307.8096-1-quic_kriskura@quicinc.com/
Link to v9: https://lore.kernel.org/all/20230621043628.21485-1-quic_kriskura@quicinc.com/
Link to v8: https://lore.kernel.org/all/20230514054917.21318-1-quic_kriskura@quicinc.com/
Link to v7: https://lore.kernel.org/all/20230501143445.3851-1-quic_kriskura@quicinc.com/
Link to v6: https://lore.kernel.org/all/20230405125759.4201-1-quic_kriskura@quicinc.com/
Link to v5: https://lore.kernel.org/all/20230310163420.7582-1-quic_kriskura@quicinc.com/
Link to RFC v4: https://lore.kernel.org/all/20230115114146.12628-1-quic_kriskura@quicinc.com/
Link to RFC v3: https://lore.kernel.org/all/1654709787-23686-1-git-send-email-quic_harshq@quicinc.com/#r
Link to RFC v2: https://lore.kernel.org/all/1653560029-6937-1-git-send-email-quic_harshq@quicinc.com/#r
Andrew Halaney (1):
arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
controller
Harsh Agarwal (1):
usb: dwc3: core: Refactor PHY logic to support Multiport Controller
Krishna Kurapati (11):
dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport
dt-bindings: usb: Add bindings for multiport properties on DWC3
controller
usb: xhci: Move extcaps related macros to respective header file
usb: dwc3: core: Access XHCI address space temporarily to read port
info
usb: dwc3: core: Skip setting event buffers for host only controllers
usb: dwc3: qcom: Add helper function to request threaded IRQ
usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver
usb: dwc3: qcom: Enable wakeup for applicable ports of multiport
usb: dwc3: qcom: Add multiport suspend/resume support for wrapper
arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
ports
.../devicetree/bindings/usb/qcom,dwc3.yaml | 29 ++
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 53 +++
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++
drivers/usb/dwc3/core.c | 324 +++++++++++++----
drivers/usb/dwc3/core.h | 16 +-
drivers/usb/dwc3/drd.c | 15 +-
drivers/usb/dwc3/dwc3-qcom.c | 328 ++++++++++++------
drivers/usb/host/xhci-ext-caps.h | 27 ++
drivers/usb/host/xhci.h | 27 --
11 files changed, 708 insertions(+), 223 deletions(-)
--
2.40.0
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v11 01/13] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller Krishna Kurapati
` (12 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati, Krzysztof Kozlowski
Add the compatible string for SC8280 Multiport USB controller from
Qualcomm.
There are 4 power event irq interrupts supported by this controller
(one for each port of multiport). Added all the 4 as non-optional
interrupts for SC8280XP-MP
Also each port of multiport has one DP and oen DM IRQ. Add all DP/DM
IRQ's related to 4 ports of SC8280XP Teritiary controller.
Also added ss phy irq for both SS Ports.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index 67591057f234..d248f454811e 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -29,6 +29,7 @@ properties:
- qcom,sc7180-dwc3
- qcom,sc7280-dwc3
- qcom,sc8280xp-dwc3
+ - qcom,sc8280xp-dwc3-mp
- qcom,sdm660-dwc3
- qcom,sdm670-dwc3
- qcom,sdm845-dwc3
@@ -258,6 +259,7 @@ allOf:
contains:
enum:
- qcom,sc8280xp-dwc3
+ - qcom,sc8280xp-dwc3-mp
then:
properties:
clocks:
@@ -479,6 +481,33 @@ allOf:
- const: dm_hs_phy_irq
- const: ss_phy_irq
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8280xp-dwc3-mp
+ then:
+ properties:
+ interrupts:
+ maxItems: 14
+ interrupt-names:
+ items:
+ - const: pwr_event_1
+ - const: pwr_event_2
+ - const: pwr_event_3
+ - const: pwr_event_4
+ - const: dp_hs_phy_1
+ - const: dm_hs_phy_1
+ - const: dp_hs_phy_2
+ - const: dm_hs_phy_2
+ - const: dp_hs_phy_3
+ - const: dm_hs_phy_3
+ - const: dp_hs_phy_4
+ - const: dm_hs_phy_4
+ - const: ss_phy_1
+ - const: ss_phy_2
+
additionalProperties: false
examples:
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 01/13] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-11-10 13:28 ` Johan Hovold
2023-08-28 13:30 ` [PATCH v11 03/13] usb: xhci: Move extcaps related macros to respective header file Krishna Kurapati
` (11 subsequent siblings)
13 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati, Bjorn Andersson, Rob Herring
Add bindings to indicate properties required to support multiport
on Synopsys DWC3 controller.
Suggested-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
index a696f23730d3..5bc941355b43 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
@@ -85,15 +85,16 @@ properties:
phys:
minItems: 1
- maxItems: 2
+ maxItems: 8
phy-names:
minItems: 1
- maxItems: 2
- items:
- enum:
- - usb2-phy
- - usb3-phy
+ maxItems: 8
+ oneOf:
+ - items:
+ enum: [ usb2-phy, usb3-phy ]
+ - items:
+ pattern: "^usb[23]-port[0-3]$"
power-domains:
description:
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 03/13] usb: xhci: Move extcaps related macros to respective header file
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 01/13] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-09-07 12:25 ` Mathias Nyman
2023-08-28 13:30 ` [PATCH v11 04/13] usb: dwc3: core: Access XHCI address space temporarily to read port info Krishna Kurapati
` (10 subsequent siblings)
13 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
DWC3 driver needs access to XHCI Extended Capabilities registers to
read number of usb2 ports and usb3 ports present on multiport controller.
Since the extcaps header is sufficient to parse this info, move port_count
related macros and structure from xhci.h to xhci-ext-caps.h.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
drivers/usb/host/xhci-ext-caps.h | 27 +++++++++++++++++++++++++++
drivers/usb/host/xhci.h | 27 ---------------------------
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
index e8af0a125f84..96eb36a58738 100644
--- a/drivers/usb/host/xhci-ext-caps.h
+++ b/drivers/usb/host/xhci-ext-caps.h
@@ -79,6 +79,33 @@
/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
#define XHCI_STS_CNR (1 << 11)
+/**
+ * struct xhci_protocol_caps
+ * @revision: major revision, minor revision, capability ID,
+ * and next capability pointer.
+ * @name_string: Four ASCII characters to say which spec this xHC
+ * follows, typically "USB ".
+ * @port_info: Port offset, count, and protocol-defined information.
+ */
+struct xhci_protocol_caps {
+ u32 revision;
+ u32 name_string;
+ u32 port_info;
+};
+
+#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
+#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
+#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
+#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
+#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
+
+#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
+#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
+#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
+#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
+#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
+#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
+
#include <linux/io.h>
/**
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 7e282b4522c0..77016338bee1 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -558,33 +558,6 @@ struct xhci_doorbell_array {
#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
#define DB_VALUE_HOST 0x00000000
-/**
- * struct xhci_protocol_caps
- * @revision: major revision, minor revision, capability ID,
- * and next capability pointer.
- * @name_string: Four ASCII characters to say which spec this xHC
- * follows, typically "USB ".
- * @port_info: Port offset, count, and protocol-defined information.
- */
-struct xhci_protocol_caps {
- u32 revision;
- u32 name_string;
- u32 port_info;
-};
-
-#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
-#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
-#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
-#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
-#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
-
-#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
-#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
-#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
-#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
-#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
-#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
-
#define PLT_MASK (0x03 << 6)
#define PLT_SYM (0x00 << 6)
#define PLT_ASYM_RX (0x02 << 6)
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 04/13] usb: dwc3: core: Access XHCI address space temporarily to read port info
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (2 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 03/13] usb: xhci: Move extcaps related macros to respective header file Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-10-02 17:10 ` Thinh Nguyen
2023-08-28 13:30 ` [PATCH v11 05/13] usb: dwc3: core: Skip setting event buffers for host only controllers Krishna Kurapati
` (9 subsequent siblings)
13 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
Currently host-only capable DWC3 controllers support Multiport.
Temporarily map XHCI address space for host-only controllers and parse
XHCI Extended Capabilities registers to read number of usb2 ports and
usb3 ports present on multiport controller. Each USB Port is at least HS
capable.
The port info for usb2 and usb3 phy are identified as num_usb2_ports
and num_usb3_ports. The intention is as follows:
Wherever we need to perform phy operations like:
LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
{
phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
}
If number of usb2 ports is 3, loop can go from index 0-2 for
usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
if the first 2 ports are SS capable or some other ports like (2 and 3)
are SS capable. So instead, num_usb2_ports is used to loop around all
phy's (both hs and ss) for performing phy operations. If any
usb3_generic_phy turns out to be NULL, phy operation just bails out.
num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
phy's as we need to know how many SS capable ports are there for this.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
drivers/usb/dwc3/core.c | 61 +++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 5 ++++
2 files changed, 66 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 9c6bf054f15d..85cebeb6d662 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -39,6 +39,7 @@
#include "io.h"
#include "debug.h"
+#include "../host/xhci-ext-caps.h"
#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
@@ -1751,6 +1752,51 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
return 0;
}
+static int dwc3_read_port_info(struct dwc3 *dwc)
+{
+ void __iomem *base;
+ u8 major_revision;
+ u32 offset = 0;
+ u32 val;
+
+ /*
+ * Remap xHCI address space to access XHCI ext cap regs,
+ * since it is needed to get port info.
+ */
+ base = ioremap(dwc->xhci_resources[0].start,
+ resource_size(&dwc->xhci_resources[0]));
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ do {
+ offset = xhci_find_next_ext_cap(base, offset,
+ XHCI_EXT_CAPS_PROTOCOL);
+ if (!offset)
+ break;
+
+ val = readl(base + offset);
+ major_revision = XHCI_EXT_PORT_MAJOR(val);
+
+ val = readl(base + offset + 0x08);
+ if (major_revision == 0x03) {
+ dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
+ } else if (major_revision <= 0x02) {
+ dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
+ } else {
+ dev_err(dwc->dev,
+ "Unrecognized port major revision %d\n",
+ major_revision);
+ }
+ } while (1);
+
+ dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
+ dwc->num_usb2_ports, dwc->num_usb3_ports);
+
+ iounmap(base);
+
+ return 0;
+}
+
static int dwc3_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1758,6 +1804,7 @@ static int dwc3_probe(struct platform_device *pdev)
void __iomem *regs;
struct dwc3 *dwc;
int ret;
+ unsigned int hw_mode;
dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
if (!dwc)
@@ -1838,6 +1885,20 @@ static int dwc3_probe(struct platform_device *pdev)
goto err_disable_clks;
}
+ /*
+ * Currently only DWC3 controllers that are host-only capable
+ * support Multiport.
+ */
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+ ret = dwc3_read_port_info(dwc);
+ if (ret)
+ goto err_disable_clks;
+ } else {
+ dwc->num_usb2_ports = 1;
+ dwc->num_usb3_ports = 1;
+ }
+
spin_lock_init(&dwc->lock);
mutex_init(&dwc->mutex);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a69ac67d89fe..5b0f2aa115d2 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1026,6 +1026,8 @@ struct dwc3_scratchpad_array {
* @usb3_phy: pointer to USB3 PHY
* @usb2_generic_phy: pointer to USB2 PHY
* @usb3_generic_phy: pointer to USB3 PHY
+ * @num_usb2_ports: number of USB2 ports
+ * @num_usb3_ports: number of USB3 ports
* @phys_ready: flag to indicate that PHYs are ready
* @ulpi: pointer to ulpi interface
* @ulpi_ready: flag to indicate that ULPI is initialized
@@ -1165,6 +1167,9 @@ struct dwc3 {
struct phy *usb2_generic_phy;
struct phy *usb3_generic_phy;
+ u8 num_usb2_ports;
+ u8 num_usb3_ports;
+
bool phys_ready;
struct ulpi *ulpi;
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 05/13] usb: dwc3: core: Skip setting event buffers for host only controllers
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (3 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 04/13] usb: dwc3: core: Access XHCI address space temporarily to read port info Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller Krishna Kurapati
` (8 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
On some SoC's like SA8295P where the tertiary controller is host-only
capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible.
Trying to access them leads to a crash.
For DRD/Peripheral supported controllers, event buffer setup is done
again in gadget_pullup. Skip setup or cleanup of event buffers if
controller is host-only capable.
Suggested-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
---
drivers/usb/dwc3/core.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 85cebeb6d662..6eacf0ff90b5 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -486,6 +486,13 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc)
static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
{
struct dwc3_event_buffer *evt;
+ unsigned int hw_mode;
+
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+ dwc->ev_buf = NULL;
+ return 0;
+ }
evt = dwc3_alloc_one_event_buffer(dwc, length);
if (IS_ERR(evt)) {
@@ -507,6 +514,9 @@ int dwc3_event_buffers_setup(struct dwc3 *dwc)
{
struct dwc3_event_buffer *evt;
+ if (!dwc->ev_buf)
+ return 0;
+
evt = dwc->ev_buf;
evt->lpos = 0;
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
@@ -524,6 +534,9 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
{
struct dwc3_event_buffer *evt;
+ if (!dwc->ev_buf)
+ return;
+
evt = dwc->ev_buf;
evt->lpos = 0;
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (4 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 05/13] usb: dwc3: core: Skip setting event buffers for host only controllers Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-09-01 1:13 ` Wesley Cheng
` (2 more replies)
2023-08-28 13:30 ` [PATCH v11 07/13] usb: dwc3: qcom: Add helper function to request threaded IRQ Krishna Kurapati
` (7 subsequent siblings)
13 siblings, 3 replies; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Harsh Agarwal, Krishna Kurapati
From: Harsh Agarwal <quic_harshq@quicinc.com>
Currently the DWC3 driver supports only single port controller
which requires at most one HS and one SS PHY.
But the DWC3 USB controller can be connected to multiple ports and
each port can have their own PHYs. Each port of the multiport
controller can either be HS+SS capable or HS only capable
Proper quantification of them is required to modify GUSB2PHYCFG
and GUSB3PIPECTL registers appropriately.
Add support for detecting, obtaining and configuring phy's supported
by a multiport controller and. Limit the max number of ports
supported to 4 as only SC8280 which is a quad port controller supports
Multiport currently.
Co-developed-by: Harsh Agarwal <quic_harshq@quicinc.com>
Signed-off-by: Harsh Agarwal <quic_harshq@quicinc.com>
Co-developed-by:Krishna Kurapati <quic_kriskura@quicinc.com>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
drivers/usb/dwc3/core.c | 252 +++++++++++++++++++++++++++-------------
drivers/usb/dwc3/core.h | 11 +-
drivers/usb/dwc3/drd.c | 15 ++-
3 files changed, 190 insertions(+), 88 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 6eacf0ff90b5..31400c309bff 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -124,6 +124,7 @@ static void __dwc3_set_mode(struct work_struct *work)
int ret;
u32 reg;
u32 desired_dr_role;
+ int i;
mutex_lock(&dwc->mutex);
spin_lock_irqsave(&dwc->lock, flags);
@@ -201,8 +202,10 @@ static void __dwc3_set_mode(struct work_struct *work)
} else {
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+ phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+ }
if (dwc->dis_split_quirk) {
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
reg |= DWC3_GUCTL3_SPLITDISABLE;
@@ -217,8 +220,8 @@ static void __dwc3_set_mode(struct work_struct *work)
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
ret = dwc3_gadget_init(dwc);
if (ret)
@@ -589,22 +592,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc)
return ret;
}
-/**
- * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
- * @dwc: Pointer to our controller context structure
- *
- * Returns 0 on success. The USB PHY interfaces are configured but not
- * initialized. The PHY interfaces and the PHYs get initialized together with
- * the core in dwc3_core_init.
- */
-static int dwc3_phy_setup(struct dwc3 *dwc)
+static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
{
unsigned int hw_mode;
u32 reg;
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
/*
* Make sure UX_EXIT_PX is cleared as that causes issues with some
@@ -659,9 +654,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->dis_del_phy_power_chg_quirk)
reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+ return 0;
+}
+
+static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
+{
+ unsigned int hw_mode;
+ u32 reg;
+
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
/* Select the HS PHY interface */
switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
@@ -673,7 +678,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
} else if (dwc->hsphy_interface &&
!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
} else {
/* Relying on default value. */
if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
@@ -740,7 +745,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->ulpi_ext_vbus_drv)
reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
+
+ return 0;
+}
+
+/**
+ * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
+ * @dwc: Pointer to our controller context structure
+ *
+ * Returns 0 on success. The USB PHY interfaces are configured but not
+ * initialized. The PHY interfaces and the PHYs get initialized together with
+ * the core in dwc3_core_init.
+ */
+static int dwc3_phy_setup(struct dwc3 *dwc)
+{
+ int i;
+ int ret;
+
+ for (i = 0; i < dwc->num_usb3_ports; i++) {
+ ret = dwc3_ss_phy_setup(dwc, i);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = dwc3_hs_phy_setup(dwc, i);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -748,23 +781,32 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
static int dwc3_phy_init(struct dwc3 *dwc)
{
int ret;
+ int i;
+ int j;
usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);
- ret = phy_init(dwc->usb2_generic_phy);
- if (ret < 0)
- goto err_shutdown_usb3_phy;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_init(dwc->usb2_generic_phy[i]);
+ if (ret < 0)
+ goto err_exit_phy;
- ret = phy_init(dwc->usb3_generic_phy);
- if (ret < 0)
- goto err_exit_usb2_phy;
+ ret = phy_init(dwc->usb3_generic_phy[i]);
+ if (ret < 0) {
+ phy_exit(dwc->usb2_generic_phy[i]);
+ goto err_exit_phy;
+ }
+ }
return 0;
-err_exit_usb2_phy:
- phy_exit(dwc->usb2_generic_phy);
-err_shutdown_usb3_phy:
+err_exit_phy:
+ for (j = i - 1; j >= 0; j--) {
+ phy_exit(dwc->usb2_generic_phy[j]);
+ phy_exit(dwc->usb3_generic_phy[j]);
+ }
+
usb_phy_shutdown(dwc->usb3_phy);
usb_phy_shutdown(dwc->usb2_phy);
@@ -773,8 +815,12 @@ static int dwc3_phy_init(struct dwc3 *dwc)
static void dwc3_phy_exit(struct dwc3 *dwc)
{
- phy_exit(dwc->usb3_generic_phy);
- phy_exit(dwc->usb2_generic_phy);
+ int i;
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_exit(dwc->usb3_generic_phy[i]);
+ phy_exit(dwc->usb2_generic_phy[i]);
+ }
usb_phy_shutdown(dwc->usb3_phy);
usb_phy_shutdown(dwc->usb2_phy);
@@ -783,23 +829,32 @@ static void dwc3_phy_exit(struct dwc3 *dwc)
static int dwc3_phy_power_on(struct dwc3 *dwc)
{
int ret;
+ int i;
+ int j;
usb_phy_set_suspend(dwc->usb2_phy, 0);
usb_phy_set_suspend(dwc->usb3_phy, 0);
- ret = phy_power_on(dwc->usb2_generic_phy);
- if (ret < 0)
- goto err_suspend_usb3_phy;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_power_on(dwc->usb2_generic_phy[i]);
+ if (ret < 0)
+ goto err_power_off_phy;
- ret = phy_power_on(dwc->usb3_generic_phy);
- if (ret < 0)
- goto err_power_off_usb2_phy;
+ ret = phy_power_on(dwc->usb3_generic_phy[i]);
+ if (ret < 0) {
+ phy_power_off(dwc->usb2_generic_phy[i]);
+ goto err_power_off_phy;
+ }
+ }
return 0;
-err_power_off_usb2_phy:
- phy_power_off(dwc->usb2_generic_phy);
-err_suspend_usb3_phy:
+err_power_off_phy:
+ for (j = i - 1; j >= 0; j--) {
+ phy_power_off(dwc->usb2_generic_phy[j]);
+ phy_power_off(dwc->usb3_generic_phy[j]);
+ }
+
usb_phy_set_suspend(dwc->usb3_phy, 1);
usb_phy_set_suspend(dwc->usb2_phy, 1);
@@ -808,8 +863,12 @@ static int dwc3_phy_power_on(struct dwc3 *dwc)
static void dwc3_phy_power_off(struct dwc3 *dwc)
{
- phy_power_off(dwc->usb3_generic_phy);
- phy_power_off(dwc->usb2_generic_phy);
+ int i;
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_power_off(dwc->usb3_generic_phy[i]);
+ phy_power_off(dwc->usb2_generic_phy[i]);
+ }
usb_phy_set_suspend(dwc->usb3_phy, 1);
usb_phy_set_suspend(dwc->usb2_phy, 1);
@@ -1082,6 +1141,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
unsigned int hw_mode;
u32 reg;
int ret;
+ int i;
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
@@ -1125,15 +1185,19 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
if (!dwc->dis_u3_susphy_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
- reg |= DWC3_GUSB3PIPECTL_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ for (i = 0; i < dwc->num_usb3_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
+ reg |= DWC3_GUSB3PIPECTL_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
+ }
}
if (!dwc->dis_u2_susphy_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- reg |= DWC3_GUSB2PHYCFG_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ reg |= DWC3_GUSB2PHYCFG_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }
}
}
@@ -1276,7 +1340,9 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
{
struct device *dev = dwc->dev;
struct device_node *node = dev->of_node;
+ char phy_name[11];
int ret;
+ int i;
if (node) {
dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
@@ -1302,22 +1368,36 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
return dev_err_probe(dev, ret, "no usb3 phy configured\n");
}
- dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(dwc->usb2_generic_phy)) {
- ret = PTR_ERR(dwc->usb2_generic_phy);
- if (ret == -ENOSYS || ret == -ENODEV)
- dwc->usb2_generic_phy = NULL;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ if (dwc->num_usb2_ports == 1)
+ sprintf(phy_name, "usb2-phy");
else
- return dev_err_probe(dev, ret, "no usb2 phy configured\n");
- }
+ sprintf(phy_name, "usb2-port%d", i);
- dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
- if (IS_ERR(dwc->usb3_generic_phy)) {
- ret = PTR_ERR(dwc->usb3_generic_phy);
- if (ret == -ENOSYS || ret == -ENODEV)
- dwc->usb3_generic_phy = NULL;
+ dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
+ if (IS_ERR(dwc->usb2_generic_phy[i])) {
+ ret = PTR_ERR(dwc->usb2_generic_phy[i]);
+ if (ret == -ENOSYS || ret == -ENODEV)
+ dwc->usb2_generic_phy[i] = NULL;
+ else
+ return dev_err_probe(dev, ret,
+ "failed to lookup phy %s\n", phy_name);
+ }
+
+ if (dwc->num_usb2_ports == 1)
+ sprintf(phy_name, "usb3-phy");
else
- return dev_err_probe(dev, ret, "no usb3 phy configured\n");
+ sprintf(phy_name, "usb3-port%d", i);
+
+ dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
+ if (IS_ERR(dwc->usb3_generic_phy[i])) {
+ ret = PTR_ERR(dwc->usb3_generic_phy[i]);
+ if (ret == -ENOSYS || ret == -ENODEV)
+ dwc->usb3_generic_phy[i] = NULL;
+ else
+ return dev_err_probe(dev, ret,
+ "failed to lookup phy %s\n", phy_name);
+ }
}
return 0;
@@ -1327,6 +1407,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
{
struct device *dev = dwc->dev;
int ret;
+ int i;
switch (dwc->dr_mode) {
case USB_DR_MODE_PERIPHERAL:
@@ -1334,8 +1415,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
ret = dwc3_gadget_init(dwc);
if (ret)
@@ -1346,8 +1427,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+ phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+ }
ret = dwc3_host_init(dwc);
if (ret)
@@ -1804,9 +1887,12 @@ static int dwc3_read_port_info(struct dwc3 *dwc)
dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
dwc->num_usb2_ports, dwc->num_usb3_ports);
-
iounmap(base);
+ if ((dwc->num_usb2_ports > DWC3_MAX_PORTS) ||
+ (dwc->num_usb3_ports > DWC3_MAX_PORTS))
+ return -ENOMEM;
+
return 0;
}
@@ -2042,6 +2128,7 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
{
unsigned long flags;
u32 reg;
+ int i;
switch (dwc->current_dr_role) {
case DWC3_GCTL_PRTCAP_DEVICE:
@@ -2060,17 +2147,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
/* Let controller to suspend HSPHY before PHY driver suspends */
if (dwc->dis_u2_susphy_quirk ||
dwc->dis_enblslpm_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
- DWC3_GUSB2PHYCFG_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
+ DWC3_GUSB2PHYCFG_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }
/* Give some time for USB2 PHY to suspend */
usleep_range(5000, 6000);
}
- phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
- phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
+ phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
+ }
break;
case DWC3_GCTL_PRTCAP_OTG:
/* do nothing during runtime_suspend */
@@ -2100,6 +2191,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
unsigned long flags;
int ret;
u32 reg;
+ int i;
switch (dwc->current_dr_role) {
case DWC3_GCTL_PRTCAP_DEVICE:
@@ -2119,17 +2211,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
break;
}
/* Restore GUSB2PHYCFG bits that were modified in suspend */
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- if (dwc->dis_u2_susphy_quirk)
- reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ if (dwc->dis_u2_susphy_quirk)
+ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
- if (dwc->dis_enblslpm_quirk)
- reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+ if (dwc->dis_enblslpm_quirk)
+ reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }
- phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
- phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
+ phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
+ }
break;
case DWC3_GCTL_PRTCAP_OTG:
/* nothing to do on runtime_resume */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 5b0f2aa115d2..5521dc9ca034 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -33,6 +33,9 @@
#include <linux/power_supply.h>
+/* Number of ports supported by a multiport controller */
+#define DWC3_MAX_PORTS 4
+
#define DWC3_MSG_MAX 500
/* Global constants */
@@ -1024,8 +1027,8 @@ struct dwc3_scratchpad_array {
* @usb_psy: pointer to power supply interface.
* @usb2_phy: pointer to USB2 PHY
* @usb3_phy: pointer to USB3 PHY
- * @usb2_generic_phy: pointer to USB2 PHY
- * @usb3_generic_phy: pointer to USB3 PHY
+ * @usb2_generic_phy: pointer to array of USB2 PHY
+ * @usb3_generic_phy: pointer to array of USB3 PHY
* @num_usb2_ports: number of USB2 ports
* @num_usb3_ports: number of USB3 ports
* @phys_ready: flag to indicate that PHYs are ready
@@ -1164,8 +1167,8 @@ struct dwc3 {
struct usb_phy *usb2_phy;
struct usb_phy *usb3_phy;
- struct phy *usb2_generic_phy;
- struct phy *usb3_generic_phy;
+ struct phy *usb2_generic_phy[DWC3_MAX_PORTS];
+ struct phy *usb3_generic_phy[DWC3_MAX_PORTS];
u8 num_usb2_ports;
u8 num_usb3_ports;
diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index 039bf241769a..9aec41f1ad43 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -331,6 +331,7 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
u32 reg;
int id;
unsigned long flags;
+ int i;
if (dwc->dr_mode != USB_DR_MODE_OTG)
return;
@@ -386,9 +387,12 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
} else {
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- if (dwc->usb2_generic_phy)
- phy_set_mode(dwc->usb2_generic_phy,
- PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ if (dwc->usb2_generic_phy[i]) {
+ phy_set_mode(dwc->usb2_generic_phy[i],
+ PHY_MODE_USB_HOST);
+ }
+ }
}
break;
case DWC3_OTG_ROLE_DEVICE:
@@ -400,9 +404,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- if (dwc->usb2_generic_phy)
- phy_set_mode(dwc->usb2_generic_phy,
- PHY_MODE_USB_DEVICE);
+ if (dwc->usb2_generic_phy[0])
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
ret = dwc3_gadget_init(dwc);
if (ret)
dev_err(dwc->dev, "failed to initialize peripheral\n");
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 07/13] usb: dwc3: qcom: Add helper function to request threaded IRQ
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (5 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-09-28 21:48 ` Bjorn Andersson
2023-08-28 13:30 ` [PATCH v11 08/13] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver Krishna Kurapati
` (6 subsequent siblings)
13 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
Cleanup setup irq call by implementing a new prep_irq helper function
and using it to request threaded IRQ's.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
drivers/usb/dwc3/dwc3-qcom.c | 63 +++++++++++++++++-------------------
1 file changed, 30 insertions(+), 33 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 3de43df6bbe8..f14ddc9c541d 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -535,6 +535,24 @@ static int dwc3_qcom_get_irq(struct platform_device *pdev,
return ret;
}
+static int dwc3_qcom_prep_irq(struct dwc3_qcom *qcom, char *irq_name,
+ char *disp_name, int irq)
+{
+ int ret;
+
+ /* Keep wakeup interrupts disabled until suspend */
+ irq_set_status_flags(irq, IRQ_NOAUTOEN);
+ ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
+ qcom_dwc3_resume_irq,
+ IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+ disp_name, qcom);
+
+ if (ret)
+ dev_err(qcom->dev, "%s failed: %d\n", irq_name, ret);
+
+ return ret;
+}
+
static int dwc3_qcom_setup_irq(struct platform_device *pdev)
{
struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
@@ -545,61 +563,40 @@ static int dwc3_qcom_setup_irq(struct platform_device *pdev)
irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
pdata ? pdata->hs_phy_irq_index : -1);
if (irq > 0) {
- /* Keep wakeup interrupts disabled until suspend */
- irq_set_status_flags(irq, IRQ_NOAUTOEN);
- ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
- qcom_dwc3_resume_irq,
- IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
- "qcom_dwc3 HS", qcom);
- if (ret) {
- dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
+ ret = dwc3_qcom_prep_irq(qcom, "hs_phy_irq",
+ "qcom_dwc3 HS", irq);
+ if (ret)
return ret;
- }
qcom->hs_phy_irq = irq;
}
irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
pdata ? pdata->dp_hs_phy_irq_index : -1);
if (irq > 0) {
- irq_set_status_flags(irq, IRQ_NOAUTOEN);
- ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
- qcom_dwc3_resume_irq,
- IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
- "qcom_dwc3 DP_HS", qcom);
- if (ret) {
- dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
+ ret = dwc3_qcom_prep_irq(qcom, "dp_hs_phy_irq",
+ "qcom_dwc3 DP_HS", irq);
+ if (ret)
return ret;
- }
qcom->dp_hs_phy_irq = irq;
}
irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
pdata ? pdata->dm_hs_phy_irq_index : -1);
if (irq > 0) {
- irq_set_status_flags(irq, IRQ_NOAUTOEN);
- ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
- qcom_dwc3_resume_irq,
- IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
- "qcom_dwc3 DM_HS", qcom);
- if (ret) {
- dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
+ ret = dwc3_qcom_prep_irq(qcom, "dm_hs_phy_irq",
+ "qcom_dwc3 DM_HS", irq);
+ if (ret)
return ret;
- }
qcom->dm_hs_phy_irq = irq;
}
irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
pdata ? pdata->ss_phy_irq_index : -1);
if (irq > 0) {
- irq_set_status_flags(irq, IRQ_NOAUTOEN);
- ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
- qcom_dwc3_resume_irq,
- IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
- "qcom_dwc3 SS", qcom);
- if (ret) {
- dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
+ ret = dwc3_qcom_prep_irq(qcom, "ss_phy_irq",
+ "qcom_dwc3 SS", irq);
+ if (ret)
return ret;
- }
qcom->ss_phy_irq = irq;
}
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 08/13] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (6 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 07/13] usb: dwc3: qcom: Add helper function to request threaded IRQ Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 09/13] usb: dwc3: qcom: Enable wakeup for applicable ports of multiport Krishna Kurapati
` (5 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
Refactor setup_irq call to facilitate reading multiport IRQ's along
with non mulitport ones. Read through the interrupt-names property
to figure out, the type of interrupt (DP/DM/HS/SS) and to which port
it belongs. Also keep track of port index to calculate port count
based on interrupts provided as input in DT.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
drivers/usb/dwc3/dwc3-qcom.c | 215 +++++++++++++++++++++++++----------
1 file changed, 155 insertions(+), 60 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index f14ddc9c541d..05990142cbc8 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -53,14 +53,24 @@
#define APPS_USB_AVG_BW 0
#define APPS_USB_PEAK_BW MBps_to_icc(40)
+#define NUM_PHY_IRQ 4
+
+#define DP_HS_PHY_IRQ_INDEX 0
+#define DM_HS_PHY_IRQ_INDEX 1
+#define SS_PHY_IRQ_INDEX 2
+#define HS_PHY_IRQ_INDEX 3
+
struct dwc3_acpi_pdata {
u32 qscratch_base_offset;
u32 qscratch_base_size;
u32 dwc3_core_base_size;
+
+ /*
+ * The phy_irq_index corresponds to ACPI indexes of (in order) DP/DM/SS
+ * IRQ's respectively.
+ */
+ int phy_irq_index[NUM_PHY_IRQ - 1];
int hs_phy_irq_index;
- int dp_hs_phy_irq_index;
- int dm_hs_phy_irq_index;
- int ss_phy_irq_index;
bool is_urs;
};
@@ -73,10 +83,12 @@ struct dwc3_qcom {
int num_clocks;
struct reset_control *resets;
+ /*
+ * The phy_irq corresponds to IRQ's registered for (in order) DP/DM/SS
+ * respectively.
+ */
+ int phy_irq[NUM_PHY_IRQ - 1][DWC3_MAX_PORTS];
int hs_phy_irq;
- int dp_hs_phy_irq;
- int dm_hs_phy_irq;
- int ss_phy_irq;
enum usb_device_speed usb2_speed;
struct extcon_dev *edev;
@@ -91,6 +103,8 @@ struct dwc3_qcom {
bool pm_suspended;
struct icc_path *icc_path_ddr;
struct icc_path *icc_path_apps;
+
+ int num_ports;
};
static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
@@ -375,16 +389,16 @@ static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
if (qcom->usb2_speed == USB_SPEED_LOW) {
- dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0]);
} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
(qcom->usb2_speed == USB_SPEED_FULL)) {
- dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0]);
} else {
- dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
- dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0]);
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0]);
}
- dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[SS_PHY_IRQ_INDEX][0]);
}
static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
@@ -401,20 +415,20 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
*/
if (qcom->usb2_speed == USB_SPEED_LOW) {
- dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0],
IRQ_TYPE_EDGE_FALLING);
} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
(qcom->usb2_speed == USB_SPEED_FULL)) {
- dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0],
IRQ_TYPE_EDGE_FALLING);
} else {
- dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0],
IRQ_TYPE_EDGE_RISING);
- dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0],
IRQ_TYPE_EDGE_RISING);
}
- dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[SS_PHY_IRQ_INDEX][0], 0);
}
static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
@@ -535,8 +549,8 @@ static int dwc3_qcom_get_irq(struct platform_device *pdev,
return ret;
}
-static int dwc3_qcom_prep_irq(struct dwc3_qcom *qcom, char *irq_name,
- char *disp_name, int irq)
+static int dwc3_qcom_prep_irq(struct dwc3_qcom *qcom, const char *irq_name,
+ const char *disp_name, int irq)
{
int ret;
@@ -553,51 +567,136 @@ static int dwc3_qcom_prep_irq(struct dwc3_qcom *qcom, char *irq_name,
return ret;
}
+static int dwc3_qcom_get_irq_index(const char *irq_name)
+{
+ /*
+ * If we are reading IRQ not supported by the driver
+ * like pwr_event_irq, then return -1 indicating the next
+ * helper function to skip processing IRQ name further.
+ */
+ int irq_index = -1;
+
+ if (strncmp(irq_name, "dp_hs_phy", strlen("dp_hs_phy")) == 0)
+ irq_index = DP_HS_PHY_IRQ_INDEX;
+ else if (strncmp(irq_name, "dm_hs_phy", strlen("dm_hs_phy")) == 0)
+ irq_index = DM_HS_PHY_IRQ_INDEX;
+ else if (strncmp(irq_name, "ss_phy", strlen("ss_phy")) == 0)
+ irq_index = SS_PHY_IRQ_INDEX;
+ else if (strncmp(irq_name, "hs_phy", strlen("hs_phy")) == 0)
+ irq_index = HS_PHY_IRQ_INDEX;
+
+ return irq_index;
+}
+
+static int dwc3_qcom_get_port_index(const char *irq_name, int irq_index)
+{
+ int port_index = -1;
+
+ switch (irq_index) {
+ case DP_HS_PHY_IRQ_INDEX:
+ if (strcmp(irq_name, "dp_hs_phy_irq") == 0)
+ port_index = 1;
+ else
+ sscanf(irq_name, "dp_hs_phy_%d", &port_index);
+ break;
+
+ case DM_HS_PHY_IRQ_INDEX:
+ if (strcmp(irq_name, "dm_hs_phy_irq") == 0)
+ port_index = 1;
+ else
+ sscanf(irq_name, "dm_hs_phy_%d", &port_index);
+ break;
+
+ case SS_PHY_IRQ_INDEX:
+ if (strcmp(irq_name, "ss_phy_irq") == 0)
+ port_index = 1;
+ else
+ sscanf(irq_name, "ss_phy_%d", &port_index);
+ break;
+
+ case HS_PHY_IRQ_INDEX:
+ port_index = 1;
+ break;
+ }
+
+ if (port_index > DWC3_MAX_PORTS)
+ port_index = -1;
+
+ return port_index;
+}
+
+static int dwc3_qcom_get_acpi_index(struct dwc3_qcom *qcom, int irq_index,
+ int port_index)
+{
+ const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
+ int acpi_index = -1;
+
+ /*
+ * Currently multiport supported targets don't have an ACPI variant.
+ * So return -1 if we are not dealing with first port of the controller.
+ */
+ if ((pdata == NULL) || (port_index != 1))
+ goto done;
+
+ if (irq_index == HS_PHY_IRQ_INDEX)
+ acpi_index = pdata->hs_phy_irq_index;
+ else
+ acpi_index = pdata->phy_irq_index[irq_index];
+
+done:
+ return acpi_index;
+}
+
static int dwc3_qcom_setup_irq(struct platform_device *pdev)
{
struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
- const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
+ struct device_node *np = pdev->dev.of_node;
+ const char **irq_names;
+ int port_index;
+ int acpi_index;
+ int irq_count;
+ int irq_index;
int irq;
int ret;
+ int i;
- irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
- pdata ? pdata->hs_phy_irq_index : -1);
- if (irq > 0) {
- ret = dwc3_qcom_prep_irq(qcom, "hs_phy_irq",
- "qcom_dwc3 HS", irq);
- if (ret)
- return ret;
- qcom->hs_phy_irq = irq;
- }
+ irq_count = of_property_count_strings(np, "interrupt-names");
+ irq_names = devm_kzalloc(&pdev->dev, sizeof(*irq_names) * irq_count, GFP_KERNEL);
+ if (!irq_names)
+ return -ENOMEM;
- irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
- pdata ? pdata->dp_hs_phy_irq_index : -1);
- if (irq > 0) {
- ret = dwc3_qcom_prep_irq(qcom, "dp_hs_phy_irq",
- "qcom_dwc3 DP_HS", irq);
- if (ret)
- return ret;
- qcom->dp_hs_phy_irq = irq;
- }
+ ret = of_property_read_string_array(np, "interrupt-names",
+ irq_names, irq_count);
+ for (i = 0; i < irq_count; i++) {
+ irq_index = dwc3_qcom_get_irq_index(irq_names[i]);
+ if (irq_index == -1) {
+ dev_dbg(&pdev->dev, "Invalid IRQ not handled");
+ continue;
+ }
- irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
- pdata ? pdata->dm_hs_phy_irq_index : -1);
- if (irq > 0) {
- ret = dwc3_qcom_prep_irq(qcom, "dm_hs_phy_irq",
- "qcom_dwc3 DM_HS", irq);
- if (ret)
- return ret;
- qcom->dm_hs_phy_irq = irq;
- }
+ port_index = dwc3_qcom_get_port_index(irq_names[i], irq_index);
+ if (port_index == -1) {
+ dev_dbg(&pdev->dev, "Port index invalid. IRQ not handled");
+ continue;
+ }
- irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
- pdata ? pdata->ss_phy_irq_index : -1);
- if (irq > 0) {
- ret = dwc3_qcom_prep_irq(qcom, "ss_phy_irq",
- "qcom_dwc3 SS", irq);
- if (ret)
- return ret;
- qcom->ss_phy_irq = irq;
+ acpi_index = dwc3_qcom_get_acpi_index(qcom, irq_index, port_index);
+
+ irq = dwc3_qcom_get_irq(pdev, irq_names[i], acpi_index);
+ if (irq > 0) {
+ ret = dwc3_qcom_prep_irq(qcom, irq_names[i],
+ irq_names[i], irq);
+ if (ret)
+ return ret;
+
+ if (irq_index == HS_PHY_IRQ_INDEX)
+ qcom->hs_phy_irq = irq;
+ else
+ qcom->phy_irq[irq_index][port_index-1] = irq;
+
+ if (qcom->num_ports < port_index)
+ qcom->num_ports = port_index;
+ }
}
return 0;
@@ -1030,20 +1129,16 @@ static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
.qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
.qscratch_base_size = SDM845_QSCRATCH_SIZE,
.dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
+ .phy_irq_index = {4, 3, 2},
.hs_phy_irq_index = 1,
- .dp_hs_phy_irq_index = 4,
- .dm_hs_phy_irq_index = 3,
- .ss_phy_irq_index = 2
};
static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
.qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
.qscratch_base_size = SDM845_QSCRATCH_SIZE,
.dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
+ .phy_irq_index = {4, 3, 2},
.hs_phy_irq_index = 1,
- .dp_hs_phy_irq_index = 4,
- .dm_hs_phy_irq_index = 3,
- .ss_phy_irq_index = 2,
.is_urs = true,
};
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 09/13] usb: dwc3: qcom: Enable wakeup for applicable ports of multiport
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (7 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 08/13] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 10/13] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Krishna Kurapati
` (4 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
Currently wakeup is supported by only single port controllers. Read speed
of each port and accordingly enable IRQ's for those ports.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
drivers/usb/dwc3/dwc3-qcom.c | 65 +++++++++++++++++++-----------------
1 file changed, 35 insertions(+), 30 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 05990142cbc8..f8f8c5e39a01 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -89,7 +89,7 @@ struct dwc3_qcom {
*/
int phy_irq[NUM_PHY_IRQ - 1][DWC3_MAX_PORTS];
int hs_phy_irq;
- enum usb_device_speed usb2_speed;
+ enum usb_device_speed usb2_speed[DWC3_MAX_PORTS];
struct extcon_dev *edev;
struct extcon_dev *host_edev;
@@ -335,7 +335,8 @@ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
return dwc->xhci;
}
-static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
+static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom,
+ int port_index)
{
struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
struct usb_device *udev;
@@ -348,12 +349,10 @@ static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
/*
* It is possible to query the speed of all children of
- * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
- * currently supports only 1 port per controller. So
- * this is sufficient.
+ * USB2.0 root hub via usb_hub_for_each_child().
*/
#ifdef CONFIG_USB
- udev = usb_hub_find_child(hcd->self.root_hub, 1);
+ udev = usb_hub_find_child(hcd->self.root_hub, port_index + 1);
#else
udev = NULL;
#endif
@@ -386,23 +385,29 @@ static void dwc3_qcom_disable_wakeup_irq(int irq)
static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
{
+ int i;
+
dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
- if (qcom->usb2_speed == USB_SPEED_LOW) {
- dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0]);
- } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
- (qcom->usb2_speed == USB_SPEED_FULL)) {
- dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0]);
- } else {
- dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0]);
- dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0]);
- }
+ for (i = 0; i < qcom->num_ports; i++) {
+ if (qcom->usb2_speed[i] == USB_SPEED_LOW) {
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][i]);
+ } else if ((qcom->usb2_speed[i] == USB_SPEED_HIGH) ||
+ (qcom->usb2_speed[i] == USB_SPEED_FULL)) {
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][i]);
+ } else {
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][i]);
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][i]);
+ }
- dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[SS_PHY_IRQ_INDEX][0]);
+ dwc3_qcom_disable_wakeup_irq(qcom->phy_irq[SS_PHY_IRQ_INDEX][i]);
+ }
}
static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
{
+ int i;
+
dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0);
/*
@@ -413,22 +418,24 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
* disconnect and remote wakeup. When no device is connected, configure both
* DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
*/
-
- if (qcom->usb2_speed == USB_SPEED_LOW) {
- dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0],
+ for (i = 0; i < qcom->num_ports; i++) {
+ qcom->usb2_speed[i] = dwc3_qcom_read_usb2_speed(qcom, i);
+ if (qcom->usb2_speed[i] == USB_SPEED_LOW) {
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][i],
IRQ_TYPE_EDGE_FALLING);
- } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
- (qcom->usb2_speed == USB_SPEED_FULL)) {
- dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0],
+ } else if ((qcom->usb2_speed[i] == USB_SPEED_HIGH) ||
+ (qcom->usb2_speed[i] == USB_SPEED_FULL)) {
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][i],
IRQ_TYPE_EDGE_FALLING);
- } else {
- dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][0],
+ } else {
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DP_HS_PHY_IRQ_INDEX][i],
IRQ_TYPE_EDGE_RISING);
- dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][0],
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[DM_HS_PHY_IRQ_INDEX][i],
IRQ_TYPE_EDGE_RISING);
- }
+ }
- dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[SS_PHY_IRQ_INDEX][0], 0);
+ dwc3_qcom_enable_wakeup_irq(qcom->phy_irq[SS_PHY_IRQ_INDEX][i], 0);
+ }
}
static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
@@ -454,10 +461,8 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
* The role is stable during suspend as role switching is done from a
* freezable workqueue.
*/
- if (dwc3_qcom_is_host(qcom) && wakeup) {
- qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
+ if (dwc3_qcom_is_host(qcom) && wakeup)
dwc3_qcom_enable_interrupts(qcom);
- }
qcom->is_suspended = true;
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 10/13] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (8 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 09/13] usb: dwc3: qcom: Enable wakeup for applicable ports of multiport Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-09-15 13:48 ` Konrad Dybcio
2023-08-28 13:30 ` [PATCH v11 11/13] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 Krishna Kurapati
` (3 subsequent siblings)
13 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
QCOM SoC SA8295P's tertiary quad port controller supports 2 HS+SS
ports and 2 HS only ports. Add support for configuring PWR_EVENT_IRQ's
for all the ports during suspend/resume.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
drivers/usb/dwc3/dwc3-qcom.c | 39 +++++++++++++++++++++++++++++-------
1 file changed, 32 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index f8f8c5e39a01..34eeebb74a6a 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -37,7 +37,11 @@
#define PIPE3_PHYSTATUS_SW BIT(3)
#define PIPE_UTMI_CLK_DIS BIT(8)
-#define PWR_EVNT_IRQ_STAT_REG 0x58
+#define PWR_EVNT_IRQ1_STAT_REG 0x58
+#define PWR_EVNT_IRQ2_STAT_REG 0x1dc
+#define PWR_EVNT_IRQ3_STAT_REG 0x228
+#define PWR_EVNT_IRQ4_STAT_REG 0x238
+
#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
@@ -107,6 +111,19 @@ struct dwc3_qcom {
int num_ports;
};
+/*
+ * SA8295 has 4 power event IRQ STAT registers to be checked
+ * during suspend resume.
+ */
+#define NUM_PWR_EVENT_STAT_REGS 4
+
+static u32 pwr_evnt_irq_stat_reg_offset[NUM_PWR_EVENT_STAT_REGS] = {
+ PWR_EVNT_IRQ1_STAT_REG,
+ PWR_EVNT_IRQ2_STAT_REG,
+ PWR_EVNT_IRQ3_STAT_REG,
+ PWR_EVNT_IRQ4_STAT_REG,
+};
+
static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
{
u32 reg;
@@ -440,15 +457,19 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
{
+ u8 num_ports;
u32 val;
int i, ret;
if (qcom->is_suspended)
return 0;
- val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
- if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
- dev_err(qcom->dev, "HS-PHY not in L2\n");
+ num_ports = qcom->num_ports;
+ for (i = 0; i < num_ports; i++) {
+ val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]);
+ if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
+ dev_err(qcom->dev, "HS-PHY not in L2\n");
+ }
for (i = qcom->num_clocks - 1; i >= 0; i--)
clk_disable_unprepare(qcom->clks[i]);
@@ -471,6 +492,7 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
{
+ u8 num_ports;
int ret;
int i;
@@ -494,9 +516,12 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
/* Clear existing events from PHY related to L2 in/out */
- dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
- PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
-
+ num_ports = qcom->num_ports;
+ for (i = 0; i < num_ports; i++) {
+ dwc3_qcom_setbits(qcom->qscratch_base,
+ pwr_evnt_irq_stat_reg_offset[i],
+ PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
+ }
qcom->is_suspended = false;
return 0;
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 11/13] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (9 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 10/13] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 12/13] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports Krishna Kurapati
` (2 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
Add USB and DWC3 node for tertiary port of SC8280 along with multiport
IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
platforms.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index ac0596dfdbc4..d31ce0d3d78b 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3329,6 +3329,83 @@ system-cache-controller@9200000 {
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ usb_2: usb@a4f8800 {
+ compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
+ reg = <0 0x0a4f8800 0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_SLEEP_CLK>,
+ <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
+ "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 126 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 129 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 128 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 131 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 130 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 133 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 132 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "dp_hs_phy_1", "dm_hs_phy_1",
+ "dp_hs_phy_2", "dm_hs_phy_2",
+ "dp_hs_phy_3", "dm_hs_phy_3",
+ "dp_hs_phy_4", "dm_hs_phy_4",
+ "ss_phy_1", "ss_phy_2",
+ "pwr_event_1",
+ "pwr_event_2",
+ "pwr_event_3",
+ "pwr_event_4";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_MP_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ wakeup-source;
+
+ status = "disabled";
+
+ usb_2_dwc3: usb@a400000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a400000 0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x800 0x0>;
+ phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
+ <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
+ <&usb_2_hsphy2>,
+ <&usb_2_hsphy3>;
+ phy-names = "usb2-port0", "usb3-port0",
+ "usb2-port1", "usb3-port1",
+ "usb2-port2",
+ "usb2-port3";
+ };
+ };
+
usb_0: usb@a6f8800 {
compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 12/13] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (10 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 11/13] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-09-13 12:11 ` Konrad Dybcio
2023-08-28 13:30 ` [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller Krishna Kurapati
[not found] ` <0814b6a2-c52d-4be2-ae06-8391767ac144@quicinc.com>
13 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
Enable tertiary controller for SA8295P (based on SC8280XP).
Add pinctrl support for usb ports to provide VBUS to connected peripherals.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 53 ++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index fd253942e5e5..473fe858fbed 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "sa8540p.dtsi"
#include "sa8540p-pmics.dtsi"
@@ -584,6 +585,20 @@ &usb_1_qmpphy {
status = "okay";
};
+&usb_2 {
+ pinctrl-0 = <&usb2_en_state>,
+ <&usb3_en_state>,
+ <&usb4_en_state>,
+ <&usb5_en_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+};
+
&usb_2_hsphy0 {
vdda-pll-supply = <&vreg_l5a>;
vdda18-supply = <&vreg_l7g>;
@@ -729,3 +744,41 @@ wake-n-pins {
};
};
};
+
+&pmm8540c_gpios {
+ usb2_en_state: usb2-en-state {
+ pins = "gpio9";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8540e_gpios {
+ usb3_en_state: usb3-en-state {
+ pins = "gpio5";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8540g_gpios {
+ usb4_en_state: usb4-en-state {
+ pins = "gpio5";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-high;
+ power-source = <0>;
+ };
+
+ usb5_en_state: usb5-en-state {
+ pins = "gpio9";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-high;
+ power-source = <0>;
+ };
+};
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
` (11 preceding siblings ...)
2023-08-28 13:30 ` [PATCH v11 12/13] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports Krishna Kurapati
@ 2023-08-28 13:30 ` Krishna Kurapati
2023-09-06 16:58 ` Konrad Dybcio
[not found] ` <0814b6a2-c52d-4be2-ae06-8391767ac144@quicinc.com>
13 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati @ 2023-08-28 13:30 UTC (permalink / raw)
To: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Krishna Kurapati
From: Andrew Halaney <ahalaney@redhat.com>
There is now support for the multiport USB controller this uses so
enable it.
The board only has a single port hooked up (despite it being wired up to
the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
which by default on boot is selected to mux properly. Grab the gpio
controlling that and ensure it stays in the right position so USB 2.0
continues to be routed from the external port to the SoC.
Co-developed-by: Andrew Halaney <ahalaney@redhat.com>
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
[Krishna: Rebased on top of usb-next]
Co-developed-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 5a26974dcf8f..69f6b13e6197 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -488,6 +488,19 @@ &usb_2_qmpphy0 {
status = "okay";
};
+&usb_2 {
+ pinctrl-0 = <&usb2_en_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+ phy-names = "usb2-port0", "usb3-port0";
+ phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
+};
+
&xo_board_clk {
clock-frequency = <38400000>;
};
@@ -640,4 +653,13 @@ wake-pins {
bias-pull-up;
};
};
+
+ usb2_en_state: usb2-en-state {
+ /* TS3USB221A USB2.0 mux select */
+ pins = "gpio24";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
};
--
2.40.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller
2023-08-28 13:30 ` [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller Krishna Kurapati
@ 2023-09-01 1:13 ` Wesley Cheng
2023-09-01 21:54 ` Krishna Kurapati PSSNV
2023-09-19 17:26 ` kernel test robot
2023-10-02 17:19 ` Thinh Nguyen
2 siblings, 1 reply; 37+ messages in thread
From: Wesley Cheng @ 2023-09-01 1:13 UTC (permalink / raw)
To: Krishna Kurapati, Thinh Nguyen, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Felipe Balbi, Johan Hovold,
Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Harsh Agarwal
Hi Krishna,
On 8/28/2023 6:30 AM, Krishna Kurapati wrote:
> From: Harsh Agarwal <quic_harshq@quicinc.com>
>
> Currently the DWC3 driver supports only single port controller
> which requires at most one HS and one SS PHY.
>
> But the DWC3 USB controller can be connected to multiple ports and
> each port can have their own PHYs. Each port of the multiport
> controller can either be HS+SS capable or HS only capable
> Proper quantification of them is required to modify GUSB2PHYCFG
> and GUSB3PIPECTL registers appropriately.
>
> Add support for detecting, obtaining and configuring phy's supported
> by a multiport controller and. Limit the max number of ports
> supported to 4 as only SC8280 which is a quad port controller supports
> Multiport currently.
>
> Co-developed-by: Harsh Agarwal <quic_harshq@quicinc.com>
> Signed-off-by: Harsh Agarwal <quic_harshq@quicinc.com>
> Co-developed-by:Krishna Kurapati <quic_kriskura@quicinc.com>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> drivers/usb/dwc3/core.c | 252 +++++++++++++++++++++++++++-------------
> drivers/usb/dwc3/core.h | 11 +-
> drivers/usb/dwc3/drd.c | 15 ++-
> 3 files changed, 190 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 6eacf0ff90b5..31400c309bff 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -124,6 +124,7 @@ static void __dwc3_set_mode(struct work_struct *work)
> int ret;
> u32 reg;
> u32 desired_dr_role;
> + int i;
>
> mutex_lock(&dwc->mutex);
> spin_lock_irqsave(&dwc->lock, flags);
> @@ -201,8 +202,10 @@ static void __dwc3_set_mode(struct work_struct *work)
> } else {
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, true);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> + }
> if (dwc->dis_split_quirk) {
> reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
> reg |= DWC3_GUCTL3_SPLITDISABLE;
> @@ -217,8 +220,8 @@ static void __dwc3_set_mode(struct work_struct *work)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, false);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
>
Throughout this patch, you are looping across all PHYs irrespective of
if we are in device mode or not. This is the only exception where you
are setting only PHY index 0 (for both SS and HS PHYs). Do you think we
should also only modify PHY index#0 for other PHY related sequences?
> ret = dwc3_gadget_init(dwc);
> if (ret)
> @@ -589,22 +592,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc)
> return ret;
> }
>
> -/**
> - * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
> - * @dwc: Pointer to our controller context structure
> - *
> - * Returns 0 on success. The USB PHY interfaces are configured but not
> - * initialized. The PHY interfaces and the PHYs get initialized together with
> - * the core in dwc3_core_init.
> - */
> -static int dwc3_phy_setup(struct dwc3 *dwc)
> +static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
> {
> unsigned int hw_mode;
> u32 reg;
>
> hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
>
> /*
> * Make sure UX_EXIT_PX is cleared as that causes issues with some
> @@ -659,9 +654,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> if (dwc->dis_del_phy_power_chg_quirk)
> reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
>
> - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
>
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> + return 0;
> +}
> +
> +static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
> +{
> + unsigned int hw_mode;
> + u32 reg;
> +
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> +
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
>
> /* Select the HS PHY interface */
> switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
> @@ -673,7 +678,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> } else if (dwc->hsphy_interface &&
> !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
> reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
> } else {
> /* Relying on default value. */
> if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
> @@ -740,7 +745,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> if (dwc->ulpi_ext_vbus_drv)
> reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
>
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
> +
> + return 0;
> +}
> +
> +/**
> + * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
> + * @dwc: Pointer to our controller context structure
> + *
> + * Returns 0 on success. The USB PHY interfaces are configured but not
> + * initialized. The PHY interfaces and the PHYs get initialized together with
> + * the core in dwc3_core_init.
> + */
> +static int dwc3_phy_setup(struct dwc3 *dwc)
> +{
> + int i;
> + int ret;
> +
> + for (i = 0; i < dwc->num_usb3_ports; i++) {
> + ret = dwc3_ss_phy_setup(dwc, i);
> + if (ret)
> + return ret;
> + }
> +
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = dwc3_hs_phy_setup(dwc, i);
> + if (ret)
> + return ret;
> + }
>
> return 0;
> }
> @@ -748,23 +781,32 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> static int dwc3_phy_init(struct dwc3 *dwc)
> {
> int ret;
> + int i;
> + int j;
>
> usb_phy_init(dwc->usb2_phy);
> usb_phy_init(dwc->usb3_phy);
>
> - ret = phy_init(dwc->usb2_generic_phy);
> - if (ret < 0)
> - goto err_shutdown_usb3_phy;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = phy_init(dwc->usb2_generic_phy[i]);
> + if (ret < 0)
> + goto err_exit_phy;
>
> - ret = phy_init(dwc->usb3_generic_phy);
> - if (ret < 0)
> - goto err_exit_usb2_phy;
> + ret = phy_init(dwc->usb3_generic_phy[i]);
> + if (ret < 0) {
> + phy_exit(dwc->usb2_generic_phy[i]);
> + goto err_exit_phy;
> + }
> + }
>
> return 0;
>
> -err_exit_usb2_phy:
> - phy_exit(dwc->usb2_generic_phy);
> -err_shutdown_usb3_phy:
> +err_exit_phy:
> + for (j = i - 1; j >= 0; j--) {
> + phy_exit(dwc->usb2_generic_phy[j]);
> + phy_exit(dwc->usb3_generic_phy[j]);
> + }
> +
> usb_phy_shutdown(dwc->usb3_phy);
> usb_phy_shutdown(dwc->usb2_phy);
>
> @@ -773,8 +815,12 @@ static int dwc3_phy_init(struct dwc3 *dwc)
>
> static void dwc3_phy_exit(struct dwc3 *dwc)
> {
> - phy_exit(dwc->usb3_generic_phy);
> - phy_exit(dwc->usb2_generic_phy);
> + int i;
> +
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_exit(dwc->usb3_generic_phy[i]);
> + phy_exit(dwc->usb2_generic_phy[i]);
> + }
>
> usb_phy_shutdown(dwc->usb3_phy);
> usb_phy_shutdown(dwc->usb2_phy);
> @@ -783,23 +829,32 @@ static void dwc3_phy_exit(struct dwc3 *dwc)
> static int dwc3_phy_power_on(struct dwc3 *dwc)
> {
> int ret;
> + int i;
> + int j;
>
> usb_phy_set_suspend(dwc->usb2_phy, 0);
> usb_phy_set_suspend(dwc->usb3_phy, 0);
>
> - ret = phy_power_on(dwc->usb2_generic_phy);
> - if (ret < 0)
> - goto err_suspend_usb3_phy;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = phy_power_on(dwc->usb2_generic_phy[i]);
> + if (ret < 0)
> + goto err_power_off_phy;
>
> - ret = phy_power_on(dwc->usb3_generic_phy);
> - if (ret < 0)
> - goto err_power_off_usb2_phy;
> + ret = phy_power_on(dwc->usb3_generic_phy[i]);
> + if (ret < 0) {
> + phy_power_off(dwc->usb2_generic_phy[i]);
> + goto err_power_off_phy;
> + }
> + }
>
> return 0;
>
> -err_power_off_usb2_phy:
> - phy_power_off(dwc->usb2_generic_phy);
> -err_suspend_usb3_phy:
> +err_power_off_phy:
> + for (j = i - 1; j >= 0; j--) {
> + phy_power_off(dwc->usb2_generic_phy[j]);
> + phy_power_off(dwc->usb3_generic_phy[j]);
> + }
> +
> usb_phy_set_suspend(dwc->usb3_phy, 1);
> usb_phy_set_suspend(dwc->usb2_phy, 1);
>
> @@ -808,8 +863,12 @@ static int dwc3_phy_power_on(struct dwc3 *dwc)
>
> static void dwc3_phy_power_off(struct dwc3 *dwc)
> {
> - phy_power_off(dwc->usb3_generic_phy);
> - phy_power_off(dwc->usb2_generic_phy);
> + int i;
> +
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_power_off(dwc->usb3_generic_phy[i]);
> + phy_power_off(dwc->usb2_generic_phy[i]);
> + }
>
> usb_phy_set_suspend(dwc->usb3_phy, 1);
> usb_phy_set_suspend(dwc->usb2_phy, 1);
> @@ -1082,6 +1141,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> unsigned int hw_mode;
> u32 reg;
> int ret;
> + int i;
>
> hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>
> @@ -1125,15 +1185,19 @@ static int dwc3_core_init(struct dwc3 *dwc)
> if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
> !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
> if (!dwc->dis_u3_susphy_quirk) {
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> - reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
> + for (i = 0; i < dwc->num_usb3_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
> + reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
> + }
> }
>
> if (!dwc->dis_u2_susphy_quirk) {
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - reg |= DWC3_GUSB2PHYCFG_SUSPHY;
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> + reg |= DWC3_GUSB2PHYCFG_SUSPHY;
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> + }
> }
> }
>
> @@ -1276,7 +1340,9 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
> {
> struct device *dev = dwc->dev;
> struct device_node *node = dev->of_node;
> + char phy_name[11];
> int ret;
> + int i;
>
> if (node) {
> dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
> @@ -1302,22 +1368,36 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
> return dev_err_probe(dev, ret, "no usb3 phy configured\n");
> }
>
> - dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
> - if (IS_ERR(dwc->usb2_generic_phy)) {
> - ret = PTR_ERR(dwc->usb2_generic_phy);
> - if (ret == -ENOSYS || ret == -ENODEV)
> - dwc->usb2_generic_phy = NULL;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + if (dwc->num_usb2_ports == 1)
> + sprintf(phy_name, "usb2-phy");
> else
> - return dev_err_probe(dev, ret, "no usb2 phy configured\n");
> - }
> + sprintf(phy_name, "usb2-port%d", i);
>
> - dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
> - if (IS_ERR(dwc->usb3_generic_phy)) {
> - ret = PTR_ERR(dwc->usb3_generic_phy);
> - if (ret == -ENOSYS || ret == -ENODEV)
> - dwc->usb3_generic_phy = NULL;
> + dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
> + if (IS_ERR(dwc->usb2_generic_phy[i])) {
> + ret = PTR_ERR(dwc->usb2_generic_phy[i]);
> + if (ret == -ENOSYS || ret == -ENODEV)
> + dwc->usb2_generic_phy[i] = NULL;
> + else
> + return dev_err_probe(dev, ret,
> + "failed to lookup phy %s\n", phy_name);
> + }
> +
> + if (dwc->num_usb2_ports == 1)
> + sprintf(phy_name, "usb3-phy");
> else
> - return dev_err_probe(dev, ret, "no usb3 phy configured\n");
> + sprintf(phy_name, "usb3-port%d", i);
> +
> + dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
> + if (IS_ERR(dwc->usb3_generic_phy[i])) {
> + ret = PTR_ERR(dwc->usb3_generic_phy[i]);
> + if (ret == -ENOSYS || ret == -ENODEV)
> + dwc->usb3_generic_phy[i] = NULL;
> + else
> + return dev_err_probe(dev, ret,
> + "failed to lookup phy %s\n", phy_name);
> + }
> }
>
> return 0;
> @@ -1327,6 +1407,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
> {
> struct device *dev = dwc->dev;
> int ret;
> + int i;
>
> switch (dwc->dr_mode) {
> case USB_DR_MODE_PERIPHERAL:
> @@ -1334,8 +1415,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, false);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
>
> ret = dwc3_gadget_init(dwc);
> if (ret)
> @@ -1346,8 +1427,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, true);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> + }
>
> ret = dwc3_host_init(dwc);
> if (ret)
> @@ -1804,9 +1887,12 @@ static int dwc3_read_port_info(struct dwc3 *dwc)
>
> dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
> dwc->num_usb2_ports, dwc->num_usb3_ports);
> -
> iounmap(base);
>
> + if ((dwc->num_usb2_ports > DWC3_MAX_PORTS) ||
> + (dwc->num_usb3_ports > DWC3_MAX_PORTS))
> + return -ENOMEM;
> +
Shouldn't this be more applicable to be included in patch#4 in this series?
Thanks
Wesley Cheng
> return 0;
> }
>
> @@ -2042,6 +2128,7 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
> {
> unsigned long flags;
> u32 reg;
> + int i;
>
> switch (dwc->current_dr_role) {
> case DWC3_GCTL_PRTCAP_DEVICE:
> @@ -2060,17 +2147,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
> /* Let controller to suspend HSPHY before PHY driver suspends */
> if (dwc->dis_u2_susphy_quirk ||
> dwc->dis_enblslpm_quirk) {
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
> - DWC3_GUSB2PHYCFG_SUSPHY;
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> + reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
> + DWC3_GUSB2PHYCFG_SUSPHY;
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> + }
>
> /* Give some time for USB2 PHY to suspend */
> usleep_range(5000, 6000);
> }
>
> - phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
> - phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
> + phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
> + }
> break;
> case DWC3_GCTL_PRTCAP_OTG:
> /* do nothing during runtime_suspend */
> @@ -2100,6 +2191,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
> unsigned long flags;
> int ret;
> u32 reg;
> + int i;
>
> switch (dwc->current_dr_role) {
> case DWC3_GCTL_PRTCAP_DEVICE:
> @@ -2119,17 +2211,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
> break;
> }
> /* Restore GUSB2PHYCFG bits that were modified in suspend */
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - if (dwc->dis_u2_susphy_quirk)
> - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> + if (dwc->dis_u2_susphy_quirk)
> + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
>
> - if (dwc->dis_enblslpm_quirk)
> - reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
> + if (dwc->dis_enblslpm_quirk)
> + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
>
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> + }
>
> - phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
> - phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
> + phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
> + }
> break;
> case DWC3_GCTL_PRTCAP_OTG:
> /* nothing to do on runtime_resume */
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 5b0f2aa115d2..5521dc9ca034 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -33,6 +33,9 @@
>
> #include <linux/power_supply.h>
>
> +/* Number of ports supported by a multiport controller */
> +#define DWC3_MAX_PORTS 4
> +
> #define DWC3_MSG_MAX 500
>
> /* Global constants */
> @@ -1024,8 +1027,8 @@ struct dwc3_scratchpad_array {
> * @usb_psy: pointer to power supply interface.
> * @usb2_phy: pointer to USB2 PHY
> * @usb3_phy: pointer to USB3 PHY
> - * @usb2_generic_phy: pointer to USB2 PHY
> - * @usb3_generic_phy: pointer to USB3 PHY
> + * @usb2_generic_phy: pointer to array of USB2 PHY
> + * @usb3_generic_phy: pointer to array of USB3 PHY
> * @num_usb2_ports: number of USB2 ports
> * @num_usb3_ports: number of USB3 ports
> * @phys_ready: flag to indicate that PHYs are ready
> @@ -1164,8 +1167,8 @@ struct dwc3 {
> struct usb_phy *usb2_phy;
> struct usb_phy *usb3_phy;
>
> - struct phy *usb2_generic_phy;
> - struct phy *usb3_generic_phy;
> + struct phy *usb2_generic_phy[DWC3_MAX_PORTS];
> + struct phy *usb3_generic_phy[DWC3_MAX_PORTS];
>
> u8 num_usb2_ports;
> u8 num_usb3_ports;
> diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
> index 039bf241769a..9aec41f1ad43 100644
> --- a/drivers/usb/dwc3/drd.c
> +++ b/drivers/usb/dwc3/drd.c
> @@ -331,6 +331,7 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
> u32 reg;
> int id;
> unsigned long flags;
> + int i;
>
> if (dwc->dr_mode != USB_DR_MODE_OTG)
> return;
> @@ -386,9 +387,12 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
> } else {
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, true);
> - if (dwc->usb2_generic_phy)
> - phy_set_mode(dwc->usb2_generic_phy,
> - PHY_MODE_USB_HOST);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + if (dwc->usb2_generic_phy[i]) {
> + phy_set_mode(dwc->usb2_generic_phy[i],
> + PHY_MODE_USB_HOST);
> + }
> + }
> }
> break;
> case DWC3_OTG_ROLE_DEVICE:
> @@ -400,9 +404,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, false);
> - if (dwc->usb2_generic_phy)
> - phy_set_mode(dwc->usb2_generic_phy,
> - PHY_MODE_USB_DEVICE);
> + if (dwc->usb2_generic_phy[0])
> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
> ret = dwc3_gadget_init(dwc);
> if (ret)
> dev_err(dwc->dev, "failed to initialize peripheral\n");
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller
2023-09-01 1:13 ` Wesley Cheng
@ 2023-09-01 21:54 ` Krishna Kurapati PSSNV
0 siblings, 0 replies; 37+ messages in thread
From: Krishna Kurapati PSSNV @ 2023-09-01 21:54 UTC (permalink / raw)
To: Wesley Cheng, Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Felipe Balbi, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Harsh Agarwal
On 9/1/2023 6:43 AM, Wesley Cheng wrote:
> Hi Krishna,
>
>> if (dwc->usb2_phy)
>> otg_set_vbus(dwc->usb2_phy->otg, false);
>> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
>> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
>> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
>> + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
>
> Throughout this patch, you are looping across all PHYs irrespective of
> if we are in device mode or not. This is the only exception where you
> are setting only PHY index 0 (for both SS and HS PHYs). Do you think we
> should also only modify PHY index#0 for other PHY related sequences?
>
Hi Wesley,
Multiport controllers are host only capable currently. So if the
GHWPARAMS indicate we are DRD/peripheral capable, we set
num_usb2/3_ports to "1" unconditionally. So there would not be any
looping necessary here.
>> if (ret)
>> @@ -1804,9 +1887,12 @@ static int dwc3_read_port_info(struct dwc3 *dwc)
>> dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
>> dwc->num_usb2_ports, dwc->num_usb3_ports);
>> -
>> iounmap(base);
>> + if ((dwc->num_usb2_ports > DWC3_MAX_PORTS) ||
>> + (dwc->num_usb3_ports > DWC3_MAX_PORTS))
>> + return -ENOMEM;
>> +
>
> Shouldn't this be more applicable to be included in patch#4 in this series?
>
The read_port_info function was only initially intended to read only
port count and later the macro was added. So the check was put here.
Regards,
Krishna,
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller
2023-08-28 13:30 ` [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller Krishna Kurapati
@ 2023-09-06 16:58 ` Konrad Dybcio
2023-09-07 3:36 ` Krishna Kurapati PSSNV
0 siblings, 1 reply; 37+ messages in thread
From: Konrad Dybcio @ 2023-09-06 16:58 UTC (permalink / raw)
To: Krishna Kurapati, Thinh Nguyen, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Felipe Balbi, Wesley Cheng, Johan Hovold,
Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 28.08.2023 15:30, Krishna Kurapati wrote:
> From: Andrew Halaney <ahalaney@redhat.com>
>
> There is now support for the multiport USB controller this uses so
> enable it.
>
> The board only has a single port hooked up (despite it being wired up to
> the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
> which by default on boot is selected to mux properly. Grab the gpio
> controlling that and ensure it stays in the right position so USB 2.0
> continues to be routed from the external port to the SoC.
>
> Co-developed-by: Andrew Halaney <ahalaney@redhat.com>
> Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
> [Krishna: Rebased on top of usb-next]
> Co-developed-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
Is there any benefit to removing the other ports?
i.e. are ports 1-3 not parked properly by the dwc3 driver if
they're never connected to anything?
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller
2023-09-06 16:58 ` Konrad Dybcio
@ 2023-09-07 3:36 ` Krishna Kurapati PSSNV
2023-09-13 12:10 ` Konrad Dybcio
0 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati PSSNV @ 2023-09-07 3:36 UTC (permalink / raw)
To: Konrad Dybcio, Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel,
Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 9/6/2023 10:28 PM, Konrad Dybcio wrote:
> On 28.08.2023 15:30, Krishna Kurapati wrote:
>> From: Andrew Halaney <ahalaney@redhat.com>
>>
>> There is now support for the multiport USB controller this uses so
>> enable it.
>>
>> The board only has a single port hooked up (despite it being wired up to
>> the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
>> which by default on boot is selected to mux properly. Grab the gpio
>> controlling that and ensure it stays in the right position so USB 2.0
>> continues to be routed from the external port to the SoC.
>>
>> Co-developed-by: Andrew Halaney <ahalaney@redhat.com>
>> Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
>> [Krishna: Rebased on top of usb-next]
>> Co-developed-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>> ---
> Is there any benefit to removing the other ports?
>
> i.e. are ports 1-3 not parked properly by the dwc3 driver if
> they're never connected to anything?
>
Hi Konrad,
Whether or not the phy is connected to a port, the controller would
modify the GUSB2PHYCFG/GUSB3PIPECTL registers. But if we don't specify
only one phy and let phys from base DTSI take effect (4 HS / 2 SS), we
would end up initializing and powering on phy's which are never
connected to a port. To avoid that we need to specify only one phy for
this platform.
Regards,
Krishna,
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 03/13] usb: xhci: Move extcaps related macros to respective header file
2023-08-28 13:30 ` [PATCH v11 03/13] usb: xhci: Move extcaps related macros to respective header file Krishna Kurapati
@ 2023-09-07 12:25 ` Mathias Nyman
0 siblings, 0 replies; 37+ messages in thread
From: Mathias Nyman @ 2023-09-07 12:25 UTC (permalink / raw)
To: Krishna Kurapati, Thinh Nguyen, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Felipe Balbi, Wesley Cheng,
Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 28.8.2023 16.30, Krishna Kurapati wrote:
> DWC3 driver needs access to XHCI Extended Capabilities registers to
> read number of usb2 ports and usb3 ports present on multiport controller.
> Since the extcaps header is sufficient to parse this info, move port_count
> related macros and structure from xhci.h to xhci-ext-caps.h.
>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller
2023-09-07 3:36 ` Krishna Kurapati PSSNV
@ 2023-09-13 12:10 ` Konrad Dybcio
2023-09-14 15:45 ` Krishna Kurapati PSSNV
0 siblings, 1 reply; 37+ messages in thread
From: Konrad Dybcio @ 2023-09-13 12:10 UTC (permalink / raw)
To: Krishna Kurapati PSSNV, Thinh Nguyen, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Felipe Balbi, Wesley Cheng, Johan Hovold,
Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 7.09.2023 05:36, Krishna Kurapati PSSNV wrote:
>
>
> On 9/6/2023 10:28 PM, Konrad Dybcio wrote:
>> On 28.08.2023 15:30, Krishna Kurapati wrote:
>>> From: Andrew Halaney <ahalaney@redhat.com>
>>>
>>> There is now support for the multiport USB controller this uses so
>>> enable it.
>>>
>>> The board only has a single port hooked up (despite it being wired up to
>>> the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
>>> which by default on boot is selected to mux properly. Grab the gpio
>>> controlling that and ensure it stays in the right position so USB 2.0
>>> continues to be routed from the external port to the SoC.
>>>
>>> Co-developed-by: Andrew Halaney <ahalaney@redhat.com>
>>> Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
>>> [Krishna: Rebased on top of usb-next]
>>> Co-developed-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>>> ---
>> Is there any benefit to removing the other ports?
>>
>> i.e. are ports 1-3 not parked properly by the dwc3 driver if
>> they're never connected to anything?
>>
> Hi Konrad,
>
> Whether or not the phy is connected to a port, the controller would modify the GUSB2PHYCFG/GUSB3PIPECTL registers. But if we don't specify only one phy and let phys from base DTSI take effect (4 HS / 2 SS), we would end up initializing and powering on phy's which are never connected to a port. To avoid that we need to specify only one phy for this platform.
And does that have any major effect on power use?
Do these PHYs not have some dormant/low power mode?
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 12/13] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports
2023-08-28 13:30 ` [PATCH v11 12/13] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports Krishna Kurapati
@ 2023-09-13 12:11 ` Konrad Dybcio
2023-09-14 15:44 ` Krishna Kurapati PSSNV
0 siblings, 1 reply; 37+ messages in thread
From: Konrad Dybcio @ 2023-09-13 12:11 UTC (permalink / raw)
To: Krishna Kurapati, Thinh Nguyen, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Felipe Balbi, Wesley Cheng, Johan Hovold,
Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 28.08.2023 15:30, Krishna Kurapati wrote:
> Enable tertiary controller for SA8295P (based on SC8280XP).
> Add pinctrl support for usb ports to provide VBUS to connected peripherals.
>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 53 ++++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> index fd253942e5e5..473fe858fbed 100644
> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> @@ -9,6 +9,7 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> #include <dt-bindings/spmi/spmi.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
>
> #include "sa8540p.dtsi"
> #include "sa8540p-pmics.dtsi"
> @@ -584,6 +585,20 @@ &usb_1_qmpphy {
> status = "okay";
> };
>
> +&usb_2 {
> + pinctrl-0 = <&usb2_en_state>,
> + <&usb3_en_state>,
> + <&usb4_en_state>,
> + <&usb5_en_state>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&usb_2_dwc3 {
> + dr_mode = "host";
I believe you mentioned that the MP controller is host-only
by design. If that's true, move this property to the SoC dtsi
and leave an appropriate comment.
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 12/13] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports
2023-09-13 12:11 ` Konrad Dybcio
@ 2023-09-14 15:44 ` Krishna Kurapati PSSNV
0 siblings, 0 replies; 37+ messages in thread
From: Krishna Kurapati PSSNV @ 2023-09-14 15:44 UTC (permalink / raw)
To: Konrad Dybcio, Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel,
Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 9/13/2023 5:41 PM, Konrad Dybcio wrote:
> On 28.08.2023 15:30, Krishna Kurapati wrote:
>> Enable tertiary controller for SA8295P (based on SC8280XP).
>> Add pinctrl support for usb ports to provide VBUS to connected peripherals.
>>
>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 53 ++++++++++++++++++++++++
>> 1 file changed, 53 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>> index fd253942e5e5..473fe858fbed 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>> @@ -9,6 +9,7 @@
>> #include <dt-bindings/gpio/gpio.h>
>> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> #include <dt-bindings/spmi/spmi.h>
>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
>>
>> #include "sa8540p.dtsi"
>> #include "sa8540p-pmics.dtsi"
>> @@ -584,6 +585,20 @@ &usb_1_qmpphy {
>> status = "okay";
>> };
>>
>> +&usb_2 {
>> + pinctrl-0 = <&usb2_en_state>,
>> + <&usb3_en_state>,
>> + <&usb4_en_state>,
>> + <&usb5_en_state>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> +};
>> +
>> +&usb_2_dwc3 {
>> + dr_mode = "host";
> I believe you mentioned that the MP controller is host-only
> by design. If that's true, move this property to the SoC dtsi
> and leave an appropriate comment.
>
Hi Konrad,
Yes, it is host only controller. We can move this to sc8280xp.dtsi but
wanted to keep uniformity, so made the change here. I can move it to
base DT.
Regards,
Krishna,
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller
2023-09-13 12:10 ` Konrad Dybcio
@ 2023-09-14 15:45 ` Krishna Kurapati PSSNV
2023-10-02 9:47 ` Konrad Dybcio
0 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati PSSNV @ 2023-09-14 15:45 UTC (permalink / raw)
To: Konrad Dybcio, Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel,
Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 9/13/2023 5:40 PM, Konrad Dybcio wrote:
> On 7.09.2023 05:36, Krishna Kurapati PSSNV wrote:
>>
>>
>>> Is there any benefit to removing the other ports?
>>>
>>> i.e. are ports 1-3 not parked properly by the dwc3 driver if
>>> they're never connected to anything?
>>>
>> Hi Konrad,
>>
>> Whether or not the phy is connected to a port, the controller would modify the GUSB2PHYCFG/GUSB3PIPECTL registers. But if we don't specify only one phy and let phys from base DTSI take effect (4 HS / 2 SS), we would end up initializing and powering on phy's which are never connected to a port. To avoid that we need to specify only one phy for this platform.
> And does that have any major effect on power use?
>
> Do these PHYs not have some dormant/low power mode?
>
Hi Konrad,
I believe there will be some minimal power use. IMO its best to keep
only one phy enabled for this variant instead of giving all and
initializing/powering-on all 4 of them.
Regards,
Krishna,
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 10/13] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper
2023-08-28 13:30 ` [PATCH v11 10/13] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Krishna Kurapati
@ 2023-09-15 13:48 ` Konrad Dybcio
2023-09-18 7:42 ` Krishna Kurapati PSSNV
0 siblings, 1 reply; 37+ messages in thread
From: Konrad Dybcio @ 2023-09-15 13:48 UTC (permalink / raw)
To: Krishna Kurapati, Thinh Nguyen, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Felipe Balbi, Wesley Cheng, Johan Hovold,
Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 28.08.2023 15:30, Krishna Kurapati wrote:
> QCOM SoC SA8295P's tertiary quad port controller supports 2 HS+SS
> ports and 2 HS only ports. Add support for configuring PWR_EVENT_IRQ's
> for all the ports during suspend/resume.
>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 39 +++++++++++++++++++++++++++++-------
> 1 file changed, 32 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index f8f8c5e39a01..34eeebb74a6a 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -37,7 +37,11 @@
> #define PIPE3_PHYSTATUS_SW BIT(3)
> #define PIPE_UTMI_CLK_DIS BIT(8)
>
> -#define PWR_EVNT_IRQ_STAT_REG 0x58
> +#define PWR_EVNT_IRQ1_STAT_REG 0x58
> +#define PWR_EVNT_IRQ2_STAT_REG 0x1dc
> +#define PWR_EVNT_IRQ3_STAT_REG 0x228
> +#define PWR_EVNT_IRQ4_STAT_REG 0x238
> +
> #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
> #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
>
> @@ -107,6 +111,19 @@ struct dwc3_qcom {
> int num_ports;
> };
>
> +/*
> + * SA8295 has 4 power event IRQ STAT registers to be checked
> + * during suspend resume.
> + */
But this driver supports much more than just SA8295?
> +#define NUM_PWR_EVENT_STAT_REGS 4
> +
> +static u32 pwr_evnt_irq_stat_reg_offset[NUM_PWR_EVENT_STAT_REGS] = {
> + PWR_EVNT_IRQ1_STAT_REG,
> + PWR_EVNT_IRQ2_STAT_REG,
> + PWR_EVNT_IRQ3_STAT_REG,
> + PWR_EVNT_IRQ4_STAT_REG,
> +};
> +
> static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
> {
> u32 reg;
> @@ -440,15 +457,19 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
>
> static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> {
> + u8 num_ports;
Maybe I'm picky, but I'm not sure defining a variable for
a single use of an object with a rather short name
(qcom->num_ports) is justified, here and below..
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 10/13] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper
2023-09-15 13:48 ` Konrad Dybcio
@ 2023-09-18 7:42 ` Krishna Kurapati PSSNV
0 siblings, 0 replies; 37+ messages in thread
From: Krishna Kurapati PSSNV @ 2023-09-18 7:42 UTC (permalink / raw)
To: Konrad Dybcio, Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel,
Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 9/15/2023 7:18 PM, Konrad Dybcio wrote:
>>
>> -#define PWR_EVNT_IRQ_STAT_REG 0x58
>> +#define PWR_EVNT_IRQ1_STAT_REG 0x58
>> +#define PWR_EVNT_IRQ2_STAT_REG 0x1dc
>> +#define PWR_EVNT_IRQ3_STAT_REG 0x228
>> +#define PWR_EVNT_IRQ4_STAT_REG 0x238
>> +
>> #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
>> #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
>>
>> @@ -107,6 +111,19 @@ struct dwc3_qcom {
>> int num_ports;
>> };
>>
>> +/*
>> + * SA8295 has 4 power event IRQ STAT registers to be checked
>> + * during suspend resume.
>> + */
> But this driver supports much more than just SA8295?
>
Yes. Other than SA8295, all single port controllers and SA8195(2 port
controller), have these reigsters.
The rational behind adding this array was that depending on num_ports,
any controller can access its required pwr_event_irq_stat register and
loop in the suspend/resume code would take care of it. Perhaps I can
change the comments to indicate that the array would be used by all
controllers and not just SA8295.
>> +#define NUM_PWR_EVENT_STAT_REGS 4
>> +
>> +static u32 pwr_evnt_irq_stat_reg_offset[NUM_PWR_EVENT_STAT_REGS] = {
>> + PWR_EVNT_IRQ1_STAT_REG,
>> + PWR_EVNT_IRQ2_STAT_REG,
>> + PWR_EVNT_IRQ3_STAT_REG,
>> + PWR_EVNT_IRQ4_STAT_REG,
>> +};
>> +
>> static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
>> {
>> u32 reg;
>> @@ -440,15 +457,19 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
>>
>> static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
>> {
>> + u8 num_ports;
> Maybe I'm picky, but I'm not sure defining a variable for
> a single use of an object with a rather short name
> (qcom->num_ports) is justified, here and below..
>
Sure, will replace num_ports with (qcom->num_ports) and remove the extra
variable.
Regards,
Krishna,
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller
2023-08-28 13:30 ` [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller Krishna Kurapati
2023-09-01 1:13 ` Wesley Cheng
@ 2023-09-19 17:26 ` kernel test robot
2023-10-02 17:19 ` Thinh Nguyen
2 siblings, 0 replies; 37+ messages in thread
From: kernel test robot @ 2023-09-19 17:26 UTC (permalink / raw)
To: Krishna Kurapati, Thinh Nguyen, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Felipe Balbi, Wesley Cheng,
Johan Hovold, Mathias Nyman
Cc: oe-kbuild-all, linux-usb, linux-kernel, linux-arm-msm,
devicetree, quic_pkondeti, quic_ppratap, quic_jackp, ahalaney,
quic_shazhuss, Harsh Agarwal, Krishna Kurapati
Hi Krishna,
kernel test robot noticed the following build warnings:
[auto build test WARNING on usb/usb-testing]
[also build test WARNING on usb/usb-next usb/usb-linus robh/for-next pza/reset/next linus/master v6.6-rc2 next-20230919]
[cannot apply to pza/imx-drm/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Krishna-Kurapati/dt-bindings-usb-qcom-dwc3-Add-bindings-for-SC8280-Multiport/20230828-214326
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-testing
patch link: https://lore.kernel.org/r/20230828133033.11988-7-quic_kriskura%40quicinc.com
patch subject: [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller
config: x86_64-randconfig-011-20230902 (https://download.01.org/0day-ci/archive/20230920/202309200156.CxQ3yaLY-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230920/202309200156.CxQ3yaLY-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309200156.CxQ3yaLY-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/usb/dwc3/core.c: In function 'dwc3_core_get_phy':
>> drivers/usb/dwc3/core.c:1375:53: warning: '%d' directive writing between 1 and 3 bytes into a region of size 2 [-Wformat-overflow=]
1375 | sprintf(phy_name, "usb2-port%d", i);
| ^~
drivers/usb/dwc3/core.c:1375:43: note: directive argument in the range [0, 254]
1375 | sprintf(phy_name, "usb2-port%d", i);
| ^~~~~~~~~~~~~
drivers/usb/dwc3/core.c:1375:25: note: 'sprintf' output between 11 and 13 bytes into a destination of size 11
1375 | sprintf(phy_name, "usb2-port%d", i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/usb/dwc3/core.c:1390:53: warning: '%d' directive writing between 1 and 3 bytes into a region of size 2 [-Wformat-overflow=]
1390 | sprintf(phy_name, "usb3-port%d", i);
| ^~
drivers/usb/dwc3/core.c:1390:43: note: directive argument in the range [0, 254]
1390 | sprintf(phy_name, "usb3-port%d", i);
| ^~~~~~~~~~~~~
drivers/usb/dwc3/core.c:1390:25: note: 'sprintf' output between 11 and 13 bytes into a destination of size 11
1390 | sprintf(phy_name, "usb3-port%d", i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +1375 drivers/usb/dwc3/core.c
1338
1339 static int dwc3_core_get_phy(struct dwc3 *dwc)
1340 {
1341 struct device *dev = dwc->dev;
1342 struct device_node *node = dev->of_node;
1343 char phy_name[11];
1344 int ret;
1345 int i;
1346
1347 if (node) {
1348 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1349 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1350 } else {
1351 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1352 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1353 }
1354
1355 if (IS_ERR(dwc->usb2_phy)) {
1356 ret = PTR_ERR(dwc->usb2_phy);
1357 if (ret == -ENXIO || ret == -ENODEV)
1358 dwc->usb2_phy = NULL;
1359 else
1360 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1361 }
1362
1363 if (IS_ERR(dwc->usb3_phy)) {
1364 ret = PTR_ERR(dwc->usb3_phy);
1365 if (ret == -ENXIO || ret == -ENODEV)
1366 dwc->usb3_phy = NULL;
1367 else
1368 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1369 }
1370
1371 for (i = 0; i < dwc->num_usb2_ports; i++) {
1372 if (dwc->num_usb2_ports == 1)
1373 sprintf(phy_name, "usb2-phy");
1374 else
> 1375 sprintf(phy_name, "usb2-port%d", i);
1376
1377 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
1378 if (IS_ERR(dwc->usb2_generic_phy[i])) {
1379 ret = PTR_ERR(dwc->usb2_generic_phy[i]);
1380 if (ret == -ENOSYS || ret == -ENODEV)
1381 dwc->usb2_generic_phy[i] = NULL;
1382 else
1383 return dev_err_probe(dev, ret,
1384 "failed to lookup phy %s\n", phy_name);
1385 }
1386
1387 if (dwc->num_usb2_ports == 1)
1388 sprintf(phy_name, "usb3-phy");
1389 else
1390 sprintf(phy_name, "usb3-port%d", i);
1391
1392 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
1393 if (IS_ERR(dwc->usb3_generic_phy[i])) {
1394 ret = PTR_ERR(dwc->usb3_generic_phy[i]);
1395 if (ret == -ENOSYS || ret == -ENODEV)
1396 dwc->usb3_generic_phy[i] = NULL;
1397 else
1398 return dev_err_probe(dev, ret,
1399 "failed to lookup phy %s\n", phy_name);
1400 }
1401 }
1402
1403 return 0;
1404 }
1405
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 07/13] usb: dwc3: qcom: Add helper function to request threaded IRQ
2023-08-28 13:30 ` [PATCH v11 07/13] usb: dwc3: qcom: Add helper function to request threaded IRQ Krishna Kurapati
@ 2023-09-28 21:48 ` Bjorn Andersson
0 siblings, 0 replies; 37+ messages in thread
From: Bjorn Andersson @ 2023-09-28 21:48 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman,
linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On Mon, Aug 28, 2023 at 07:00:27PM +0530, Krishna Kurapati wrote:
> Cleanup setup irq call by implementing a new prep_irq helper function
> and using it to request threaded IRQ's.
>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 63 +++++++++++++++++-------------------
> 1 file changed, 30 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index 3de43df6bbe8..f14ddc9c541d 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -535,6 +535,24 @@ static int dwc3_qcom_get_irq(struct platform_device *pdev,
> return ret;
> }
>
> +static int dwc3_qcom_prep_irq(struct dwc3_qcom *qcom, char *irq_name,
> + char *disp_name, int irq)
> +{
> + int ret;
> +
> + /* Keep wakeup interrupts disabled until suspend */
> + irq_set_status_flags(irq, IRQ_NOAUTOEN);
> + ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
> + qcom_dwc3_resume_irq,
> + IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
> + disp_name, qcom);
> +
> + if (ret)
> + dev_err(qcom->dev, "%s failed: %d\n", irq_name, ret);
> +
> + return ret;
> +}
> +
> static int dwc3_qcom_setup_irq(struct platform_device *pdev)
> {
> struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
> @@ -545,61 +563,40 @@ static int dwc3_qcom_setup_irq(struct platform_device *pdev)
> irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
> pdata ? pdata->hs_phy_irq_index : -1);
> if (irq > 0) {
> - /* Keep wakeup interrupts disabled until suspend */
> - irq_set_status_flags(irq, IRQ_NOAUTOEN);
> - ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
> - qcom_dwc3_resume_irq,
> - IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
> - "qcom_dwc3 HS", qcom);
> - if (ret) {
> - dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
> + ret = dwc3_qcom_prep_irq(qcom, "hs_phy_irq",
> + "qcom_dwc3 HS", irq);
Please leave these lines unwrapped.
Nice cleanup.
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Regards,
Bjorn
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller
2023-09-14 15:45 ` Krishna Kurapati PSSNV
@ 2023-10-02 9:47 ` Konrad Dybcio
0 siblings, 0 replies; 37+ messages in thread
From: Konrad Dybcio @ 2023-10-02 9:47 UTC (permalink / raw)
To: Krishna Kurapati PSSNV, Thinh Nguyen, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Felipe Balbi, Wesley Cheng, Johan Hovold,
Mathias Nyman
Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
On 9/14/23 17:45, Krishna Kurapati PSSNV wrote:
>
>
> On 9/13/2023 5:40 PM, Konrad Dybcio wrote:
>> On 7.09.2023 05:36, Krishna Kurapati PSSNV wrote:
>>>
>>>
>>>> Is there any benefit to removing the other ports?
>>>>
>>>> i.e. are ports 1-3 not parked properly by the dwc3 driver if
>>>> they're never connected to anything?
>>>>
>>> Hi Konrad,
>>>
>>> Whether or not the phy is connected to a port, the controller would
>>> modify the GUSB2PHYCFG/GUSB3PIPECTL registers. But if we don't
>>> specify only one phy and let phys from base DTSI take effect (4 HS /
>>> 2 SS), we would end up initializing and powering on phy's which are
>>> never connected to a port. To avoid that we need to specify only one
>>> phy for this platform.
>> And does that have any major effect on power use?
>>
>> Do these PHYs not have some dormant/low power mode?
>>
> Hi Konrad,
>
> I believe there will be some minimal power use. IMO its best to keep
> only one phy enabled for this variant instead of giving all and
> initializing/powering-on all 4 of them.
Okay let's not waste power..
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 04/13] usb: dwc3: core: Access XHCI address space temporarily to read port info
2023-08-28 13:30 ` [PATCH v11 04/13] usb: dwc3: core: Access XHCI address space temporarily to read port info Krishna Kurapati
@ 2023-10-02 17:10 ` Thinh Nguyen
0 siblings, 0 replies; 37+ messages in thread
From: Thinh Nguyen @ 2023-10-02 17:10 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman,
linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss
Sorry for the delay,
On Mon, Aug 28, 2023, Krishna Kurapati wrote:
> Currently host-only capable DWC3 controllers support Multiport.
> Temporarily map XHCI address space for host-only controllers and parse
> XHCI Extended Capabilities registers to read number of usb2 ports and
> usb3 ports present on multiport controller. Each USB Port is at least HS
> capable.
>
> The port info for usb2 and usb3 phy are identified as num_usb2_ports
> and num_usb3_ports. The intention is as follows:
>
> Wherever we need to perform phy operations like:
>
> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> {
> phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> }
>
> If number of usb2 ports is 3, loop can go from index 0-2 for
> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> if the first 2 ports are SS capable or some other ports like (2 and 3)
> are SS capable. So instead, num_usb2_ports is used to loop around all
> phy's (both hs and ss) for performing phy operations. If any
> usb3_generic_phy turns out to be NULL, phy operation just bails out.
>
> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> phy's as we need to know how many SS capable ports are there for this.
>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> drivers/usb/dwc3/core.c | 61 +++++++++++++++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 5 ++++
> 2 files changed, 66 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 9c6bf054f15d..85cebeb6d662 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -39,6 +39,7 @@
> #include "io.h"
>
> #include "debug.h"
> +#include "../host/xhci-ext-caps.h"
>
> #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
>
> @@ -1751,6 +1752,51 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
> return 0;
> }
>
> +static int dwc3_read_port_info(struct dwc3 *dwc)
> +{
> + void __iomem *base;
> + u8 major_revision;
> + u32 offset = 0;
> + u32 val;
> +
> + /*
> + * Remap xHCI address space to access XHCI ext cap regs,
> + * since it is needed to get port info.
> + */
> + base = ioremap(dwc->xhci_resources[0].start,
> + resource_size(&dwc->xhci_resources[0]));
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + do {
> + offset = xhci_find_next_ext_cap(base, offset,
> + XHCI_EXT_CAPS_PROTOCOL);
> + if (!offset)
> + break;
> +
> + val = readl(base + offset);
> + major_revision = XHCI_EXT_PORT_MAJOR(val);
> +
> + val = readl(base + offset + 0x08);
> + if (major_revision == 0x03) {
> + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
> + } else if (major_revision <= 0x02) {
> + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
> + } else {
> + dev_err(dwc->dev,
> + "Unrecognized port major revision %d\n",
> + major_revision);
> + }
> + } while (1);
> +
> + dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
> + dwc->num_usb2_ports, dwc->num_usb3_ports);
> +
> + iounmap(base);
> +
> + return 0;
> +}
> +
> static int dwc3_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -1758,6 +1804,7 @@ static int dwc3_probe(struct platform_device *pdev)
> void __iomem *regs;
> struct dwc3 *dwc;
> int ret;
> + unsigned int hw_mode;
>
> dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
> if (!dwc)
> @@ -1838,6 +1885,20 @@ static int dwc3_probe(struct platform_device *pdev)
> goto err_disable_clks;
> }
>
> + /*
> + * Currently only DWC3 controllers that are host-only capable
> + * support Multiport.
> + */
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
> + ret = dwc3_read_port_info(dwc);
> + if (ret)
> + goto err_disable_clks;
> + } else {
> + dwc->num_usb2_ports = 1;
> + dwc->num_usb3_ports = 1;
> + }
> +
> spin_lock_init(&dwc->lock);
> mutex_init(&dwc->mutex);
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index a69ac67d89fe..5b0f2aa115d2 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -1026,6 +1026,8 @@ struct dwc3_scratchpad_array {
> * @usb3_phy: pointer to USB3 PHY
> * @usb2_generic_phy: pointer to USB2 PHY
> * @usb3_generic_phy: pointer to USB3 PHY
> + * @num_usb2_ports: number of USB2 ports
> + * @num_usb3_ports: number of USB3 ports
> * @phys_ready: flag to indicate that PHYs are ready
> * @ulpi: pointer to ulpi interface
> * @ulpi_ready: flag to indicate that ULPI is initialized
> @@ -1165,6 +1167,9 @@ struct dwc3 {
> struct phy *usb2_generic_phy;
> struct phy *usb3_generic_phy;
>
> + u8 num_usb2_ports;
> + u8 num_usb3_ports;
> +
> bool phys_ready;
>
> struct ulpi *ulpi;
> --
> 2.40.0
>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Thanks,
Thinh
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller
2023-08-28 13:30 ` [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller Krishna Kurapati
2023-09-01 1:13 ` Wesley Cheng
2023-09-19 17:26 ` kernel test robot
@ 2023-10-02 17:19 ` Thinh Nguyen
2 siblings, 0 replies; 37+ messages in thread
From: Thinh Nguyen @ 2023-10-02 17:19 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Johan Hovold, Mathias Nyman,
linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Harsh Agarwal
On Mon, Aug 28, 2023, Krishna Kurapati wrote:
> From: Harsh Agarwal <quic_harshq@quicinc.com>
>
> Currently the DWC3 driver supports only single port controller
> which requires at most one HS and one SS PHY.
>
> But the DWC3 USB controller can be connected to multiple ports and
> each port can have their own PHYs. Each port of the multiport
> controller can either be HS+SS capable or HS only capable
> Proper quantification of them is required to modify GUSB2PHYCFG
> and GUSB3PIPECTL registers appropriately.
>
> Add support for detecting, obtaining and configuring phy's supported
> by a multiport controller and. Limit the max number of ports
> supported to 4 as only SC8280 which is a quad port controller supports
> Multiport currently.
>
> Co-developed-by: Harsh Agarwal <quic_harshq@quicinc.com>
> Signed-off-by: Harsh Agarwal <quic_harshq@quicinc.com>
> Co-developed-by:Krishna Kurapati <quic_kriskura@quicinc.com>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> drivers/usb/dwc3/core.c | 252 +++++++++++++++++++++++++++-------------
> drivers/usb/dwc3/core.h | 11 +-
> drivers/usb/dwc3/drd.c | 15 ++-
> 3 files changed, 190 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 6eacf0ff90b5..31400c309bff 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -124,6 +124,7 @@ static void __dwc3_set_mode(struct work_struct *work)
> int ret;
> u32 reg;
> u32 desired_dr_role;
> + int i;
>
> mutex_lock(&dwc->mutex);
> spin_lock_irqsave(&dwc->lock, flags);
> @@ -201,8 +202,10 @@ static void __dwc3_set_mode(struct work_struct *work)
> } else {
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, true);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> + }
> if (dwc->dis_split_quirk) {
> reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
> reg |= DWC3_GUCTL3_SPLITDISABLE;
> @@ -217,8 +220,8 @@ static void __dwc3_set_mode(struct work_struct *work)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, false);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
>
> ret = dwc3_gadget_init(dwc);
> if (ret)
> @@ -589,22 +592,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc)
> return ret;
> }
>
> -/**
> - * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
> - * @dwc: Pointer to our controller context structure
> - *
> - * Returns 0 on success. The USB PHY interfaces are configured but not
> - * initialized. The PHY interfaces and the PHYs get initialized together with
> - * the core in dwc3_core_init.
> - */
> -static int dwc3_phy_setup(struct dwc3 *dwc)
> +static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
> {
> unsigned int hw_mode;
> u32 reg;
>
> hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
>
> /*
> * Make sure UX_EXIT_PX is cleared as that causes issues with some
> @@ -659,9 +654,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> if (dwc->dis_del_phy_power_chg_quirk)
> reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
>
> - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
>
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> + return 0;
> +}
> +
> +static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
> +{
> + unsigned int hw_mode;
> + u32 reg;
> +
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> +
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
>
> /* Select the HS PHY interface */
> switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
> @@ -673,7 +678,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> } else if (dwc->hsphy_interface &&
> !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
> reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
> } else {
> /* Relying on default value. */
> if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
> @@ -740,7 +745,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> if (dwc->ulpi_ext_vbus_drv)
> reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
>
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
> +
> + return 0;
> +}
> +
> +/**
> + * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
> + * @dwc: Pointer to our controller context structure
> + *
> + * Returns 0 on success. The USB PHY interfaces are configured but not
> + * initialized. The PHY interfaces and the PHYs get initialized together with
> + * the core in dwc3_core_init.
> + */
> +static int dwc3_phy_setup(struct dwc3 *dwc)
> +{
> + int i;
> + int ret;
> +
> + for (i = 0; i < dwc->num_usb3_ports; i++) {
> + ret = dwc3_ss_phy_setup(dwc, i);
> + if (ret)
> + return ret;
> + }
> +
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = dwc3_hs_phy_setup(dwc, i);
> + if (ret)
> + return ret;
> + }
>
> return 0;
> }
> @@ -748,23 +781,32 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> static int dwc3_phy_init(struct dwc3 *dwc)
> {
> int ret;
> + int i;
> + int j;
>
> usb_phy_init(dwc->usb2_phy);
> usb_phy_init(dwc->usb3_phy);
>
> - ret = phy_init(dwc->usb2_generic_phy);
> - if (ret < 0)
> - goto err_shutdown_usb3_phy;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = phy_init(dwc->usb2_generic_phy[i]);
> + if (ret < 0)
> + goto err_exit_phy;
>
> - ret = phy_init(dwc->usb3_generic_phy);
> - if (ret < 0)
> - goto err_exit_usb2_phy;
> + ret = phy_init(dwc->usb3_generic_phy[i]);
> + if (ret < 0) {
> + phy_exit(dwc->usb2_generic_phy[i]);
> + goto err_exit_phy;
> + }
> + }
>
> return 0;
>
> -err_exit_usb2_phy:
> - phy_exit(dwc->usb2_generic_phy);
> -err_shutdown_usb3_phy:
> +err_exit_phy:
> + for (j = i - 1; j >= 0; j--) {
> + phy_exit(dwc->usb2_generic_phy[j]);
> + phy_exit(dwc->usb3_generic_phy[j]);
> + }
> +
> usb_phy_shutdown(dwc->usb3_phy);
> usb_phy_shutdown(dwc->usb2_phy);
>
> @@ -773,8 +815,12 @@ static int dwc3_phy_init(struct dwc3 *dwc)
>
> static void dwc3_phy_exit(struct dwc3 *dwc)
> {
> - phy_exit(dwc->usb3_generic_phy);
> - phy_exit(dwc->usb2_generic_phy);
> + int i;
> +
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_exit(dwc->usb3_generic_phy[i]);
> + phy_exit(dwc->usb2_generic_phy[i]);
> + }
>
> usb_phy_shutdown(dwc->usb3_phy);
> usb_phy_shutdown(dwc->usb2_phy);
> @@ -783,23 +829,32 @@ static void dwc3_phy_exit(struct dwc3 *dwc)
> static int dwc3_phy_power_on(struct dwc3 *dwc)
> {
> int ret;
> + int i;
> + int j;
>
> usb_phy_set_suspend(dwc->usb2_phy, 0);
> usb_phy_set_suspend(dwc->usb3_phy, 0);
>
> - ret = phy_power_on(dwc->usb2_generic_phy);
> - if (ret < 0)
> - goto err_suspend_usb3_phy;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = phy_power_on(dwc->usb2_generic_phy[i]);
> + if (ret < 0)
> + goto err_power_off_phy;
>
> - ret = phy_power_on(dwc->usb3_generic_phy);
> - if (ret < 0)
> - goto err_power_off_usb2_phy;
> + ret = phy_power_on(dwc->usb3_generic_phy[i]);
> + if (ret < 0) {
> + phy_power_off(dwc->usb2_generic_phy[i]);
> + goto err_power_off_phy;
> + }
> + }
>
> return 0;
>
> -err_power_off_usb2_phy:
> - phy_power_off(dwc->usb2_generic_phy);
> -err_suspend_usb3_phy:
> +err_power_off_phy:
> + for (j = i - 1; j >= 0; j--) {
> + phy_power_off(dwc->usb2_generic_phy[j]);
> + phy_power_off(dwc->usb3_generic_phy[j]);
> + }
> +
> usb_phy_set_suspend(dwc->usb3_phy, 1);
> usb_phy_set_suspend(dwc->usb2_phy, 1);
>
> @@ -808,8 +863,12 @@ static int dwc3_phy_power_on(struct dwc3 *dwc)
>
> static void dwc3_phy_power_off(struct dwc3 *dwc)
> {
> - phy_power_off(dwc->usb3_generic_phy);
> - phy_power_off(dwc->usb2_generic_phy);
> + int i;
> +
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_power_off(dwc->usb3_generic_phy[i]);
> + phy_power_off(dwc->usb2_generic_phy[i]);
> + }
>
> usb_phy_set_suspend(dwc->usb3_phy, 1);
> usb_phy_set_suspend(dwc->usb2_phy, 1);
> @@ -1082,6 +1141,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> unsigned int hw_mode;
> u32 reg;
> int ret;
> + int i;
>
> hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>
> @@ -1125,15 +1185,19 @@ static int dwc3_core_init(struct dwc3 *dwc)
> if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
> !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
> if (!dwc->dis_u3_susphy_quirk) {
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> - reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
> + for (i = 0; i < dwc->num_usb3_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
> + reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
> + }
> }
>
> if (!dwc->dis_u2_susphy_quirk) {
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - reg |= DWC3_GUSB2PHYCFG_SUSPHY;
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> + reg |= DWC3_GUSB2PHYCFG_SUSPHY;
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> + }
> }
> }
>
> @@ -1276,7 +1340,9 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
> {
> struct device *dev = dwc->dev;
> struct device_node *node = dev->of_node;
> + char phy_name[11];
> int ret;
> + int i;
>
> if (node) {
> dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
> @@ -1302,22 +1368,36 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
> return dev_err_probe(dev, ret, "no usb3 phy configured\n");
> }
>
> - dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
> - if (IS_ERR(dwc->usb2_generic_phy)) {
> - ret = PTR_ERR(dwc->usb2_generic_phy);
> - if (ret == -ENOSYS || ret == -ENODEV)
> - dwc->usb2_generic_phy = NULL;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + if (dwc->num_usb2_ports == 1)
> + sprintf(phy_name, "usb2-phy");
> else
> - return dev_err_probe(dev, ret, "no usb2 phy configured\n");
> - }
> + sprintf(phy_name, "usb2-port%d", i);
>
> - dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
> - if (IS_ERR(dwc->usb3_generic_phy)) {
> - ret = PTR_ERR(dwc->usb3_generic_phy);
> - if (ret == -ENOSYS || ret == -ENODEV)
> - dwc->usb3_generic_phy = NULL;
> + dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
> + if (IS_ERR(dwc->usb2_generic_phy[i])) {
> + ret = PTR_ERR(dwc->usb2_generic_phy[i]);
> + if (ret == -ENOSYS || ret == -ENODEV)
> + dwc->usb2_generic_phy[i] = NULL;
> + else
> + return dev_err_probe(dev, ret,
> + "failed to lookup phy %s\n", phy_name);
> + }
> +
> + if (dwc->num_usb2_ports == 1)
> + sprintf(phy_name, "usb3-phy");
> else
> - return dev_err_probe(dev, ret, "no usb3 phy configured\n");
> + sprintf(phy_name, "usb3-port%d", i);
> +
> + dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
> + if (IS_ERR(dwc->usb3_generic_phy[i])) {
> + ret = PTR_ERR(dwc->usb3_generic_phy[i]);
> + if (ret == -ENOSYS || ret == -ENODEV)
> + dwc->usb3_generic_phy[i] = NULL;
> + else
> + return dev_err_probe(dev, ret,
> + "failed to lookup phy %s\n", phy_name);
> + }
> }
>
> return 0;
> @@ -1327,6 +1407,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
> {
> struct device *dev = dwc->dev;
> int ret;
> + int i;
>
> switch (dwc->dr_mode) {
> case USB_DR_MODE_PERIPHERAL:
> @@ -1334,8 +1415,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, false);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
>
> ret = dwc3_gadget_init(dwc);
> if (ret)
> @@ -1346,8 +1427,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, true);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> + }
>
> ret = dwc3_host_init(dwc);
> if (ret)
> @@ -1804,9 +1887,12 @@ static int dwc3_read_port_info(struct dwc3 *dwc)
>
> dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
> dwc->num_usb2_ports, dwc->num_usb3_ports);
> -
> iounmap(base);
>
> + if ((dwc->num_usb2_ports > DWC3_MAX_PORTS) ||
> + (dwc->num_usb3_ports > DWC3_MAX_PORTS))
> + return -ENOMEM;
> +
> return 0;
> }
>
> @@ -2042,6 +2128,7 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
> {
> unsigned long flags;
> u32 reg;
> + int i;
>
> switch (dwc->current_dr_role) {
> case DWC3_GCTL_PRTCAP_DEVICE:
> @@ -2060,17 +2147,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
> /* Let controller to suspend HSPHY before PHY driver suspends */
> if (dwc->dis_u2_susphy_quirk ||
> dwc->dis_enblslpm_quirk) {
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
> - DWC3_GUSB2PHYCFG_SUSPHY;
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> + reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
> + DWC3_GUSB2PHYCFG_SUSPHY;
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> + }
>
> /* Give some time for USB2 PHY to suspend */
> usleep_range(5000, 6000);
> }
>
> - phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
> - phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
> + phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
> + }
> break;
> case DWC3_GCTL_PRTCAP_OTG:
> /* do nothing during runtime_suspend */
> @@ -2100,6 +2191,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
> unsigned long flags;
> int ret;
> u32 reg;
> + int i;
>
> switch (dwc->current_dr_role) {
> case DWC3_GCTL_PRTCAP_DEVICE:
> @@ -2119,17 +2211,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
> break;
> }
> /* Restore GUSB2PHYCFG bits that were modified in suspend */
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - if (dwc->dis_u2_susphy_quirk)
> - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> + if (dwc->dis_u2_susphy_quirk)
> + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
>
> - if (dwc->dis_enblslpm_quirk)
> - reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
> + if (dwc->dis_enblslpm_quirk)
> + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
>
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> + }
>
> - phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
> - phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
> + phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
> + }
> break;
> case DWC3_GCTL_PRTCAP_OTG:
> /* nothing to do on runtime_resume */
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 5b0f2aa115d2..5521dc9ca034 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -33,6 +33,9 @@
>
> #include <linux/power_supply.h>
>
> +/* Number of ports supported by a multiport controller */
> +#define DWC3_MAX_PORTS 4
> +
> #define DWC3_MSG_MAX 500
>
> /* Global constants */
> @@ -1024,8 +1027,8 @@ struct dwc3_scratchpad_array {
> * @usb_psy: pointer to power supply interface.
> * @usb2_phy: pointer to USB2 PHY
> * @usb3_phy: pointer to USB3 PHY
> - * @usb2_generic_phy: pointer to USB2 PHY
> - * @usb3_generic_phy: pointer to USB3 PHY
> + * @usb2_generic_phy: pointer to array of USB2 PHY
> + * @usb3_generic_phy: pointer to array of USB3 PHY
> * @num_usb2_ports: number of USB2 ports
> * @num_usb3_ports: number of USB3 ports
> * @phys_ready: flag to indicate that PHYs are ready
> @@ -1164,8 +1167,8 @@ struct dwc3 {
> struct usb_phy *usb2_phy;
> struct usb_phy *usb3_phy;
>
> - struct phy *usb2_generic_phy;
> - struct phy *usb3_generic_phy;
> + struct phy *usb2_generic_phy[DWC3_MAX_PORTS];
> + struct phy *usb3_generic_phy[DWC3_MAX_PORTS];
>
> u8 num_usb2_ports;
> u8 num_usb3_ports;
> diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
> index 039bf241769a..9aec41f1ad43 100644
> --- a/drivers/usb/dwc3/drd.c
> +++ b/drivers/usb/dwc3/drd.c
> @@ -331,6 +331,7 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
> u32 reg;
> int id;
> unsigned long flags;
> + int i;
>
> if (dwc->dr_mode != USB_DR_MODE_OTG)
> return;
> @@ -386,9 +387,12 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
> } else {
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, true);
> - if (dwc->usb2_generic_phy)
> - phy_set_mode(dwc->usb2_generic_phy,
> - PHY_MODE_USB_HOST);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + if (dwc->usb2_generic_phy[i]) {
> + phy_set_mode(dwc->usb2_generic_phy[i],
> + PHY_MODE_USB_HOST);
> + }
> + }
> }
> break;
> case DWC3_OTG_ROLE_DEVICE:
> @@ -400,9 +404,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, false);
> - if (dwc->usb2_generic_phy)
> - phy_set_mode(dwc->usb2_generic_phy,
> - PHY_MODE_USB_DEVICE);
> + if (dwc->usb2_generic_phy[0])
> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
> ret = dwc3_gadget_init(dwc);
> if (ret)
> dev_err(dwc->dev, "failed to initialize peripheral\n");
> --
> 2.40.0
>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Thanks,
Thinh
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 00/13] Add multiport support for DWC3 controllers
[not found] ` <0814b6a2-c52d-4be2-ae06-8391767ac144@quicinc.com>
@ 2023-10-04 7:40 ` Krishna Kurapati PSSNV
2023-10-04 12:22 ` Greg Kroah-Hartman
0 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati PSSNV @ 2023-10-04 7:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Thinh Nguyen; +Cc: Jack Pham, Wesley Cheng, linux-usb
Hi Greg,
Thanks for picking first 3 patches into usb-testing branch.
Can you help pick patches 4/5 of this series as well into usb-testing
(I checked and they apply cleanly) so that I can fix comments and rebase
patches starting from 6 to 13 in my v12.
Patch 4 been approved yesterday by Thinh and so far no kernel build
bot has reported issues on these 2 patches for any configs (on v9 / v10
/ v11).
Regards,
Krishna,
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 00/13] Add multiport support for DWC3 controllers
2023-10-04 7:40 ` [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati PSSNV
@ 2023-10-04 12:22 ` Greg Kroah-Hartman
0 siblings, 0 replies; 37+ messages in thread
From: Greg Kroah-Hartman @ 2023-10-04 12:22 UTC (permalink / raw)
To: Krishna Kurapati PSSNV; +Cc: Thinh Nguyen, Jack Pham, Wesley Cheng, linux-usb
On Wed, Oct 04, 2023 at 01:10:29PM +0530, Krishna Kurapati PSSNV wrote:
> Hi Greg,
>
> Thanks for picking first 3 patches into usb-testing branch.
>
> Can you help pick patches 4/5 of this series as well into usb-testing (I
> checked and they apply cleanly) so that I can fix comments and rebase
> patches starting from 6 to 13 in my v12.
>
> Patch 4 been approved yesterday by Thinh and so far no kernel build bot has
> reported issues on these 2 patches for any configs (on v9 / v10 / v11).
It's hard to pick up individual patches, especially with acks from
others. Please just send that one alone with the reviewed-by and I can
pick it up that way.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller
2023-08-28 13:30 ` [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller Krishna Kurapati
@ 2023-11-10 13:28 ` Johan Hovold
2023-11-11 8:30 ` Krishna Kurapati PSSNV
0 siblings, 1 reply; 37+ messages in thread
From: Johan Hovold @ 2023-11-10 13:28 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Thinh Nguyen, Greg Kroah-Hartman, Philipp Zabel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Felipe Balbi, Wesley Cheng, Mathias Nyman, linux-usb,
linux-kernel, linux-arm-msm, devicetree, quic_pkondeti,
quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Bjorn Andersson, Rob Herring
On Mon, Aug 28, 2023 at 07:00:22PM +0530, Krishna Kurapati wrote:
> Add bindings to indicate properties required to support multiport
> on Synopsys DWC3 controller.
>
> Suggested-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> index a696f23730d3..5bc941355b43 100644
> --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> @@ -85,15 +85,16 @@ properties:
>
> phys:
> minItems: 1
> - maxItems: 2
> + maxItems: 8
>
> phy-names:
> minItems: 1
> - maxItems: 2
> - items:
> - enum:
> - - usb2-phy
> - - usb3-phy
> + maxItems: 8
> + oneOf:
> + - items:
> + enum: [ usb2-phy, usb3-phy ]
> + - items:
> + pattern: "^usb[23]-port[0-3]$"
Shouldn't this just be
pattern: "^usb[23]-[0-3]$"
so that it matches the names that are used by the nvidia bindings?
We already have some inconsistency in that Amlogic uses a variant based
on the legacy names that needlessly includes "phy" in the names:
const: usb2-phy0
const: usb2-phy1
const: usb3-phy0
...
I don't think we should be introducing a third naming scheme here so I
suggest just following the nvidia bindings.
Johan
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller
2023-11-10 13:28 ` Johan Hovold
@ 2023-11-11 8:30 ` Krishna Kurapati PSSNV
2023-11-11 9:47 ` Krishna Kurapati PSSNV
0 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati PSSNV @ 2023-11-11 8:30 UTC (permalink / raw)
To: Johan Hovold, Thinh Nguyen
Cc: Greg Kroah-Hartman, Philipp Zabel, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Felipe Balbi,
Wesley Cheng, Mathias Nyman, linux-usb, linux-kernel,
linux-arm-msm, devicetree, quic_pkondeti, quic_ppratap,
quic_jackp, ahalaney, quic_shazhuss, Bjorn Andersson,
Rob Herring
On 11/10/2023 6:58 PM, Johan Hovold wrote:
> On Mon, Aug 28, 2023 at 07:00:22PM +0530, Krishna Kurapati wrote:
>> Add bindings to indicate properties required to support multiport
>> on Synopsys DWC3 controller.
>>
>> Suggested-by: Bjorn Andersson <quic_bjorande@quicinc.com>
>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> ---
>> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------
>> 1 file changed, 7 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>> index a696f23730d3..5bc941355b43 100644
>> --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>> @@ -85,15 +85,16 @@ properties:
>>
>> phys:
>> minItems: 1
>> - maxItems: 2
>> + maxItems: 8
>>
>> phy-names:
>> minItems: 1
>> - maxItems: 2
>> - items:
>> - enum:
>> - - usb2-phy
>> - - usb3-phy
>> + maxItems: 8
>> + oneOf:
>> + - items:
>> + enum: [ usb2-phy, usb3-phy ]
>> + - items:
>> + pattern: "^usb[23]-port[0-3]$"
>
> Shouldn't this just be
>
> pattern: "^usb[23]-[0-3]$"
>
> so that it matches the names that are used by the nvidia bindings?
>
> We already have some inconsistency in that Amlogic uses a variant based
> on the legacy names that needlessly includes "phy" in the names:
>
> const: usb2-phy0
> const: usb2-phy1
> const: usb3-phy0
> ...
>
> I don't think we should be introducing a third naming scheme here so I
> suggest just following the nvidia bindings.
>
In that case, why don't we use "^usb[23]-phy[0-3]$". I think its close
to what we have on dwc3 core already today (usb2-phy/usb3-phy).
Regards,
Krishna,
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller
2023-11-11 8:30 ` Krishna Kurapati PSSNV
@ 2023-11-11 9:47 ` Krishna Kurapati PSSNV
2023-11-11 10:55 ` Johan Hovold
0 siblings, 1 reply; 37+ messages in thread
From: Krishna Kurapati PSSNV @ 2023-11-11 9:47 UTC (permalink / raw)
To: Johan Hovold, Thinh Nguyen, Krzysztof Kozlowski
Cc: Greg Kroah-Hartman, Philipp Zabel, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Felipe Balbi, Wesley Cheng,
Mathias Nyman, linux-usb, linux-kernel, linux-arm-msm,
devicetree, quic_pkondeti, quic_ppratap, quic_jackp, ahalaney,
quic_shazhuss, Bjorn Andersson, Rob Herring
On 11/11/2023 2:00 PM, Krishna Kurapati PSSNV wrote:
>
>
> On 11/10/2023 6:58 PM, Johan Hovold wrote:
>> On Mon, Aug 28, 2023 at 07:00:22PM +0530, Krishna Kurapati wrote:
>>> Add bindings to indicate properties required to support multiport
>>> on Synopsys DWC3 controller.
>>>
>>> Suggested-by: Bjorn Andersson <quic_bjorande@quicinc.com>
>>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> ---
>>> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------
>>> 1 file changed, 7 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>>> b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>>> index a696f23730d3..5bc941355b43 100644
>>> --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>>> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>>> @@ -85,15 +85,16 @@ properties:
>>> phys:
>>> minItems: 1
>>> - maxItems: 2
>>> + maxItems: 8
>>> phy-names:
>>> minItems: 1
>>> - maxItems: 2
>>> - items:
>>> - enum:
>>> - - usb2-phy
>>> - - usb3-phy
>>> + maxItems: 8
>>> + oneOf:
>>> + - items:
>>> + enum: [ usb2-phy, usb3-phy ]
>>> + - items:
>>> + pattern: "^usb[23]-port[0-3]$"
>>
>> Shouldn't this just be
>>
>> pattern: "^usb[23]-[0-3]$"
>>
>> so that it matches the names that are used by the nvidia bindings?
>>
>> We already have some inconsistency in that Amlogic uses a variant based
>> on the legacy names that needlessly includes "phy" in the names:
>>
>> const: usb2-phy0
>> const: usb2-phy1
>> const: usb3-phy0
>> ...
>>
>> I don't think we should be introducing a third naming scheme here so I
>> suggest just following the nvidia bindings.
>> > In that case, why don't we use "^usb[23]-phy[0-3]$". I think its close
> to what we have on dwc3 core already today (usb2-phy/usb3-phy).
>
I mean, it isn't needless. It is a phy and shouldn't the binding suggest
that and include "-phy" in the name ?
Regards,
Krishna,
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller
2023-11-11 9:47 ` Krishna Kurapati PSSNV
@ 2023-11-11 10:55 ` Johan Hovold
2023-11-11 13:04 ` Krishna Kurapati PSSNV
0 siblings, 1 reply; 37+ messages in thread
From: Johan Hovold @ 2023-11-11 10:55 UTC (permalink / raw)
To: Krishna Kurapati PSSNV
Cc: Thinh Nguyen, Krzysztof Kozlowski, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Felipe Balbi, Wesley Cheng, Mathias Nyman,
linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Bjorn Andersson, Rob Herring
On Sat, Nov 11, 2023 at 03:17:40PM +0530, Krishna Kurapati PSSNV wrote:
> On 11/11/2023 2:00 PM, Krishna Kurapati PSSNV wrote:
> > On 11/10/2023 6:58 PM, Johan Hovold wrote:
> >>> phy-names:
> >>> minItems: 1
> >>> - maxItems: 2
> >>> - items:
> >>> - enum:
> >>> - - usb2-phy
> >>> - - usb3-phy
> >>> + maxItems: 8
> >>> + oneOf:
> >>> + - items:
> >>> + enum: [ usb2-phy, usb3-phy ]
> >>> + - items:
> >>> + pattern: "^usb[23]-port[0-3]$"
> >>
> >> Shouldn't this just be
> >>
> >> pattern: "^usb[23]-[0-3]$"
> >>
> >> so that it matches the names that are used by the nvidia bindings?
> >>
> >> We already have some inconsistency in that Amlogic uses a variant based
> >> on the legacy names that needlessly includes "phy" in the names:
> >>
> >> const: usb2-phy0
> >> const: usb2-phy1
> >> const: usb3-phy0
> >> ...
> >>
> >> I don't think we should be introducing a third naming scheme here so I
> >> suggest just following the nvidia bindings.
> >> > In that case, why don't we use "^usb[23]-phy[0-3]$". I think its close
> > to what we have on dwc3 core already today (usb2-phy/usb3-phy).
>
> I mean, it isn't needless. It is a phy and shouldn't the binding suggest
> that and include "-phy" in the name ?
No, adding a '-phy' suffix to each name is unnecessary since the
property is called 'phy-names'.
This is also documented:
For names used in {clock,dma,interrupt,reset}-names, do not add
any suffix, e.g.: "tx" instead of "txirq" (for interrupt).
https://docs.kernel.org/devicetree/bindings/writing-bindings.html
and we've already discussed this when I asked you to drop the likewise
redundant '_irq' suffix from the interrupt names.
Johan
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller
2023-11-11 10:55 ` Johan Hovold
@ 2023-11-11 13:04 ` Krishna Kurapati PSSNV
0 siblings, 0 replies; 37+ messages in thread
From: Krishna Kurapati PSSNV @ 2023-11-11 13:04 UTC (permalink / raw)
To: Johan Hovold
Cc: Thinh Nguyen, Krzysztof Kozlowski, Greg Kroah-Hartman,
Philipp Zabel, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Felipe Balbi, Wesley Cheng, Mathias Nyman,
linux-usb, linux-kernel, linux-arm-msm, devicetree,
quic_pkondeti, quic_ppratap, quic_jackp, ahalaney, quic_shazhuss,
Bjorn Andersson, Rob Herring
On 11/11/2023 4:25 PM, Johan Hovold wrote:
> On Sat, Nov 11, 2023 at 03:17:40PM +0530, Krishna Kurapati PSSNV wrote:
>> On 11/11/2023 2:00 PM, Krishna Kurapati PSSNV wrote:
>>> On 11/10/2023 6:58 PM, Johan Hovold wrote:
>
>>>>> phy-names:
>>>>> minItems: 1
>>>>> - maxItems: 2
>>>>> - items:
>>>>> - enum:
>>>>> - - usb2-phy
>>>>> - - usb3-phy
>>>>> + maxItems: 8
>>>>> + oneOf:
>>>>> + - items:
>>>>> + enum: [ usb2-phy, usb3-phy ]
>>>>> + - items:
>>>>> + pattern: "^usb[23]-port[0-3]$"
>>>>
>>>> Shouldn't this just be
>>>>
>>>> pattern: "^usb[23]-[0-3]$"
>>>>
>>>> so that it matches the names that are used by the nvidia bindings?
>>>>
>>>> We already have some inconsistency in that Amlogic uses a variant based
>>>> on the legacy names that needlessly includes "phy" in the names:
>>>>
>>>> const: usb2-phy0
>>>> const: usb2-phy1
>>>> const: usb3-phy0
>>>> ...
>>>>
>>>> I don't think we should be introducing a third naming scheme here so I
>>>> suggest just following the nvidia bindings.
>
>>>>> In that case, why don't we use "^usb[23]-phy[0-3]$". I think its close
>>> to what we have on dwc3 core already today (usb2-phy/usb3-phy).
>>
>> I mean, it isn't needless. It is a phy and shouldn't the binding suggest
>> that and include "-phy" in the name ?
>
> No, adding a '-phy' suffix to each name is unnecessary since the
> property is called 'phy-names'.
>
> This is also documented:
>
> For names used in {clock,dma,interrupt,reset}-names, do not add
> any suffix, e.g.: "tx" instead of "txirq" (for interrupt).
>
> https://docs.kernel.org/devicetree/bindings/writing-bindings.html
>
Thanks for the explanation.
> and we've already discussed this when I asked you to drop the likewise
> redundant '_irq' suffix from the interrupt names.
Yes, we did discuss this in irq context. But in this case I thought it
was fine because we already have usb(2/3)-"phy" already present.
When pushing v14, will make this change to usb(2/3)-(0-3) and skip port/phy.
Regards,
Krishna,
^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2023-11-11 13:05 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-28 13:30 [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 01/13] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 02/13] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller Krishna Kurapati
2023-11-10 13:28 ` Johan Hovold
2023-11-11 8:30 ` Krishna Kurapati PSSNV
2023-11-11 9:47 ` Krishna Kurapati PSSNV
2023-11-11 10:55 ` Johan Hovold
2023-11-11 13:04 ` Krishna Kurapati PSSNV
2023-08-28 13:30 ` [PATCH v11 03/13] usb: xhci: Move extcaps related macros to respective header file Krishna Kurapati
2023-09-07 12:25 ` Mathias Nyman
2023-08-28 13:30 ` [PATCH v11 04/13] usb: dwc3: core: Access XHCI address space temporarily to read port info Krishna Kurapati
2023-10-02 17:10 ` Thinh Nguyen
2023-08-28 13:30 ` [PATCH v11 05/13] usb: dwc3: core: Skip setting event buffers for host only controllers Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 06/13] usb: dwc3: core: Refactor PHY logic to support Multiport Controller Krishna Kurapati
2023-09-01 1:13 ` Wesley Cheng
2023-09-01 21:54 ` Krishna Kurapati PSSNV
2023-09-19 17:26 ` kernel test robot
2023-10-02 17:19 ` Thinh Nguyen
2023-08-28 13:30 ` [PATCH v11 07/13] usb: dwc3: qcom: Add helper function to request threaded IRQ Krishna Kurapati
2023-09-28 21:48 ` Bjorn Andersson
2023-08-28 13:30 ` [PATCH v11 08/13] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 09/13] usb: dwc3: qcom: Enable wakeup for applicable ports of multiport Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 10/13] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Krishna Kurapati
2023-09-15 13:48 ` Konrad Dybcio
2023-09-18 7:42 ` Krishna Kurapati PSSNV
2023-08-28 13:30 ` [PATCH v11 11/13] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 Krishna Kurapati
2023-08-28 13:30 ` [PATCH v11 12/13] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports Krishna Kurapati
2023-09-13 12:11 ` Konrad Dybcio
2023-09-14 15:44 ` Krishna Kurapati PSSNV
2023-08-28 13:30 ` [PATCH v11 13/13] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller Krishna Kurapati
2023-09-06 16:58 ` Konrad Dybcio
2023-09-07 3:36 ` Krishna Kurapati PSSNV
2023-09-13 12:10 ` Konrad Dybcio
2023-09-14 15:45 ` Krishna Kurapati PSSNV
2023-10-02 9:47 ` Konrad Dybcio
[not found] ` <0814b6a2-c52d-4be2-ae06-8391767ac144@quicinc.com>
2023-10-04 7:40 ` [PATCH v11 00/13] Add multiport support for DWC3 controllers Krishna Kurapati PSSNV
2023-10-04 12:22 ` Greg Kroah-Hartman
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.