* [PULL 0/4] target-arm queue @ 2023-11-13 17:46 Peter Maydell 2023-11-13 17:46 ` [PULL 1/4] hw/arm/virt: fix GIC maintenance IRQ registration Peter Maydell ` (4 more replies) 0 siblings, 5 replies; 12+ messages in thread From: Peter Maydell @ 2023-11-13 17:46 UTC (permalink / raw) To: qemu-devel Hi; here are a handful of small bug fixes for Arm guests for rc0. thanks -- PMM The following changes since commit 69680740eafa1838527c90155a7432d51b8ff203: Merge tag 'qdev-array-prop' of https://repo.or.cz/qemu/kevin into staging (2023-11-11 11:23:25 +0800) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231113 for you to fetch changes up to f6e8d1ef05a126de796ae03dd81e048e3ff48ff1: target/arm/tcg: enable PMU feature for Cortex-A8 and A9 (2023-11-13 16:31:41 +0000) ---------------------------------------------------------------- target-arm queue: * hw/arm/virt: fix GIC maintenance IRQ registration * target/arm: HVC at EL3 should go to EL3, not EL2 * target/arm: Correct MTE tag checking for reverse-copy MOPS * target/arm/tcg: enable PMU feature for Cortex-A8 and A9 ---------------------------------------------------------------- Jean-Philippe Brucker (1): hw/arm/virt: fix GIC maintenance IRQ registration Nikita Ostrenkov (1): target/arm/tcg: enable PMU feature for Cortex-A8 and A9 Peter Maydell (2): target/arm: HVC at EL3 should go to EL3, not EL2 target/arm: Correct MTE tag checking for reverse-copy MOPS hw/arm/virt.c | 6 ++++-- target/arm/tcg/cpu32.c | 2 ++ target/arm/tcg/mte_helper.c | 12 ++++++++++-- target/arm/tcg/translate-a64.c | 4 +++- 4 files changed, 19 insertions(+), 5 deletions(-) ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PULL 1/4] hw/arm/virt: fix GIC maintenance IRQ registration 2023-11-13 17:46 [PULL 0/4] target-arm queue Peter Maydell @ 2023-11-13 17:46 ` Peter Maydell 2023-11-13 17:46 ` [PULL 2/4] target/arm: HVC at EL3 should go to EL3, not EL2 Peter Maydell ` (3 subsequent siblings) 4 siblings, 0 replies; 12+ messages in thread From: Peter Maydell @ 2023-11-13 17:46 UTC (permalink / raw) To: qemu-devel From: Jean-Philippe Brucker <jean-philippe@linaro.org> Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"), GIC maintenance IRQ registration fails on arm64: [ 0.979743] kvm [1]: Cannot register interrupt 9 That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case where the maintenance IRQ is actually referred by its PPI index. Just like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there shouldn't be more similar issues. Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20231110090557.3219206-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 85e3c5ba9d2..be2856c018a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -576,7 +576,8 @@ static void fdt_add_gic_node(VirtMachineState *vms) if (vms->virt) { qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), GIC_FDT_IRQ_FLAGS_LEVEL_HI); } } else { @@ -600,7 +601,8 @@ static void fdt_add_gic_node(VirtMachineState *vms) 2, vms->memmap[VIRT_GIC_VCPU].base, 2, vms->memmap[VIRT_GIC_VCPU].size); qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), GIC_FDT_IRQ_FLAGS_LEVEL_HI); } } -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PULL 2/4] target/arm: HVC at EL3 should go to EL3, not EL2 2023-11-13 17:46 [PULL 0/4] target-arm queue Peter Maydell 2023-11-13 17:46 ` [PULL 1/4] hw/arm/virt: fix GIC maintenance IRQ registration Peter Maydell @ 2023-11-13 17:46 ` Peter Maydell 2023-11-13 17:46 ` [PULL 3/4] target/arm: Correct MTE tag checking for reverse-copy MOPS Peter Maydell ` (2 subsequent siblings) 4 siblings, 0 replies; 12+ messages in thread From: Peter Maydell @ 2023-11-13 17:46 UTC (permalink / raw) To: qemu-devel AArch64 permits code at EL3 to use the HVC instruction; however the exception we take should go to EL3, not down to EL2 (see the pseudocode AArch64.CallHypervisor()). Fix the target EL. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Message-id: 20231109151917.1925107-1-peter.maydell@linaro.org --- target/arm/tcg/translate-a64.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 41484d8ae54..a2e49c39f9f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2351,6 +2351,8 @@ static bool trans_SVC(DisasContext *s, arg_i *a) static bool trans_HVC(DisasContext *s, arg_i *a) { + int target_el = s->current_el == 3 ? 3 : 2; + if (s->current_el == 0) { unallocated_encoding(s); return true; @@ -2363,7 +2365,7 @@ static bool trans_HVC(DisasContext *s, arg_i *a) gen_helper_pre_hvc(tcg_env); /* Architecture requires ss advance before we do the actual work */ gen_ss_advance(s); - gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2); + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), target_el); return true; } -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PULL 3/4] target/arm: Correct MTE tag checking for reverse-copy MOPS 2023-11-13 17:46 [PULL 0/4] target-arm queue Peter Maydell 2023-11-13 17:46 ` [PULL 1/4] hw/arm/virt: fix GIC maintenance IRQ registration Peter Maydell 2023-11-13 17:46 ` [PULL 2/4] target/arm: HVC at EL3 should go to EL3, not EL2 Peter Maydell @ 2023-11-13 17:46 ` Peter Maydell 2023-11-13 17:46 ` [PULL 4/4] target/arm/tcg: enable PMU feature for Cortex-A8 and A9 Peter Maydell 2023-11-14 17:31 ` [PULL 0/4] target-arm queue Stefan Hajnoczi 4 siblings, 0 replies; 12+ messages in thread From: Peter Maydell @ 2023-11-13 17:46 UTC (permalink / raw) To: qemu-devel When we are doing a FEAT_MOPS copy that must be performed backwards, we call mte_mops_probe_rev(), passing it the address of the last byte in the region we are probing. However, allocation_tag_mem_probe() wants the address of the first byte to get the tag memory for. Because we passed it (ptr, size) we could incorrectly trip the allocation_tag_mem_probe() check for "does this access run across to the following page", and if that following page happened not to be valid then we would assert. We know we will always be only dealing with a single page because the code that calls mte_mops_probe_rev() ensures that. We could make mte_mops_probe_rev() pass 'ptr - (size - 1)' to allocation_tag_mem_probe(), but then we would have to adjust the returned 'mem' pointer to get back to the tag RAM for the last byte of the region. It's simpler to just pass in a size of 1 byte, because we know that allocation_tag_mem_probe() in pure-probe single-page mode doesn't care about the size. Fixes: 69c51dc3723b ("target/arm: Implement MTE tag-checking functions for FEAT_MOPS copies") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231110162546.2192512-1-peter.maydell@linaro.org --- target/arm/tcg/mte_helper.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 70ac876105f..ffb8ea1c349 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -1101,10 +1101,18 @@ uint64_t mte_mops_probe_rev(CPUARMState *env, uint64_t ptr, uint64_t size, uint32_t n; mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); - /* True probe; this will never fault */ + /* + * True probe; this will never fault. Note that our caller passes + * us a pointer to the end of the region, but allocation_tag_mem_probe() + * wants a pointer to the start. Because we know we don't span a page + * boundary and that allocation_tag_mem_probe() doesn't otherwise care + * about the size, pass in a size of 1 byte. This is simpler than + * adjusting the ptr to point to the start of the region and then having + * to adjust the returned 'mem' to get the end of the tag memory. + */ mem = allocation_tag_mem_probe(env, mmu_idx, ptr, w ? MMU_DATA_STORE : MMU_DATA_LOAD, - size, MMU_DATA_LOAD, true, 0); + 1, MMU_DATA_LOAD, true, 0); if (!mem) { return size; } -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PULL 4/4] target/arm/tcg: enable PMU feature for Cortex-A8 and A9 2023-11-13 17:46 [PULL 0/4] target-arm queue Peter Maydell ` (2 preceding siblings ...) 2023-11-13 17:46 ` [PULL 3/4] target/arm: Correct MTE tag checking for reverse-copy MOPS Peter Maydell @ 2023-11-13 17:46 ` Peter Maydell 2023-11-14 17:31 ` [PULL 0/4] target-arm queue Stefan Hajnoczi 4 siblings, 0 replies; 12+ messages in thread From: Peter Maydell @ 2023-11-13 17:46 UTC (permalink / raw) To: qemu-devel From: Nikita Ostrenkov <n.ostrenkov@gmail.com> According to the technical reference manual, the Cortex-A9 has a Perfomance Unit Monitor (PMU): https://developer.arm.com/documentation/100511/0401/performance-monitoring-unit/about-the-performance-monitoring-unit The Cortex-A8 does also. We already already define the PMU registers when emulating the Cortex-A8 and Cortex-A9, because we put them in v7_cp_reginfo[] rather than guarding them behind ARM_FEATURE_PMU. So the only thing that setting the feature bit changes is that the registers actually do something. Enable ARM_FEATURE_PMU for Cortex-A8 and Cortex-A9, to avoid this anomaly. (The A8 and A9 PMU predates the standardisation of ID_DFR0.PerfMon, so the field there is 0, but the PMU is still present.) Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com> Message-id: 20231112165658.2335-1-n.ostrenkov@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message; also enable PMU for A8] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/cpu32.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 0d5d8e307dd..d9e0e2a4ddf 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -351,6 +351,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->isar.mvfr0 = 0x11110222; @@ -418,6 +419,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); /* * Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PULL 0/4] target-arm queue 2023-11-13 17:46 [PULL 0/4] target-arm queue Peter Maydell ` (3 preceding siblings ...) 2023-11-13 17:46 ` [PULL 4/4] target/arm/tcg: enable PMU feature for Cortex-A8 and A9 Peter Maydell @ 2023-11-14 17:31 ` Stefan Hajnoczi 4 siblings, 0 replies; 12+ messages in thread From: Stefan Hajnoczi @ 2023-11-14 17:31 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel [-- Attachment #1: Type: text/plain, Size: 115 bytes --] Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PULL 0/4] target-arm queue @ 2023-04-03 16:01 Peter Maydell 2023-04-04 12:43 ` Peter Maydell 0 siblings, 1 reply; 12+ messages in thread From: Peter Maydell @ 2023-04-03 16:01 UTC (permalink / raw) To: qemu-devel The following changes since commit efcd0ec14b0fe9ee0ee70277763b2d538d19238d: Merge tag 'misc-fixes-20230330' of https://github.com/philmd/qemu into staging (2023-03-30 14:22:29 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230403 for you to fetch changes up to a0eaa126af3c5a43937a22c58cfb9bb36e4a5001: hw/ssi: Fix Linux driver init issue with xilinx_spi (2023-04-03 16:12:30 +0100) ---------------------------------------------------------------- * target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask() * hw/arm: do not free machine->fdt in arm_load_dtb() * target/arm: Fix generated code for cpreg reads when HSTR is active * hw/ssi: Fix Linux driver init issue with xilinx_spi ---------------------------------------------------------------- Chris Rauer (1): hw/ssi: Fix Linux driver init issue with xilinx_spi Markus Armbruster (1): hw/arm: do not free machine->fdt in arm_load_dtb() Peter Maydell (1): target/arm: Fix generated code for cpreg reads when HSTR is active Philippe Mathieu-Daudé (1): target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask() target/arm/internals.h | 15 ++++++++++----- hw/arm/boot.c | 5 ++++- hw/ssi/xilinx_spi.c | 1 + target/arm/gdbstub64.c | 7 +++++-- target/arm/tcg/pauth_helper.c | 18 +----------------- target/arm/tcg/translate.c | 6 ++++++ 6 files changed, 27 insertions(+), 25 deletions(-) ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PULL 0/4] target-arm queue 2023-04-03 16:01 Peter Maydell @ 2023-04-04 12:43 ` Peter Maydell 0 siblings, 0 replies; 12+ messages in thread From: Peter Maydell @ 2023-04-04 12:43 UTC (permalink / raw) To: qemu-devel On Mon, 3 Apr 2023 at 17:01, Peter Maydell <peter.maydell@linaro.org> wrote: > > The following changes since commit efcd0ec14b0fe9ee0ee70277763b2d538d19238d: > > Merge tag 'misc-fixes-20230330' of https://github.com/philmd/qemu into staging (2023-03-30 14:22:29 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230403 > > for you to fetch changes up to a0eaa126af3c5a43937a22c58cfb9bb36e4a5001: > > hw/ssi: Fix Linux driver init issue with xilinx_spi (2023-04-03 16:12:30 +0100) > > ---------------------------------------------------------------- > * target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask() > * hw/arm: do not free machine->fdt in arm_load_dtb() > * target/arm: Fix generated code for cpreg reads when HSTR is active > * hw/ssi: Fix Linux driver init issue with xilinx_spi > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PULL 0/4] target-arm queue @ 2021-11-15 20:19 Peter Maydell 2021-11-16 11:49 ` Richard Henderson 0 siblings, 1 reply; 12+ messages in thread From: Peter Maydell @ 2021-11-15 20:19 UTC (permalink / raw) To: qemu-devel; +Cc: Richard Henderson Hi; some minor changes for 6.2, which I think can be classified as bug fixes and are OK for this point in the release cycle. (Wouldn't be the end of the world if they slipped to 7.0.) -- PMM The following changes since commit 42f6c9179be4401974dd3a75ee72defd16b5092d: Merge tag 'pull-ppc-20211112' of https://github.com/legoater/qemu into staging (2021-11-12 12:28:25 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211115-1 for you to fetch changes up to 1adf528ec3bdf62ea3b580b7ad562534a3676ff5: hw/rtc/pl031: Send RTC_CHANGE QMP event (2021-11-15 18:53:00 +0000) ---------------------------------------------------------------- target-arm queue: * Support multiple redistributor regions for TCG GICv3 * Send RTC_CHANGE QMP event from pl031 ---------------------------------------------------------------- Eric Auger (1): hw/rtc/pl031: Send RTC_CHANGE QMP event Peter Maydell (3): hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1 hw/intc/arm_gicv3: Support multiple redistributor regions include/hw/intc/arm_gicv3_common.h | 14 ++++++++-- hw/intc/arm_gicv3.c | 12 +------- hw/intc/arm_gicv3_common.c | 56 ++++++++++++++++++++++++-------------- hw/intc/arm_gicv3_kvm.c | 10 ++----- hw/intc/arm_gicv3_redist.c | 40 +++++++++++++++------------ hw/rtc/pl031.c | 10 ++++++- hw/rtc/meson.build | 2 +- 7 files changed, 83 insertions(+), 61 deletions(-) ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PULL 0/4] target-arm queue 2021-11-15 20:19 Peter Maydell @ 2021-11-16 11:49 ` Richard Henderson 0 siblings, 0 replies; 12+ messages in thread From: Richard Henderson @ 2021-11-16 11:49 UTC (permalink / raw) To: Peter Maydell, qemu-devel On 11/15/21 9:19 PM, Peter Maydell wrote: > Hi; some minor changes for 6.2, which I think can be classified > as bug fixes and are OK for this point in the release cycle. > (Wouldn't be the end of the world if they slipped to 7.0.) > > -- PMM > > The following changes since commit 42f6c9179be4401974dd3a75ee72defd16b5092d: > > Merge tag 'pull-ppc-20211112' of https://github.com/legoater/qemu into staging (2021-11-12 12:28:25 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211115-1 > > for you to fetch changes up to 1adf528ec3bdf62ea3b580b7ad562534a3676ff5: > > hw/rtc/pl031: Send RTC_CHANGE QMP event (2021-11-15 18:53:00 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * Support multiple redistributor regions for TCG GICv3 > * Send RTC_CHANGE QMP event from pl031 > > ---------------------------------------------------------------- > Eric Auger (1): > hw/rtc/pl031: Send RTC_CHANGE QMP event > > Peter Maydell (3): > hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize > hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1 > hw/intc/arm_gicv3: Support multiple redistributor regions > > include/hw/intc/arm_gicv3_common.h | 14 ++++++++-- > hw/intc/arm_gicv3.c | 12 +------- > hw/intc/arm_gicv3_common.c | 56 ++++++++++++++++++++++++-------------- > hw/intc/arm_gicv3_kvm.c | 10 ++----- > hw/intc/arm_gicv3_redist.c | 40 +++++++++++++++------------ > hw/rtc/pl031.c | 10 ++++++- > hw/rtc/meson.build | 2 +- > 7 files changed, 83 insertions(+), 61 deletions(-) Applied, thanks. r~ ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PULL 0/4] target-arm queue @ 2019-11-26 14:12 Peter Maydell 2019-11-26 19:47 ` Peter Maydell 0 siblings, 1 reply; 12+ messages in thread From: Peter Maydell @ 2019-11-26 14:12 UTC (permalink / raw) To: qemu-devel Arm patches for rc3 : just a handful of bug fixes. thanks -- PMM The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c: Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126 for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317: target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000) ---------------------------------------------------------------- target-arm queue: * handle FTYPE flag correctly in v7M exception return for v7M CPUs with an FPU (v8M CPUs were already correct) * versal: Add the CRP as unimplemented * Fix ISR_EL1 tracking when executing at EL2 * Honor HCR_EL2.TID3 trapping requirements ---------------------------------------------------------------- Edgar E. Iglesias (1): hw/arm: versal: Add the CRP as unimplemented Jean-Hugues Deschênes (1): target/arm: Fix handling of cortex-m FTYPE flag in EXCRET Marc Zyngier (2): target/arm: Fix ISR_EL1 tracking when executing at EL2 target/arm: Honor HCR_EL2.TID3 trapping requirements include/hw/arm/xlnx-versal.h | 3 ++ hw/arm/xlnx-versal.c | 2 ++ target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++-- target/arm/m_helper.c | 7 ++-- 4 files changed, 89 insertions(+), 6 deletions(-) ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PULL 0/4] target-arm queue 2019-11-26 14:12 Peter Maydell @ 2019-11-26 19:47 ` Peter Maydell 0 siblings, 0 replies; 12+ messages in thread From: Peter Maydell @ 2019-11-26 19:47 UTC (permalink / raw) To: QEMU Developers On Tue, 26 Nov 2019 at 14:12, Peter Maydell <peter.maydell@linaro.org> wrote: > > Arm patches for rc3 : just a handful of bug fixes. > > thanks > -- PMM > > > The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c: > > Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126 > > for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317: > > target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * handle FTYPE flag correctly in v7M exception return > for v7M CPUs with an FPU (v8M CPUs were already correct) > * versal: Add the CRP as unimplemented > * Fix ISR_EL1 tracking when executing at EL2 > * Honor HCR_EL2.TID3 trapping requirements > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-11-14 17:35 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-11-13 17:46 [PULL 0/4] target-arm queue Peter Maydell 2023-11-13 17:46 ` [PULL 1/4] hw/arm/virt: fix GIC maintenance IRQ registration Peter Maydell 2023-11-13 17:46 ` [PULL 2/4] target/arm: HVC at EL3 should go to EL3, not EL2 Peter Maydell 2023-11-13 17:46 ` [PULL 3/4] target/arm: Correct MTE tag checking for reverse-copy MOPS Peter Maydell 2023-11-13 17:46 ` [PULL 4/4] target/arm/tcg: enable PMU feature for Cortex-A8 and A9 Peter Maydell 2023-11-14 17:31 ` [PULL 0/4] target-arm queue Stefan Hajnoczi -- strict thread matches above, loose matches on Subject: below -- 2023-04-03 16:01 Peter Maydell 2023-04-04 12:43 ` Peter Maydell 2021-11-15 20:19 Peter Maydell 2021-11-16 11:49 ` Richard Henderson 2019-11-26 14:12 Peter Maydell 2019-11-26 19:47 ` Peter Maydell
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