All of lore.kernel.org
 help / color / mirror / Atom feed
From: Andrew Jones <ajones@ventanamicro.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Deepak Gupta <debug@rivosinc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	 Catalin Marinas <catalin.marinas@arm.com>,
	linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org,
	 Conor Dooley <conor@kernel.org>,
	kasan-dev@googlegroups.com,
	 Evgenii Stepanov <eugenis@google.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Rob Herring <robh+dt@kernel.org>, Guo Ren <guoren@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	 Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [RISC-V] [tech-j-ext] [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits
Date: Fri, 22 Mar 2024 08:58:43 +0100	[thread overview]
Message-ID: <20240322-168f191eeb8479b2ea169a5e@orel> (raw)
In-Reply-To: <40ab1ce5-8700-4a63-b182-1e864f6c9225@sifive.com>

On Tue, Mar 19, 2024 at 09:20:59PM -0500, Samuel Holland wrote:
...
> This is really a separate concern than when we write envcfg. The per-CPU
> variable is only necessary to support hardware where a subset of harts support
> Zicboz. Since the riscv_cpu_has_extension_[un]likely() helpers were added
> specifically for Zicboz, I assume this is an important use case, and dropping
> support for this hardware would be a regression. After all, hwprobe() allows
> userspace to see that Zicboz is implemented at a per-CPU level. Maybe Andrew can
> weigh in on that.
>

Hi Samuel,

I've approached Zicboz the same way I would approach all extensions, which
is to be per-hart. I'm not currently aware of a platform that is / will be
composed of harts where some have Zicboz and others don't, but there's
nothing stopping a platform like that from being built. I realize this
adds complexity that we may not want to manage in Linux without an actual
use case requiring it. I wouldn't be opposed to keeping things simple for
now, only bringing in complexity when needed (for this extension or for a
future extension with envcfg bits), but we should ensure we make it clear
that we're making those simplifications now based on assumptions, and we
may need to change things later.

Thanks,
drew

WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Deepak Gupta <debug@rivosinc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	 Catalin Marinas <catalin.marinas@arm.com>,
	linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org,
	 Conor Dooley <conor@kernel.org>,
	kasan-dev@googlegroups.com,
	 Evgenii Stepanov <eugenis@google.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Rob Herring <robh+dt@kernel.org>, Guo Ren <guoren@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	 Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [RISC-V] [tech-j-ext] [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits
Date: Fri, 22 Mar 2024 08:58:43 +0100	[thread overview]
Message-ID: <20240322-168f191eeb8479b2ea169a5e@orel> (raw)
In-Reply-To: <40ab1ce5-8700-4a63-b182-1e864f6c9225@sifive.com>

On Tue, Mar 19, 2024 at 09:20:59PM -0500, Samuel Holland wrote:
...
> This is really a separate concern than when we write envcfg. The per-CPU
> variable is only necessary to support hardware where a subset of harts support
> Zicboz. Since the riscv_cpu_has_extension_[un]likely() helpers were added
> specifically for Zicboz, I assume this is an important use case, and dropping
> support for this hardware would be a regression. After all, hwprobe() allows
> userspace to see that Zicboz is implemented at a per-CPU level. Maybe Andrew can
> weigh in on that.
>

Hi Samuel,

I've approached Zicboz the same way I would approach all extensions, which
is to be per-hart. I'm not currently aware of a platform that is / will be
composed of harts where some have Zicboz and others don't, but there's
nothing stopping a platform like that from being built. I realize this
adds complexity that we may not want to manage in Linux without an actual
use case requiring it. I wouldn't be opposed to keeping things simple for
now, only bringing in complexity when needed (for this extension or for a
future extension with envcfg bits), but we should ensure we make it clear
that we're making those simplifications now based on assumptions, and we
may need to change things later.

Thanks,
drew

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2024-03-22  7:58 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-19 21:58 [RFC PATCH 0/9] riscv: Userspace pointer masking and tagged address ABI Samuel Holland
2024-03-19 21:58 ` Samuel Holland
2024-03-19 21:58 ` [RFC PATCH 1/9] dt-bindings: riscv: Add pointer masking ISA extensions Samuel Holland
2024-03-19 21:58   ` Samuel Holland
2024-03-19 21:58 ` [RFC PATCH 2/9] riscv: Add ISA extension parsing for pointer masking Samuel Holland
2024-03-19 21:58   ` Samuel Holland
2024-03-19 21:58 ` [RFC PATCH 3/9] riscv: Add CSR definitions " Samuel Holland
2024-03-19 21:58   ` Samuel Holland
2024-03-19 21:58 ` [RFC PATCH 4/9] riscv: Define is_compat_thread() Samuel Holland
2024-03-19 21:58   ` Samuel Holland
2024-03-19 21:58 ` [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits Samuel Holland
2024-03-19 21:58   ` Samuel Holland
2024-03-19 23:55   ` [RISC-V] [tech-j-ext] " Deepak Gupta
2024-03-19 23:55     ` Deepak Gupta
2024-03-20  2:20     ` Samuel Holland
2024-03-20  2:20       ` Samuel Holland
2024-03-20  4:39       ` Deepak Gupta
2024-03-20  4:39         ` Deepak Gupta
2024-03-22  0:13         ` Samuel Holland
2024-03-22  0:13           ` Samuel Holland
2024-03-22 17:13           ` Deepak Gupta
2024-03-22 17:13             ` Deepak Gupta
2024-03-23  9:35             ` Andrew Jones
2024-03-23  9:35               ` Andrew Jones
2024-03-23 20:37               ` Deepak Gupta
2024-03-23 20:37                 ` Deepak Gupta
2024-03-22  8:09         ` Andrew Jones
2024-03-22  8:09           ` Andrew Jones
2024-03-22 16:52           ` Deepak Gupta
2024-03-22 16:52             ` Deepak Gupta
2024-03-20  8:06       ` Conor Dooley
2024-03-20  8:06         ` Conor Dooley
     [not found]       ` <17BE5F38AFE245E5.29196@lists.riscv.org>
2024-03-20 23:27         ` Deepak Gupta
2024-03-20 23:27           ` Deepak Gupta
2024-03-22  3:43           ` Samuel Holland
2024-03-22  3:43             ` Samuel Holland
2024-03-22  7:58       ` Andrew Jones [this message]
2024-03-22  7:58         ` Andrew Jones
2024-03-28  1:58       ` Deepak Gupta
2024-03-28  1:58         ` Deepak Gupta
     [not found]       ` <17C0CB122DBB0EAE.6770@lists.riscv.org>
2024-03-28 19:34         ` Deepak Gupta
2024-03-28 19:34           ` Deepak Gupta
2024-03-19 21:58 ` [RFC PATCH 6/9] riscv: Add support for userspace pointer masking Samuel Holland
2024-03-19 21:58   ` Samuel Holland
2024-03-19 21:58 ` [RFC PATCH 7/9] riscv: Add support for the tagged address ABI Samuel Holland
2024-03-19 21:58   ` Samuel Holland
2024-03-19 21:58 ` [RFC PATCH 8/9] riscv: Allow ptrace control of " Samuel Holland
2024-03-19 21:58   ` Samuel Holland
2024-03-19 21:58 ` [RFC PATCH 9/9] selftests: riscv: Add a pointer masking test Samuel Holland
2024-03-19 21:58   ` Samuel Holland
2024-03-20 17:21   ` Conor Dooley
2024-03-20 17:21     ` Conor Dooley
2024-03-20 18:04     ` Samuel Holland
2024-03-20 18:04       ` Samuel Holland

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240322-168f191eeb8479b2ea169a5e@orel \
    --to=ajones@ventanamicro.com \
    --cc=catalin.marinas@arm.com \
    --cc=conor@kernel.org \
    --cc=debug@rivosinc.com \
    --cc=devicetree@vger.kernel.org \
    --cc=eugenis@google.com \
    --cc=guoren@kernel.org \
    --cc=heiko@sntech.de \
    --cc=kasan-dev@googlegroups.com \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    --cc=samuel.holland@sifive.com \
    --cc=tech-j-ext@lists.risc-v.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.