From: Deepak Gupta <debug@rivosinc.com> To: Samuel Holland <samuel.holland@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>, linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org, Conor Dooley <conor@kernel.org>, kasan-dev@googlegroups.com, Evgenii Stepanov <eugenis@google.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, Andrew Jones <ajones@ventanamicro.com>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>, Paul Walmsley <paul.walmsley@sifive.com> Subject: Re: [RISC-V] [tech-j-ext] [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits Date: Thu, 28 Mar 2024 12:34:03 -0700 [thread overview] Message-ID: <ZgXGKxp0KAQI/+NC@debug.ba.rivosinc.com> (raw) In-Reply-To: <17C0CB122DBB0EAE.6770@lists.riscv.org> On Wed, Mar 27, 2024 at 06:58:45PM -0700, Deepak Gupta via lists.riscv.org wrote: >On Tue, Mar 19, 2024 at 7:21 PM Samuel Holland ><samuel.holland@sifive.com> wrote: >> >> > else >> > regs->status |= SR_UXL_64; >> > #endif >> > + current->thread_info.envcfg = ENVCFG_BASE; >> > } >> > >> > And instead of context switching in `_switch_to`, >> > In `entry.S` pick up `envcfg` from `thread_info` and write it into CSR. >> >> The immediate reason is that writing envcfg in ret_from_exception() adds cycles >> to every IRQ and system call exit, even though most of them will not change the >> envcfg value. This is especially the case when returning from an IRQ/exception >> back to S-mode, since envcfg has zero effect there. >> > >A quick observation: >So I tried this on my setup. When I put `senvcfg` writes in >`__switch_to ` path, qemu suddenly >just tanks and takes a lot of time to boot up as opposed to when >`senvcfg` was in trap return path. >In my case entire userspace (all processes) have cfi enabled for them >via `senvcfg` and it gets >context switched. Not sure it's specific to my setup. I don't think it >should be an issue on actual >hardware. > >Still debugging why it slows down my qemu drastically when same writes >to same CSR >are moved from `ret_from_exception` to `switch_to` Nevermind and sorry for the bother. An issue on my setup. > > >-=-=-=-=-=-=-=-=-=-=-=- >Links: You receive all messages sent to this group. >View/Reply Online (#680): https://lists.riscv.org/g/tech-j-ext/message/680 >Mute This Topic: https://lists.riscv.org/mt/105033914/7300952 >Group Owner: tech-j-ext+owner@lists.riscv.org >Unsubscribe: https://lists.riscv.org/g/tech-j-ext/unsub [debug@rivosinc.com] >-=-=-=-=-=-=-=-=-=-=-=- > >
WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com> To: Samuel Holland <samuel.holland@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>, linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org, Conor Dooley <conor@kernel.org>, kasan-dev@googlegroups.com, Evgenii Stepanov <eugenis@google.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, Andrew Jones <ajones@ventanamicro.com>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>, Paul Walmsley <paul.walmsley@sifive.com> Subject: Re: [RISC-V] [tech-j-ext] [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits Date: Thu, 28 Mar 2024 12:34:03 -0700 [thread overview] Message-ID: <ZgXGKxp0KAQI/+NC@debug.ba.rivosinc.com> (raw) In-Reply-To: <17C0CB122DBB0EAE.6770@lists.riscv.org> On Wed, Mar 27, 2024 at 06:58:45PM -0700, Deepak Gupta via lists.riscv.org wrote: >On Tue, Mar 19, 2024 at 7:21 PM Samuel Holland ><samuel.holland@sifive.com> wrote: >> >> > else >> > regs->status |= SR_UXL_64; >> > #endif >> > + current->thread_info.envcfg = ENVCFG_BASE; >> > } >> > >> > And instead of context switching in `_switch_to`, >> > In `entry.S` pick up `envcfg` from `thread_info` and write it into CSR. >> >> The immediate reason is that writing envcfg in ret_from_exception() adds cycles >> to every IRQ and system call exit, even though most of them will not change the >> envcfg value. This is especially the case when returning from an IRQ/exception >> back to S-mode, since envcfg has zero effect there. >> > >A quick observation: >So I tried this on my setup. When I put `senvcfg` writes in >`__switch_to ` path, qemu suddenly >just tanks and takes a lot of time to boot up as opposed to when >`senvcfg` was in trap return path. >In my case entire userspace (all processes) have cfi enabled for them >via `senvcfg` and it gets >context switched. Not sure it's specific to my setup. I don't think it >should be an issue on actual >hardware. > >Still debugging why it slows down my qemu drastically when same writes >to same CSR >are moved from `ret_from_exception` to `switch_to` Nevermind and sorry for the bother. An issue on my setup. > > >-=-=-=-=-=-=-=-=-=-=-=- >Links: You receive all messages sent to this group. >View/Reply Online (#680): https://lists.riscv.org/g/tech-j-ext/message/680 >Mute This Topic: https://lists.riscv.org/mt/105033914/7300952 >Group Owner: tech-j-ext+owner@lists.riscv.org >Unsubscribe: https://lists.riscv.org/g/tech-j-ext/unsub [debug@rivosinc.com] >-=-=-=-=-=-=-=-=-=-=-=- > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-03-28 19:34 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-19 21:58 [RFC PATCH 0/9] riscv: Userspace pointer masking and tagged address ABI Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-19 21:58 ` [RFC PATCH 1/9] dt-bindings: riscv: Add pointer masking ISA extensions Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-19 21:58 ` [RFC PATCH 2/9] riscv: Add ISA extension parsing for pointer masking Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-19 21:58 ` [RFC PATCH 3/9] riscv: Add CSR definitions " Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-19 21:58 ` [RFC PATCH 4/9] riscv: Define is_compat_thread() Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-19 21:58 ` [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-19 23:55 ` [RISC-V] [tech-j-ext] " Deepak Gupta 2024-03-19 23:55 ` Deepak Gupta 2024-03-20 2:20 ` Samuel Holland 2024-03-20 2:20 ` Samuel Holland 2024-03-20 4:39 ` Deepak Gupta 2024-03-20 4:39 ` Deepak Gupta 2024-03-22 0:13 ` Samuel Holland 2024-03-22 0:13 ` Samuel Holland 2024-03-22 17:13 ` Deepak Gupta 2024-03-22 17:13 ` Deepak Gupta 2024-03-23 9:35 ` Andrew Jones 2024-03-23 9:35 ` Andrew Jones 2024-03-23 20:37 ` Deepak Gupta 2024-03-23 20:37 ` Deepak Gupta 2024-03-22 8:09 ` Andrew Jones 2024-03-22 8:09 ` Andrew Jones 2024-03-22 16:52 ` Deepak Gupta 2024-03-22 16:52 ` Deepak Gupta 2024-03-20 8:06 ` Conor Dooley 2024-03-20 8:06 ` Conor Dooley [not found] ` <17BE5F38AFE245E5.29196@lists.riscv.org> 2024-03-20 23:27 ` Deepak Gupta 2024-03-20 23:27 ` Deepak Gupta 2024-03-22 3:43 ` Samuel Holland 2024-03-22 3:43 ` Samuel Holland 2024-03-22 7:58 ` Andrew Jones 2024-03-22 7:58 ` Andrew Jones 2024-03-28 1:58 ` Deepak Gupta 2024-03-28 1:58 ` Deepak Gupta [not found] ` <17C0CB122DBB0EAE.6770@lists.riscv.org> 2024-03-28 19:34 ` Deepak Gupta [this message] 2024-03-28 19:34 ` Deepak Gupta 2024-03-19 21:58 ` [RFC PATCH 6/9] riscv: Add support for userspace pointer masking Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-19 21:58 ` [RFC PATCH 7/9] riscv: Add support for the tagged address ABI Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-19 21:58 ` [RFC PATCH 8/9] riscv: Allow ptrace control of " Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-19 21:58 ` [RFC PATCH 9/9] selftests: riscv: Add a pointer masking test Samuel Holland 2024-03-19 21:58 ` Samuel Holland 2024-03-20 17:21 ` Conor Dooley 2024-03-20 17:21 ` Conor Dooley 2024-03-20 18:04 ` Samuel Holland 2024-03-20 18:04 ` Samuel Holland
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