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* [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2
@ 2024-03-29  3:09 Tao Zhou
  2024-03-29  7:16 ` Zhang, Hawking
  0 siblings, 1 reply; 4+ messages in thread
From: Tao Zhou @ 2024-03-29  3:09 UTC (permalink / raw)
  To: amd-gfx; +Cc: Tao Zhou, Hawking Zhang

SDMA_CNTL is not set in some cases, driver configures it by itself.

v2: simplify code

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 71c2f50530cb..f8e2cd514493 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1602,19 +1602,9 @@ static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
 	u32 sdma_cntl;
 
 	sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
-	switch (state) {
-	case AMDGPU_IRQ_STATE_DISABLE:
-		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
-					  DRAM_ECC_INT_ENABLE, 0);
-		WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
-		break;
-	/* sdma ecc interrupt is enabled by default
-	 * driver doesn't need to do anything to
-	 * enable the interrupt */
-	case AMDGPU_IRQ_STATE_ENABLE:
-	default:
-		break;
-	}
+	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
+					state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+	WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
 
 	return 0;
 }
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2
  2024-03-29  3:09 [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2 Tao Zhou
@ 2024-03-29  7:16 ` Zhang, Hawking
  0 siblings, 0 replies; 4+ messages in thread
From: Zhang, Hawking @ 2024-03-29  7:16 UTC (permalink / raw)
  To: Zhou1, Tao, amd-gfx

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: Zhou1, Tao <Tao.Zhou1@amd.com>
Sent: Friday, March 29, 2024 11:10
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

SDMA_CNTL is not set in some cases, driver configures it by itself.

v2: simplify code

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 71c2f50530cb..f8e2cd514493 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1602,19 +1602,9 @@ static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
        u32 sdma_cntl;

        sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
-       switch (state) {
-       case AMDGPU_IRQ_STATE_DISABLE:
-               sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
-                                         DRAM_ECC_INT_ENABLE, 0);
-               WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
-               break;
-       /* sdma ecc interrupt is enabled by default
-        * driver doesn't need to do anything to
-        * enable the interrupt */
-       case AMDGPU_IRQ_STATE_ENABLE:
-       default:
-               break;
-       }
+       sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
+                                       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+       WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);

        return 0;
 }
--
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2
  2024-03-28 10:27 Tao Zhou
@ 2024-03-28 12:29 ` Zhang, Hawking
  0 siblings, 0 replies; 4+ messages in thread
From: Zhang, Hawking @ 2024-03-28 12:29 UTC (permalink / raw)
  To: Zhou1, Tao, amd-gfx; +Cc: Zhou1, Tao

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Tao Zhou
Sent: Thursday, March 28, 2024 18:28
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>
Subject: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

SDMA_CNTL is not set in some cases, driver configures it by itself.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 71c2f50530cb..d10ae4ce5ddd 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1608,10 +1608,11 @@ static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
                                          DRAM_ECC_INT_ENABLE, 0);
                WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
                break;
-       /* sdma ecc interrupt is enabled by default
-        * driver doesn't need to do anything to
-        * enable the interrupt */
        case AMDGPU_IRQ_STATE_ENABLE:
+               sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
+                                         DRAM_ECC_INT_ENABLE, 1);
+               WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
+               break;
        default:
                break;
        }
--
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2
@ 2024-03-28 10:27 Tao Zhou
  2024-03-28 12:29 ` Zhang, Hawking
  0 siblings, 1 reply; 4+ messages in thread
From: Tao Zhou @ 2024-03-28 10:27 UTC (permalink / raw)
  To: amd-gfx; +Cc: Tao Zhou

SDMA_CNTL is not set in some cases, driver configures it by itself.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 71c2f50530cb..d10ae4ce5ddd 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1608,10 +1608,11 @@ static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
 					  DRAM_ECC_INT_ENABLE, 0);
 		WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
 		break;
-	/* sdma ecc interrupt is enabled by default
-	 * driver doesn't need to do anything to
-	 * enable the interrupt */
 	case AMDGPU_IRQ_STATE_ENABLE:
+		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
+					  DRAM_ECC_INT_ENABLE, 1);
+		WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
+		break;
 	default:
 		break;
 	}
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-03-29  7:16 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2024-03-29  3:09 [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2 Tao Zhou
2024-03-29  7:16 ` Zhang, Hawking
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2024-03-28 10:27 Tao Zhou
2024-03-28 12:29 ` Zhang, Hawking

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