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From: via <qemu-devel@nongnu.org>
To: <bmeng.cn@gmail.com>, <anup@brainfault.org>
Cc: <Alistair.Francis@wdc.com>, <kbastian@mail.uni-paderborn.de>,
	<palmerdabbelt@google.com>, <sagark@eecs.berkeley.edu>,
	<qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>,
	<peter.maydell@linaro.org>,  <alistair@alistair23.me>,
	<qemu-block@nongnu.org>, <jasowang@redhat.com>,
	<bin.meng@windriver.com>, <pbonzini@redhat.com>,
	<palmer@dabbelt.com>, <qemu-arm@nongnu.org>,
	<marcandre.lureau@redhat.com>, <edgar.iglesias@gmail.com>,
	<philmd@redhat.com>
Subject: Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support
Date: Mon, 17 Aug 2020 15:44:06 +0000	[thread overview]
Message-ID: <202949f7-c9d5-4d4d-3ebe-53727f4fa169@microchip.com> (raw)
In-Reply-To: <CAEUhbmV5=B5xKhYqMj1MQb61nt5cNUJG1MXT++C1w1YMYTfLCQ@mail.gmail.com>

Hi Anup,

On 8/17/20 11:30 AM, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Anup,
>
> On Sat, Aug 15, 2020 at 1:44 AM Anup Patel <anup@brainfault.org> wrote:
>> On Fri, Aug 14, 2020 at 10:12 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>> From: Bin Meng <bin.meng@windriver.com>
>>>
>>> This adds support for Microchip PolarFire SoC Icicle Kit board.
>>> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
>>> E51 plus four U54 cores and many on-chip peripherals and an FPGA.
>> Nice Work !!! This is very helpful.
> Thanks!
>
>> The Microchip HSS is quite convoluted. It has:
>> 1. DDR Init
>> 2. Boot device support
>> 3. SBI support using OpenSBI as library
>> 4. Simple TEE support
>>
>> I think point 1) and 2) above should be part of U-Boot SPL.
>> The point 3) can be OpenSBI FW_DYNAMIC.
>>
>> Lastly,for point 4), we are working on a new OpenSBI feature using
>> which we can run independent Secure OS and Non-Secure OS using
>> U-Boot_SPL+OpenSBI (for both SiFive Unleashed and Microchip
>> PolarFire).
>>
>> Do you have plans for adding U-Boot SPL support for this board ??
> + Cyril Jean from Microchip
>
> I will have to leave this question to Cyril to comment.
>
I currently do not have a plan to support U-Boot SPL. The idea of the 
HSS is to contain all the silicon specific initialization and 
configuration code within the HSS before jumping to U-Boot S-mode. I 
would rather keep all this within the HSS for the time being. I would 
wait until we reach production silicon before attempting to move this to 
U-Boot SPL as the HSS is likely to contain some opaque silicon related 
changes for another while.


Regards,

Cyril.


WARNING: multiple messages have this Message-ID (diff)
From: <Cyril.Jean@microchip.com>
To: <bmeng.cn@gmail.com>, <anup@brainfault.org>
Cc: <Alistair.Francis@wdc.com>, <kbastian@mail.uni-paderborn.de>,
	<palmerdabbelt@google.com>, <sagark@eecs.berkeley.edu>,
	<qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>,
	<peter.maydell@linaro.org>,  <alistair@alistair23.me>,
	<qemu-block@nongnu.org>, <jasowang@redhat.com>,
	<bin.meng@windriver.com>, <pbonzini@redhat.com>,
	<palmer@dabbelt.com>, <qemu-arm@nongnu.org>,
	<marcandre.lureau@redhat.com>, <edgar.iglesias@gmail.com>,
	<philmd@redhat.com>
Subject: Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support
Date: Mon, 17 Aug 2020 15:44:06 +0000	[thread overview]
Message-ID: <202949f7-c9d5-4d4d-3ebe-53727f4fa169@microchip.com> (raw)
In-Reply-To: <CAEUhbmV5=B5xKhYqMj1MQb61nt5cNUJG1MXT++C1w1YMYTfLCQ@mail.gmail.com>

Hi Anup,

On 8/17/20 11:30 AM, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Anup,
>
> On Sat, Aug 15, 2020 at 1:44 AM Anup Patel <anup@brainfault.org> wrote:
>> On Fri, Aug 14, 2020 at 10:12 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>> From: Bin Meng <bin.meng@windriver.com>
>>>
>>> This adds support for Microchip PolarFire SoC Icicle Kit board.
>>> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
>>> E51 plus four U54 cores and many on-chip peripherals and an FPGA.
>> Nice Work !!! This is very helpful.
> Thanks!
>
>> The Microchip HSS is quite convoluted. It has:
>> 1. DDR Init
>> 2. Boot device support
>> 3. SBI support using OpenSBI as library
>> 4. Simple TEE support
>>
>> I think point 1) and 2) above should be part of U-Boot SPL.
>> The point 3) can be OpenSBI FW_DYNAMIC.
>>
>> Lastly,for point 4), we are working on a new OpenSBI feature using
>> which we can run independent Secure OS and Non-Secure OS using
>> U-Boot_SPL+OpenSBI (for both SiFive Unleashed and Microchip
>> PolarFire).
>>
>> Do you have plans for adding U-Boot SPL support for this board ??
> + Cyril Jean from Microchip
>
> I will have to leave this question to Cyril to comment.
>
I currently do not have a plan to support U-Boot SPL. The idea of the 
HSS is to contain all the silicon specific initialization and 
configuration code within the HSS before jumping to U-Boot S-mode. I 
would rather keep all this within the HSS for the time being. I would 
wait until we reach production silicon before attempting to move this to 
U-Boot SPL as the HSS is likely to contain some opaque silicon related 
changes for another while.


Regards,

Cyril.


  reply	other threads:[~2020-08-17 18:13 UTC|newest]

Thread overview: 100+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-14 16:40 [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-08-14 16:40 ` Bin Meng
2020-08-14 16:40 ` [PATCH 01/18] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-08-17 17:49   ` Alistair Francis
2020-08-17 17:49     ` Alistair Francis
2020-08-14 16:40 ` [PATCH 02/18] hw/riscv: hart: " Bin Meng
2020-08-17 17:49   ` Alistair Francis
2020-08-17 17:49     ` Alistair Francis
2020-08-14 16:40 ` [PATCH 03/18] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-08-17 17:52   ` Alistair Francis
2020-08-17 17:52     ` Alistair Francis
2020-08-14 16:40 ` [PATCH 04/18] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-08-17 19:39   ` Alistair Francis
2020-08-17 19:39     ` Alistair Francis
2020-08-14 16:40 ` [PATCH 05/18] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-08-14 16:40   ` Bin Meng
2020-08-17 20:51   ` Alistair Francis
2020-08-17 20:51     ` Alistair Francis
2020-08-14 16:40 ` [PATCH 06/18] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-08-17 21:06   ` Alistair Francis
2020-08-17 21:06     ` Alistair Francis
2020-08-14 16:40 ` [PATCH 07/18] hw/sd: sd: Fix incorrect populated function switch status data structure Bin Meng
2020-08-15  7:58   ` Philippe Mathieu-Daudé
2020-08-18 16:30     ` Sai Pavan Boddu
2020-08-21 10:09       ` Sai Pavan Boddu
2020-08-21 10:09         ` Sai Pavan Boddu
2020-08-21 10:08         ` Bin Meng
2020-08-21 10:08           ` Bin Meng
2020-08-24  4:13           ` Sai Pavan Boddu
2020-08-24  4:13             ` Sai Pavan Boddu
2020-08-14 16:40 ` [PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit Bin Meng
2020-08-15  8:38   ` Philippe Mathieu-Daudé
2020-08-16  8:54     ` Bin Meng
2020-08-16  8:54       ` Bin Meng
2020-08-14 16:40 ` [PATCH 09/18] hw/sd: sdhci: Make sdhci_poweron_reset() internal visible Bin Meng
2020-08-15  7:51   ` Philippe Mathieu-Daudé
2020-08-16  8:50     ` Bin Meng
2020-08-16  8:50       ` Bin Meng
2020-08-16 11:06       ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 10/18] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-08-14 16:40   ` Bin Meng
2020-08-15  8:51   ` Philippe Mathieu-Daudé
2020-08-15  8:51     ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 11/18] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-08-15  8:55   ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 12/18] hw/dma: Add Microchip PolarFire Soc DMA controller emulation Bin Meng
2020-08-14 16:40 ` [PATCH 13/18] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-08-15  9:00   ` Philippe Mathieu-Daudé
2020-08-16  8:57     ` Bin Meng
2020-08-16  8:57       ` Bin Meng
2020-08-16 11:08       ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-08-14 16:40   ` Bin Meng
2020-08-15  9:06   ` Philippe Mathieu-Daudé
2020-08-16  8:29     ` Bin Meng
2020-08-16  8:29       ` Bin Meng
2020-08-16 11:14       ` Philippe Mathieu-Daudé
2020-08-16 11:14         ` Philippe Mathieu-Daudé
2020-08-16 12:08       ` Nathan Rossi
2020-08-16 12:08         ` Nathan Rossi
2020-08-16 13:42         ` Bin Meng
2020-08-16 13:42           ` Bin Meng
2020-08-16 16:31           ` Philippe Mathieu-Daudé
2020-08-16 16:31             ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-08-21 18:46   ` Alistair Francis
2020-08-21 18:46     ` Alistair Francis
2020-08-14 16:40 ` [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-08-21 18:47   ` Alistair Francis
2020-08-21 18:47     ` Alistair Francis
2020-08-14 16:40 ` [PATCH 17/18] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-08-25 18:33   ` Alistair Francis
2020-08-25 18:33     ` Alistair Francis
2020-08-14 16:40 ` [PATCH 18/18] hw/riscv: microchip_pfsoc: Document the software used for testing Bin Meng
2020-08-21 18:51   ` Alistair Francis
2020-08-21 18:51     ` Alistair Francis
2020-08-14 17:44 ` [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Anup Patel
2020-08-14 17:44   ` Anup Patel
2020-08-17 10:30   ` Bin Meng
2020-08-17 10:30     ` Bin Meng
2020-08-17 15:44     ` via [this message]
2020-08-17 15:44       ` Cyril.Jean
2020-08-17 19:28       ` Alistair Francis
2020-08-17 19:28         ` Alistair Francis
2020-08-17 19:53         ` via
2020-08-17 19:53           ` Cyril.Jean
2020-08-18  6:17           ` Anup Patel
2020-08-18  6:17             ` Anup Patel
2020-08-18 13:09             ` via
2020-08-18 13:09               ` Cyril.Jean
2020-08-18 13:55               ` Anup Patel
2020-08-18 13:55                 ` Anup Patel
2020-08-19  1:34                 ` Bin Meng
2020-08-19  1:34                   ` Bin Meng
2020-08-19 10:13                   ` via
2020-08-19 10:13                     ` Cyril.Jean
2020-08-21 18:23                     ` Alistair Francis
2020-08-21 18:23                       ` Alistair Francis
2020-08-14 18:10 ` no-reply
2020-08-14 18:10   ` no-reply

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