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From: <Daire.McNamara@microchip.com>
To: <Conor.Dooley@microchip.com>, <geert@linux-m68k.org>
Cc: <linux-riscv@lists.infradead.org>, <linux-usb@vger.kernel.org>,
	<Lewis.Hanly@microchip.com>, <linux-rtc@vger.kernel.org>,
	<linux-gpio@vger.kernel.org>, <atish.patra@wdc.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<alexandre.belloni@bootlin.com>, <paul.walmsley@sifive.com>,
	<Ivan.Griffin@microchip.com>, <devicetree@vger.kernel.org>,
	<bin.meng@windriver.com>, <a.zummo@towertech.it>,
	<jassisinghbrar@gmail.com>, <linus.walleij@linaro.org>,
	<linux-kernel@vger.kernel.org>, <robh+dt@kernel.org>,
	<linux-crypto@vger.kernel.org>, <bgolaszewski@baylibre.com>,
	<gregkh@linuxfoundation.org>, <linux-spi@vger.kernel.org>,
	<krzysztof.kozlowski@canonical.com>, <broonie@kernel.org>,
	<linux-i2c@vger.kernel.org>
Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree
Date: Wed, 17 Nov 2021 12:17:45 +0000	[thread overview]
Message-ID: <22e550697eaf362e6c47f6ce0da7182ceec2d44d.camel@microchip.com> (raw)
In-Reply-To: <CAMuHMdUQRJHkbwj++jJBMG7QqLd5_bmzUrMzyxEd92bgZbvDYw@mail.gmail.com>

On Mon, 2021-11-15 at 17:17 +0100, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> Hi Conor,
> 
> On Mon, Nov 15, 2021 at 4:39 PM <Conor.Dooley@microchip.com> wrote:
> > On 10/11/2021 14:58, Geert Uytterhoeven wrote:
> > > On Wed, Nov 10, 2021 at 3:20 PM <Conor.Dooley@microchip.com>
> > > wrote:
> > > > On 09/11/2021 09:04, Geert Uytterhoeven wrote:
> > > > > On Mon, Nov 8, 2021 at 4:07 PM <conor.dooley@microchip.com>
> > > > > wrote:
> > > > > > From: Conor Dooley <conor.dooley@microchip.com>
> > > > > > 
> > > > > > +&gpio2 {
> > > > > > +       interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT>;
> > > > > 
> > > > > Why override interrupts in the board .dts file?
> > > > > Doesn't this belong in the SoC .dtsi file?
> > > > The interrupt setup for the gpio isnt fixed, there is an option
> > > > to
> > > > either connect the individual gpio interrupts to the plic *or*
> > > > they can
> > > > be connected to a per gpio controller common interrupt, and it
> > > > is up to
> > > > the driver to read a register to determine which interrupt
> > > > triggered the
> > > > common/NON_DIRECT interrupt. This decision is made by a write
> > > > to a
> > > > system register in application code, which to us didn't seem
> > > > like it
> > > > belonged in the soc .dtsi.
> > > 
> > > So it is software policy? Then it doesn't belong in the board DTS
> > > either.
> > 
> > The write (if was to be done) would be done by the bootloader,
> > based on
> > the bitstream written to the FPGA, before even u-boot is started.
> > By
> > application I meant the bootloader (or some other bare metal
> > application), not a program running in userspace in case that's
> > what you
> > interpreted. Am I incorrect in thinking that if it is set up by the
> > bootloader that Linux can take it for granted?
> 
> If it is to be provided by the boot loader, the boot loader should
> fill
> in the interrupts property, just like it already does (or should do,
> if it
> doesn't) for /memory and chosen/bootargs.
Whether a given GPIO is routed via a bank where it has its own
interrupt line or via a bank where it shares an interrupt line is an
SoC capability.  A particular routing is instantiated by a particular
board (e.g. Icicle).  A custom bootloader feels like complete overkill
for this job.
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a
> hacker. But
> when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds

WARNING: multiple messages have this Message-ID (diff)
From: <Daire.McNamara@microchip.com>
To: <Conor.Dooley@microchip.com>, <geert@linux-m68k.org>
Cc: <linux-riscv@lists.infradead.org>, <linux-usb@vger.kernel.org>,
	<Lewis.Hanly@microchip.com>, <linux-rtc@vger.kernel.org>,
	<linux-gpio@vger.kernel.org>, <atish.patra@wdc.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<alexandre.belloni@bootlin.com>, <paul.walmsley@sifive.com>,
	<Ivan.Griffin@microchip.com>, <devicetree@vger.kernel.org>,
	<bin.meng@windriver.com>, <a.zummo@towertech.it>,
	<jassisinghbrar@gmail.com>, <linus.walleij@linaro.org>,
	<linux-kernel@vger.kernel.org>, <robh+dt@kernel.org>,
	<linux-crypto@vger.kernel.org>, <bgolaszewski@baylibre.com>,
	<gregkh@linuxfoundation.org>, <linux-spi@vger.kernel.org>,
	<krzysztof.kozlowski@canonical.com>, <broonie@kernel.org>,
	<linux-i2c@vger.kernel.org>
Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree
Date: Wed, 17 Nov 2021 12:17:45 +0000	[thread overview]
Message-ID: <22e550697eaf362e6c47f6ce0da7182ceec2d44d.camel@microchip.com> (raw)
In-Reply-To: <CAMuHMdUQRJHkbwj++jJBMG7QqLd5_bmzUrMzyxEd92bgZbvDYw@mail.gmail.com>

On Mon, 2021-11-15 at 17:17 +0100, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> Hi Conor,
> 
> On Mon, Nov 15, 2021 at 4:39 PM <Conor.Dooley@microchip.com> wrote:
> > On 10/11/2021 14:58, Geert Uytterhoeven wrote:
> > > On Wed, Nov 10, 2021 at 3:20 PM <Conor.Dooley@microchip.com>
> > > wrote:
> > > > On 09/11/2021 09:04, Geert Uytterhoeven wrote:
> > > > > On Mon, Nov 8, 2021 at 4:07 PM <conor.dooley@microchip.com>
> > > > > wrote:
> > > > > > From: Conor Dooley <conor.dooley@microchip.com>
> > > > > > 
> > > > > > +&gpio2 {
> > > > > > +       interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT
> > > > > > +               PLIC_INT_GPIO2_NON_DIRECT>;
> > > > > 
> > > > > Why override interrupts in the board .dts file?
> > > > > Doesn't this belong in the SoC .dtsi file?
> > > > The interrupt setup for the gpio isnt fixed, there is an option
> > > > to
> > > > either connect the individual gpio interrupts to the plic *or*
> > > > they can
> > > > be connected to a per gpio controller common interrupt, and it
> > > > is up to
> > > > the driver to read a register to determine which interrupt
> > > > triggered the
> > > > common/NON_DIRECT interrupt. This decision is made by a write
> > > > to a
> > > > system register in application code, which to us didn't seem
> > > > like it
> > > > belonged in the soc .dtsi.
> > > 
> > > So it is software policy? Then it doesn't belong in the board DTS
> > > either.
> > 
> > The write (if was to be done) would be done by the bootloader,
> > based on
> > the bitstream written to the FPGA, before even u-boot is started.
> > By
> > application I meant the bootloader (or some other bare metal
> > application), not a program running in userspace in case that's
> > what you
> > interpreted. Am I incorrect in thinking that if it is set up by the
> > bootloader that Linux can take it for granted?
> 
> If it is to be provided by the boot loader, the boot loader should
> fill
> in the interrupts property, just like it already does (or should do,
> if it
> doesn't) for /memory and chosen/bootargs.
Whether a given GPIO is routed via a bank where it has its own
interrupt line or via a bank where it shares an interrupt line is an
SoC capability.  A particular routing is instantiated by a particular
board (e.g. Icicle).  A custom bootloader feels like complete overkill
for this job.
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a
> hacker. But
> when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2021-11-17 12:18 UTC|newest]

Thread overview: 140+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-08 15:05 [PATCH 00/13]Update the icicle kit device tree conor.dooley
2021-11-08 15:05 ` conor.dooley
2021-11-08 15:05 ` [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-23 11:07   ` Heiko Stübner
2021-11-23 11:07     ` Heiko Stübner
2021-11-23 11:35     ` Anup Patel
2021-11-23 11:35       ` Anup Patel
2021-11-29 19:57   ` Rob Herring
2021-11-29 19:57     ` Rob Herring
2021-11-08 15:05 ` [PATCH 02/13] dt-bindings: interrupt-controller: add defines for mpfs-plic conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-23 11:17   ` Heiko Stübner
2021-11-23 11:17     ` Heiko Stübner
2021-11-29 19:56   ` Rob Herring
2021-11-29 19:56     ` Rob Herring
2021-11-30  8:15     ` Conor.Dooley
2021-11-30  8:15       ` Conor.Dooley
2021-11-08 15:05 ` [PATCH 03/13] dt-bindings: soc/microchip: update sys ctrlr compat string conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:09   ` Krzysztof Kozlowski
2021-11-08 21:09     ` Krzysztof Kozlowski
2021-11-09  8:33   ` Geert Uytterhoeven
2021-11-09  8:33     ` Geert Uytterhoeven
2021-11-09 15:20     ` Conor.Dooley
2021-11-09 15:20       ` Conor.Dooley
2021-11-29 20:03   ` Rob Herring
2021-11-29 20:03     ` Rob Herring
2021-11-30  8:35     ` Conor.Dooley
2021-11-30  8:35       ` Conor.Dooley
2021-11-08 15:05 ` [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:10   ` Krzysztof Kozlowski
2021-11-08 21:10     ` Krzysztof Kozlowski
2021-11-09  8:34   ` Geert Uytterhoeven
2021-11-09  8:34     ` Geert Uytterhoeven
2021-11-09 12:08     ` Conor.Dooley
2021-11-09 12:08       ` Conor.Dooley
2021-11-09 13:04       ` Geert Uytterhoeven
2021-11-09 13:04         ` Geert Uytterhoeven
2021-11-23 11:24         ` Heiko Stübner
2021-11-23 11:24           ` Heiko Stübner
2021-11-08 15:05 ` [PATCH 05/13] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:13   ` Krzysztof Kozlowski
2021-11-08 21:13     ` Krzysztof Kozlowski
2021-11-09  4:06   ` Rob Herring
2021-11-09  4:06     ` Rob Herring
2021-11-08 15:05 ` [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:16   ` Krzysztof Kozlowski
2021-11-08 21:16     ` Krzysztof Kozlowski
2021-11-09 12:54     ` Conor.Dooley
2021-11-09 12:54       ` Conor.Dooley
2021-11-09 12:56       ` Krzysztof Kozlowski
2021-11-09 12:56         ` Krzysztof Kozlowski
2021-11-09 13:36         ` Conor.Dooley
2021-11-09 13:36           ` Conor.Dooley
2021-11-10  7:43           ` Krzysztof Kozlowski
2021-11-10  7:43             ` Krzysztof Kozlowski
2021-11-10  9:46             ` Conor.Dooley
2021-11-10  9:46               ` Conor.Dooley
2021-11-29 20:08               ` Rob Herring
2021-11-29 20:08                 ` Rob Herring
2021-11-09  8:37   ` Geert Uytterhoeven
2021-11-09  8:37     ` Geert Uytterhoeven
2021-11-09 11:55     ` Conor.Dooley
2021-11-09 11:55       ` Conor.Dooley
2021-11-08 15:05 ` [PATCH 07/13] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:20   ` Krzysztof Kozlowski
2021-11-08 21:20     ` Krzysztof Kozlowski
2021-11-09  4:06   ` Rob Herring
2021-11-09  4:06     ` Rob Herring
2021-11-09  8:39   ` Geert Uytterhoeven
2021-11-09  8:39     ` Geert Uytterhoeven
2021-11-08 15:05 ` [PATCH 08/13] dt-bindings: soc/microchip: add bindings for mpfs system services conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:20   ` Krzysztof Kozlowski
2021-11-08 21:20     ` Krzysztof Kozlowski
2021-11-08 15:05 ` [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:22   ` Krzysztof Kozlowski
2021-11-08 21:22     ` Krzysztof Kozlowski
2021-11-09  4:06   ` Rob Herring
2021-11-09  4:06     ` Rob Herring
2021-11-09  8:43   ` Geert Uytterhoeven
2021-11-09  8:43     ` Geert Uytterhoeven
2021-11-08 15:05 ` [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:24   ` Krzysztof Kozlowski
2021-11-08 21:24     ` Krzysztof Kozlowski
2021-11-09  4:06   ` Rob Herring
2021-11-09  4:06     ` Rob Herring
2021-11-09 12:16     ` Conor.Dooley
2021-11-09 12:16       ` Conor.Dooley
2021-11-09 12:53       ` Krzysztof Kozlowski
2021-11-09 12:53         ` Krzysztof Kozlowski
2021-11-09 12:58         ` Conor.Dooley
2021-11-09 12:58           ` Conor.Dooley
2021-11-09 13:04           ` Krzysztof Kozlowski
2021-11-09 13:04             ` Krzysztof Kozlowski
2021-11-09 13:20             ` Conor.Dooley
2021-11-09 13:20               ` Conor.Dooley
2021-11-10  7:45               ` Krzysztof Kozlowski
2021-11-10  7:45                 ` Krzysztof Kozlowski
2021-11-09  8:45   ` Geert Uytterhoeven
2021-11-09  8:45     ` Geert Uytterhoeven
2021-11-09 10:56     ` Conor.Dooley
2021-11-09 10:56       ` Conor.Dooley
2021-11-08 15:05 ` [PATCH 11/13] dt-bindings: usb: add bindings for microchip mpfs musb conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:27   ` Krzysztof Kozlowski
2021-11-08 21:27     ` Krzysztof Kozlowski
2021-11-09  4:06   ` Rob Herring
2021-11-09  4:06     ` Rob Herring
2021-11-09  8:48   ` Geert Uytterhoeven
2021-11-09  8:48     ` Geert Uytterhoeven
2021-11-08 15:05 ` [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree conor.dooley
2021-11-08 15:05   ` conor.dooley
2021-11-08 21:40   ` Krzysztof Kozlowski
2021-11-08 21:40     ` Krzysztof Kozlowski
2021-11-10 12:07     ` Conor.Dooley
2021-11-10 12:07       ` Conor.Dooley
2021-11-09  9:04   ` Geert Uytterhoeven
2021-11-09  9:04     ` Geert Uytterhoeven
2021-11-10 14:19     ` Conor.Dooley
2021-11-10 14:19       ` Conor.Dooley
2021-11-10 14:58       ` Geert Uytterhoeven
2021-11-10 14:58         ` Geert Uytterhoeven
2021-11-10 15:07         ` Conor.Dooley
2021-11-10 15:07           ` Conor.Dooley
2021-11-15 15:39         ` Conor.Dooley
2021-11-15 15:39           ` Conor.Dooley
2021-11-15 16:17           ` Geert Uytterhoeven
2021-11-15 16:17             ` Geert Uytterhoeven
2021-11-17 12:17             ` Daire.McNamara [this message]
2021-11-17 12:17               ` Daire.McNamara
2021-11-08 15:05 ` [PATCH 13/13] MAINTAINERS: update riscv/microchip entry conor.dooley
2021-11-08 15:05   ` conor.dooley

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