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From: Alistair Francis <alistair.francis@xilinx.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alindsay@codeaurora.org,
	alistair.francis@xilinx.com, crosthwaitepeter@gmail.com,
	cov@codeaurora.org, nathan@nathanrossi.com
Subject: [Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug feature register
Date: Fri, 5 Feb 2016 16:55:26 -0800	[thread overview]
Message-ID: <24060e5dc8377b31c33a0e5f0ce6909910042aef.1454720021.git.alistair.francis@xilinx.com> (raw)
In-Reply-To: <cover.1454720020.git.alistair.francis@xilinx.com>

The previously missing registers are now present in QEMU.

Signed-off-by: Christopher Covington <christopher.covington@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---

 target-arm/helper.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index b4bf6fa..1775768 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4267,12 +4267,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_CONST,
-              /* We mask out the PMUVer field, because we don't currently
-               * implement the PMU. Not advertising it prevents the guest
-               * from trying to use it and getting UNDEFs on registers we
-               * don't implement.
-               */
-              .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
+              .resetvalue = cpu->id_aa64dfr0 },
             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.5.0

  parent reply	other threads:[~2016-02-06  0:58 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-06  0:55 [Qemu-devel] [PATCH v2 0/5] Extend the performance monitoring registers Alistair Francis
2016-02-06  0:55 ` [Qemu-devel] [PATCH v2 1/5] target-arm: Add the pmceid0 and pmceid1 registers Alistair Francis
2016-02-09 17:19   ` Peter Maydell
2016-02-09 17:48     ` Christopher Covington
2016-02-09 17:55       ` Peter Maydell
2016-02-09 23:11     ` Alistair Francis
2016-02-10 13:52       ` Aaron Lindsay
2016-02-16 13:58         ` Peter Maydell
2016-02-06  0:55 ` [Qemu-devel] [PATCH v2 2/5] target-arm: Add Some of the performance monitor registers Alistair Francis
2016-02-09 17:32   ` Peter Maydell
2016-02-09 23:25     ` Alistair Francis
2016-02-06  0:55 ` [Qemu-devel] [PATCH v2 3/5] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers Alistair Francis
2016-02-09 17:35   ` Peter Maydell
2016-02-06  0:55 ` [Qemu-devel] [PATCH v2 4/5] target-arm: Add PMUSERENR_EL0 register Alistair Francis
2016-02-09 17:37   ` Peter Maydell
2016-02-06  0:55 ` Alistair Francis [this message]
2016-02-09 17:43   ` [Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug feature register Peter Maydell

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