Re: [Qemu-devel] [PATCH v2 1/5] target-arm: Add the pmceid0 and pmceid1 registers

[Peter Maydell <peter.maydell@linaro.org>]

On 10 February 2016 at 13:52, Aaron Lindsay <alindsay@codeaurora.org> wrote:
> On Feb 09 15:11, Alistair Francis wrote:
>> On Tue, Feb 9, 2016 at 9:19 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> > On 6 February 2016 at 00:55, Alistair Francis
>> > <alistair.francis@xilinx.com> wrote:
>> >> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
>> >> index 7ddbf3d..937f845 100644
>> >> --- a/target-arm/cpu.c
>> >> +++ b/target-arm/cpu.c
>> >> @@ -1156,6 +1156,8 @@ static void cortex_a15_initfn(Object *obj)
>> >>      cpu->id_pfr0 = 0x00001131;
>> >>      cpu->id_pfr1 = 0x00011011;
>> >>      cpu->id_dfr0 = 0x02010555;
>> >> +    cpu->pmceid0 = 0x00000481; /* PMUv3 events 0x0, 0x8, and 0x11 */
>> >
>> > These are:
>> >  SW_INCR   # insn architecturally executed, cc pass, software increment
>> >  INST_RETIRED # insn architecturally executed
>> >  CPU_CYCLES # cycle
>> >
>> > However we don't actually implement any of these, so should
>> > we be advertising them?
>>
>> So this part I took directly from Chris's RFC. I'm happy to take it
>> out if you would like.
>
> I think removing the PMCEID0 change makes sense since these patches
> don't implement the advertised counters. We have other patches which do
> implement them, but they need some more work, so we can make this change
> if/when they're actually implemented.

I agree, so I propose to take Alistair's v3 series into target-arm.next
with the following change:

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 1203783..e95b030 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1156,7 +1156,7 @@ static void cortex_a15_initfn(Object *obj)
     cpu->id_pfr0 = 0x00001131;
     cpu->id_pfr1 = 0x00011011;
     cpu->id_dfr0 = 0x02010555;
-    cpu->pmceid0 = 0x00000481; /* PMUv3 events 0x0, 0x8, and 0x11 */
+    cpu->pmceid0 = 0x0000000;
     cpu->pmceid1 = 0x00000000;
     cpu->id_afr0 = 0x00000000;
     cpu->id_mmfr0 = 0x10201105;
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index fc336e1..fa5eda2 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -135,7 +135,7 @@ static void aarch64_a57_initfn(Object *obj)
     cpu->id_isar5 = 0x00011121;
     cpu->id_aa64pfr0 = 0x00002222;
     cpu->id_aa64dfr0 = 0x10305106;
-    cpu->pmceid0 = 0x00000481; /* PMUv3 events 0x0, 0x8, and 0x11 */
+    cpu->pmceid0 = 0x00000000;
     cpu->pmceid1 = 0x00000000;
     cpu->id_aa64isar0 = 0x00011120;
     cpu->id_aa64mmfr0 = 0x00001124;

If anybody disagrees let me know; otherwise this will go into a pullreq
later this week.

thanks
-- PMM