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From: liweiwei <liweiwei@iscas.ac.cn>
To: Richard Henderson <richard.henderson@linaro.org>,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, ardxwe@gmail.com
Subject: Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx
Date: Sun, 26 Dec 2021 09:54:04 +0800	[thread overview]
Message-ID: <25f6e9a9-ebee-e3d3-9b06-dd4a0d11cd79@iscas.ac.cn> (raw)
In-Reply-To: <9ea3554f-367a-bd4e-fc4f-a98367b96260@iscas.ac.cn>

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OK. It have been changed to sign-extended in the "processing of Narrower 
Values" section of the new spec(version 1.0.0.rc) . I'll fix this and 
update other nan-boxing processing in current implementation.

在 2021/12/26 上午9:42, liweiwei 写道:
>
> Sorry. In the old spec(version 0.41), nanboxing is not totally 
> disabled, but "NaN-boxing is limited to |XLEN| bits, not |FLEN| bits". 
> Taking misa.mxl into acount, if misa.mxl is RV32, and maximum is RV64, 
> this should be sign-extended. Is there any other new update for 
> nanboxing  to the spec?
>
> 在 2021/12/26 上午6:00, Richard Henderson 写道:
>> On 12/24/21 7:13 PM, liweiwei wrote:
>>> In RV64 case, this should be nan-boxing value( upper bits are all 
>>> ones).  However, zfinx will not check nan-boxing of source, the 
>>> upper 32 bits have no effect on the final result. So I think both 
>>> zero-extended or sign-extended are OK.
>>
>> There is no nanboxing in zfinx at all -- values are sign-extended.
>>
>>
>> r~

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  reply	other threads:[~2021-12-26  1:56 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-24  3:49 [PATCH 0/6] support subsets of Float-Point in Integer Registers extensions liweiwei
2021-12-24  3:49 ` liweiwei
2021-12-24  3:49 ` [PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 21:40   ` Richard Henderson
2022-01-03 22:47   ` Alistair Francis
2022-01-03 22:47     ` Alistair Francis
2021-12-24  3:49 ` [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:00   ` Richard Henderson
2021-12-25  3:13     ` liweiwei
2021-12-25 22:00       ` Richard Henderson
2021-12-26  1:42         ` liweiwei
2021-12-26  1:54           ` liweiwei [this message]
2021-12-26  3:48           ` Richard Henderson
2021-12-24  3:49 ` [PATCH 3/6] target/riscv: add " liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:26   ` Richard Henderson
2021-12-25  3:24     ` liweiwei
2021-12-24  3:49 ` [PATCH 4/6] target/riscv: add support for zdinx liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:30   ` Richard Henderson
2021-12-25  3:27     ` liweiwei
2021-12-24  3:49 ` [PATCH 5/6] target/riscv: add support for zhinx/zhinxmin liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:32   ` Richard Henderson
2021-12-25  3:35     ` liweiwei
2021-12-24  3:49 ` [PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:32   ` Richard Henderson

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