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From: Richard Henderson <richard.henderson@linaro.org>
To: liweiwei <liweiwei@iscas.ac.cn>,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, ardxwe@gmail.com
Subject: Re: [PATCH 4/6] target/riscv: add support for zdinx
Date: Fri, 24 Dec 2021 14:30:56 -0800	[thread overview]
Message-ID: <39665e5f-f672-45d6-d3f1-39136a5c1c08@linaro.org> (raw)
In-Reply-To: <20211224034915.17204-5-liweiwei@iscas.ac.cn>

On 12/23/21 7:49 PM, liweiwei wrote:
>   static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
>   {
> +    REQUIRE_FPU;
> +    REQUIRE_ZDINX_OR_D(ctx);
> +
> +    TCGv_i64 dest = dest_fpr(ctx, a->rd);
> +    TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
> +    TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
> +
>       if (a->rs1 == a->rs2) { /* FMOV */

Applies to the F version as well, but we should not assemble src2 when we don't need it.

> -        tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
> +        tcg_gen_mov_i64(dest, src1);


I think this can just be dest = get_fpr_d(ctx, a->src1), leaving the final "move" to 
gen_set_fpr_d.


r~


  reply	other threads:[~2021-12-24 22:32 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-24  3:49 [PATCH 0/6] support subsets of Float-Point in Integer Registers extensions liweiwei
2021-12-24  3:49 ` liweiwei
2021-12-24  3:49 ` [PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 21:40   ` Richard Henderson
2022-01-03 22:47   ` Alistair Francis
2022-01-03 22:47     ` Alistair Francis
2021-12-24  3:49 ` [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:00   ` Richard Henderson
2021-12-25  3:13     ` liweiwei
2021-12-25 22:00       ` Richard Henderson
2021-12-26  1:42         ` liweiwei
2021-12-26  1:54           ` liweiwei
2021-12-26  3:48           ` Richard Henderson
2021-12-24  3:49 ` [PATCH 3/6] target/riscv: add " liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:26   ` Richard Henderson
2021-12-25  3:24     ` liweiwei
2021-12-24  3:49 ` [PATCH 4/6] target/riscv: add support for zdinx liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:30   ` Richard Henderson [this message]
2021-12-25  3:27     ` liweiwei
2021-12-24  3:49 ` [PATCH 5/6] target/riscv: add support for zhinx/zhinxmin liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:32   ` Richard Henderson
2021-12-25  3:35     ` liweiwei
2021-12-24  3:49 ` [PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:32   ` Richard Henderson

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