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From: Richard Henderson <richard.henderson@linaro.org>
To: liweiwei <liweiwei@iscas.ac.cn>,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, ardxwe@gmail.com
Subject: Re: [PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
Date: Fri, 24 Dec 2021 14:32:37 -0800	[thread overview]
Message-ID: <e2209460-1592-e6fa-18be-54a7f66c9387@linaro.org> (raw)
In-Reply-To: <20211224034915.17204-7-liweiwei@iscas.ac.cn>

On 12/23/21 7:49 PM, liweiwei wrote:
> Co-authored-by: ardxwe <ardxwe@gmail.com>
> Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
> Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/cpu.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a5fa14f2ac..dbd15693be 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -657,6 +657,10 @@ static Property riscv_cpu_properties[] = {
>       DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>       DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
>       DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> +    DEFINE_PROP_BOOL("Zdinx", RISCVCPU, cfg.ext_zdinx, false),
> +    DEFINE_PROP_BOOL("Zfinx", RISCVCPU, cfg.ext_zfinx, false),
> +    DEFINE_PROP_BOOL("Zhinx", RISCVCPU, cfg.ext_zhinx, false),
> +    DEFINE_PROP_BOOL("Zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
>       DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>       DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>       /* ePMP 0.9.3 */
> 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


      reply	other threads:[~2021-12-24 22:34 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-24  3:49 [PATCH 0/6] support subsets of Float-Point in Integer Registers extensions liweiwei
2021-12-24  3:49 ` liweiwei
2021-12-24  3:49 ` [PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 21:40   ` Richard Henderson
2022-01-03 22:47   ` Alistair Francis
2022-01-03 22:47     ` Alistair Francis
2021-12-24  3:49 ` [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:00   ` Richard Henderson
2021-12-25  3:13     ` liweiwei
2021-12-25 22:00       ` Richard Henderson
2021-12-26  1:42         ` liweiwei
2021-12-26  1:54           ` liweiwei
2021-12-26  3:48           ` Richard Henderson
2021-12-24  3:49 ` [PATCH 3/6] target/riscv: add " liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:26   ` Richard Henderson
2021-12-25  3:24     ` liweiwei
2021-12-24  3:49 ` [PATCH 4/6] target/riscv: add support for zdinx liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:30   ` Richard Henderson
2021-12-25  3:27     ` liweiwei
2021-12-24  3:49 ` [PATCH 5/6] target/riscv: add support for zhinx/zhinxmin liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:32   ` Richard Henderson
2021-12-25  3:35     ` liweiwei
2021-12-24  3:49 ` [PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties liweiwei
2021-12-24  3:49   ` liweiwei
2021-12-24 22:32   ` Richard Henderson [this message]

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