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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>,
	linux-arm-kernel@lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	coresight@lists.linaro.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 2/7] arm64: errata: Add detection for TRBE ignored system register writes
Date: Fri, 7 Jan 2022 11:39:08 +0000	[thread overview]
Message-ID: <267afb26-00c3-63e6-6b8f-6f20785cab82@arm.com> (raw)
In-Reply-To: <1641517808-5735-3-git-send-email-anshuman.khandual@arm.com>

On 07/01/2022 01:10, Anshuman Khandual wrote:
> TRBE implementations affected by Arm erratum #2064142 might fail to write
> into certain system registers after the TRBE has been disabled. Under some
> conditions after TRBE has been disabled, writes into certain TRBE registers
> TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1 and TRBTRG_EL1 will be
> ignored and not be effected. This adds a new errata ARM64_ERRATUM_2064142
> in arm64 errata framework.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> Cc: coresight@lists.linaro.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>   Documentation/arm64/silicon-errata.rst |  2 ++
>   arch/arm64/Kconfig                     | 18 ++++++++++++++++++
>   arch/arm64/kernel/cpu_errata.c         |  9 +++++++++
>   arch/arm64/tools/cpucaps               |  1 +
>   4 files changed, 30 insertions(+)
> 


Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>,
	linux-arm-kernel@lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	 Mathieu Poirier <mathieu.poirier@linaro.org>,
	coresight@lists.linaro.org,  linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 2/7] arm64: errata: Add detection for TRBE ignored system register writes
Date: Fri, 7 Jan 2022 11:39:08 +0000	[thread overview]
Message-ID: <267afb26-00c3-63e6-6b8f-6f20785cab82@arm.com> (raw)
In-Reply-To: <1641517808-5735-3-git-send-email-anshuman.khandual@arm.com>

On 07/01/2022 01:10, Anshuman Khandual wrote:
> TRBE implementations affected by Arm erratum #2064142 might fail to write
> into certain system registers after the TRBE has been disabled. Under some
> conditions after TRBE has been disabled, writes into certain TRBE registers
> TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1 and TRBTRG_EL1 will be
> ignored and not be effected. This adds a new errata ARM64_ERRATUM_2064142
> in arm64 errata framework.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> Cc: coresight@lists.linaro.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>   Documentation/arm64/silicon-errata.rst |  2 ++
>   arch/arm64/Kconfig                     | 18 ++++++++++++++++++
>   arch/arm64/kernel/cpu_errata.c         |  9 +++++++++
>   arch/arm64/tools/cpucaps               |  1 +
>   4 files changed, 30 insertions(+)
> 


Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2022-01-07 11:39 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-07  1:10 [PATCH V2 0/7] coresight: trbe: Workaround Cortex-A510 erratas Anshuman Khandual
2022-01-07  1:10 ` Anshuman Khandual
2022-01-07  1:10 ` [PATCH V2 1/7] arm64: Add Cortex-A510 CPU part definition Anshuman Khandual
2022-01-07  1:10   ` Anshuman Khandual
2022-01-07 10:56   ` Catalin Marinas
2022-01-07 10:56     ` Catalin Marinas
2022-01-07  1:10 ` [PATCH V2 2/7] arm64: errata: Add detection for TRBE ignored system register writes Anshuman Khandual
2022-01-07  1:10   ` Anshuman Khandual
2022-01-07 10:58   ` Catalin Marinas
2022-01-07 10:58     ` Catalin Marinas
2022-01-07 11:39   ` Suzuki K Poulose [this message]
2022-01-07 11:39     ` Suzuki K Poulose
2022-01-07  1:10 ` [PATCH V2 3/7] arm64: errata: Add detection for TRBE invalid prohibited states Anshuman Khandual
2022-01-07  1:10   ` Anshuman Khandual
2022-01-07 10:59   ` Catalin Marinas
2022-01-07 10:59     ` Catalin Marinas
2022-01-07 11:56   ` Suzuki K Poulose
2022-01-07 11:56     ` Suzuki K Poulose
2022-01-07  1:10 ` [PATCH V2 4/7] arm64: errata: Add detection for TRBE trace data corruption Anshuman Khandual
2022-01-07  1:10   ` Anshuman Khandual
2022-01-07 10:59   ` Catalin Marinas
2022-01-07 10:59     ` Catalin Marinas
2022-01-07 11:58   ` Suzuki K Poulose
2022-01-07 11:58     ` Suzuki K Poulose
2022-01-07  1:10 ` [PATCH V2 5/7] coresight: trbe: Work around the ignored system register writes Anshuman Khandual
2022-01-07  1:10   ` Anshuman Khandual
2022-01-10 11:03   ` Suzuki K Poulose
2022-01-10 11:03     ` Suzuki K Poulose
2022-01-10 11:59     ` Anshuman Khandual
2022-01-10 11:59       ` Anshuman Khandual
2022-01-07  1:10 ` [PATCH V2 6/7] coresight: trbe: Work around the invalid prohibited states Anshuman Khandual
2022-01-07  1:10   ` Anshuman Khandual
2022-01-10 12:03   ` Suzuki K Poulose
2022-01-10 12:03     ` Suzuki K Poulose
2022-01-07  1:10 ` [PATCH V2 7/7] coresight: trbe: Work around the trace data corruption Anshuman Khandual
2022-01-07  1:10   ` Anshuman Khandual
2022-01-10 12:04   ` Suzuki K Poulose
2022-01-10 12:04     ` Suzuki K Poulose

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