[Intel-gfx] [PATCH 00/15] drm/i915/tgl: Render/media decompression support

[Intel-gfx] [PATCH 00/15] drm/i915/tgl: Render/media decompression support

[Imre Deak]

This is an updated version of DK's and RK's patchset enabling
render/media decompression. The fixes in this version apply mostly to
get YUV formats working. Wrt. RK's last patchset the order of planes in
semiplanar YUV FBs has changed, see patch 11 for details.

I tested the normal and panned (non-zero FB source coords) scan out of
the following formats: RGB32, YUYV, NV12, P0xx. I'll follow up for the
actual IGT tests for these.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>

Dhinakaran Pandiyan (9):
  drm/framebuffer: Format modifier for Intel Gen-12 render compression
  drm/i915: Use intel_tile_height() instead of re-implementing
  drm/i915: Move CCS stride alignment W/A inside
    intel_fb_stride_alignment
  drm/i915: Extract framebufer CCS offset checks into a function
  drm/i915/tgl: Gen-12 render decompression
  drm/i915: Skip rotated offset adjustment for unsupported modifiers
  drm/framebuffer: Format modifier for Intel Gen-12 media compression
  drm/fb: Extend format_info member arrays to handle four planes
  drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the
    media engine

Imre Deak (4):
  drm/i915: Add helpers to select correct ccs/aux planes
  drm/i915/tgl: Make sure FBs have a correct CCS plane stride
  drm/i915: Make sure Y slave planes get all the required state
  drm/i915: Make sure CCS YUV semiplanar format checks work

Radhakrishna Sripada (2):
  drm/framebuffer: Format modifier for Intel Gen 12 render compression
    with Clear Color
  drm/i915/tgl: Add Clear Color support for TGL Render Decompression

 .../gpu/drm/i915/display/intel_atomic_plane.c |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 581 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_display.h  |   5 +
 .../drm/i915/display/intel_display_types.h    |   9 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  87 ++-
 drivers/gpu/drm/i915/i915_reg.h               |  14 +
 drivers/gpu/drm/i915/intel_pm.c               |   7 +-
 include/drm/drm_fourcc.h                      |   8 +-
 include/uapi/drm/drm_fourcc.h                 |  43 ++
 9 files changed, 615 insertions(+), 141 deletions(-)

-- 
2.22.0

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[Intel-gfx] [PATCH 01/15] drm/framebuffer: Format modifier for Intel Gen-12 render compression

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 has a new compression format, add a new modifier to indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8caaaf7ff91b..5ba481f49931 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 01/15] drm/framebuffer: Format modifier for Intel Gen-12 render compression

[Kahola, Mika]

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Gen-12 has a new compression format, add a new modifier to indicate
> that.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  include/uapi/drm/drm_fourcc.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h
> index 8caaaf7ff91b..5ba481f49931 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -410,6 +410,17 @@ extern "C" {
>  #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
>  #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
>  
> +/*
> + * Intel color control surfaces (CCS) for Gen-12 render compression.
> + *
> + * The main surface is Y-tiled and at plane index 0, the CCS is
> linear and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1
> tiles in
> + * main surface. In other words, 4 bits in CCS map to a main surface
> cache
> + * line pair. The main surface pitch is required to be a multiple of
> four
> + * Y-tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL,
> 6)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized
> macroblocks
>   *
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Re: [Intel-gfx] [PATCH 01/15] drm/framebuffer: Format modifier for Intel Gen-12 render compression

[Matt Roper]

On Wed, Dec 18, 2019 at 06:10:51PM +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Gen-12 has a new compression format, add a new modifier to indicate that.

There's been some recent hallway chat about this, but it might be worth
naming this "TGL" rather then "GEN12" and using a fresh modifier even if
future gen12+ platforms seemingly have the same general CCS layout and
programming model.  Using the same modifier between multiple platforms
implies that the data format truly is compatible between them and that
one platform can consume the surfaces generated by another (even if you
can't do direct sharing via dma_buf, you could theoretically copy buffer
contents over the network, save/restore buffers from disk, etc.).  Even
if things look identical at the bspec level, there's no guarantee that
the hardware guys won't tweak the underlying compression algorithm
between platforms in a way that makes the buffers generated by one GPU
incompatible with a different platform.

In fact we've already seen one instance of this type of incompatibility
--- EHL/JSL's GT uses a very slightly different packing format than ICL
did.  In that case there was a chicken register we could use to make the
EHL GT use the ICL-style packing (and we had to set this bit anyway for
the display controller to be able to consume GT-rendered buffers).  But
going forward I think we probably want to use per-platform modifiers
rather than per-generation modifiers by default.


Matt

> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 8caaaf7ff91b..5ba481f49931 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -410,6 +410,17 @@ extern "C" {
>  #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
>  #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
>  
> +/*
> + * Intel color control surfaces (CCS) for Gen-12 render compression.
> + *
> + * The main surface is Y-tiled and at plane index 0, the CCS is linear and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
> + * main surface. In other words, 4 bits in CCS map to a main surface cache
> + * line pair. The main surface pitch is required to be a multiple of four
> + * Y-tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> -- 
> 2.22.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 01/15] drm/framebuffer: Format modifier for Intel Gen-12 render compression

[Imre Deak]

On Thu, Dec 19, 2019 at 01:03:52PM -0800, Matt Roper wrote:
> On Wed, Dec 18, 2019 at 06:10:51PM +0200, Imre Deak wrote:
> > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > 
> > Gen-12 has a new compression format, add a new modifier to indicate that.
> 
> There's been some recent hallway chat about this, but it might be worth
> naming this "TGL" rather then "GEN12" and using a fresh modifier even if
> future gen12+ platforms seemingly have the same general CCS layout and
> programming model.  Using the same modifier between multiple platforms
> implies that the data format truly is compatible between them and that
> one platform can consume the surfaces generated by another (even if you
> can't do direct sharing via dma_buf, you could theoretically copy buffer
> contents over the network, save/restore buffers from disk, etc.).  Even
> if things look identical at the bspec level, there's no guarantee that
> the hardware guys won't tweak the underlying compression algorithm
> between platforms in a way that makes the buffers generated by one GPU
> incompatible with a different platform.
> 
> In fact we've already seen one instance of this type of incompatibility
> --- EHL/JSL's GT uses a very slightly different packing format than ICL
> did.  In that case there was a chicken register we could use to make the
> EHL GT use the ICL-style packing (and we had to set this bit anyway for
> the display controller to be able to consume GT-rendered buffers).  But
> going forward I think we probably want to use per-platform modifiers
> rather than per-generation modifiers by default.

Okay, however, the possibility to share the buffers between GPUs
(without having to decompress/recompress) is an important feature imo,
so I wouldn't be surprised if HW would be designed with this in mind.
Some kind of architecture document proposed actually these modifier
names, not sure if the authors of that didn't think about buffer
sharing.

Can't we assume that the design would be sensible and call the format
that is shareable at least among GEN12 platforms GEN12? I think we could
use a new modifier name for a platform generating an incompatible
format. I agree that we should make sure the buffers are truly shareable
before allowing to share modifier names.

--Imre

> 
> Matt
> 
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  include/uapi/drm/drm_fourcc.h | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 8caaaf7ff91b..5ba481f49931 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -410,6 +410,17 @@ extern "C" {
> >  #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
> >  #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
> >  
> > +/*
> > + * Intel color control surfaces (CCS) for Gen-12 render compression.
> > + *
> > + * The main surface is Y-tiled and at plane index 0, the CCS is linear and
> > + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
> > + * main surface. In other words, 4 bits in CCS map to a main surface cache
> > + * line pair. The main surface pitch is required to be a multiple of four
> > + * Y-tile widths.
> > + */
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
> > +
> >  /*
> >   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> >   *
> > -- 
> > 2.22.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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[PATCH 01/15] drm/framebuffer: Format modifier for Intel Gen-12 render compression

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 has a new compression format, add a new modifier to indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8caaaf7ff91b..5ba481f49931 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.22.0

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[Intel-gfx] [PATCH 01/15] drm/framebuffer: Format modifier for Intel Gen-12 render compression

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 has a new compression format, add a new modifier to indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8caaaf7ff91b..5ba481f49931 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.22.0

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[Intel-gfx] [PATCH 02/15] drm/i915: Use intel_tile_height() instead of re-implementing

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

intel_tile_dims() computes tile height using size and width, when there
is already a function to do just that - intel_tile_height()

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 25af0ffe1c3a..928a581336a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1997,7 +1997,7 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
 	unsigned int cpp = fb->format->cpp[color_plane];
 
 	*tile_width = tile_width_bytes / cpp;
-	*tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
+	*tile_height = intel_tile_height(fb, color_plane);
 }
 
 unsigned int
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 02/15] drm/i915: Use intel_tile_height() instead of re-implementing

[Kahola, Mika]

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> intel_tile_dims() computes tile height using size and width, when
> there
> is already a function to do just that - intel_tile_height()
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 25af0ffe1c3a..928a581336a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1997,7 +1997,7 @@ static void intel_tile_dims(const struct
> drm_framebuffer *fb, int color_plane,
>  	unsigned int cpp = fb->format->cpp[color_plane];
>  
>  	*tile_width = tile_width_bytes / cpp;
> -	*tile_height = intel_tile_size(to_i915(fb->dev)) /
> tile_width_bytes;
> +	*tile_height = intel_tile_height(fb, color_plane);
>  }
>  
>  unsigned int
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Re: [Intel-gfx] [PATCH 02/15] drm/i915: Use intel_tile_height() instead of re-implementing

[Matt Roper]

On Wed, Dec 18, 2019 at 06:10:52PM +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> intel_tile_dims() computes tile height using size and width, when there
> is already a function to do just that - intel_tile_height()
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 25af0ffe1c3a..928a581336a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1997,7 +1997,7 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
>  	unsigned int cpp = fb->format->cpp[color_plane];
>  
>  	*tile_width = tile_width_bytes / cpp;
> -	*tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
> +	*tile_height = intel_tile_height(fb, color_plane);
>  }
>  
>  unsigned int
> -- 
> 2.22.0
> 

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 03/15] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Easier to read if all the alignment changes are in one place and contained
within a function.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 928a581336a7..9c27cf651e08 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2589,7 +2589,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		else
 			return 64;
 	} else {
-		return intel_tile_width_bytes(fb, color_plane);
+		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+
+		/*
+		 * Display WA #0531: skl,bxt,kbl,glk
+		 *
+		 * Render decompression and plane width > 3840
+		 * combined with horizontal panning requires the
+		 * plane stride to be a multiple of 4. We'll just
+		 * require the entire fb to accommodate that to avoid
+		 * potential runtime errors at plane configuration time.
+		 */
+		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
+		    color_plane == 0 && fb->width > 3840)
+			tile_width *= 4;
+
+		return tile_width;
 	}
 }
 
@@ -16341,20 +16356,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		}
 
 		stride_alignment = intel_fb_stride_alignment(fb, i);
-
-		/*
-		 * Display WA #0531: skl,bxt,kbl,glk
-		 *
-		 * Render decompression and plane width > 3840
-		 * combined with horizontal panning requires the
-		 * plane stride to be a multiple of 4. We'll just
-		 * require the entire fb to accommodate that to avoid
-		 * potential runtime errors at plane configuration time.
-		 */
-		if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
-		    is_ccs_modifier(fb->modifier))
-			stride_alignment *= 4;
-
 		if (fb->pitches[i] & (stride_alignment - 1)) {
 			DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
 				      i, fb->pitches[i], stride_alignment);
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 03/15] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

[Kahola, Mika]

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Easier to read if all the alignment changes are in one place and
> contained
> within a function.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++------
> ----
>  1 file changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 928a581336a7..9c27cf651e08 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2589,7 +2589,22 @@ intel_fb_stride_alignment(const struct
> drm_framebuffer *fb, int color_plane)
>  		else
>  			return 64;
>  	} else {
> -		return intel_tile_width_bytes(fb, color_plane);
> +		u32 tile_width = intel_tile_width_bytes(fb,
> color_plane);
> +
> +		/*
> +		 * Display WA #0531: skl,bxt,kbl,glk
> +		 *
> +		 * Render decompression and plane width > 3840
> +		 * combined with horizontal panning requires the
> +		 * plane stride to be a multiple of 4. We'll just
> +		 * require the entire fb to accommodate that to avoid
> +		 * potential runtime errors at plane configuration
> time.
> +		 */
> +		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb-
> >modifier) &&
> +		    color_plane == 0 && fb->width > 3840)
> +			tile_width *= 4;
> +
> +		return tile_width;
>  	}
>  }
>  
> @@ -16341,20 +16356,6 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
>  		}
>  
>  		stride_alignment = intel_fb_stride_alignment(fb, i);
> -
> -		/*
> -		 * Display WA #0531: skl,bxt,kbl,glk
> -		 *
> -		 * Render decompression and plane width > 3840
> -		 * combined with horizontal panning requires the
> -		 * plane stride to be a multiple of 4. We'll just
> -		 * require the entire fb to accommodate that to avoid
> -		 * potential runtime errors at plane configuration
> time.
> -		 */
> -		if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840
> &&
> -		    is_ccs_modifier(fb->modifier))
> -			stride_alignment *= 4;
> -
>  		if (fb->pitches[i] & (stride_alignment - 1)) {
>  			DRM_DEBUG_KMS("plane %d pitch (%d) must be at
> least %u byte aligned\n",
>  				      i, fb->pitches[i],
> stride_alignment);
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Re: [Intel-gfx] [PATCH 03/15] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

[Matt Roper]

On Wed, Dec 18, 2019 at 06:10:53PM +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Easier to read if all the alignment changes are in one place and contained
> within a function.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
>  1 file changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 928a581336a7..9c27cf651e08 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2589,7 +2589,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  		else
>  			return 64;
>  	} else {
> -		return intel_tile_width_bytes(fb, color_plane);
> +		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
> +
> +		/*
> +		 * Display WA #0531: skl,bxt,kbl,glk
> +		 *
> +		 * Render decompression and plane width > 3840
> +		 * combined with horizontal panning requires the
> +		 * plane stride to be a multiple of 4. We'll just
> +		 * require the entire fb to accommodate that to avoid
> +		 * potential runtime errors at plane configuration time.
> +		 */
> +		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
> +		    color_plane == 0 && fb->width > 3840)
> +			tile_width *= 4;
> +
> +		return tile_width;
>  	}
>  }
>  
> @@ -16341,20 +16356,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  		}
>  
>  		stride_alignment = intel_fb_stride_alignment(fb, i);
> -
> -		/*
> -		 * Display WA #0531: skl,bxt,kbl,glk
> -		 *
> -		 * Render decompression and plane width > 3840
> -		 * combined with horizontal panning requires the
> -		 * plane stride to be a multiple of 4. We'll just
> -		 * require the entire fb to accommodate that to avoid
> -		 * potential runtime errors at plane configuration time.
> -		 */
> -		if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
> -		    is_ccs_modifier(fb->modifier))
> -			stride_alignment *= 4;
> -
>  		if (fb->pitches[i] & (stride_alignment - 1)) {
>  			DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
>  				      i, fb->pitches[i], stride_alignment);
> -- 
> 2.22.0
> 

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 04/15] drm/i915: Extract framebufer CCS offset checks into a function

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 70 +++++++++++---------
 1 file changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9c27cf651e08..4b8b44c39724 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2676,6 +2676,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static int
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+{
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	int hsub = fb->format->hsub;
+	int vsub = fb->format->vsub;
+	int tile_width, tile_height;
+	int ccs_x, ccs_y;
+	int main_x, main_y;
+
+	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+
+	tile_width *= hsub;
+	tile_height *= vsub;
+
+	ccs_x = (x * hsub) % tile_width;
+	ccs_y = (y * vsub) % tile_height;
+	main_x = intel_fb->normal[0].x % tile_width;
+	main_y = intel_fb->normal[0].y % tile_height;
+
+	/*
+	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
+	 * x/y offsets must match between CCS and the main surface.
+	 */
+	if (main_x != ccs_x || main_y != ccs_y) {
+		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
+			      main_x, main_y,
+			      ccs_x, ccs_y,
+			      intel_fb->normal[0].x,
+			      intel_fb->normal[0].y,
+			      x, y);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int
 intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		   struct drm_framebuffer *fb)
@@ -2706,36 +2743,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			return ret;
 		}
 
-		if (is_ccs_modifier(fb->modifier) && i == 1) {
-			int hsub = fb->format->hsub;
-			int vsub = fb->format->vsub;
-			int tile_width, tile_height;
-			int main_x, main_y;
-			int ccs_x, ccs_y;
-
-			intel_tile_dims(fb, i, &tile_width, &tile_height);
-			tile_width *= hsub;
-			tile_height *= vsub;
-
-			ccs_x = (x * hsub) % tile_width;
-			ccs_y = (y * vsub) % tile_height;
-			main_x = intel_fb->normal[0].x % tile_width;
-			main_y = intel_fb->normal[0].y % tile_height;
-
-			/*
-			 * CCS doesn't have its own x/y offset register, so the intra CCS tile
-			 * x/y offsets must match between CCS and the main surface.
-			 */
-			if (main_x != ccs_x || main_y != ccs_y) {
-				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
-					      main_x, main_y,
-					      ccs_x, ccs_y,
-					      intel_fb->normal[0].x,
-					      intel_fb->normal[0].y,
-					      x, y);
-				return -EINVAL;
-			}
-		}
+		ret = intel_fb_check_ccs_xy(fb, x, y);
+		if (ret)
+			return ret;
 
 		/*
 		 * The fence (if used) is aligned to the start of the object
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 04/15] drm/i915: Extract framebufer CCS offset checks into a function

[Kahola, Mika]

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> intel_fill_fb_info() has grown quite large and wrapping the offset
> checks
> into a separate function makes the loop a bit easier to follow.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 70 +++++++++++-------
> --
>  1 file changed, 40 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9c27cf651e08..4b8b44c39724 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2676,6 +2676,43 @@ static bool intel_plane_needs_remap(const
> struct intel_plane_state *plane_state)
>  	return stride > max_stride;
>  }
>  
> +static int
> +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> +{
> +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	int hsub = fb->format->hsub;
> +	int vsub = fb->format->vsub;
> +	int tile_width, tile_height;
> +	int ccs_x, ccs_y;
> +	int main_x, main_y;
> +
> +	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> +
> +	tile_width *= hsub;
> +	tile_height *= vsub;
> +
> +	ccs_x = (x * hsub) % tile_width;
> +	ccs_y = (y * vsub) % tile_height;
> +	main_x = intel_fb->normal[0].x % tile_width;
> +	main_y = intel_fb->normal[0].y % tile_height;
> +
> +	/*
> +	 * CCS doesn't have its own x/y offset register, so the intra
> CCS tile
> +	 * x/y offsets must match between CCS and the main surface.
> +	 */
> +	if (main_x != ccs_x || main_y != ccs_y) {
> +		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full
> (main %d,%d ccs %d,%d)\n",
> +			      main_x, main_y,
> +			      ccs_x, ccs_y,
> +			      intel_fb->normal[0].x,
> +			      intel_fb->normal[0].y,
> +			      x, y);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int
>  intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		   struct drm_framebuffer *fb)
> @@ -2706,36 +2743,9 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
>  			return ret;
>  		}
>  
> -		if (is_ccs_modifier(fb->modifier) && i == 1) {
> -			int hsub = fb->format->hsub;
> -			int vsub = fb->format->vsub;
> -			int tile_width, tile_height;
> -			int main_x, main_y;
> -			int ccs_x, ccs_y;
> -
> -			intel_tile_dims(fb, i, &tile_width,
> &tile_height);
> -			tile_width *= hsub;
> -			tile_height *= vsub;
> -
> -			ccs_x = (x * hsub) % tile_width;
> -			ccs_y = (y * vsub) % tile_height;
> -			main_x = intel_fb->normal[0].x % tile_width;
> -			main_y = intel_fb->normal[0].y % tile_height;
> -
> -			/*
> -			 * CCS doesn't have its own x/y offset
> register, so the intra CCS tile
> -			 * x/y offsets must match between CCS and the
> main surface.
> -			 */
> -			if (main_x != ccs_x || main_y != ccs_y) {
> -				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d
> ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
> -					      main_x, main_y,
> -					      ccs_x, ccs_y,
> -					      intel_fb->normal[0].x,
> -					      intel_fb->normal[0].y,
> -					      x, y);
> -				return -EINVAL;
> -			}
> -		}
> +		ret = intel_fb_check_ccs_xy(fb, x, y);
We should check the ccs offsets only when we have ccs modifier in
question.  

+		if (ret)
> +			return ret;
>  
>  		/*
>  		 * The fence (if used) is aligned to the start of the
> object
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Re: [Intel-gfx] [PATCH 04/15] drm/i915: Extract framebufer CCS offset checks into a function

[Imre Deak]

On Thu, Dec 19, 2019 at 01:10:52PM +0200, Kahola, Mika wrote:
> On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote:
> > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > 
> > intel_fill_fb_info() has grown quite large and wrapping the offset
> > checks
> > into a separate function makes the loop a bit easier to follow.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 70 +++++++++++-------
> > --
> >  1 file changed, 40 insertions(+), 30 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 9c27cf651e08..4b8b44c39724 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2676,6 +2676,43 @@ static bool intel_plane_needs_remap(const
> > struct intel_plane_state *plane_state)
> >  	return stride > max_stride;
> >  }
> >  
> > +static int
> > +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> > +{
> > +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > +	int hsub = fb->format->hsub;
> > +	int vsub = fb->format->vsub;
> > +	int tile_width, tile_height;
> > +	int ccs_x, ccs_y;
> > +	int main_x, main_y;
> > +
> > +	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> > +
> > +	tile_width *= hsub;
> > +	tile_height *= vsub;
> > +
> > +	ccs_x = (x * hsub) % tile_width;
> > +	ccs_y = (y * vsub) % tile_height;
> > +	main_x = intel_fb->normal[0].x % tile_width;
> > +	main_y = intel_fb->normal[0].y % tile_height;
> > +
> > +	/*
> > +	 * CCS doesn't have its own x/y offset register, so the intra
> > CCS tile
> > +	 * x/y offsets must match between CCS and the main surface.
> > +	 */
> > +	if (main_x != ccs_x || main_y != ccs_y) {
> > +		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full
> > (main %d,%d ccs %d,%d)\n",
> > +			      main_x, main_y,
> > +			      ccs_x, ccs_y,
> > +			      intel_fb->normal[0].x,
> > +			      intel_fb->normal[0].y,
> > +			      x, y);
> > +		return -EINVAL;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  static int
> >  intel_fill_fb_info(struct drm_i915_private *dev_priv,
> >  		   struct drm_framebuffer *fb)
> > @@ -2706,36 +2743,9 @@ intel_fill_fb_info(struct drm_i915_private
> > *dev_priv,
> >  			return ret;
> >  		}
> >  
> > -		if (is_ccs_modifier(fb->modifier) && i == 1) {
> > -			int hsub = fb->format->hsub;
> > -			int vsub = fb->format->vsub;
> > -			int tile_width, tile_height;
> > -			int main_x, main_y;
> > -			int ccs_x, ccs_y;
> > -
> > -			intel_tile_dims(fb, i, &tile_width,
> > &tile_height);
> > -			tile_width *= hsub;
> > -			tile_height *= vsub;
> > -
> > -			ccs_x = (x * hsub) % tile_width;
> > -			ccs_y = (y * vsub) % tile_height;
> > -			main_x = intel_fb->normal[0].x % tile_width;
> > -			main_y = intel_fb->normal[0].y % tile_height;
> > -
> > -			/*
> > -			 * CCS doesn't have its own x/y offset
> > register, so the intra CCS tile
> > -			 * x/y offsets must match between CCS and the
> > main surface.
> > -			 */
> > -			if (main_x != ccs_x || main_y != ccs_y) {
> > -				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d
> > ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
> > -					      main_x, main_y,
> > -					      ccs_x, ccs_y,
> > -					      intel_fb->normal[0].x,
> > -					      intel_fb->normal[0].y,
> > -					      x, y);
> > -				return -EINVAL;
> > -			}
> > -		}
> > +		ret = intel_fb_check_ccs_xy(fb, x, y);
> We should check the ccs offsets only when we have ccs modifier in
> question.  

Yes, thanks for spotting it. It gets fixed up in patch 6, but I'll
resend this fixing it here already.

> 
> +		if (ret)
> > +			return ret;
> >  
> >  		/*
> >  		 * The fence (if used) is aligned to the start of the
> > object
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[Intel-gfx] [PATCH v2 04/15] drm/i915: Extract framebufer CCS offset checks into a function

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.

v2: Skip the check for non-CCS planes. (Mika)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 73 ++++++++++++--------
 1 file changed, 43 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9c27cf651e08..2665ea7300a0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2676,6 +2676,46 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static int
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
+{
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	int hsub = fb->format->hsub;
+	int vsub = fb->format->vsub;
+	int tile_width, tile_height;
+	int ccs_x, ccs_y;
+	int main_x, main_y;
+
+	if (!is_ccs_modifier(fb->modifier) || ccs_plane != 1)
+		return 0;
+
+	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+
+	tile_width *= hsub;
+	tile_height *= vsub;
+
+	ccs_x = (x * hsub) % tile_width;
+	ccs_y = (y * vsub) % tile_height;
+	main_x = intel_fb->normal[0].x % tile_width;
+	main_y = intel_fb->normal[0].y % tile_height;
+
+	/*
+	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
+	 * x/y offsets must match between CCS and the main surface.
+	 */
+	if (main_x != ccs_x || main_y != ccs_y) {
+		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
+			      main_x, main_y,
+			      ccs_x, ccs_y,
+			      intel_fb->normal[0].x,
+			      intel_fb->normal[0].y,
+			      x, y);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int
 intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		   struct drm_framebuffer *fb)
@@ -2706,36 +2746,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			return ret;
 		}
 
-		if (is_ccs_modifier(fb->modifier) && i == 1) {
-			int hsub = fb->format->hsub;
-			int vsub = fb->format->vsub;
-			int tile_width, tile_height;
-			int main_x, main_y;
-			int ccs_x, ccs_y;
-
-			intel_tile_dims(fb, i, &tile_width, &tile_height);
-			tile_width *= hsub;
-			tile_height *= vsub;
-
-			ccs_x = (x * hsub) % tile_width;
-			ccs_y = (y * vsub) % tile_height;
-			main_x = intel_fb->normal[0].x % tile_width;
-			main_y = intel_fb->normal[0].y % tile_height;
-
-			/*
-			 * CCS doesn't have its own x/y offset register, so the intra CCS tile
-			 * x/y offsets must match between CCS and the main surface.
-			 */
-			if (main_x != ccs_x || main_y != ccs_y) {
-				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
-					      main_x, main_y,
-					      ccs_x, ccs_y,
-					      intel_fb->normal[0].x,
-					      intel_fb->normal[0].y,
-					      x, y);
-				return -EINVAL;
-			}
-		}
+		ret = intel_fb_check_ccs_xy(fb, i, x, y);
+		if (ret)
+			return ret;
 
 		/*
 		 * The fence (if used) is aligned to the start of the object
-- 
2.22.0

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Re: [Intel-gfx] [PATCH v2 04/15] drm/i915: Extract framebufer CCS offset checks into a function

[Kahola, Mika]

On Fri, 2019-12-20 at 12:49 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> intel_fill_fb_info() has grown quite large and wrapping the offset
> checks
> into a separate function makes the loop a bit easier to follow.
> 
> v2: Skip the check for non-CCS planes. (Mika)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 73 ++++++++++++----
> ----
>  1 file changed, 43 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9c27cf651e08..2665ea7300a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2676,6 +2676,46 @@ static bool intel_plane_needs_remap(const
> struct intel_plane_state *plane_state)
>  	return stride > max_stride;
>  }
>  
> +static int
> +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int
> x, int y)
> +{
> +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	int hsub = fb->format->hsub;
> +	int vsub = fb->format->vsub;
> +	int tile_width, tile_height;
> +	int ccs_x, ccs_y;
> +	int main_x, main_y;
> +
> +	if (!is_ccs_modifier(fb->modifier) || ccs_plane != 1)
> +		return 0;
> +
> +	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> +
> +	tile_width *= hsub;
> +	tile_height *= vsub;
> +
> +	ccs_x = (x * hsub) % tile_width;
> +	ccs_y = (y * vsub) % tile_height;
> +	main_x = intel_fb->normal[0].x % tile_width;
> +	main_y = intel_fb->normal[0].y % tile_height;
> +
> +	/*
> +	 * CCS doesn't have its own x/y offset register, so the intra
> CCS tile
> +	 * x/y offsets must match between CCS and the main surface.
> +	 */
> +	if (main_x != ccs_x || main_y != ccs_y) {
> +		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full
> (main %d,%d ccs %d,%d)\n",
> +			      main_x, main_y,
> +			      ccs_x, ccs_y,
> +			      intel_fb->normal[0].x,
> +			      intel_fb->normal[0].y,
> +			      x, y);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int
>  intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		   struct drm_framebuffer *fb)
> @@ -2706,36 +2746,9 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
>  			return ret;
>  		}
>  
> -		if (is_ccs_modifier(fb->modifier) && i == 1) {
> -			int hsub = fb->format->hsub;
> -			int vsub = fb->format->vsub;
> -			int tile_width, tile_height;
> -			int main_x, main_y;
> -			int ccs_x, ccs_y;
> -
> -			intel_tile_dims(fb, i, &tile_width,
> &tile_height);
> -			tile_width *= hsub;
> -			tile_height *= vsub;
> -
> -			ccs_x = (x * hsub) % tile_width;
> -			ccs_y = (y * vsub) % tile_height;
> -			main_x = intel_fb->normal[0].x % tile_width;
> -			main_y = intel_fb->normal[0].y % tile_height;
> -
> -			/*
> -			 * CCS doesn't have its own x/y offset
> register, so the intra CCS tile
> -			 * x/y offsets must match between CCS and the
> main surface.
> -			 */
> -			if (main_x != ccs_x || main_y != ccs_y) {
> -				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d
> ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
> -					      main_x, main_y,
> -					      ccs_x, ccs_y,
> -					      intel_fb->normal[0].x,
> -					      intel_fb->normal[0].y,
> -					      x, y);
> -				return -EINVAL;
> -			}
> -		}
> +		ret = intel_fb_check_ccs_xy(fb, i, x, y);
> +		if (ret)
> +			return ret;
>  
>  		/*
>  		 * The fence (if used) is aligned to the start of the
> object
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[Intel-gfx] [PATCH 05/15] drm/i915: Add helpers to select correct ccs/aux planes

[Imre Deak]

Using helpers instead of open coding this to select a CCS plane for a
main plane makes the code cleaner and less error-prone when the location
of CCS plane can be different based on the format (packed vs. YUV
semiplanar). The same applies to selecting an AUX plane which can be a
UV plane (for an uncompressed YUV semiplanar format), or a CCS plane.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 63 ++++++++++++++++----
 1 file changed, 50 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4b8b44c39724..6bda397ae677 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1933,6 +1933,40 @@ static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
 	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
 }
 
+static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
+{
+	if (!is_ccs_modifier(fb->modifier))
+		return false;
+
+	return plane >= fb->format->num_planes / 2;
+}
+
+static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
+{
+	if (is_ccs_modifier(fb->modifier))
+		return is_ccs_plane(fb, plane);
+
+	return plane == 1;
+}
+
+static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
+{
+	WARN_ON(!is_ccs_modifier(fb->modifier) ||
+		(main_plane && main_plane >= fb->format->num_planes / 2));
+
+	return fb->format->num_planes / 2 + main_plane;
+}
+
+/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
+static int
+intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
+{
+	if (is_ccs_modifier(fb->modifier))
+		return main_to_ccs_plane(fb, main_plane);
+
+	return 1;
+}
+
 static unsigned int
 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 {
@@ -1948,7 +1982,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		else
 			return 512;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
-		if (color_plane == 1)
+		if (is_ccs_plane(fb, color_plane))
 			return 128;
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
@@ -1957,7 +1991,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		else
 			return 512;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
-		if (color_plane == 1)
+		if (is_ccs_plane(fb, color_plane))
 			return 128;
 		/* fall through */
 	case I915_FORMAT_MOD_Yf_TILED:
@@ -2074,7 +2108,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
 
 	/* AUX_DIST needs only 4K alignment */
-	if (color_plane == 1)
+	if (is_aux_plane(fb, color_plane))
 		return 4096;
 
 	switch (fb->modifier) {
@@ -3457,10 +3491,11 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int hsub = fb->format->hsub;
 	int vsub = fb->format->vsub;
-	int aux_x = plane_state->color_plane[1].x;
-	int aux_y = plane_state->color_plane[1].y;
-	u32 aux_offset = plane_state->color_plane[1].offset;
-	u32 alignment = intel_surf_alignment(fb, 1);
+	int ccs_plane = main_to_ccs_plane(fb, 0);
+	int aux_x = plane_state->color_plane[ccs_plane].x;
+	int aux_y = plane_state->color_plane[ccs_plane].y;
+	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
+	u32 alignment = intel_surf_alignment(fb, ccs_plane);
 
 	while (aux_offset >= main_offset && aux_y <= main_y) {
 		int x, y;
@@ -3473,7 +3508,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 
 		x = aux_x / hsub;
 		y = aux_y / vsub;
-		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, ccs_plane,
 							       aux_offset, aux_offset - alignment);
 		aux_x = x * hsub + aux_x % hsub;
 		aux_y = y * vsub + aux_y % vsub;
@@ -3482,9 +3517,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 	if (aux_x != main_x || aux_y != main_y)
 		return false;
 
-	plane_state->color_plane[1].offset = aux_offset;
-	plane_state->color_plane[1].x = aux_x;
-	plane_state->color_plane[1].y = aux_y;
+	plane_state->color_plane[ccs_plane].offset = aux_offset;
+	plane_state->color_plane[ccs_plane].x = aux_x;
+	plane_state->color_plane[ccs_plane].y = aux_y;
 
 	return true;
 }
@@ -3500,7 +3535,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	int h = drm_rect_height(&plane_state->uapi.src) >> 16;
 	int max_width;
 	int max_height;
-	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
+	int aux_plane = intel_main_to_aux_plane(fb, 0);
+	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		max_width = icl_max_plane_width(fb, 0, rotation);
@@ -3566,7 +3602,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 								   offset, offset - alignment);
 		}
 
-		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
+		if (x != plane_state->color_plane[aux_plane].x ||
+		    y != plane_state->color_plane[aux_plane].y) {
 			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
 			return -EINVAL;
 		}
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 05/15] drm/i915: Add helpers to select correct ccs/aux planes

[Kahola, Mika]

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote:
> Using helpers instead of open coding this to select a CCS plane for a
> main plane makes the code cleaner and less error-prone when the
> location
> of CCS plane can be different based on the format (packed vs. YUV
> semiplanar). The same applies to selecting an AUX plane which can be
> a
> UV plane (for an uncompressed YUV semiplanar format), or a CCS plane.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 63 ++++++++++++++++
> ----
>  1 file changed, 50 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4b8b44c39724..6bda397ae677 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1933,6 +1933,40 @@ static unsigned int intel_tile_size(const
> struct drm_i915_private *dev_priv)
>  	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
>  }
>  
> +static bool is_ccs_plane(const struct drm_framebuffer *fb, int
> plane)
> +{
> +	if (!is_ccs_modifier(fb->modifier))
> +		return false;
> +
> +	return plane >= fb->format->num_planes / 2;
> +}
> +
> +static bool is_aux_plane(const struct drm_framebuffer *fb, int
> plane)
> +{
> +	if (is_ccs_modifier(fb->modifier))
> +		return is_ccs_plane(fb, plane);
> +
> +	return plane == 1;
> +}
> +
> +static int main_to_ccs_plane(const struct drm_framebuffer *fb, int
> main_plane)
> +{
> +	WARN_ON(!is_ccs_modifier(fb->modifier) ||
> +		(main_plane && main_plane >= fb->format->num_planes /
> 2));
> +
> +	return fb->format->num_planes / 2 + main_plane;
> +}
> +
> +/* Return either the main plane's CCS or - if not a CCS FB - UV
> plane */
> +static int
> +intel_main_to_aux_plane(const struct drm_framebuffer *fb, int
> main_plane)
> +{
> +	if (is_ccs_modifier(fb->modifier))
> +		return main_to_ccs_plane(fb, main_plane);
> +
> +	return 1;
> +}
> +
>  static unsigned int
>  intel_tile_width_bytes(const struct drm_framebuffer *fb, int
> color_plane)
>  {
> @@ -1948,7 +1982,7 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
>  		else
>  			return 512;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -1957,7 +1991,7 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
>  		else
>  			return 512;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Yf_TILED:
> @@ -2074,7 +2108,7 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
>  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
>  
>  	/* AUX_DIST needs only 4K alignment */
> -	if (color_plane == 1)
> +	if (is_aux_plane(fb, color_plane))
>  		return 4096;
>  
>  	switch (fb->modifier) {
> @@ -3457,10 +3491,11 @@ static bool
> skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	int hsub = fb->format->hsub;
>  	int vsub = fb->format->vsub;
> -	int aux_x = plane_state->color_plane[1].x;
> -	int aux_y = plane_state->color_plane[1].y;
> -	u32 aux_offset = plane_state->color_plane[1].offset;
> -	u32 alignment = intel_surf_alignment(fb, 1);
> +	int ccs_plane = main_to_ccs_plane(fb, 0);
> +	int aux_x = plane_state->color_plane[ccs_plane].x;
> +	int aux_y = plane_state->color_plane[ccs_plane].y;
> +	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
> +	u32 alignment = intel_surf_alignment(fb, ccs_plane);
>  
>  	while (aux_offset >= main_offset && aux_y <= main_y) {
>  		int x, y;
> @@ -3473,7 +3508,7 @@ static bool
> skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  
>  		x = aux_x / hsub;
>  		y = aux_y / vsub;
> -		aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
> plane_state, 1,
> +		aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
> plane_state, ccs_plane,
>  							       aux_offs
> et, aux_offset - alignment);
>  		aux_x = x * hsub + aux_x % hsub;
>  		aux_y = y * vsub + aux_y % vsub;
> @@ -3482,9 +3517,9 @@ static bool
> skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  	if (aux_x != main_x || aux_y != main_y)
>  		return false;
>  
> -	plane_state->color_plane[1].offset = aux_offset;
> -	plane_state->color_plane[1].x = aux_x;
> -	plane_state->color_plane[1].y = aux_y;
> +	plane_state->color_plane[ccs_plane].offset = aux_offset;
> +	plane_state->color_plane[ccs_plane].x = aux_x;
> +	plane_state->color_plane[ccs_plane].y = aux_y;
>  
>  	return true;
>  }
> @@ -3500,7 +3535,8 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
>  	int h = drm_rect_height(&plane_state->uapi.src) >> 16;
>  	int max_width;
>  	int max_height;
> -	u32 alignment, offset, aux_offset = plane_state-
> >color_plane[1].offset;
> +	int aux_plane = intel_main_to_aux_plane(fb, 0);
> +	u32 alignment, offset, aux_offset = plane_state-
> >color_plane[aux_plane].offset;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		max_width = icl_max_plane_width(fb, 0, rotation);
> @@ -3566,7 +3602,8 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
>  								   offs
> et, offset - alignment);
>  		}
>  
> -		if (x != plane_state->color_plane[1].x || y !=
> plane_state->color_plane[1].y) {
> +		if (x != plane_state->color_plane[aux_plane].x ||
> +		    y != plane_state->color_plane[aux_plane].y) {
>  			DRM_DEBUG_KMS("Unable to find suitable display
> surface offset due to CCS\n");
>  			return -EINVAL;
>  		}
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Re: [Intel-gfx] [PATCH 05/15] drm/i915: Add helpers to select correct ccs/aux planes

[Matt Roper]

On Wed, Dec 18, 2019 at 06:10:55PM +0200, Imre Deak wrote:
> Using helpers instead of open coding this to select a CCS plane for a
> main plane makes the code cleaner and less error-prone when the location
> of CCS plane can be different based on the format (packed vs. YUV
> semiplanar). The same applies to selecting an AUX plane which can be a
> UV plane (for an uncompressed YUV semiplanar format), or a CCS plane.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Looking at this makes me wonder if some of the aux stuff that we're
doing for YUV in skl_check_main_surface is actually necessary for gen11+
now that we have separate planes rather than an AUX surface in the same
plane.

But none of the logic should be impacted by your changes here so,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 63 ++++++++++++++++----
>  1 file changed, 50 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4b8b44c39724..6bda397ae677 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1933,6 +1933,40 @@ static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
>  	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
>  }
>  
> +static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> +{
> +	if (!is_ccs_modifier(fb->modifier))
> +		return false;
> +
> +	return plane >= fb->format->num_planes / 2;
> +}
> +
> +static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
> +{
> +	if (is_ccs_modifier(fb->modifier))
> +		return is_ccs_plane(fb, plane);
> +
> +	return plane == 1;
> +}
> +
> +static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
> +{
> +	WARN_ON(!is_ccs_modifier(fb->modifier) ||
> +		(main_plane && main_plane >= fb->format->num_planes / 2));
> +
> +	return fb->format->num_planes / 2 + main_plane;
> +}
> +
> +/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
> +static int
> +intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
> +{
> +	if (is_ccs_modifier(fb->modifier))
> +		return main_to_ccs_plane(fb, main_plane);
> +
> +	return 1;
> +}
> +
>  static unsigned int
>  intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  {
> @@ -1948,7 +1982,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  		else
>  			return 512;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -1957,7 +1991,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  		else
>  			return 512;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Yf_TILED:
> @@ -2074,7 +2108,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
>  
>  	/* AUX_DIST needs only 4K alignment */
> -	if (color_plane == 1)
> +	if (is_aux_plane(fb, color_plane))
>  		return 4096;
>  
>  	switch (fb->modifier) {
> @@ -3457,10 +3491,11 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	int hsub = fb->format->hsub;
>  	int vsub = fb->format->vsub;
> -	int aux_x = plane_state->color_plane[1].x;
> -	int aux_y = plane_state->color_plane[1].y;
> -	u32 aux_offset = plane_state->color_plane[1].offset;
> -	u32 alignment = intel_surf_alignment(fb, 1);
> +	int ccs_plane = main_to_ccs_plane(fb, 0);
> +	int aux_x = plane_state->color_plane[ccs_plane].x;
> +	int aux_y = plane_state->color_plane[ccs_plane].y;
> +	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
> +	u32 alignment = intel_surf_alignment(fb, ccs_plane);
>  
>  	while (aux_offset >= main_offset && aux_y <= main_y) {
>  		int x, y;
> @@ -3473,7 +3508,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  
>  		x = aux_x / hsub;
>  		y = aux_y / vsub;
> -		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> +		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, ccs_plane,
>  							       aux_offset, aux_offset - alignment);
>  		aux_x = x * hsub + aux_x % hsub;
>  		aux_y = y * vsub + aux_y % vsub;
> @@ -3482,9 +3517,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  	if (aux_x != main_x || aux_y != main_y)
>  		return false;
>  
> -	plane_state->color_plane[1].offset = aux_offset;
> -	plane_state->color_plane[1].x = aux_x;
> -	plane_state->color_plane[1].y = aux_y;
> +	plane_state->color_plane[ccs_plane].offset = aux_offset;
> +	plane_state->color_plane[ccs_plane].x = aux_x;
> +	plane_state->color_plane[ccs_plane].y = aux_y;
>  
>  	return true;
>  }
> @@ -3500,7 +3535,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  	int h = drm_rect_height(&plane_state->uapi.src) >> 16;
>  	int max_width;
>  	int max_height;
> -	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> +	int aux_plane = intel_main_to_aux_plane(fb, 0);
> +	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		max_width = icl_max_plane_width(fb, 0, rotation);
> @@ -3566,7 +3602,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  								   offset, offset - alignment);
>  		}
>  
> -		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
> +		if (x != plane_state->color_plane[aux_plane].x ||
> +		    y != plane_state->color_plane[aux_plane].y) {
>  			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
>  			return -EINVAL;
>  		}
> -- 
> 2.22.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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Re: [Intel-gfx] [PATCH 05/15] drm/i915: Add helpers to select correct ccs/aux planes

[Imre Deak]

On Thu, Dec 19, 2019 at 01:04:33PM -0800, Matt Roper wrote:
> On Wed, Dec 18, 2019 at 06:10:55PM +0200, Imre Deak wrote:
> > Using helpers instead of open coding this to select a CCS plane for a
> > main plane makes the code cleaner and less error-prone when the location
> > of CCS plane can be different based on the format (packed vs. YUV
> > semiplanar). The same applies to selecting an AUX plane which can be a
> > UV plane (for an uncompressed YUV semiplanar format), or a CCS plane.
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> 
> Looking at this makes me wonder if some of the aux stuff that we're
> doing for YUV in skl_check_main_surface is actually necessary for gen11+
> now that we have separate planes rather than an AUX surface in the same
> plane.

I also wondered if programming the UV surface's offset in the Y plane's
AUX_DIST register is necessary or not on GEN11+, however that's what we
do atm.

> 
> But none of the logic should be impacted by your changes here so,
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 63 ++++++++++++++++----
> >  1 file changed, 50 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4b8b44c39724..6bda397ae677 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1933,6 +1933,40 @@ static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
> >  	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> >  }
> >  
> > +static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > +{
> > +	if (!is_ccs_modifier(fb->modifier))
> > +		return false;
> > +
> > +	return plane >= fb->format->num_planes / 2;
> > +}
> > +
> > +static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
> > +{
> > +	if (is_ccs_modifier(fb->modifier))
> > +		return is_ccs_plane(fb, plane);
> > +
> > +	return plane == 1;
> > +}
> > +
> > +static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
> > +{
> > +	WARN_ON(!is_ccs_modifier(fb->modifier) ||
> > +		(main_plane && main_plane >= fb->format->num_planes / 2));
> > +
> > +	return fb->format->num_planes / 2 + main_plane;
> > +}
> > +
> > +/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
> > +static int
> > +intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
> > +{
> > +	if (is_ccs_modifier(fb->modifier))
> > +		return main_to_ccs_plane(fb, main_plane);
> > +
> > +	return 1;
> > +}
> > +
> >  static unsigned int
> >  intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  {
> > @@ -1948,7 +1982,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  		else
> >  			return 512;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 128;
> >  		/* fall through */
> >  	case I915_FORMAT_MOD_Y_TILED:
> > @@ -1957,7 +1991,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  		else
> >  			return 512;
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 128;
> >  		/* fall through */
> >  	case I915_FORMAT_MOD_Yf_TILED:
> > @@ -2074,7 +2108,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> >  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
> >  
> >  	/* AUX_DIST needs only 4K alignment */
> > -	if (color_plane == 1)
> > +	if (is_aux_plane(fb, color_plane))
> >  		return 4096;
> >  
> >  	switch (fb->modifier) {
> > @@ -3457,10 +3491,11 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> >  	int hsub = fb->format->hsub;
> >  	int vsub = fb->format->vsub;
> > -	int aux_x = plane_state->color_plane[1].x;
> > -	int aux_y = plane_state->color_plane[1].y;
> > -	u32 aux_offset = plane_state->color_plane[1].offset;
> > -	u32 alignment = intel_surf_alignment(fb, 1);
> > +	int ccs_plane = main_to_ccs_plane(fb, 0);
> > +	int aux_x = plane_state->color_plane[ccs_plane].x;
> > +	int aux_y = plane_state->color_plane[ccs_plane].y;
> > +	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
> > +	u32 alignment = intel_surf_alignment(fb, ccs_plane);
> >  
> >  	while (aux_offset >= main_offset && aux_y <= main_y) {
> >  		int x, y;
> > @@ -3473,7 +3508,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> >  
> >  		x = aux_x / hsub;
> >  		y = aux_y / vsub;
> > -		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > +		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, ccs_plane,
> >  							       aux_offset, aux_offset - alignment);
> >  		aux_x = x * hsub + aux_x % hsub;
> >  		aux_y = y * vsub + aux_y % vsub;
> > @@ -3482,9 +3517,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> >  	if (aux_x != main_x || aux_y != main_y)
> >  		return false;
> >  
> > -	plane_state->color_plane[1].offset = aux_offset;
> > -	plane_state->color_plane[1].x = aux_x;
> > -	plane_state->color_plane[1].y = aux_y;
> > +	plane_state->color_plane[ccs_plane].offset = aux_offset;
> > +	plane_state->color_plane[ccs_plane].x = aux_x;
> > +	plane_state->color_plane[ccs_plane].y = aux_y;
> >  
> >  	return true;
> >  }
> > @@ -3500,7 +3535,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  	int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> >  	int max_width;
> >  	int max_height;
> > -	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> > +	int aux_plane = intel_main_to_aux_plane(fb, 0);
> > +	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
> >  
> >  	if (INTEL_GEN(dev_priv) >= 11)
> >  		max_width = icl_max_plane_width(fb, 0, rotation);
> > @@ -3566,7 +3602,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  								   offset, offset - alignment);
> >  		}
> >  
> > -		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
> > +		if (x != plane_state->color_plane[aux_plane].x ||
> > +		    y != plane_state->color_plane[aux_plane].y) {
> >  			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
> >  			return -EINVAL;
> >  		}
> > -- 
> > 2.22.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
_______________________________________________
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Re: [Intel-gfx] [PATCH 05/15] drm/i915: Add helpers to select correct ccs/aux planes

[Ville Syrjälä]

On Fri, Dec 20, 2019 at 02:26:07AM +0200, Imre Deak wrote:
> On Thu, Dec 19, 2019 at 01:04:33PM -0800, Matt Roper wrote:
> > On Wed, Dec 18, 2019 at 06:10:55PM +0200, Imre Deak wrote:
> > > Using helpers instead of open coding this to select a CCS plane for a
> > > main plane makes the code cleaner and less error-prone when the location
> > > of CCS plane can be different based on the format (packed vs. YUV
> > > semiplanar). The same applies to selecting an AUX plane which can be a
> > > UV plane (for an uncompressed YUV semiplanar format), or a CCS plane.
> > > 
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > 
> > Looking at this makes me wonder if some of the aux stuff that we're
> > doing for YUV in skl_check_main_surface is actually necessary for gen11+
> > now that we have separate planes rather than an AUX surface in the same
> > plane.
> 
> I also wondered if programming the UV surface's offset in the Y plane's
> AUX_DIST register is necessary or not on GEN11+, however that's what we
> do atm.

Shouldn't be needed. But I presume you're changing that anyway for media
compression since you need aux for both Y and UV?

> 
> > 
> > But none of the logic should be impacted by your changes here so,
> > 
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 63 ++++++++++++++++----
> > >  1 file changed, 50 insertions(+), 13 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 4b8b44c39724..6bda397ae677 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1933,6 +1933,40 @@ static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
> > >  	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> > >  }
> > >  
> > > +static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > > +{
> > > +	if (!is_ccs_modifier(fb->modifier))
> > > +		return false;
> > > +
> > > +	return plane >= fb->format->num_planes / 2;
> > > +}
> > > +
> > > +static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
> > > +{
> > > +	if (is_ccs_modifier(fb->modifier))
> > > +		return is_ccs_plane(fb, plane);
> > > +
> > > +	return plane == 1;
> > > +}
> > > +
> > > +static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
> > > +{
> > > +	WARN_ON(!is_ccs_modifier(fb->modifier) ||
> > > +		(main_plane && main_plane >= fb->format->num_planes / 2));
> > > +
> > > +	return fb->format->num_planes / 2 + main_plane;
> > > +}
> > > +
> > > +/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
> > > +static int
> > > +intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
> > > +{
> > > +	if (is_ccs_modifier(fb->modifier))
> > > +		return main_to_ccs_plane(fb, main_plane);
> > > +
> > > +	return 1;
> > > +}
> > > +
> > >  static unsigned int
> > >  intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > >  {
> > > @@ -1948,7 +1982,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > >  		else
> > >  			return 512;
> > >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > > -		if (color_plane == 1)
> > > +		if (is_ccs_plane(fb, color_plane))
> > >  			return 128;
> > >  		/* fall through */
> > >  	case I915_FORMAT_MOD_Y_TILED:
> > > @@ -1957,7 +1991,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > >  		else
> > >  			return 512;
> > >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > -		if (color_plane == 1)
> > > +		if (is_ccs_plane(fb, color_plane))
> > >  			return 128;
> > >  		/* fall through */
> > >  	case I915_FORMAT_MOD_Yf_TILED:
> > > @@ -2074,7 +2108,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > >  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
> > >  
> > >  	/* AUX_DIST needs only 4K alignment */
> > > -	if (color_plane == 1)
> > > +	if (is_aux_plane(fb, color_plane))
> > >  		return 4096;
> > >  
> > >  	switch (fb->modifier) {
> > > @@ -3457,10 +3491,11 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> > >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > >  	int hsub = fb->format->hsub;
> > >  	int vsub = fb->format->vsub;
> > > -	int aux_x = plane_state->color_plane[1].x;
> > > -	int aux_y = plane_state->color_plane[1].y;
> > > -	u32 aux_offset = plane_state->color_plane[1].offset;
> > > -	u32 alignment = intel_surf_alignment(fb, 1);
> > > +	int ccs_plane = main_to_ccs_plane(fb, 0);
> > > +	int aux_x = plane_state->color_plane[ccs_plane].x;
> > > +	int aux_y = plane_state->color_plane[ccs_plane].y;
> > > +	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
> > > +	u32 alignment = intel_surf_alignment(fb, ccs_plane);
> > >  
> > >  	while (aux_offset >= main_offset && aux_y <= main_y) {
> > >  		int x, y;
> > > @@ -3473,7 +3508,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> > >  
> > >  		x = aux_x / hsub;
> > >  		y = aux_y / vsub;
> > > -		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > > +		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, ccs_plane,
> > >  							       aux_offset, aux_offset - alignment);
> > >  		aux_x = x * hsub + aux_x % hsub;
> > >  		aux_y = y * vsub + aux_y % vsub;
> > > @@ -3482,9 +3517,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> > >  	if (aux_x != main_x || aux_y != main_y)
> > >  		return false;
> > >  
> > > -	plane_state->color_plane[1].offset = aux_offset;
> > > -	plane_state->color_plane[1].x = aux_x;
> > > -	plane_state->color_plane[1].y = aux_y;
> > > +	plane_state->color_plane[ccs_plane].offset = aux_offset;
> > > +	plane_state->color_plane[ccs_plane].x = aux_x;
> > > +	plane_state->color_plane[ccs_plane].y = aux_y;
> > >  
> > >  	return true;
> > >  }
> > > @@ -3500,7 +3535,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > >  	int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > >  	int max_width;
> > >  	int max_height;
> > > -	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> > > +	int aux_plane = intel_main_to_aux_plane(fb, 0);
> > > +	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
> > >  
> > >  	if (INTEL_GEN(dev_priv) >= 11)
> > >  		max_width = icl_max_plane_width(fb, 0, rotation);
> > > @@ -3566,7 +3602,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > >  								   offset, offset - alignment);
> > >  		}
> > >  
> > > -		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
> > > +		if (x != plane_state->color_plane[aux_plane].x ||
> > > +		    y != plane_state->color_plane[aux_plane].y) {
> > >  			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
> > >  			return -EINVAL;
> > >  		}
> > > -- 
> > > 2.22.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
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Re: [Intel-gfx] [PATCH 05/15] drm/i915: Add helpers to select correct ccs/aux planes

[Imre Deak]

On Fri, Dec 20, 2019 at 04:03:20PM +0200, Ville Syrjälä wrote:
> On Fri, Dec 20, 2019 at 02:26:07AM +0200, Imre Deak wrote:
> > On Thu, Dec 19, 2019 at 01:04:33PM -0800, Matt Roper wrote:
> > > On Wed, Dec 18, 2019 at 06:10:55PM +0200, Imre Deak wrote:
> > > > Using helpers instead of open coding this to select a CCS plane for a
> > > > main plane makes the code cleaner and less error-prone when the location
> > > > of CCS plane can be different based on the format (packed vs. YUV
> > > > semiplanar). The same applies to selecting an AUX plane which can be a
> > > > UV plane (for an uncompressed YUV semiplanar format), or a CCS plane.
> > > > 
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > 
> > > Looking at this makes me wonder if some of the aux stuff that we're
> > > doing for YUV in skl_check_main_surface is actually necessary for gen11+
> > > now that we have separate planes rather than an AUX surface in the same
> > > plane.
> > 
> > I also wondered if programming the UV surface's offset in the Y plane's
> > AUX_DIST register is necessary or not on GEN11+, however that's what we
> > do atm.
> 
> Shouldn't be needed. But I presume you're changing that anyway for media
> compression since you need aux for both Y and UV?

Right, CCS planes (both for RGB and YUV) will need to be programmed as
an AUX plane of their main surface (and for that the
main_to_aux_plane() helper came handy since the code is shared since
GEN9).

What I was pondering after Matt's comment is that for GEN11 we could
stop programming the UV AUX plane in skl_program_plane() which means the
UV coords need not match the main plane coords, what we require now even
on GEN11 (otoh for CCS AUX we need coordinates to match there too).
But this is unrelated to the change in this patch, so we can ignore that
for now.

> > > 
> > > But none of the logic should be impacted by your changes here so,
> > > 
> > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > > 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display.c | 63 ++++++++++++++++----
> > > >  1 file changed, 50 insertions(+), 13 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 4b8b44c39724..6bda397ae677 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -1933,6 +1933,40 @@ static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
> > > >  	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> > > >  }
> > > >  
> > > > +static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > > > +{
> > > > +	if (!is_ccs_modifier(fb->modifier))
> > > > +		return false;
> > > > +
> > > > +	return plane >= fb->format->num_planes / 2;
> > > > +}
> > > > +
> > > > +static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
> > > > +{
> > > > +	if (is_ccs_modifier(fb->modifier))
> > > > +		return is_ccs_plane(fb, plane);
> > > > +
> > > > +	return plane == 1;
> > > > +}
> > > > +
> > > > +static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
> > > > +{
> > > > +	WARN_ON(!is_ccs_modifier(fb->modifier) ||
> > > > +		(main_plane && main_plane >= fb->format->num_planes / 2));
> > > > +
> > > > +	return fb->format->num_planes / 2 + main_plane;
> > > > +}
> > > > +
> > > > +/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
> > > > +static int
> > > > +intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
> > > > +{
> > > > +	if (is_ccs_modifier(fb->modifier))
> > > > +		return main_to_ccs_plane(fb, main_plane);
> > > > +
> > > > +	return 1;
> > > > +}
> > > > +
> > > >  static unsigned int
> > > >  intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > >  {
> > > > @@ -1948,7 +1982,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > >  		else
> > > >  			return 512;
> > > >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > -		if (color_plane == 1)
> > > > +		if (is_ccs_plane(fb, color_plane))
> > > >  			return 128;
> > > >  		/* fall through */
> > > >  	case I915_FORMAT_MOD_Y_TILED:
> > > > @@ -1957,7 +1991,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > >  		else
> > > >  			return 512;
> > > >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > > -		if (color_plane == 1)
> > > > +		if (is_ccs_plane(fb, color_plane))
> > > >  			return 128;
> > > >  		/* fall through */
> > > >  	case I915_FORMAT_MOD_Yf_TILED:
> > > > @@ -2074,7 +2108,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > >  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
> > > >  
> > > >  	/* AUX_DIST needs only 4K alignment */
> > > > -	if (color_plane == 1)
> > > > +	if (is_aux_plane(fb, color_plane))
> > > >  		return 4096;
> > > >  
> > > >  	switch (fb->modifier) {
> > > > @@ -3457,10 +3491,11 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> > > >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > >  	int hsub = fb->format->hsub;
> > > >  	int vsub = fb->format->vsub;
> > > > -	int aux_x = plane_state->color_plane[1].x;
> > > > -	int aux_y = plane_state->color_plane[1].y;
> > > > -	u32 aux_offset = plane_state->color_plane[1].offset;
> > > > -	u32 alignment = intel_surf_alignment(fb, 1);
> > > > +	int ccs_plane = main_to_ccs_plane(fb, 0);
> > > > +	int aux_x = plane_state->color_plane[ccs_plane].x;
> > > > +	int aux_y = plane_state->color_plane[ccs_plane].y;
> > > > +	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
> > > > +	u32 alignment = intel_surf_alignment(fb, ccs_plane);
> > > >  
> > > >  	while (aux_offset >= main_offset && aux_y <= main_y) {
> > > >  		int x, y;
> > > > @@ -3473,7 +3508,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> > > >  
> > > >  		x = aux_x / hsub;
> > > >  		y = aux_y / vsub;
> > > > -		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > > > +		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, ccs_plane,
> > > >  							       aux_offset, aux_offset - alignment);
> > > >  		aux_x = x * hsub + aux_x % hsub;
> > > >  		aux_y = y * vsub + aux_y % vsub;
> > > > @@ -3482,9 +3517,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> > > >  	if (aux_x != main_x || aux_y != main_y)
> > > >  		return false;
> > > >  
> > > > -	plane_state->color_plane[1].offset = aux_offset;
> > > > -	plane_state->color_plane[1].x = aux_x;
> > > > -	plane_state->color_plane[1].y = aux_y;
> > > > +	plane_state->color_plane[ccs_plane].offset = aux_offset;
> > > > +	plane_state->color_plane[ccs_plane].x = aux_x;
> > > > +	plane_state->color_plane[ccs_plane].y = aux_y;
> > > >  
> > > >  	return true;
> > > >  }
> > > > @@ -3500,7 +3535,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > > >  	int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > >  	int max_width;
> > > >  	int max_height;
> > > > -	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> > > > +	int aux_plane = intel_main_to_aux_plane(fb, 0);
> > > > +	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
> > > >  
> > > >  	if (INTEL_GEN(dev_priv) >= 11)
> > > >  		max_width = icl_max_plane_width(fb, 0, rotation);
> > > > @@ -3566,7 +3602,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > > >  								   offset, offset - alignment);
> > > >  		}
> > > >  
> > > > -		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
> > > > +		if (x != plane_state->color_plane[aux_plane].x ||
> > > > +		    y != plane_state->color_plane[aux_plane].y) {
> > > >  			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
> > > >  			return -EINVAL;
> > > >  		}
> > > > -- 
> > > > 2.22.0
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
> > > -- 
> > > Matt Roper
> > > Graphics Software Engineer
> > > VTT-OSGC Platform Enablement
> > > Intel Corporation
> > > (916) 356-2795
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH 06/15] drm/i915/tgl: Gen-12 render decompression

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to identify gen-12 compression. Another notable change is that
render decompression is supported on all planes except cursor and on all
pipes. Start by adding render decompression support for [A,X]BGR888 pixel
formats.

v2: Fix checkpatch warnings (Lucas)
v3:
Rebase, disable color clear, styling changes and modify
intel_tile_width_bytes and intel_tile_height to handle linear CCS
v4:
- Use format block descriptors and the i915 specific func to get the
  subsampling for each color plane.
- Use helpers to convert between CCS and main planes.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 185 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_sprite.c  |  23 ++-
 drivers/gpu/drm/i915/i915_reg.h              |   1 +
 3 files changed, 169 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6bda397ae677..641ea24539eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1941,6 +1941,16 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
 	return plane >= fb->format->num_planes / 2;
 }
 
+static bool is_gen12_ccs_modifier(u64 modifier)
+{
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+}
+
+static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
+{
+	return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
+}
+
 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
 {
 	if (is_ccs_modifier(fb->modifier))
@@ -1957,6 +1967,14 @@ static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
 	return fb->format->num_planes / 2 + main_plane;
 }
 
+static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
+{
+	WARN_ON(!is_ccs_modifier(fb->modifier) ||
+		ccs_plane < fb->format->num_planes / 2);
+
+	return ccs_plane - fb->format->num_planes / 2;
+}
+
 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
 static int
 intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
@@ -1985,6 +2003,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (is_ccs_plane(fb, color_plane))
 			return 128;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		if (is_ccs_plane(fb, color_plane))
+			return 64;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
 		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
 			return 128;
@@ -2018,6 +2040,9 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 static unsigned int
 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
 {
+	if (is_gen12_ccs_plane(fb, color_plane))
+		return 1;
+
 	return intel_tile_size(to_i915(fb->dev)) /
 		intel_tile_width_bytes(fb, color_plane);
 }
@@ -2118,6 +2143,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 		if (INTEL_GEN(dev_priv) >= 9)
 			return 256 * 1024;
 		return 0;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2310,9 +2337,10 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 	return new_offset;
 }
 
-static bool is_surface_linear(u64 modifier, int color_plane)
+static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR;
+	return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
+	       is_gen12_ccs_plane(fb, color_plane);
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2327,7 +2355,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
 
 	WARN_ON(new_offset > old_offset);
 
-	if (!is_surface_linear(fb->modifier, color_plane)) {
+	if (!is_surface_linear(fb, color_plane)) {
 		unsigned int tile_size, tile_width, tile_height;
 		unsigned int pitch_tiles;
 
@@ -2397,7 +2425,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
 	if (alignment)
 		alignment--;
 
-	if (!is_surface_linear(fb->modifier, color_plane)) {
+	if (!is_surface_linear(fb, color_plane)) {
 		unsigned int tile_size, tile_width, tile_height;
 		unsigned int tile_rows, tiles, pitch_tiles;
 
@@ -2499,6 +2527,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 		return I915_TILING_X;
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2519,7 +2548,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
  * us a ratio of one byte in the CCS for each 8x16 pixels in the
  * main surface.
  */
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2530,6 +2559,28 @@ static const struct drm_format_info ccs_formats[] = {
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
 };
 
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2550,8 +2601,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 	switch (cmd->modifier[0]) {
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
-		return lookup_format_info(ccs_formats,
-					  ARRAY_SIZE(ccs_formats),
+		return lookup_format_info(skl_ccs_formats,
+					  ARRAY_SIZE(skl_ccs_formats),
+					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return lookup_format_info(gen12_ccs_formats,
+					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
 	default:
 		return NULL;
@@ -2560,7 +2615,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 
 bool is_ccs_modifier(u64 modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
 
@@ -2608,8 +2664,9 @@ static u32
 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 {
 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
+	u32 tile_width;
 
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+	if (is_surface_linear(fb, color_plane)) {
 		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
 							   fb->format->format,
 							   fb->modifier);
@@ -2618,13 +2675,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * To make remapping with linear generally feasible
 		 * we need the stride to be page aligned.
 		 */
-		if (fb->pitches[color_plane] > max_stride)
+		if (fb->pitches[color_plane] > max_stride && !is_ccs_modifier(fb->modifier))
 			return intel_tile_size(dev_priv);
 		else
 			return 64;
-	} else {
-		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+	}
 
+	tile_width = intel_tile_width_bytes(fb, color_plane);
+	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2634,12 +2692,16 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
-		    color_plane == 0 && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+			tile_width *= 4;
+		/*
+		 * The main surface pitch must be padded to a multiple of four
+		 * tile widths.
+		 */
+		else if (INTEL_GEN(dev_priv) >= 12)
 			tile_width *= 4;
-
-		return tile_width;
 	}
+	return tile_width;
 }
 
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
@@ -2710,25 +2772,74 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub,
+			       const struct drm_framebuffer *fb,
+			       int color_plane)
+{
+	int main_plane;
+
+	if (color_plane == 0) {
+		*hsub = 1;
+		*vsub = 1;
+
+		return;
+	}
+
+	/*
+	 * TODO: Deduct the subsampling from the char block for all CCS
+	 * formats and planes.
+	 */
+	if (!is_gen12_ccs_plane(fb, color_plane)) {
+		*hsub = fb->format->hsub;
+		*vsub = fb->format->vsub;
+
+		return;
+	}
+
+	main_plane = ccs_to_main_plane(fb, color_plane);
+	*hsub = drm_format_info_block_width(fb->format, color_plane) /
+	        drm_format_info_block_width(fb->format, main_plane);
+
+	/*
+	 * The min stride check in the core framebuffer_check() function
+	 * assumes that format->hsub applies to every plane except for the
+	 * first plane. That's incorrect for the CCS AUX plane of the first
+	 * plane, but for the above check to pass we must define the block
+	 * width with that subsampling applied to it. Adjust the width here
+	 * accordingly, so we can calculate the actual subsampling factor.
+	 */
+	if (color_plane == 1)
+		*hsub *= fb->format->hsub;
+
+	*vsub = 32;
+}
 static int
 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
+	int main_plane;
+	int hsub, vsub;
 	int tile_width, tile_height;
 	int ccs_x, ccs_y;
 	int main_x, main_y;
+	int ccs_plane = 1;
 
-	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+	if (!is_ccs_plane(fb, ccs_plane))
+		return 0;
+
+	intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
 
 	tile_width *= hsub;
 	tile_height *= vsub;
 
 	ccs_x = (x * hsub) % tile_width;
 	ccs_y = (y * vsub) % tile_height;
-	main_x = intel_fb->normal[0].x % tile_width;
-	main_y = intel_fb->normal[0].y % tile_height;
+
+	main_plane = ccs_to_main_plane(fb, ccs_plane);
+	main_x = intel_fb->normal[main_plane].x % tile_width;
+	main_y = intel_fb->normal[main_plane].y % tile_height;
 
 	/*
 	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
@@ -2738,8 +2849,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
 		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
 			      main_x, main_y,
 			      ccs_x, ccs_y,
-			      intel_fb->normal[0].x,
-			      intel_fb->normal[0].y,
+			      intel_fb->normal[main_plane].x,
+			      intel_fb->normal[main_plane].y,
 			      x, y);
 		return -EINVAL;
 	}
@@ -2810,7 +2921,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 						      tile_size);
 		offset /= tile_size;
 
-		if (!is_surface_linear(fb->modifier, i)) {
+		if (!is_surface_linear(fb, i)) {
 			unsigned int tile_width, tile_height;
 			unsigned int pitch_tiles;
 			struct drm_rect r;
@@ -3489,14 +3600,15 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 					   int main_x, int main_y, u32 main_offset)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
 	int ccs_plane = main_to_ccs_plane(fb, 0);
 	int aux_x = plane_state->color_plane[ccs_plane].x;
 	int aux_y = plane_state->color_plane[ccs_plane].y;
 	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
 	u32 alignment = intel_surf_alignment(fb, ccs_plane);
+	int hsub;
+	int vsub;
 
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
 	while (aux_offset >= main_offset && aux_y <= main_y) {
 		int x, y;
 
@@ -3657,12 +3769,15 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int src_x = plane_state->uapi.src.x1 >> 16;
 	int src_y = plane_state->uapi.src.y1 >> 16;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
-	int x = src_x / hsub;
-	int y = src_y / vsub;
+	int hsub;
+	int vsub;
+	int x;
+	int y;
 	u32 offset;
 
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
+	x = src_x / hsub;
+	y = src_y / vsub;
 	intel_add_fb_offsets(&x, &y, plane_state, 1);
 	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
 
@@ -4158,7 +4273,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+	if (is_surface_linear(fb, color_plane))
 		return 64;
 	else if (drm_rotation_90_or_270(rotation))
 		return intel_tile_height(fb, color_plane);
@@ -4286,6 +4401,10 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return PLANE_CTL_TILED_Y |
+		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+		       PLANE_CTL_CLEAR_COLOR_DISABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -10021,7 +10140,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 	case PLANE_CTL_TILED_Y:
 		plane_config->tiling = I915_TILING_Y;
 		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+				I915_FORMAT_MOD_Y_TILED_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 8394502b092d..67a90059900f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -583,6 +583,7 @@ skl_program_plane(struct intel_plane *plane,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
+	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
 	u32 aux_stride = skl_plane_stride(plane_state, 1);
 	int crtc_x = plane_state->uapi.dst.x1;
 	int crtc_y = plane_state->uapi.dst.y1;
@@ -624,8 +625,10 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+	if (INTEL_GEN(dev_priv) < 12)
+		aux_dist |= aux_stride;
+	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
 
 	if (icl_is_hdr_plane(dev_priv, plane_id))
 		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);
@@ -2102,7 +2105,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2573,7 +2577,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2744,6 +2749,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		break;
 	default:
 		return false;
@@ -2754,6 +2760,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_ABGR8888:
+		if (is_ccs_modifier(modifier))
+			return true;
+		/* fall through */
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
@@ -2963,13 +2972,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		formats = skl_get_plane_formats(dev_priv, pipe,
 						plane_id, &num_formats);
 
+	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		/* TODO: Implement support for gen-12 CCS modifiers */
-		plane->has_ccs = false;
-		modifiers = gen12_plane_format_modifiers_noccs;
+		modifiers = gen12_plane_format_modifiers_ccs;
 		plane_funcs = &gen12_plane_funcs;
 	} else {
-		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 		if (plane->has_ccs)
 			modifiers = skl_plane_format_modifiers_ccs;
 		else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbb4689af432..bbfedeb00b7f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6800,6 +6800,7 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
+#define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
 #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
-- 
2.22.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 06/15] drm/i915/tgl: Gen-12 render decompression

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to identify gen-12 compression. Another notable change is that
render decompression is supported on all planes except cursor and on all
pipes. Start by adding render decompression support for [A,X]BGR888 pixel
formats.

v2: Fix checkpatch warnings (Lucas)
v3:
Rebase, disable color clear, styling changes and modify
intel_tile_width_bytes and intel_tile_height to handle linear CCS
v4:
- Use format block descriptors and the i915 specific func to get the
  subsampling for each color plane.
- Use helpers to convert between CCS and main planes.
v5:
- Fix subsampling returned by intel_fb_plane_get_subsampling() for
  the CCS plane of the first plane.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 185 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_sprite.c  |  23 ++-
 drivers/gpu/drm/i915/i915_reg.h              |   1 +
 3 files changed, 169 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6bda397ae677..c9a92d62a70f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1941,6 +1941,16 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
 	return plane >= fb->format->num_planes / 2;
 }
 
+static bool is_gen12_ccs_modifier(u64 modifier)
+{
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+}
+
+static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
+{
+	return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
+}
+
 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
 {
 	if (is_ccs_modifier(fb->modifier))
@@ -1957,6 +1967,14 @@ static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
 	return fb->format->num_planes / 2 + main_plane;
 }
 
+static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
+{
+	WARN_ON(!is_ccs_modifier(fb->modifier) ||
+		ccs_plane < fb->format->num_planes / 2);
+
+	return ccs_plane - fb->format->num_planes / 2;
+}
+
 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
 static int
 intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
@@ -1985,6 +2003,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (is_ccs_plane(fb, color_plane))
 			return 128;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		if (is_ccs_plane(fb, color_plane))
+			return 64;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
 		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
 			return 128;
@@ -2018,6 +2040,9 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 static unsigned int
 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
 {
+	if (is_gen12_ccs_plane(fb, color_plane))
+		return 1;
+
 	return intel_tile_size(to_i915(fb->dev)) /
 		intel_tile_width_bytes(fb, color_plane);
 }
@@ -2118,6 +2143,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 		if (INTEL_GEN(dev_priv) >= 9)
 			return 256 * 1024;
 		return 0;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2310,9 +2337,10 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 	return new_offset;
 }
 
-static bool is_surface_linear(u64 modifier, int color_plane)
+static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR;
+	return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
+	       is_gen12_ccs_plane(fb, color_plane);
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2327,7 +2355,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
 
 	WARN_ON(new_offset > old_offset);
 
-	if (!is_surface_linear(fb->modifier, color_plane)) {
+	if (!is_surface_linear(fb, color_plane)) {
 		unsigned int tile_size, tile_width, tile_height;
 		unsigned int pitch_tiles;
 
@@ -2397,7 +2425,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
 	if (alignment)
 		alignment--;
 
-	if (!is_surface_linear(fb->modifier, color_plane)) {
+	if (!is_surface_linear(fb, color_plane)) {
 		unsigned int tile_size, tile_width, tile_height;
 		unsigned int tile_rows, tiles, pitch_tiles;
 
@@ -2499,6 +2527,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 		return I915_TILING_X;
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2519,7 +2548,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
  * us a ratio of one byte in the CCS for each 8x16 pixels in the
  * main surface.
  */
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2530,6 +2559,28 @@ static const struct drm_format_info ccs_formats[] = {
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
 };
 
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2550,8 +2601,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 	switch (cmd->modifier[0]) {
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
-		return lookup_format_info(ccs_formats,
-					  ARRAY_SIZE(ccs_formats),
+		return lookup_format_info(skl_ccs_formats,
+					  ARRAY_SIZE(skl_ccs_formats),
+					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return lookup_format_info(gen12_ccs_formats,
+					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
 	default:
 		return NULL;
@@ -2560,7 +2615,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 
 bool is_ccs_modifier(u64 modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
 
@@ -2608,8 +2664,9 @@ static u32
 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 {
 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
+	u32 tile_width;
 
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+	if (is_surface_linear(fb, color_plane)) {
 		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
 							   fb->format->format,
 							   fb->modifier);
@@ -2618,13 +2675,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * To make remapping with linear generally feasible
 		 * we need the stride to be page aligned.
 		 */
-		if (fb->pitches[color_plane] > max_stride)
+		if (fb->pitches[color_plane] > max_stride && !is_ccs_modifier(fb->modifier))
 			return intel_tile_size(dev_priv);
 		else
 			return 64;
-	} else {
-		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+	}
 
+	tile_width = intel_tile_width_bytes(fb, color_plane);
+	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2634,12 +2692,16 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
-		    color_plane == 0 && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+			tile_width *= 4;
+		/*
+		 * The main surface pitch must be padded to a multiple of four
+		 * tile widths.
+		 */
+		else if (INTEL_GEN(dev_priv) >= 12)
 			tile_width *= 4;
-
-		return tile_width;
 	}
+	return tile_width;
 }
 
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
@@ -2710,25 +2772,74 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub,
+			       const struct drm_framebuffer *fb,
+			       int color_plane)
+{
+	int main_plane;
+
+	if (color_plane == 0) {
+		*hsub = 1;
+		*vsub = 1;
+
+		return;
+	}
+
+	/*
+	 * TODO: Deduct the subsampling from the char block for all CCS
+	 * formats and planes.
+	 */
+	if (!is_gen12_ccs_plane(fb, color_plane)) {
+		*hsub = fb->format->hsub;
+		*vsub = fb->format->vsub;
+
+		return;
+	}
+
+	main_plane = ccs_to_main_plane(fb, color_plane);
+	*hsub = drm_format_info_block_width(fb->format, color_plane) /
+	        drm_format_info_block_width(fb->format, main_plane);
+
+	/*
+	 * The min stride check in the core framebuffer_check() function
+	 * assumes that format->hsub applies to every plane except for the
+	 * first plane. That's incorrect for the CCS AUX plane of the first
+	 * plane, but for the above check to pass we must define the block
+	 * width with that subsampling applied to it. Adjust the width here
+	 * accordingly, so we can calculate the actual subsampling factor.
+	 */
+	if (main_plane == 0)
+		*hsub *= fb->format->hsub;
+
+	*vsub = 32;
+}
 static int
 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
+	int main_plane;
+	int hsub, vsub;
 	int tile_width, tile_height;
 	int ccs_x, ccs_y;
 	int main_x, main_y;
+	int ccs_plane = 1;
 
-	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+	if (!is_ccs_plane(fb, ccs_plane))
+		return 0;
+
+	intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
 
 	tile_width *= hsub;
 	tile_height *= vsub;
 
 	ccs_x = (x * hsub) % tile_width;
 	ccs_y = (y * vsub) % tile_height;
-	main_x = intel_fb->normal[0].x % tile_width;
-	main_y = intel_fb->normal[0].y % tile_height;
+
+	main_plane = ccs_to_main_plane(fb, ccs_plane);
+	main_x = intel_fb->normal[main_plane].x % tile_width;
+	main_y = intel_fb->normal[main_plane].y % tile_height;
 
 	/*
 	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
@@ -2738,8 +2849,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
 		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
 			      main_x, main_y,
 			      ccs_x, ccs_y,
-			      intel_fb->normal[0].x,
-			      intel_fb->normal[0].y,
+			      intel_fb->normal[main_plane].x,
+			      intel_fb->normal[main_plane].y,
 			      x, y);
 		return -EINVAL;
 	}
@@ -2810,7 +2921,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 						      tile_size);
 		offset /= tile_size;
 
-		if (!is_surface_linear(fb->modifier, i)) {
+		if (!is_surface_linear(fb, i)) {
 			unsigned int tile_width, tile_height;
 			unsigned int pitch_tiles;
 			struct drm_rect r;
@@ -3489,14 +3600,15 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 					   int main_x, int main_y, u32 main_offset)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
 	int ccs_plane = main_to_ccs_plane(fb, 0);
 	int aux_x = plane_state->color_plane[ccs_plane].x;
 	int aux_y = plane_state->color_plane[ccs_plane].y;
 	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
 	u32 alignment = intel_surf_alignment(fb, ccs_plane);
+	int hsub;
+	int vsub;
 
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
 	while (aux_offset >= main_offset && aux_y <= main_y) {
 		int x, y;
 
@@ -3657,12 +3769,15 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int src_x = plane_state->uapi.src.x1 >> 16;
 	int src_y = plane_state->uapi.src.y1 >> 16;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
-	int x = src_x / hsub;
-	int y = src_y / vsub;
+	int hsub;
+	int vsub;
+	int x;
+	int y;
 	u32 offset;
 
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
+	x = src_x / hsub;
+	y = src_y / vsub;
 	intel_add_fb_offsets(&x, &y, plane_state, 1);
 	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
 
@@ -4158,7 +4273,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+	if (is_surface_linear(fb, color_plane))
 		return 64;
 	else if (drm_rotation_90_or_270(rotation))
 		return intel_tile_height(fb, color_plane);
@@ -4286,6 +4401,10 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return PLANE_CTL_TILED_Y |
+		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+		       PLANE_CTL_CLEAR_COLOR_DISABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -10021,7 +10140,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 	case PLANE_CTL_TILED_Y:
 		plane_config->tiling = I915_TILING_Y;
 		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+				I915_FORMAT_MOD_Y_TILED_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 8394502b092d..67a90059900f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -583,6 +583,7 @@ skl_program_plane(struct intel_plane *plane,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
+	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
 	u32 aux_stride = skl_plane_stride(plane_state, 1);
 	int crtc_x = plane_state->uapi.dst.x1;
 	int crtc_y = plane_state->uapi.dst.y1;
@@ -624,8 +625,10 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+	if (INTEL_GEN(dev_priv) < 12)
+		aux_dist |= aux_stride;
+	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
 
 	if (icl_is_hdr_plane(dev_priv, plane_id))
 		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);
@@ -2102,7 +2105,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2573,7 +2577,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2744,6 +2749,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		break;
 	default:
 		return false;
@@ -2754,6 +2760,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_ABGR8888:
+		if (is_ccs_modifier(modifier))
+			return true;
+		/* fall through */
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
@@ -2963,13 +2972,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		formats = skl_get_plane_formats(dev_priv, pipe,
 						plane_id, &num_formats);
 
+	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		/* TODO: Implement support for gen-12 CCS modifiers */
-		plane->has_ccs = false;
-		modifiers = gen12_plane_format_modifiers_noccs;
+		modifiers = gen12_plane_format_modifiers_ccs;
 		plane_funcs = &gen12_plane_funcs;
 	} else {
-		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 		if (plane->has_ccs)
 			modifiers = skl_plane_format_modifiers_ccs;
 		else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbb4689af432..bbfedeb00b7f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6800,6 +6800,7 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
+#define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
 #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
-- 
2.22.0

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Re: [Intel-gfx] [PATCH v2 06/15] drm/i915/tgl: Gen-12 render decompression

[Sripada, Radhakrishna]

On Wed, 2019-12-18 at 19:07 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Gen-12 display decompression operates on Y-tiled compressed main
> surface.
> The CCS is linear and has 4 bits of metadata for each main surface
> cache
> line pair, a size ratio of 1:256. Gen-12 display decompression is
> incompatible with buffers compressed by earlier GPUs, so make use of
> a new
> modifier to identify gen-12 compression. Another notable change is
> that
> render decompression is supported on all planes except cursor and on
> all
> pipes. Start by adding render decompression support for [A,X]BGR888
> pixel
> formats.
> 
> v2: Fix checkpatch warnings (Lucas)
> v3:
> Rebase, disable color clear, styling changes and modify
> intel_tile_width_bytes and intel_tile_height to handle linear CCS
> v4:
> - Use format block descriptors and the i915 specific func to get the
>   subsampling for each color plane.
> - Use helpers to convert between CCS and main planes.
> v5:
> - Fix subsampling returned by intel_fb_plane_get_subsampling() for
>   the CCS plane of the first plane.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
r-b for the correct version of the patch
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 185 +++++++++++++++
> ----
>  drivers/gpu/drm/i915/display/intel_sprite.c  |  23 ++-
>  drivers/gpu/drm/i915/i915_reg.h              |   1 +
>  3 files changed, 169 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6bda397ae677..c9a92d62a70f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1941,6 +1941,16 @@ static bool is_ccs_plane(const struct
> drm_framebuffer *fb, int plane)
>  	return plane >= fb->format->num_planes / 2;
>  }
>  
> +static bool is_gen12_ccs_modifier(u64 modifier)
> +{
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> +}
> +
> +static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int
> plane)
> +{
> +	return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb,
> plane);
> +}
> +
>  static bool is_aux_plane(const struct drm_framebuffer *fb, int
> plane)
>  {
>  	if (is_ccs_modifier(fb->modifier))
> @@ -1957,6 +1967,14 @@ static int main_to_ccs_plane(const struct
> drm_framebuffer *fb, int main_plane)
>  	return fb->format->num_planes / 2 + main_plane;
>  }
>  
> +static int ccs_to_main_plane(const struct drm_framebuffer *fb, int
> ccs_plane)
> +{
> +	WARN_ON(!is_ccs_modifier(fb->modifier) ||
> +		ccs_plane < fb->format->num_planes / 2);
> +
> +	return ccs_plane - fb->format->num_planes / 2;
> +}
> +
>  /* Return either the main plane's CCS or - if not a CCS FB - UV
> plane */
>  static int
>  intel_main_to_aux_plane(const struct drm_framebuffer *fb, int
> main_plane)
> @@ -1985,6 +2003,10 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
>  		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		if (is_ccs_plane(fb, color_plane))
> +			return 64;
> +		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
>  		if (IS_GEN(dev_priv, 2) ||
> HAS_128_BYTE_Y_TILING(dev_priv))
>  			return 128;
> @@ -2018,6 +2040,9 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
>  static unsigned int
>  intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
>  {
> +	if (is_gen12_ccs_plane(fb, color_plane))
> +		return 1;
> +
>  	return intel_tile_size(to_i915(fb->dev)) /
>  		intel_tile_width_bytes(fb, color_plane);
>  }
> @@ -2118,6 +2143,8 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
>  		if (INTEL_GEN(dev_priv) >= 9)
>  			return 256 * 1024;
>  		return 0;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return 16 * 1024;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -2310,9 +2337,10 @@ static u32 intel_adjust_tile_offset(int *x,
> int *y,
>  	return new_offset;
>  }
>  
> -static bool is_surface_linear(u64 modifier, int color_plane)
> +static bool is_surface_linear(const struct drm_framebuffer *fb, int
> color_plane)
>  {
> -	return modifier == DRM_FORMAT_MOD_LINEAR;
> +	return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
> +	       is_gen12_ccs_plane(fb, color_plane);
>  }
>  
>  static u32 intel_adjust_aligned_offset(int *x, int *y,
> @@ -2327,7 +2355,7 @@ static u32 intel_adjust_aligned_offset(int *x,
> int *y,
>  
>  	WARN_ON(new_offset > old_offset);
>  
> -	if (!is_surface_linear(fb->modifier, color_plane)) {
> +	if (!is_surface_linear(fb, color_plane)) {
>  		unsigned int tile_size, tile_width, tile_height;
>  		unsigned int pitch_tiles;
>  
> @@ -2397,7 +2425,7 @@ static u32 intel_compute_aligned_offset(struct
> drm_i915_private *dev_priv,
>  	if (alignment)
>  		alignment--;
>  
> -	if (!is_surface_linear(fb->modifier, color_plane)) {
> +	if (!is_surface_linear(fb, color_plane)) {
>  		unsigned int tile_size, tile_width, tile_height;
>  		unsigned int tile_rows, tiles, pitch_tiles;
>  
> @@ -2499,6 +2527,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
>  		return I915_TILING_X;
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return I915_TILING_Y;
>  	default:
>  		return I915_TILING_NONE;
> @@ -2519,7 +2548,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
>   * us a ratio of one byte in the CCS for each 8x16 pixels in the
>   * main surface.
>   */
> -static const struct drm_format_info ccs_formats[] = {
> +static const struct drm_format_info skl_ccs_formats[] = {
>  	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
>  	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> @@ -2530,6 +2559,28 @@ static const struct drm_format_info
> ccs_formats[] = {
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true,
> },
>  };
>  
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line
> pair in the
> + * main surface. And each 64B CCS cache line represents an area of
> 4x1 Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having
> dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32
> pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> +	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> +	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> +	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> +	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +};
> +
>  static const struct drm_format_info *
>  lookup_format_info(const struct drm_format_info formats[],
>  		   int num_formats, u32 format)
> @@ -2550,8 +2601,12 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
>  	switch (cmd->modifier[0]) {
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> -		return lookup_format_info(ccs_formats,
> -					  ARRAY_SIZE(ccs_formats),
> +		return lookup_format_info(skl_ccs_formats,
> +					  ARRAY_SIZE(skl_ccs_formats),
> +					  cmd->pixel_format);
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return lookup_format_info(gen12_ccs_formats,
> +					  ARRAY_SIZE(gen12_ccs_formats)
> ,
>  					  cmd->pixel_format);
>  	default:
>  		return NULL;
> @@ -2560,7 +2615,8 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
>  
>  bool is_ccs_modifier(u64 modifier)
>  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
>  
> @@ -2608,8 +2664,9 @@ static u32
>  intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> color_plane)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
> +	u32 tile_width;
>  
> -	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> +	if (is_surface_linear(fb, color_plane)) {
>  		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
>  							   fb->format-
> >format,
>  							   fb-
> >modifier);
> @@ -2618,13 +2675,14 @@ intel_fb_stride_alignment(const struct
> drm_framebuffer *fb, int color_plane)
>  		 * To make remapping with linear generally feasible
>  		 * we need the stride to be page aligned.
>  		 */
> -		if (fb->pitches[color_plane] > max_stride)
> +		if (fb->pitches[color_plane] > max_stride &&
> !is_ccs_modifier(fb->modifier))
>  			return intel_tile_size(dev_priv);
>  		else
>  			return 64;
> -	} else {
> -		u32 tile_width = intel_tile_width_bytes(fb,
> color_plane);
> +	}
>  
> +	tile_width = intel_tile_width_bytes(fb, color_plane);
> +	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
>  		/*
>  		 * Display WA #0531: skl,bxt,kbl,glk
>  		 *
> @@ -2634,12 +2692,16 @@ intel_fb_stride_alignment(const struct
> drm_framebuffer *fb, int color_plane)
>  		 * require the entire fb to accommodate that to avoid
>  		 * potential runtime errors at plane configuration
> time.
>  		 */
> -		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb-
> >modifier) &&
> -		    color_plane == 0 && fb->width > 3840)
> +		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
> +			tile_width *= 4;
> +		/*
> +		 * The main surface pitch must be padded to a multiple
> of four
> +		 * tile widths.
> +		 */
> +		else if (INTEL_GEN(dev_priv) >= 12)
>  			tile_width *= 4;
> -
> -		return tile_width;
>  	}
> +	return tile_width;
>  }
>  
>  bool intel_plane_can_remap(const struct intel_plane_state
> *plane_state)
> @@ -2710,25 +2772,74 @@ static bool intel_plane_needs_remap(const
> struct intel_plane_state *plane_state)
>  	return stride > max_stride;
>  }
>  
> +static void
> +intel_fb_plane_get_subsampling(int *hsub, int *vsub,
> +			       const struct drm_framebuffer *fb,
> +			       int color_plane)
> +{
> +	int main_plane;
> +
> +	if (color_plane == 0) {
> +		*hsub = 1;
> +		*vsub = 1;
> +
> +		return;
> +	}
> +
> +	/*
> +	 * TODO: Deduct the subsampling from the char block for all CCS
> +	 * formats and planes.
> +	 */
> +	if (!is_gen12_ccs_plane(fb, color_plane)) {
> +		*hsub = fb->format->hsub;
> +		*vsub = fb->format->vsub;
> +
> +		return;
> +	}
> +
> +	main_plane = ccs_to_main_plane(fb, color_plane);
> +	*hsub = drm_format_info_block_width(fb->format, color_plane) /
> +	        drm_format_info_block_width(fb->format, main_plane);
> +
> +	/*
> +	 * The min stride check in the core framebuffer_check()
> function
> +	 * assumes that format->hsub applies to every plane except for
> the
> +	 * first plane. That's incorrect for the CCS AUX plane of the
> first
> +	 * plane, but for the above check to pass we must define the
> block
> +	 * width with that subsampling applied to it. Adjust the width
> here
> +	 * accordingly, so we can calculate the actual subsampling
> factor.
> +	 */
> +	if (main_plane == 0)
> +		*hsub *= fb->format->hsub;
> +
> +	*vsub = 32;
> +}
>  static int
>  intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
>  {
>  	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> +	int main_plane;
> +	int hsub, vsub;
>  	int tile_width, tile_height;
>  	int ccs_x, ccs_y;
>  	int main_x, main_y;
> +	int ccs_plane = 1;
>  
> -	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> +	if (!is_ccs_plane(fb, ccs_plane))
> +		return 0;
> +
> +	intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
>  
>  	tile_width *= hsub;
>  	tile_height *= vsub;
>  
>  	ccs_x = (x * hsub) % tile_width;
>  	ccs_y = (y * vsub) % tile_height;
> -	main_x = intel_fb->normal[0].x % tile_width;
> -	main_y = intel_fb->normal[0].y % tile_height;
> +
> +	main_plane = ccs_to_main_plane(fb, ccs_plane);
> +	main_x = intel_fb->normal[main_plane].x % tile_width;
> +	main_y = intel_fb->normal[main_plane].y % tile_height;
>  
>  	/*
>  	 * CCS doesn't have its own x/y offset register, so the intra
> CCS tile
> @@ -2738,8 +2849,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer
> *fb, int x, int y)
>  		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full
> (main %d,%d ccs %d,%d)\n",
>  			      main_x, main_y,
>  			      ccs_x, ccs_y,
> -			      intel_fb->normal[0].x,
> -			      intel_fb->normal[0].y,
> +			      intel_fb->normal[main_plane].x,
> +			      intel_fb->normal[main_plane].y,
>  			      x, y);
>  		return -EINVAL;
>  	}
> @@ -2810,7 +2921,7 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
>  						      tile_size);
>  		offset /= tile_size;
>  
> -		if (!is_surface_linear(fb->modifier, i)) {
> +		if (!is_surface_linear(fb, i)) {
>  			unsigned int tile_width, tile_height;
>  			unsigned int pitch_tiles;
>  			struct drm_rect r;
> @@ -3489,14 +3600,15 @@ static bool
> skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  					   int main_x, int main_y, u32
> main_offset)
>  {
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
>  	int ccs_plane = main_to_ccs_plane(fb, 0);
>  	int aux_x = plane_state->color_plane[ccs_plane].x;
>  	int aux_y = plane_state->color_plane[ccs_plane].y;
>  	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
>  	u32 alignment = intel_surf_alignment(fb, ccs_plane);
> +	int hsub;
> +	int vsub;
>  
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
>  	while (aux_offset >= main_offset && aux_y <= main_y) {
>  		int x, y;
>  
> @@ -3657,12 +3769,15 @@ static int skl_check_ccs_aux_surface(struct
> intel_plane_state *plane_state)
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	int src_x = plane_state->uapi.src.x1 >> 16;
>  	int src_y = plane_state->uapi.src.y1 >> 16;
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> -	int x = src_x / hsub;
> -	int y = src_y / vsub;
> +	int hsub;
> +	int vsub;
> +	int x;
> +	int y;
>  	u32 offset;
>  
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
> +	x = src_x / hsub;
> +	y = src_y / vsub;
>  	intel_add_fb_offsets(&x, &y, plane_state, 1);
>  	offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 1);
>  
> @@ -4158,7 +4273,7 @@ static unsigned int skl_plane_stride_mult(const
> struct drm_framebuffer *fb,
>  	 * The stride is either expressed as a multiple of 64 bytes
> chunks for
>  	 * linear buffers or in number of tiles for tiled buffers.
>  	 */
> -	if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> +	if (is_surface_linear(fb, color_plane))
>  		return 64;
>  	else if (drm_rotation_90_or_270(rotation))
>  		return intel_tile_height(fb, color_plane);
> @@ -4286,6 +4401,10 @@ static u32 skl_plane_ctl_tiling(u64
> fb_modifier)
>  		return PLANE_CTL_TILED_Y;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  		return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return PLANE_CTL_TILED_Y |
> +		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> +		       PLANE_CTL_CLEAR_COLOR_DISABLE;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return PLANE_CTL_TILED_YF;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -10021,7 +10140,9 @@ skylake_get_initial_plane_config(struct
> intel_crtc *crtc,
>  	case PLANE_CTL_TILED_Y:
>  		plane_config->tiling = I915_TILING_Y;
>  		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> -			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
> +			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> +				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> +				I915_FORMAT_MOD_Y_TILED_CCS;
>  		else
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 8394502b092d..67a90059900f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -583,6 +583,7 @@ skl_program_plane(struct intel_plane *plane,
>  	const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
>  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
>  	u32 stride = skl_plane_stride(plane_state, color_plane);
> +	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
>  	u32 aux_stride = skl_plane_stride(plane_state, 1);
>  	int crtc_x = plane_state->uapi.dst.x1;
>  	int crtc_y = plane_state->uapi.dst.y1;
> @@ -624,8 +625,10 @@ skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
>  	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) |
> crtc_x);
>  	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) |
> src_w);
> -	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
> -		      (plane_state->color_plane[1].offset - surf_addr)
> | aux_stride);
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		aux_dist |= aux_stride;
> +	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
>  
>  	if (icl_is_hdr_plane(dev_priv, plane_id))
>  		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id),
> plane_state->cus_ctl);
> @@ -2102,7 +2105,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
>  	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> mode\n");
>  		return -EINVAL;
>  	}
> @@ -2573,7 +2577,8 @@ static const u64
> skl_plane_format_modifiers_ccs[] = {
>  	DRM_FORMAT_MOD_INVALID
>  };
>  
> -static const u64 gen12_plane_format_modifiers_noccs[] = {
> +static const u64 gen12_plane_format_modifiers_ccs[] = {
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
>  	DRM_FORMAT_MOD_LINEAR,
> @@ -2744,6 +2749,7 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		break;
>  	default:
>  		return false;
> @@ -2754,6 +2760,9 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_XBGR8888:
>  	case DRM_FORMAT_ARGB8888:
>  	case DRM_FORMAT_ABGR8888:
> +		if (is_ccs_modifier(modifier))
> +			return true;
> +		/* fall through */
>  	case DRM_FORMAT_RGB565:
>  	case DRM_FORMAT_XRGB2101010:
>  	case DRM_FORMAT_XBGR2101010:
> @@ -2963,13 +2972,11 @@ skl_universal_plane_create(struct
> drm_i915_private *dev_priv,
>  		formats = skl_get_plane_formats(dev_priv, pipe,
>  						plane_id,
> &num_formats);
>  
> +	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		/* TODO: Implement support for gen-12 CCS modifiers */
> -		plane->has_ccs = false;
> -		modifiers = gen12_plane_format_modifiers_noccs;
> +		modifiers = gen12_plane_format_modifiers_ccs;
>  		plane_funcs = &gen12_plane_funcs;
>  	} else {
> -		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
> plane_id);
>  		if (plane->has_ccs)
>  			modifiers = skl_plane_format_modifiers_ccs;
>  		else
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index cbb4689af432..bbfedeb00b7f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6800,6 +6800,7 @@ enum {
>  #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
>  #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
>  #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
> +#define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /*
> TGL+ */
>  #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /*
> Pre-GLK */
>  #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
>  #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 06/15] drm/i915/tgl: Gen-12 render decompression

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to identify gen-12 compression. Another notable change is that
render decompression is supported on all planes except cursor and on all
pipes. Start by adding render decompression support for [A,X]BGR888 pixel
formats.

v2: Fix checkpatch warnings (Lucas)
v3:
Rebase, disable color clear, styling changes and modify
intel_tile_width_bytes and intel_tile_height to handle linear CCS
v4:
- Use format block descriptors and the i915 specific func to get the
  subsampling for each color plane.
- Use helpers to convert between CCS and main planes.
v5:
- Fix subsampling returned by intel_fb_plane_get_subsampling() for
  the CCS plane of the first plane.
v6:
- Rebased on v2 of patch 4.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 183 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_sprite.c  |  23 ++-
 drivers/gpu/drm/i915/i915_reg.h              |   1 +
 3 files changed, 166 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5445f0d5b005..afed0331e8af 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1941,6 +1941,16 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
 	return plane >= fb->format->num_planes / 2;
 }
 
+static bool is_gen12_ccs_modifier(u64 modifier)
+{
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+}
+
+static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
+{
+	return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
+}
+
 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
 {
 	if (is_ccs_modifier(fb->modifier))
@@ -1957,6 +1967,14 @@ static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
 	return fb->format->num_planes / 2 + main_plane;
 }
 
+static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
+{
+	WARN_ON(!is_ccs_modifier(fb->modifier) ||
+		ccs_plane < fb->format->num_planes / 2);
+
+	return ccs_plane - fb->format->num_planes / 2;
+}
+
 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
 static int
 intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
@@ -1985,6 +2003,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (is_ccs_plane(fb, color_plane))
 			return 128;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		if (is_ccs_plane(fb, color_plane))
+			return 64;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
 		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
 			return 128;
@@ -2018,6 +2040,9 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 static unsigned int
 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
 {
+	if (is_gen12_ccs_plane(fb, color_plane))
+		return 1;
+
 	return intel_tile_size(to_i915(fb->dev)) /
 		intel_tile_width_bytes(fb, color_plane);
 }
@@ -2118,6 +2143,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 		if (INTEL_GEN(dev_priv) >= 9)
 			return 256 * 1024;
 		return 0;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2310,9 +2337,10 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 	return new_offset;
 }
 
-static bool is_surface_linear(u64 modifier, int color_plane)
+static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR;
+	return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
+	       is_gen12_ccs_plane(fb, color_plane);
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2327,7 +2355,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
 
 	WARN_ON(new_offset > old_offset);
 
-	if (!is_surface_linear(fb->modifier, color_plane)) {
+	if (!is_surface_linear(fb, color_plane)) {
 		unsigned int tile_size, tile_width, tile_height;
 		unsigned int pitch_tiles;
 
@@ -2397,7 +2425,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
 	if (alignment)
 		alignment--;
 
-	if (!is_surface_linear(fb->modifier, color_plane)) {
+	if (!is_surface_linear(fb, color_plane)) {
 		unsigned int tile_size, tile_width, tile_height;
 		unsigned int tile_rows, tiles, pitch_tiles;
 
@@ -2499,6 +2527,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 		return I915_TILING_X;
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2519,7 +2548,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
  * us a ratio of one byte in the CCS for each 8x16 pixels in the
  * main surface.
  */
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2530,6 +2559,28 @@ static const struct drm_format_info ccs_formats[] = {
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
 };
 
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2550,8 +2601,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 	switch (cmd->modifier[0]) {
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
-		return lookup_format_info(ccs_formats,
-					  ARRAY_SIZE(ccs_formats),
+		return lookup_format_info(skl_ccs_formats,
+					  ARRAY_SIZE(skl_ccs_formats),
+					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return lookup_format_info(gen12_ccs_formats,
+					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
 	default:
 		return NULL;
@@ -2560,7 +2615,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 
 bool is_ccs_modifier(u64 modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
 
@@ -2608,8 +2664,9 @@ static u32
 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 {
 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
+	u32 tile_width;
 
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+	if (is_surface_linear(fb, color_plane)) {
 		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
 							   fb->format->format,
 							   fb->modifier);
@@ -2618,13 +2675,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * To make remapping with linear generally feasible
 		 * we need the stride to be page aligned.
 		 */
-		if (fb->pitches[color_plane] > max_stride)
+		if (fb->pitches[color_plane] > max_stride && !is_ccs_modifier(fb->modifier))
 			return intel_tile_size(dev_priv);
 		else
 			return 64;
-	} else {
-		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+	}
 
+	tile_width = intel_tile_width_bytes(fb, color_plane);
+	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2634,12 +2692,16 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
-		    color_plane == 0 && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+			tile_width *= 4;
+		/*
+		 * The main surface pitch must be padded to a multiple of four
+		 * tile widths.
+		 */
+		else if (INTEL_GEN(dev_priv) >= 12)
 			tile_width *= 4;
-
-		return tile_width;
 	}
+	return tile_width;
 }
 
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
@@ -2710,28 +2772,73 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub,
+			       const struct drm_framebuffer *fb,
+			       int color_plane)
+{
+	int main_plane;
+
+	if (color_plane == 0) {
+		*hsub = 1;
+		*vsub = 1;
+
+		return;
+	}
+
+	/*
+	 * TODO: Deduct the subsampling from the char block for all CCS
+	 * formats and planes.
+	 */
+	if (!is_gen12_ccs_plane(fb, color_plane)) {
+		*hsub = fb->format->hsub;
+		*vsub = fb->format->vsub;
+
+		return;
+	}
+
+	main_plane = ccs_to_main_plane(fb, color_plane);
+	*hsub = drm_format_info_block_width(fb->format, color_plane) /
+		drm_format_info_block_width(fb->format, main_plane);
+
+	/*
+	 * The min stride check in the core framebuffer_check() function
+	 * assumes that format->hsub applies to every plane except for the
+	 * first plane. That's incorrect for the CCS AUX plane of the first
+	 * plane, but for the above check to pass we must define the block
+	 * width with that subsampling applied to it. Adjust the width here
+	 * accordingly, so we can calculate the actual subsampling factor.
+	 */
+	if (main_plane == 0)
+		*hsub *= fb->format->hsub;
+
+	*vsub = 32;
+}
 static int
 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
+	int main_plane;
+	int hsub, vsub;
 	int tile_width, tile_height;
 	int ccs_x, ccs_y;
 	int main_x, main_y;
 
-	if (!is_ccs_modifier(fb->modifier) || ccs_plane != 1)
+	if (!is_ccs_plane(fb, ccs_plane))
 		return 0;
 
-	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+	intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
 
 	tile_width *= hsub;
 	tile_height *= vsub;
 
 	ccs_x = (x * hsub) % tile_width;
 	ccs_y = (y * vsub) % tile_height;
-	main_x = intel_fb->normal[0].x % tile_width;
-	main_y = intel_fb->normal[0].y % tile_height;
+
+	main_plane = ccs_to_main_plane(fb, ccs_plane);
+	main_x = intel_fb->normal[main_plane].x % tile_width;
+	main_y = intel_fb->normal[main_plane].y % tile_height;
 
 	/*
 	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
@@ -2741,8 +2848,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
 		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
 			      main_x, main_y,
 			      ccs_x, ccs_y,
-			      intel_fb->normal[0].x,
-			      intel_fb->normal[0].y,
+			      intel_fb->normal[main_plane].x,
+			      intel_fb->normal[main_plane].y,
 			      x, y);
 		return -EINVAL;
 	}
@@ -2813,7 +2920,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 						      tile_size);
 		offset /= tile_size;
 
-		if (!is_surface_linear(fb->modifier, i)) {
+		if (!is_surface_linear(fb, i)) {
 			unsigned int tile_width, tile_height;
 			unsigned int pitch_tiles;
 			struct drm_rect r;
@@ -3492,14 +3599,15 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 					   int main_x, int main_y, u32 main_offset)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
 	int ccs_plane = main_to_ccs_plane(fb, 0);
 	int aux_x = plane_state->color_plane[ccs_plane].x;
 	int aux_y = plane_state->color_plane[ccs_plane].y;
 	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
 	u32 alignment = intel_surf_alignment(fb, ccs_plane);
+	int hsub;
+	int vsub;
 
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
 	while (aux_offset >= main_offset && aux_y <= main_y) {
 		int x, y;
 
@@ -3660,12 +3768,15 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int src_x = plane_state->uapi.src.x1 >> 16;
 	int src_y = plane_state->uapi.src.y1 >> 16;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
-	int x = src_x / hsub;
-	int y = src_y / vsub;
+	int hsub;
+	int vsub;
+	int x;
+	int y;
 	u32 offset;
 
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
+	x = src_x / hsub;
+	y = src_y / vsub;
 	intel_add_fb_offsets(&x, &y, plane_state, 1);
 	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
 
@@ -4161,7 +4272,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+	if (is_surface_linear(fb, color_plane))
 		return 64;
 	else if (drm_rotation_90_or_270(rotation))
 		return intel_tile_height(fb, color_plane);
@@ -4289,6 +4400,10 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return PLANE_CTL_TILED_Y |
+		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+		       PLANE_CTL_CLEAR_COLOR_DISABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -10024,7 +10139,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 	case PLANE_CTL_TILED_Y:
 		plane_config->tiling = I915_TILING_Y;
 		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+				I915_FORMAT_MOD_Y_TILED_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 8394502b092d..67a90059900f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -583,6 +583,7 @@ skl_program_plane(struct intel_plane *plane,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
+	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
 	u32 aux_stride = skl_plane_stride(plane_state, 1);
 	int crtc_x = plane_state->uapi.dst.x1;
 	int crtc_y = plane_state->uapi.dst.y1;
@@ -624,8 +625,10 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+	if (INTEL_GEN(dev_priv) < 12)
+		aux_dist |= aux_stride;
+	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
 
 	if (icl_is_hdr_plane(dev_priv, plane_id))
 		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);
@@ -2102,7 +2105,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2573,7 +2577,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2744,6 +2749,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		break;
 	default:
 		return false;
@@ -2754,6 +2760,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_ABGR8888:
+		if (is_ccs_modifier(modifier))
+			return true;
+		/* fall through */
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
@@ -2963,13 +2972,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		formats = skl_get_plane_formats(dev_priv, pipe,
 						plane_id, &num_formats);
 
+	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		/* TODO: Implement support for gen-12 CCS modifiers */
-		plane->has_ccs = false;
-		modifiers = gen12_plane_format_modifiers_noccs;
+		modifiers = gen12_plane_format_modifiers_ccs;
 		plane_funcs = &gen12_plane_funcs;
 	} else {
-		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 		if (plane->has_ccs)
 			modifiers = skl_plane_format_modifiers_ccs;
 		else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbb4689af432..bbfedeb00b7f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6800,6 +6800,7 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
+#define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
 #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 06/15] drm/i915/tgl: Gen-12 render decompression

[Sripada, Radhakrishna]

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Gen-12 display decompression operates on Y-tiled compressed main
> surface.
> The CCS is linear and has 4 bits of metadata for each main surface
> cache
> line pair, a size ratio of 1:256. Gen-12 display decompression is
> incompatible with buffers compressed by earlier GPUs, so make use of
> a new
> modifier to identify gen-12 compression. Another notable change is
> that
> render decompression is supported on all planes except cursor and on
> all
> pipes. Start by adding render decompression support for [A,X]BGR888
> pixel
> formats.
> 
> v2: Fix checkpatch warnings (Lucas)
> v3:
> Rebase, disable color clear, styling changes and modify
> intel_tile_width_bytes and intel_tile_height to handle linear CCS
> v4:
> - Use format block descriptors and the i915 specific func to get the
>   subsampling for each color plane.
> - Use helpers to convert between CCS and main planes.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 185 +++++++++++++++
> ----
>  drivers/gpu/drm/i915/display/intel_sprite.c  |  23 ++-
>  drivers/gpu/drm/i915/i915_reg.h              |   1 +
>  3 files changed, 169 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6bda397ae677..641ea24539eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1941,6 +1941,16 @@ static bool is_ccs_plane(const struct
> drm_framebuffer *fb, int plane)
>  	return plane >= fb->format->num_planes / 2;
>  }
>  
> +static bool is_gen12_ccs_modifier(u64 modifier)
> +{
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> +}
> +
> +static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int
> plane)
> +{
> +	return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb,
> plane);
> +}
> +
>  static bool is_aux_plane(const struct drm_framebuffer *fb, int
> plane)
>  {
>  	if (is_ccs_modifier(fb->modifier))
> @@ -1957,6 +1967,14 @@ static int main_to_ccs_plane(const struct
> drm_framebuffer *fb, int main_plane)
>  	return fb->format->num_planes / 2 + main_plane;
>  }
>  
> +static int ccs_to_main_plane(const struct drm_framebuffer *fb, int
> ccs_plane)
> +{
> +	WARN_ON(!is_ccs_modifier(fb->modifier) ||
> +		ccs_plane < fb->format->num_planes / 2);
> +
> +	return ccs_plane - fb->format->num_planes / 2;
> +}
> +
>  /* Return either the main plane's CCS or - if not a CCS FB - UV
> plane */
>  static int
>  intel_main_to_aux_plane(const struct drm_framebuffer *fb, int
> main_plane)
> @@ -1985,6 +2003,10 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
>  		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		if (is_ccs_plane(fb, color_plane))
> +			return 64;
> +		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
>  		if (IS_GEN(dev_priv, 2) ||
> HAS_128_BYTE_Y_TILING(dev_priv))
>  			return 128;
> @@ -2018,6 +2040,9 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
>  static unsigned int
>  intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
>  {
> +	if (is_gen12_ccs_plane(fb, color_plane))
> +		return 1;
> +
>  	return intel_tile_size(to_i915(fb->dev)) /
>  		intel_tile_width_bytes(fb, color_plane);
>  }
> @@ -2118,6 +2143,8 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
>  		if (INTEL_GEN(dev_priv) >= 9)
>  			return 256 * 1024;
>  		return 0;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return 16 * 1024;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -2310,9 +2337,10 @@ static u32 intel_adjust_tile_offset(int *x,
> int *y,
>  	return new_offset;
>  }
>  
> -static bool is_surface_linear(u64 modifier, int color_plane)
> +static bool is_surface_linear(const struct drm_framebuffer *fb, int
> color_plane)
>  {
> -	return modifier == DRM_FORMAT_MOD_LINEAR;
> +	return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
> +	       is_gen12_ccs_plane(fb, color_plane);
>  }
>  
>  static u32 intel_adjust_aligned_offset(int *x, int *y,
> @@ -2327,7 +2355,7 @@ static u32 intel_adjust_aligned_offset(int *x,
> int *y,
>  
>  	WARN_ON(new_offset > old_offset);
>  
> -	if (!is_surface_linear(fb->modifier, color_plane)) {
> +	if (!is_surface_linear(fb, color_plane)) {
>  		unsigned int tile_size, tile_width, tile_height;
>  		unsigned int pitch_tiles;
>  
> @@ -2397,7 +2425,7 @@ static u32 intel_compute_aligned_offset(struct
> drm_i915_private *dev_priv,
>  	if (alignment)
>  		alignment--;
>  
> -	if (!is_surface_linear(fb->modifier, color_plane)) {
> +	if (!is_surface_linear(fb, color_plane)) {
>  		unsigned int tile_size, tile_width, tile_height;
>  		unsigned int tile_rows, tiles, pitch_tiles;
>  
> @@ -2499,6 +2527,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
>  		return I915_TILING_X;
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return I915_TILING_Y;
>  	default:
>  		return I915_TILING_NONE;
> @@ -2519,7 +2548,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
>   * us a ratio of one byte in the CCS for each 8x16 pixels in the
>   * main surface.
>   */
> -static const struct drm_format_info ccs_formats[] = {
> +static const struct drm_format_info skl_ccs_formats[] = {
>  	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
>  	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> @@ -2530,6 +2559,28 @@ static const struct drm_format_info
> ccs_formats[] = {
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true,
> },
>  };
>  
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line
> pair in the
> + * main surface. And each 64B CCS cache line represents an area of
> 4x1 Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having
> dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32
> pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> +	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> +	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> +	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> +	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +};
> +
>  static const struct drm_format_info *
>  lookup_format_info(const struct drm_format_info formats[],
>  		   int num_formats, u32 format)
> @@ -2550,8 +2601,12 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
>  	switch (cmd->modifier[0]) {
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> -		return lookup_format_info(ccs_formats,
> -					  ARRAY_SIZE(ccs_formats),
> +		return lookup_format_info(skl_ccs_formats,
> +					  ARRAY_SIZE(skl_ccs_formats),
> +					  cmd->pixel_format);
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return lookup_format_info(gen12_ccs_formats,
> +					  ARRAY_SIZE(gen12_ccs_formats)
> ,
>  					  cmd->pixel_format);
>  	default:
>  		return NULL;
> @@ -2560,7 +2615,8 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
>  
>  bool is_ccs_modifier(u64 modifier)
>  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
>  
> @@ -2608,8 +2664,9 @@ static u32
>  intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> color_plane)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
> +	u32 tile_width;
>  
> -	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> +	if (is_surface_linear(fb, color_plane)) {
>  		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
>  							   fb->format-
> >format,
>  							   fb-
> >modifier);
> @@ -2618,13 +2675,14 @@ intel_fb_stride_alignment(const struct
> drm_framebuffer *fb, int color_plane)
>  		 * To make remapping with linear generally feasible
>  		 * we need the stride to be page aligned.
>  		 */
> -		if (fb->pitches[color_plane] > max_stride)
> +		if (fb->pitches[color_plane] > max_stride &&
> !is_ccs_modifier(fb->modifier))
>  			return intel_tile_size(dev_priv);
>  		else
>  			return 64;
> -	} else {
> -		u32 tile_width = intel_tile_width_bytes(fb,
> color_plane);
> +	}
>  
> +	tile_width = intel_tile_width_bytes(fb, color_plane);
> +	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
>  		/*
>  		 * Display WA #0531: skl,bxt,kbl,glk
>  		 *
> @@ -2634,12 +2692,16 @@ intel_fb_stride_alignment(const struct
> drm_framebuffer *fb, int color_plane)
>  		 * require the entire fb to accommodate that to avoid
>  		 * potential runtime errors at plane configuration
> time.
>  		 */
> -		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb-
> >modifier) &&
> -		    color_plane == 0 && fb->width > 3840)
> +		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
> +			tile_width *= 4;
> +		/*
> +		 * The main surface pitch must be padded to a multiple
> of four
> +		 * tile widths.
> +		 */
> +		else if (INTEL_GEN(dev_priv) >= 12)
>  			tile_width *= 4;
> -
> -		return tile_width;
>  	}
> +	return tile_width;
>  }
>  
>  bool intel_plane_can_remap(const struct intel_plane_state
> *plane_state)
> @@ -2710,25 +2772,74 @@ static bool intel_plane_needs_remap(const
> struct intel_plane_state *plane_state)
>  	return stride > max_stride;
>  }
>  
> +static void
> +intel_fb_plane_get_subsampling(int *hsub, int *vsub,
> +			       const struct drm_framebuffer *fb,
> +			       int color_plane)
> +{
> +	int main_plane;
> +
> +	if (color_plane == 0) {
> +		*hsub = 1;
> +		*vsub = 1;
> +
> +		return;
> +	}
> +
> +	/*
> +	 * TODO: Deduct the subsampling from the char block for all CCS
> +	 * formats and planes.
> +	 */
> +	if (!is_gen12_ccs_plane(fb, color_plane)) {
> +		*hsub = fb->format->hsub;
> +		*vsub = fb->format->vsub;
> +
> +		return;
> +	}
> +
> +	main_plane = ccs_to_main_plane(fb, color_plane);
> +	*hsub = drm_format_info_block_width(fb->format, color_plane) /
> +	        drm_format_info_block_width(fb->format, main_plane);
> +
> +	/*
> +	 * The min stride check in the core framebuffer_check()
> function
> +	 * assumes that format->hsub applies to every plane except for
> the
> +	 * first plane. That's incorrect for the CCS AUX plane of the
> first
> +	 * plane, but for the above check to pass we must define the
> block
> +	 * width with that subsampling applied to it. Adjust the width
> here
> +	 * accordingly, so we can calculate the actual subsampling
> factor.
> +	 */
> +	if (color_plane == 1)
> +		*hsub *= fb->format->hsub;
> +
> +	*vsub = 32;
> +}
>  static int
>  intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
>  {
>  	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> +	int main_plane;
> +	int hsub, vsub;
>  	int tile_width, tile_height;
>  	int ccs_x, ccs_y;
>  	int main_x, main_y;
> +	int ccs_plane = 1;
>  
> -	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> +	if (!is_ccs_plane(fb, ccs_plane))
> +		return 0;
> +
> +	intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
>  
>  	tile_width *= hsub;
>  	tile_height *= vsub;
>  
>  	ccs_x = (x * hsub) % tile_width;
>  	ccs_y = (y * vsub) % tile_height;
> -	main_x = intel_fb->normal[0].x % tile_width;
> -	main_y = intel_fb->normal[0].y % tile_height;
> +
> +	main_plane = ccs_to_main_plane(fb, ccs_plane);
> +	main_x = intel_fb->normal[main_plane].x % tile_width;
> +	main_y = intel_fb->normal[main_plane].y % tile_height;
>  
>  	/*
>  	 * CCS doesn't have its own x/y offset register, so the intra
> CCS tile
> @@ -2738,8 +2849,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer
> *fb, int x, int y)
>  		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full
> (main %d,%d ccs %d,%d)\n",
>  			      main_x, main_y,
>  			      ccs_x, ccs_y,
> -			      intel_fb->normal[0].x,
> -			      intel_fb->normal[0].y,
> +			      intel_fb->normal[main_plane].x,
> +			      intel_fb->normal[main_plane].y,
>  			      x, y);
>  		return -EINVAL;
>  	}
> @@ -2810,7 +2921,7 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
>  						      tile_size);
>  		offset /= tile_size;
>  
> -		if (!is_surface_linear(fb->modifier, i)) {
> +		if (!is_surface_linear(fb, i)) {
>  			unsigned int tile_width, tile_height;
>  			unsigned int pitch_tiles;
>  			struct drm_rect r;
> @@ -3489,14 +3600,15 @@ static bool
> skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  					   int main_x, int main_y, u32
> main_offset)
>  {
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
>  	int ccs_plane = main_to_ccs_plane(fb, 0);
>  	int aux_x = plane_state->color_plane[ccs_plane].x;
>  	int aux_y = plane_state->color_plane[ccs_plane].y;
>  	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
>  	u32 alignment = intel_surf_alignment(fb, ccs_plane);
> +	int hsub;
> +	int vsub;
>  
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
>  	while (aux_offset >= main_offset && aux_y <= main_y) {
>  		int x, y;
>  
> @@ -3657,12 +3769,15 @@ static int skl_check_ccs_aux_surface(struct
> intel_plane_state *plane_state)
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	int src_x = plane_state->uapi.src.x1 >> 16;
>  	int src_y = plane_state->uapi.src.y1 >> 16;
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> -	int x = src_x / hsub;
> -	int y = src_y / vsub;
> +	int hsub;
> +	int vsub;
> +	int x;
> +	int y;
>  	u32 offset;
>  
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
> +	x = src_x / hsub;
> +	y = src_y / vsub;
>  	intel_add_fb_offsets(&x, &y, plane_state, 1);
>  	offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 1);
>  
> @@ -4158,7 +4273,7 @@ static unsigned int skl_plane_stride_mult(const
> struct drm_framebuffer *fb,
>  	 * The stride is either expressed as a multiple of 64 bytes
> chunks for
>  	 * linear buffers or in number of tiles for tiled buffers.
>  	 */
> -	if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> +	if (is_surface_linear(fb, color_plane))
>  		return 64;
>  	else if (drm_rotation_90_or_270(rotation))
>  		return intel_tile_height(fb, color_plane);
> @@ -4286,6 +4401,10 @@ static u32 skl_plane_ctl_tiling(u64
> fb_modifier)
>  		return PLANE_CTL_TILED_Y;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  		return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return PLANE_CTL_TILED_Y |
> +		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> +		       PLANE_CTL_CLEAR_COLOR_DISABLE;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return PLANE_CTL_TILED_YF;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -10021,7 +10140,9 @@ skylake_get_initial_plane_config(struct
> intel_crtc *crtc,
>  	case PLANE_CTL_TILED_Y:
>  		plane_config->tiling = I915_TILING_Y;
>  		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> -			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
> +			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> +				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> +				I915_FORMAT_MOD_Y_TILED_CCS;
>  		else
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 8394502b092d..67a90059900f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -583,6 +583,7 @@ skl_program_plane(struct intel_plane *plane,
>  	const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
>  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
>  	u32 stride = skl_plane_stride(plane_state, color_plane);
> +	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
>  	u32 aux_stride = skl_plane_stride(plane_state, 1);
>  	int crtc_x = plane_state->uapi.dst.x1;
>  	int crtc_y = plane_state->uapi.dst.y1;
> @@ -624,8 +625,10 @@ skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
>  	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) |
> crtc_x);
>  	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) |
> src_w);
> -	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
> -		      (plane_state->color_plane[1].offset - surf_addr)
> | aux_stride);
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		aux_dist |= aux_stride;
> +	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
>  
>  	if (icl_is_hdr_plane(dev_priv, plane_id))
>  		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id),
> plane_state->cus_ctl);
> @@ -2102,7 +2105,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
>  	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> mode\n");
>  		return -EINVAL;
>  	}
> @@ -2573,7 +2577,8 @@ static const u64
> skl_plane_format_modifiers_ccs[] = {
>  	DRM_FORMAT_MOD_INVALID
>  };
>  
> -static const u64 gen12_plane_format_modifiers_noccs[] = {
> +static const u64 gen12_plane_format_modifiers_ccs[] = {
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
>  	DRM_FORMAT_MOD_LINEAR,
> @@ -2744,6 +2749,7 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		break;
>  	default:
>  		return false;
> @@ -2754,6 +2760,9 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_XBGR8888:
>  	case DRM_FORMAT_ARGB8888:
>  	case DRM_FORMAT_ABGR8888:
> +		if (is_ccs_modifier(modifier))
> +			return true;
> +		/* fall through */
>  	case DRM_FORMAT_RGB565:
>  	case DRM_FORMAT_XRGB2101010:
>  	case DRM_FORMAT_XBGR2101010:
> @@ -2963,13 +2972,11 @@ skl_universal_plane_create(struct
> drm_i915_private *dev_priv,
>  		formats = skl_get_plane_formats(dev_priv, pipe,
>  						plane_id,
> &num_formats);
>  
> +	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		/* TODO: Implement support for gen-12 CCS modifiers */
> -		plane->has_ccs = false;
> -		modifiers = gen12_plane_format_modifiers_noccs;
> +		modifiers = gen12_plane_format_modifiers_ccs;
>  		plane_funcs = &gen12_plane_funcs;
>  	} else {
> -		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
> plane_id);
>  		if (plane->has_ccs)
>  			modifiers = skl_plane_format_modifiers_ccs;
>  		else
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index cbb4689af432..bbfedeb00b7f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6800,6 +6800,7 @@ enum {
>  #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
>  #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
>  #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
> +#define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /*
> TGL+ */
>  #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /*
> Pre-GLK */
>  #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
>  #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
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[Intel-gfx] [PATCH 07/15] drm/i915/tgl: Make sure FBs have a correct CCS plane stride

[Imre Deak]

The CCS plane stride must be fixed on TGL, as it's not configurable for
the display. Instead the HW has a hardwired logic to determine it from
the main plane stride. Make sure userspace passes in the correct stride.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 641ea24539eb..7c52591172e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2620,6 +2620,11 @@ bool is_ccs_modifier(u64 modifier)
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
 
+static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
+{
+	return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)], 512) * 64;
+}
+
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier)
 {
@@ -16530,6 +16535,16 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			goto err;
 		}
 
+		if (is_gen12_ccs_plane(fb, i)) {
+			int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
+
+			if (fb->pitches[i] != ccs_aux_stride) {
+				DRM_DEBUG_KMS("ccs aux plane %d pitch (%d) must be %d\n",
+					      i, fb->pitches[i], ccs_aux_stride);
+				goto err;
+			}
+		}
+
 		fb->obj[i] = &obj->base;
 	}
 
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 07/15] drm/i915/tgl: Make sure FBs have a correct CCS plane stride

[Kahola, Mika]

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote:
> The CCS plane stride must be fixed on TGL, as it's not configurable
> for
> the display. Instead the HW has a hardwired logic to determine it
> from
> the main plane stride. Make sure userspace passes in the correct
> stride.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 641ea24539eb..7c52591172e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2620,6 +2620,11 @@ bool is_ccs_modifier(u64 modifier)
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
>  
> +static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int
> ccs_plane)
> +{
> +	return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb,
> ccs_plane)], 512) * 64;
> +}
> +
>  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  			      u32 pixel_format, u64 modifier)
>  {
> @@ -16530,6 +16535,16 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
>  			goto err;
>  		}
>  
> +		if (is_gen12_ccs_plane(fb, i)) {
> +			int ccs_aux_stride = gen12_ccs_aux_stride(fb,
> i);
> +
> +			if (fb->pitches[i] != ccs_aux_stride) {
> +				DRM_DEBUG_KMS("ccs aux plane %d pitch
> (%d) must be %d\n",
> +					      i, fb->pitches[i],
> ccs_aux_stride);
> +				goto err;
> +			}
> +		}
> +
>  		fb->obj[i] = &obj->base;
>  	}
>  
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Re: [Intel-gfx] [PATCH 07/15] drm/i915/tgl: Make sure FBs have a correct CCS plane stride

[Matt Roper]

On Wed, Dec 18, 2019 at 06:10:57PM +0200, Imre Deak wrote:
> The CCS plane stride must be fixed on TGL, as it's not configurable for
> the display. Instead the HW has a hardwired logic to determine it from
> the main plane stride. Make sure userspace passes in the correct stride.

Do you have a bspec page number reference for this?  I don't see it
mentioned anywhere obvious.


Matt

> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 641ea24539eb..7c52591172e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2620,6 +2620,11 @@ bool is_ccs_modifier(u64 modifier)
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
>  
> +static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
> +{
> +	return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)], 512) * 64;
> +}
> +
>  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  			      u32 pixel_format, u64 modifier)
>  {
> @@ -16530,6 +16535,16 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  			goto err;
>  		}
>  
> +		if (is_gen12_ccs_plane(fb, i)) {
> +			int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
> +
> +			if (fb->pitches[i] != ccs_aux_stride) {
> +				DRM_DEBUG_KMS("ccs aux plane %d pitch (%d) must be %d\n",
> +					      i, fb->pitches[i], ccs_aux_stride);
> +				goto err;
> +			}
> +		}
> +
>  		fb->obj[i] = &obj->base;
>  	}
>  
> -- 
> 2.22.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 07/15] drm/i915/tgl: Make sure FBs have a correct CCS plane stride

[Imre Deak]

On Thu, Dec 19, 2019 at 02:48:50PM -0800, Matt Roper wrote:
> On Wed, Dec 18, 2019 at 06:10:57PM +0200, Imre Deak wrote:
> > The CCS plane stride must be fixed on TGL, as it's not configurable for
> > the display. Instead the HW has a hardwired logic to determine it from
> > the main plane stride. Make sure userspace passes in the correct stride.
> 
> Do you have a bspec page number reference for this?  I don't see it
> mentioned anywhere obvious.

At Index/49253:
"Control surface stride is not used for media compression."

Assuming this refers to the stride we program to PLANE_AUX_DIST on
other platforms. The description of that field tells us:
"This field is unused. Leave at default value."

Practice does match this, since there seems to be no significance what
is programmed to this field (things keep working fine if the assumed
fixed stride was used for the CCS surface whatever I programmed to the
above field).

So the only explanation I see is what I wrote in the commit log.

The same must be true for render compression too and my test results
match with that assumption. There is no mention about constraints on the
stride or it being configureable somehow (unlike on other engines which
use the AUX pagetables), so I also added now a ticket to the render
compression page.

> 
> 
> Matt
> 
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 641ea24539eb..7c52591172e1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2620,6 +2620,11 @@ bool is_ccs_modifier(u64 modifier)
> >  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> >  }
> >  
> > +static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
> > +{
> > +	return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)], 512) * 64;
> > +}
> > +
> >  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> >  			      u32 pixel_format, u64 modifier)
> >  {
> > @@ -16530,6 +16535,16 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> >  			goto err;
> >  		}
> >  
> > +		if (is_gen12_ccs_plane(fb, i)) {
> > +			int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
> > +
> > +			if (fb->pitches[i] != ccs_aux_stride) {
> > +				DRM_DEBUG_KMS("ccs aux plane %d pitch (%d) must be %d\n",
> > +					      i, fb->pitches[i], ccs_aux_stride);
> > +				goto err;
> > +			}
> > +		}
> > +
> >  		fb->obj[i] = &obj->base;
> >  	}
> >  
> > -- 
> > 2.22.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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[Intel-gfx] [PATCH 08/15] drm/i915: Skip rotated offset adjustment for unsupported modifiers

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

During framebuffer creation, we pre-compute offsets for 90/270 plane
rotation. However, only Y and Yf modifiers support 90/270 rotation. So,
skip the calculations for other modifiers.

v2: Add a bounds check WARN for the rotation info array.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7c52591172e1..b4eb0d2147f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2926,13 +2926,16 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 						      tile_size);
 		offset /= tile_size;
 
-		if (!is_surface_linear(fb, i)) {
+		/* Y or Yf modifiers required for 90/270 rotation */
+		if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
+		    fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
 			unsigned int tile_width, tile_height;
 			unsigned int pitch_tiles;
 			struct drm_rect r;
 
 			intel_tile_dims(fb, i, &tile_width, &tile_height);
 
+			WARN_ON(i >= ARRAY_SIZE(rot_info->plane));
 			rot_info->plane[i].offset = offset;
 			rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
 			rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
@@ -3063,6 +3066,7 @@ intel_plane_remap_gtt(struct intel_plane_state *plane_state)
 						      DRM_MODE_ROTATE_0, tile_size);
 		offset /= tile_size;
 
+		WARN_ON(i >= ARRAY_SIZE(info->plane));
 		info->plane[i].offset = offset;
 		info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
 						     tile_width * cpp);
-- 
2.22.0

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[Intel-gfx] [PATCH v2 08/15] drm/i915: Skip rotated offset adjustment for unsupported modifiers

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

During framebuffer creation, we pre-compute offsets for 90/270 plane
rotation. However, only Y and Yf modifiers support 90/270 rotation. So,
skip the calculations for other modifiers.

To keep the gem buffer size check still working for tiled planes, factor
out the logic needed for rotation setup and skip only this part for
tiled planes other than Y/Yf.

v2: Add a bounds check WARN for the rotation info array.
v3: Keep the gem buffer size check working for tiled planes.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 117 ++++++++++++-------
 1 file changed, 76 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3180c1817b60..9c0f22410c4a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2863,12 +2863,71 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
 	return 0;
 }
 
+/*
+ * Setup the rotated view for an FB plane and return the size the GTT mapping
+ * requires for this view.
+ */
+static u32
+setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
+		  u32 gtt_offset_rotated, int x, int y,
+		  unsigned int width, unsigned int height,
+		  unsigned int tile_size,
+		  unsigned int tile_width, unsigned int tile_height,
+		  struct drm_framebuffer *fb)
+{
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	struct intel_rotation_info *rot_info = &intel_fb->rot_info;
+	unsigned int pitch_tiles;
+	struct drm_rect r;
+
+	if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
+	    fb->modifier != I915_FORMAT_MOD_Yf_TILED)
+		return 0;
+
+	if (WARN_ON(plane >= ARRAY_SIZE(rot_info->plane)))
+		return 0;
+
+	rot_info->plane[plane] = *plane_info;
+
+	intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
+
+	/* rotate the x/y offsets to match the GTT view */
+	drm_rect_init(&r, x, y, width, height);
+	drm_rect_rotate(&r,
+			plane_info->width * tile_width,
+			plane_info->height * tile_height,
+			DRM_MODE_ROTATE_270);
+	x = r.x1;
+	y = r.y1;
+
+	/* rotate the tile dimensions to match the GTT view */
+	pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
+	swap(tile_width, tile_height);
+
+	/*
+	 * We only keep the x/y offsets, so push all of the
+	 * gtt offset into the x/y offsets.
+	 */
+	intel_adjust_tile_offset(&x, &y,
+				 tile_width, tile_height,
+				 tile_size, pitch_tiles,
+				 gtt_offset_rotated * tile_size, 0);
+
+	/*
+	 * First pixel of the framebuffer from
+	 * the start of the rotated gtt mapping.
+	 */
+	intel_fb->rotated[plane].x = x;
+	intel_fb->rotated[plane].y = y;
+
+	return plane_info->width * plane_info->height;
+}
+
 static int
 intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		   struct drm_framebuffer *fb)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	struct intel_rotation_info *rot_info = &intel_fb->rot_info;
 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	u32 gtt_offset_rotated = 0;
 	unsigned int max_size = 0;
@@ -2926,23 +2985,21 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 						      tile_size);
 		offset /= tile_size;
 
+		/* Y or Yf modifiers required for 90/270 rotation */
 		if (!is_surface_linear(fb, i)) {
+			struct intel_remapped_plane_info plane_info;
 			unsigned int tile_width, tile_height;
-			unsigned int pitch_tiles;
-			struct drm_rect r;
 
 			intel_tile_dims(fb, i, &tile_width, &tile_height);
 
-			rot_info->plane[i].offset = offset;
-			rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
-			rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
-			rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
-
-			intel_fb->rotated[i].pitch =
-				rot_info->plane[i].height * tile_height;
+			plane_info.offset = offset;
+			plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
+							 tile_width * cpp);
+			plane_info.width = DIV_ROUND_UP(x + width, tile_width);
+			plane_info.height = DIV_ROUND_UP(y + height, tile_height);
 
 			/* how many tiles does this plane need */
-			size = rot_info->plane[i].stride * rot_info->plane[i].height;
+			size = plane_info.stride * plane_info.height;
 			/*
 			 * If the plane isn't horizontally tile aligned,
 			 * we need one more tile.
@@ -2950,36 +3007,13 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			if (x != 0)
 				size++;
 
-			/* rotate the x/y offsets to match the GTT view */
-			drm_rect_init(&r, x, y, width, height);
-			drm_rect_rotate(&r,
-					rot_info->plane[i].width * tile_width,
-					rot_info->plane[i].height * tile_height,
-					DRM_MODE_ROTATE_270);
-			x = r.x1;
-			y = r.y1;
-
-			/* rotate the tile dimensions to match the GTT view */
-			pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
-			swap(tile_width, tile_height);
-
-			/*
-			 * We only keep the x/y offsets, so push all of the
-			 * gtt offset into the x/y offsets.
-			 */
-			intel_adjust_tile_offset(&x, &y,
-						 tile_width, tile_height,
-						 tile_size, pitch_tiles,
-						 gtt_offset_rotated * tile_size, 0);
-
-			gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
-
-			/*
-			 * First pixel of the framebuffer from
-			 * the start of the rotated gtt mapping.
-			 */
-			intel_fb->rotated[i].x = x;
-			intel_fb->rotated[i].y = y;
+			gtt_offset_rotated +=
+				setup_fb_rotation(i, &plane_info,
+						  gtt_offset_rotated,
+						  x, y, width, height,
+						  tile_size,
+						  tile_width, tile_height,
+						  fb);
 		} else {
 			size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
 					    x * cpp, tile_size);
@@ -3063,6 +3097,7 @@ intel_plane_remap_gtt(struct intel_plane_state *plane_state)
 						      DRM_MODE_ROTATE_0, tile_size);
 		offset /= tile_size;
 
+		WARN_ON(i >= ARRAY_SIZE(info->plane));
 		info->plane[i].offset = offset;
 		info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
 						     tile_width * cpp);
-- 
2.22.0

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Re: [Intel-gfx] [PATCH v2 08/15] drm/i915: Skip rotated offset adjustment for unsupported modifiers

[Kahola, Mika]

On Thu, 2019-12-19 at 01:34 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> During framebuffer creation, we pre-compute offsets for 90/270 plane
> rotation. However, only Y and Yf modifiers support 90/270 rotation.
> So,
> skip the calculations for other modifiers.
> 
> To keep the gem buffer size check still working for tiled planes,
> factor
> out the logic needed for rotation setup and skip only this part for
> tiled planes other than Y/Yf.
> 
> v2: Add a bounds check WARN for the rotation info array.
> v3: Keep the gem buffer size check working for tiled planes.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 117 ++++++++++++-----
> --
>  1 file changed, 76 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3180c1817b60..9c0f22410c4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2863,12 +2863,71 @@ intel_fb_check_ccs_xy(struct drm_framebuffer
> *fb, int x, int y)
>  	return 0;
>  }
>  
> +/*
> + * Setup the rotated view for an FB plane and return the size the
> GTT mapping
> + * requires for this view.
> + */
> +static u32
> +setup_fb_rotation(int plane, const struct intel_remapped_plane_info
> *plane_info,
> +		  u32 gtt_offset_rotated, int x, int y,
> +		  unsigned int width, unsigned int height,
> +		  unsigned int tile_size,
> +		  unsigned int tile_width, unsigned int tile_height,
> +		  struct drm_framebuffer *fb)
> +{
> +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	struct intel_rotation_info *rot_info = &intel_fb->rot_info;
> +	unsigned int pitch_tiles;
> +	struct drm_rect r;
> +
> +	if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> +	    fb->modifier != I915_FORMAT_MOD_Yf_TILED)
> +		return 0;
> +
> +	if (WARN_ON(plane >= ARRAY_SIZE(rot_info->plane)))
> +		return 0;
> +
> +	rot_info->plane[plane] = *plane_info;
> +
> +	intel_fb->rotated[plane].pitch = plane_info->height *
> tile_height;
> +
> +	/* rotate the x/y offsets to match the GTT view */
> +	drm_rect_init(&r, x, y, width, height);
> +	drm_rect_rotate(&r,
> +			plane_info->width * tile_width,
> +			plane_info->height * tile_height,
> +			DRM_MODE_ROTATE_270);
> +	x = r.x1;
> +	y = r.y1;
> +
> +	/* rotate the tile dimensions to match the GTT view */
> +	pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
> +	swap(tile_width, tile_height);
> +
> +	/*
> +	 * We only keep the x/y offsets, so push all of the
> +	 * gtt offset into the x/y offsets.
> +	 */
> +	intel_adjust_tile_offset(&x, &y,
> +				 tile_width, tile_height,
> +				 tile_size, pitch_tiles,
> +				 gtt_offset_rotated * tile_size, 0);
> +
> +	/*
> +	 * First pixel of the framebuffer from
> +	 * the start of the rotated gtt mapping.
> +	 */
> +	intel_fb->rotated[plane].x = x;
> +	intel_fb->rotated[plane].y = y;
> +
> +	return plane_info->width * plane_info->height;
> +}
> +
>  static int
>  intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		   struct drm_framebuffer *fb)
>  {
>  	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> -	struct intel_rotation_info *rot_info = &intel_fb->rot_info;
>  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>  	u32 gtt_offset_rotated = 0;
>  	unsigned int max_size = 0;
> @@ -2926,23 +2985,21 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
>  						      tile_size);
>  		offset /= tile_size;
>  
> +		/* Y or Yf modifiers required for 90/270 rotation */
>  		if (!is_surface_linear(fb, i)) {
> +			struct intel_remapped_plane_info plane_info;
>  			unsigned int tile_width, tile_height;
> -			unsigned int pitch_tiles;
> -			struct drm_rect r;
>  
>  			intel_tile_dims(fb, i, &tile_width,
> &tile_height);
>  
> -			rot_info->plane[i].offset = offset;
> -			rot_info->plane[i].stride = DIV_ROUND_UP(fb-
> >pitches[i], tile_width * cpp);
> -			rot_info->plane[i].width = DIV_ROUND_UP(x +
> width, tile_width);
> -			rot_info->plane[i].height = DIV_ROUND_UP(y +
> height, tile_height);
> -
> -			intel_fb->rotated[i].pitch =
> -				rot_info->plane[i].height *
> tile_height;
> +			plane_info.offset = offset;
> +			plane_info.stride = DIV_ROUND_UP(fb-
> >pitches[i],
> +							 tile_width *
> cpp);
> +			plane_info.width = DIV_ROUND_UP(x + width,
> tile_width);
> +			plane_info.height = DIV_ROUND_UP(y + height,
> tile_height);
>  
>  			/* how many tiles does this plane need */
> -			size = rot_info->plane[i].stride * rot_info-
> >plane[i].height;
> +			size = plane_info.stride * plane_info.height;
>  			/*
>  			 * If the plane isn't horizontally tile
> aligned,
>  			 * we need one more tile.
> @@ -2950,36 +3007,13 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
>  			if (x != 0)
>  				size++;
>  
> -			/* rotate the x/y offsets to match the GTT view
> */
> -			drm_rect_init(&r, x, y, width, height);
> -			drm_rect_rotate(&r,
> -					rot_info->plane[i].width *
> tile_width,
> -					rot_info->plane[i].height *
> tile_height,
> -					DRM_MODE_ROTATE_270);
> -			x = r.x1;
> -			y = r.y1;
> -
> -			/* rotate the tile dimensions to match the GTT
> view */
> -			pitch_tiles = intel_fb->rotated[i].pitch /
> tile_height;
> -			swap(tile_width, tile_height);
> -
> -			/*
> -			 * We only keep the x/y offsets, so push all of
> the
> -			 * gtt offset into the x/y offsets.
> -			 */
> -			intel_adjust_tile_offset(&x, &y,
> -						 tile_width,
> tile_height,
> -						 tile_size,
> pitch_tiles,
> -						 gtt_offset_rotated *
> tile_size, 0);
> -
> -			gtt_offset_rotated += rot_info->plane[i].width
> * rot_info->plane[i].height;
> -
> -			/*
> -			 * First pixel of the framebuffer from
> -			 * the start of the rotated gtt mapping.
> -			 */
> -			intel_fb->rotated[i].x = x;
> -			intel_fb->rotated[i].y = y;
> +			gtt_offset_rotated +=
> +				setup_fb_rotation(i, &plane_info,
> +						  gtt_offset_rotated,
> +						  x, y, width, height,
> +						  tile_size,
> +						  tile_width,
> tile_height,
> +						  fb);
>  		} else {
>  			size = DIV_ROUND_UP((y + height) * fb-
> >pitches[i] +
>  					    x * cpp, tile_size);
> @@ -3063,6 +3097,7 @@ intel_plane_remap_gtt(struct intel_plane_state
> *plane_state)
>  						      DRM_MODE_ROTATE_0
> , tile_size);
>  		offset /= tile_size;
>  
> +		WARN_ON(i >= ARRAY_SIZE(info->plane));
>  		info->plane[i].offset = offset;
>  		info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
>  						     tile_width * cpp);
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[Intel-gfx] [PATCH 09/15] drm/i915: Make sure Y slave planes get all the required state

[Imre Deak]

Y planes program the offset and stride of the AUX plane, so make sure we
copy the required info for this into their plane state.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b4eb0d2147f5..e350f1d40b88 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12179,7 +12179,8 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 		/* Copy parameters to slave plane */
 		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
 		linked_state->color_ctl = plane_state->color_ctl;
-		linked_state->color_plane[0] = plane_state->color_plane[0];
+		memcpy(linked_state->color_plane, plane_state->color_plane,
+		       sizeof(linked_state->color_plane));
 
 		intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
 		linked_state->uapi.src = plane_state->uapi.src;
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 09/15] drm/i915: Make sure Y slave planes get all the required state

[Kahola, Mika]

On Wed, 2019-12-18 at 18:10 +0200, Imre Deak wrote:
> Y planes program the offset and stride of the AUX plane, so make sure
> we
> copy the required info for this into their plane state.
> 
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b4eb0d2147f5..e350f1d40b88 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12179,7 +12179,8 @@ static int icl_check_nv12_planes(struct
> intel_crtc_state *crtc_state)
>  		/* Copy parameters to slave plane */
>  		linked_state->ctl = plane_state->ctl |
> PLANE_CTL_YUV420_Y_PLANE;
>  		linked_state->color_ctl = plane_state->color_ctl;
> -		linked_state->color_plane[0] = plane_state-
> >color_plane[0];
> +		memcpy(linked_state->color_plane, plane_state-
> >color_plane,
> +		       sizeof(linked_state->color_plane));
>  
>  		intel_plane_copy_uapi_to_hw_state(linked_state,
> plane_state);
>  		linked_state->uapi.src = plane_state->uapi.src;
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[Intel-gfx] [PATCH 10/15] drm/i915: Make sure CCS YUV semiplanar format checks work

[Imre Deak]

For CCS formats, the current DRM core check for YUV semiplanar formats
doesn't work; use an i915 specific function for that.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 25 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_display.h  |  4 +++
 drivers/gpu/drm/i915/display/intel_sprite.c   |  8 +++---
 drivers/gpu/drm/i915/intel_pm.c               |  7 +++---
 5 files changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 9429b8e17270..3e97af682b1b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -250,7 +250,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 		new_crtc_state->active_planes |= BIT(plane->id);
 
 	if (new_plane_state->uapi.visible &&
-	    drm_format_info_is_yuv_semiplanar(fb->format))
+	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 		new_crtc_state->nv12_planes |= BIT(plane->id);
 
 	if (new_plane_state->uapi.visible &&
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e350f1d40b88..8b36c33bb63e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1985,6 +1985,14 @@ intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
 	return 1;
 }
 
+bool
+intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
+				    uint64_t modifier)
+{
+	return info->is_yuv &&
+	       info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
+}
+
 static unsigned int
 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 {
@@ -3813,7 +3821,8 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 	 * Handle the AUX surface first since
 	 * the main surface setup depends on it.
 	 */
-	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
+	if (intel_format_info_is_yuv_semiplanar(fb->format,
+					        fb->modifier)) {
 		ret = skl_check_nv12_aux_surface(plane_state);
 		if (ret)
 			return ret;
@@ -5742,7 +5751,8 @@ static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 		  unsigned int scaler_user, int *scaler_id,
 		  int src_w, int src_h, int dst_w, int dst_h,
-		  const struct drm_format_info *format, bool need_scaler)
+		  const struct drm_format_info *format,
+		  uint64_t modifier, bool need_scaler)
 {
 	struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
@@ -5796,7 +5806,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 		return 0;
 	}
 
-	if (format && drm_format_info_is_yuv_semiplanar(format) &&
+	if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
 	    (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
 		DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
 		return -EINVAL;
@@ -5848,7 +5858,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
 				 &state->scaler_state.scaler_id,
 				 state->pipe_src_w, state->pipe_src_h,
 				 adjusted_mode->crtc_hdisplay,
-				 adjusted_mode->crtc_vdisplay, NULL, need_scaler);
+				 adjusted_mode->crtc_vdisplay, NULL, 0,
+				 need_scaler);
 }
 
 /**
@@ -5873,7 +5884,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 
 	/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
 	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
-	    fb && drm_format_info_is_yuv_semiplanar(fb->format))
+	    fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 		need_scaler = true;
 
 	ret = skl_update_scaler(crtc_state, force_detach,
@@ -5883,7 +5894,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 				drm_rect_height(&plane_state->uapi.src) >> 16,
 				drm_rect_width(&plane_state->uapi.dst),
 				drm_rect_height(&plane_state->uapi.dst),
-				fb ? fb->format : NULL, need_scaler);
+				fb ? fb->format : NULL,
+				fb ? fb->modifier : 0,
+				need_scaler);
 
 	if (ret || plane_state->scaler_id < 0)
 		return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ff496cfbd4ab..0fef9263cddc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -601,6 +601,10 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv);
 void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
 				     struct intel_display_error_state *error);
 
+bool
+intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
+				    uint64_t modifier);
+
 /* modesetting */
 void intel_modeset_init_hw(struct drm_i915_private *i915);
 int intel_modeset_init(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 67a90059900f..b7f3a1b3358f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -417,7 +417,7 @@ skl_program_scaler(struct intel_plane *plane,
 				      0, INT_MAX);
 
 	/* TODO: handle sub-pixel coordinates */
-	if (drm_format_info_is_yuv_semiplanar(fb->format) &&
+	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
 	    !icl_is_hdr_plane(dev_priv, plane->id)) {
 		y_hphase = skl_scaler_calc_phase(1, hscale, false);
 		y_vphase = skl_scaler_calc_phase(1, vscale, false);
@@ -2151,7 +2151,7 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s
 	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 
 	/* Display WA #1106 */
-	if (drm_format_info_is_yuv_semiplanar(fb->format) && src_w & 3 &&
+	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && src_w & 3 &&
 	    (rotation == DRM_MODE_ROTATE_270 ||
 	     rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
 		DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n");
@@ -2171,7 +2171,7 @@ static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
 	 * FIXME need to properly check this later.
 	 */
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
-	    !drm_format_info_is_yuv_semiplanar(fb->format))
+	    !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 		return 0x30000 - 1;
 	else
 		return 0x20000 - 1;
@@ -2233,7 +2233,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
 							     plane_state);
 
-	if (drm_format_info_is_yuv_semiplanar(fb->format) &&
+	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
 	    icl_is_hdr_plane(dev_priv, plane->id))
 		/* Enable and use MPEG-2 chroma siting */
 		plane_state->cus_ctl = PLANE_CUS_ENABLE |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7cdca06be3bd..31ec82337e4f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4135,7 +4135,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 		return 0;
 
 	if (color_plane == 1 &&
-	    !drm_format_info_is_yuv_semiplanar(fb->format))
+	    !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 		return 0;
 
 	/*
@@ -4559,7 +4559,8 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 	u32 interm_pbpl;
 
 	/* only planar format has two planes */
-	if (color_plane == 1 && !drm_format_info_is_yuv_semiplanar(format)) {
+	if (color_plane == 1 &&
+	    !intel_format_info_is_yuv_semiplanar(format, modifier)) {
 		DRM_DEBUG_KMS("Non planar format have single plane\n");
 		return -EINVAL;
 	}
@@ -4571,7 +4572,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 	wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
 	wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 			 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-	wp->is_planar = drm_format_info_is_yuv_semiplanar(format);
+	wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
 
 	wp->width = width;
 	if (color_plane == 1 && wp->is_planar)
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 10/15] drm/i915: Make sure CCS YUV semiplanar format checks work

[Kahola, Mika]

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote:
> For CCS formats, the current DRM core check for YUV semiplanar
> formats
> doesn't work; use an i915 specific function for that.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

There is still one call for drm_format_info_is_yuv_semiplanar() in
intel_pm.c. For consistency reasons, maybe we could update that one too
to use i915 specific function? Anyway,

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_display.c  | 25 ++++++++++++++---
> --
>  drivers/gpu/drm/i915/display/intel_display.h  |  4 +++
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  8 +++---
>  drivers/gpu/drm/i915/intel_pm.c               |  7 +++---
>  5 files changed, 32 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 9429b8e17270..3e97af682b1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -250,7 +250,7 @@ int intel_plane_atomic_check_with_state(const
> struct intel_crtc_state *old_crtc_
>  		new_crtc_state->active_planes |= BIT(plane->id);
>  
>  	if (new_plane_state->uapi.visible &&
> -	    drm_format_info_is_yuv_semiplanar(fb->format))
> +	    intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier))
>  		new_crtc_state->nv12_planes |= BIT(plane->id);
>  
>  	if (new_plane_state->uapi.visible &&
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e350f1d40b88..8b36c33bb63e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1985,6 +1985,14 @@ intel_main_to_aux_plane(const struct
> drm_framebuffer *fb, int main_plane)
>  	return 1;
>  }
>  
> +bool
> +intel_format_info_is_yuv_semiplanar(const struct drm_format_info
> *info,
> +				    uint64_t modifier)
> +{
> +	return info->is_yuv &&
> +	       info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
> +}
> +
>  static unsigned int
>  intel_tile_width_bytes(const struct drm_framebuffer *fb, int
> color_plane)
>  {
> @@ -3813,7 +3821,8 @@ int skl_check_plane_surface(struct
> intel_plane_state *plane_state)
>  	 * Handle the AUX surface first since
>  	 * the main surface setup depends on it.
>  	 */
> -	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> +	if (intel_format_info_is_yuv_semiplanar(fb->format,
> +					        fb->modifier)) {
>  		ret = skl_check_nv12_aux_surface(plane_state);
>  		if (ret)
>  			return ret;
> @@ -5742,7 +5751,8 @@ static int
>  skl_update_scaler(struct intel_crtc_state *crtc_state, bool
> force_detach,
>  		  unsigned int scaler_user, int *scaler_id,
>  		  int src_w, int src_h, int dst_w, int dst_h,
> -		  const struct drm_format_info *format, bool
> need_scaler)
> +		  const struct drm_format_info *format,
> +		  uint64_t modifier, bool need_scaler)
>  {
>  	struct intel_crtc_scaler_state *scaler_state =
>  		&crtc_state->scaler_state;
> @@ -5796,7 +5806,7 @@ skl_update_scaler(struct intel_crtc_state
> *crtc_state, bool force_detach,
>  		return 0;
>  	}
>  
> -	if (format && drm_format_info_is_yuv_semiplanar(format) &&
> +	if (format && intel_format_info_is_yuv_semiplanar(format,
> modifier) &&
>  	    (src_h < SKL_MIN_YUV_420_SRC_H || src_w <
> SKL_MIN_YUV_420_SRC_W)) {
>  		DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
>  		return -EINVAL;
> @@ -5848,7 +5858,8 @@ int skl_update_scaler_crtc(struct
> intel_crtc_state *state)
>  				 &state->scaler_state.scaler_id,
>  				 state->pipe_src_w, state->pipe_src_h,
>  				 adjusted_mode->crtc_hdisplay,
> -				 adjusted_mode->crtc_vdisplay, NULL,
> need_scaler);
> +				 adjusted_mode->crtc_vdisplay, NULL, 0,
> +				 need_scaler);
>  }
>  
>  /**
> @@ -5873,7 +5884,7 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
>  
>  	/* Pre-gen11 and SDR planes always need a scaler for planar
> formats. */
>  	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
> -	    fb && drm_format_info_is_yuv_semiplanar(fb->format))
> +	    fb && intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier))
>  		need_scaler = true;
>  
>  	ret = skl_update_scaler(crtc_state, force_detach,
> @@ -5883,7 +5894,9 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
>  				drm_rect_height(&plane_state->uapi.src) 
> >> 16,
>  				drm_rect_width(&plane_state->uapi.dst),
>  				drm_rect_height(&plane_state-
> >uapi.dst),
> -				fb ? fb->format : NULL, need_scaler);
> +				fb ? fb->format : NULL,
> +				fb ? fb->modifier : 0,
> +				need_scaler);
>  
>  	if (ret || plane_state->scaler_id < 0)
>  		return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index ff496cfbd4ab..0fef9263cddc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -601,6 +601,10 @@ intel_display_capture_error_state(struct
> drm_i915_private *dev_priv);
>  void intel_display_print_error_state(struct drm_i915_error_state_buf
> *e,
>  				     struct intel_display_error_state
> *error);
>  
> +bool
> +intel_format_info_is_yuv_semiplanar(const struct drm_format_info
> *info,
> +				    uint64_t modifier);
> +
>  /* modesetting */
>  void intel_modeset_init_hw(struct drm_i915_private *i915);
>  int intel_modeset_init(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 67a90059900f..b7f3a1b3358f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -417,7 +417,7 @@ skl_program_scaler(struct intel_plane *plane,
>  				      0, INT_MAX);
>  
>  	/* TODO: handle sub-pixel coordinates */
> -	if (drm_format_info_is_yuv_semiplanar(fb->format) &&
> +	if (intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier) &&
>  	    !icl_is_hdr_plane(dev_priv, plane->id)) {
>  		y_hphase = skl_scaler_calc_phase(1, hscale, false);
>  		y_vphase = skl_scaler_calc_phase(1, vscale, false);
> @@ -2151,7 +2151,7 @@ static int skl_plane_check_nv12_rotation(const
> struct intel_plane_state *plane_s
>  	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
>  
>  	/* Display WA #1106 */
> -	if (drm_format_info_is_yuv_semiplanar(fb->format) && src_w & 3
> &&
> +	if (intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier) && src_w & 3 &&
>  	    (rotation == DRM_MODE_ROTATE_270 ||
>  	     rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
>  		DRM_DEBUG_KMS("src width must be multiple of 4 for
> rotated planar YUV\n");
> @@ -2171,7 +2171,7 @@ static int skl_plane_max_scale(struct
> drm_i915_private *dev_priv,
>  	 * FIXME need to properly check this later.
>  	 */
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
> -	    !drm_format_info_is_yuv_semiplanar(fb->format))
> +	    !intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier))
>  		return 0x30000 - 1;
>  	else
>  		return 0x20000 - 1;
> @@ -2233,7 +2233,7 @@ static int skl_plane_check(struct
> intel_crtc_state *crtc_state,
>  		plane_state->color_ctl =
> glk_plane_color_ctl(crtc_state,
>  							     plane_stat
> e);
>  
> -	if (drm_format_info_is_yuv_semiplanar(fb->format) &&
> +	if (intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier) &&
>  	    icl_is_hdr_plane(dev_priv, plane->id))
>  		/* Enable and use MPEG-2 chroma siting */
>  		plane_state->cus_ctl = PLANE_CUS_ENABLE |
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 7cdca06be3bd..31ec82337e4f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4135,7 +4135,7 @@ skl_plane_relative_data_rate(const struct
> intel_crtc_state *crtc_state,
>  		return 0;
>  
>  	if (color_plane == 1 &&
> -	    !drm_format_info_is_yuv_semiplanar(fb->format))
> +	    !intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier))
>  		return 0;
>  
>  	/*
> @@ -4559,7 +4559,8 @@ skl_compute_wm_params(const struct
> intel_crtc_state *crtc_state,
>  	u32 interm_pbpl;
>  
>  	/* only planar format has two planes */
> -	if (color_plane == 1 &&
> !drm_format_info_is_yuv_semiplanar(format)) {
> +	if (color_plane == 1 &&
> +	    !intel_format_info_is_yuv_semiplanar(format, modifier)) {
>  		DRM_DEBUG_KMS("Non planar format have single plane\n");
>  		return -EINVAL;
>  	}
> @@ -4571,7 +4572,7 @@ skl_compute_wm_params(const struct
> intel_crtc_state *crtc_state,
>  	wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
>  	wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  			 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> -	wp->is_planar = drm_format_info_is_yuv_semiplanar(format);
> +	wp->is_planar = intel_format_info_is_yuv_semiplanar(format,
> modifier);
>  
>  	wp->width = width;
>  	if (color_plane == 1 && wp->is_planar)
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Re: [Intel-gfx] [PATCH 10/15] drm/i915: Make sure CCS YUV semiplanar format checks work

[Imre Deak]

On Thu, Dec 19, 2019 at 04:14:48PM +0200, Kahola, Mika wrote:
> On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote:
> > For CCS formats, the current DRM core check for YUV semiplanar
> > formats
> > doesn't work; use an i915 specific function for that.
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> 
> There is still one call for drm_format_info_is_yuv_semiplanar() in
> intel_pm.c. For consistency reasons, maybe we could update that one too
> to use i915 specific function? Anyway,

Yes, that one is called up to GEN9, where the modifier doesn't change
the layout of any YUV framebuffers (since compression for YUV is only
supported on GEN12+). We don't have the read out modifier HW state here
either so I decided to keep using drm_format_info_is_yuv_semiplanar() at
this point.

The consistent way would be to fix drm_format_info_is_yuv_semiplanar(),
probably by adding a new yuv_semiplanar flag to drm_format_info struct,
but I left that for later.

> 
> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> 
> > ---
> >  .../gpu/drm/i915/display/intel_atomic_plane.c |  2 +-
> >  drivers/gpu/drm/i915/display/intel_display.c  | 25 ++++++++++++++---
> > --
> >  drivers/gpu/drm/i915/display/intel_display.h  |  4 +++
> >  drivers/gpu/drm/i915/display/intel_sprite.c   |  8 +++---
> >  drivers/gpu/drm/i915/intel_pm.c               |  7 +++---
> >  5 files changed, 32 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index 9429b8e17270..3e97af682b1b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -250,7 +250,7 @@ int intel_plane_atomic_check_with_state(const
> > struct intel_crtc_state *old_crtc_
> >  		new_crtc_state->active_planes |= BIT(plane->id);
> >  
> >  	if (new_plane_state->uapi.visible &&
> > -	    drm_format_info_is_yuv_semiplanar(fb->format))
> > +	    intel_format_info_is_yuv_semiplanar(fb->format, fb-
> > >modifier))
> >  		new_crtc_state->nv12_planes |= BIT(plane->id);
> >  
> >  	if (new_plane_state->uapi.visible &&
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index e350f1d40b88..8b36c33bb63e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1985,6 +1985,14 @@ intel_main_to_aux_plane(const struct
> > drm_framebuffer *fb, int main_plane)
> >  	return 1;
> >  }
> >  
> > +bool
> > +intel_format_info_is_yuv_semiplanar(const struct drm_format_info
> > *info,
> > +				    uint64_t modifier)
> > +{
> > +	return info->is_yuv &&
> > +	       info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
> > +}
> > +
> >  static unsigned int
> >  intel_tile_width_bytes(const struct drm_framebuffer *fb, int
> > color_plane)
> >  {
> > @@ -3813,7 +3821,8 @@ int skl_check_plane_surface(struct
> > intel_plane_state *plane_state)
> >  	 * Handle the AUX surface first since
> >  	 * the main surface setup depends on it.
> >  	 */
> > -	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> > +	if (intel_format_info_is_yuv_semiplanar(fb->format,
> > +					        fb->modifier)) {
> >  		ret = skl_check_nv12_aux_surface(plane_state);
> >  		if (ret)
> >  			return ret;
> > @@ -5742,7 +5751,8 @@ static int
> >  skl_update_scaler(struct intel_crtc_state *crtc_state, bool
> > force_detach,
> >  		  unsigned int scaler_user, int *scaler_id,
> >  		  int src_w, int src_h, int dst_w, int dst_h,
> > -		  const struct drm_format_info *format, bool
> > need_scaler)
> > +		  const struct drm_format_info *format,
> > +		  uint64_t modifier, bool need_scaler)
> >  {
> >  	struct intel_crtc_scaler_state *scaler_state =
> >  		&crtc_state->scaler_state;
> > @@ -5796,7 +5806,7 @@ skl_update_scaler(struct intel_crtc_state
> > *crtc_state, bool force_detach,
> >  		return 0;
> >  	}
> >  
> > -	if (format && drm_format_info_is_yuv_semiplanar(format) &&
> > +	if (format && intel_format_info_is_yuv_semiplanar(format,
> > modifier) &&
> >  	    (src_h < SKL_MIN_YUV_420_SRC_H || src_w <
> > SKL_MIN_YUV_420_SRC_W)) {
> >  		DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
> >  		return -EINVAL;
> > @@ -5848,7 +5858,8 @@ int skl_update_scaler_crtc(struct
> > intel_crtc_state *state)
> >  				 &state->scaler_state.scaler_id,
> >  				 state->pipe_src_w, state->pipe_src_h,
> >  				 adjusted_mode->crtc_hdisplay,
> > -				 adjusted_mode->crtc_vdisplay, NULL,
> > need_scaler);
> > +				 adjusted_mode->crtc_vdisplay, NULL, 0,
> > +				 need_scaler);
> >  }
> >  
> >  /**
> > @@ -5873,7 +5884,7 @@ static int skl_update_scaler_plane(struct
> > intel_crtc_state *crtc_state,
> >  
> >  	/* Pre-gen11 and SDR planes always need a scaler for planar
> > formats. */
> >  	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
> > -	    fb && drm_format_info_is_yuv_semiplanar(fb->format))
> > +	    fb && intel_format_info_is_yuv_semiplanar(fb->format, fb-
> > >modifier))
> >  		need_scaler = true;
> >  
> >  	ret = skl_update_scaler(crtc_state, force_detach,
> > @@ -5883,7 +5894,9 @@ static int skl_update_scaler_plane(struct
> > intel_crtc_state *crtc_state,
> >  				drm_rect_height(&plane_state->uapi.src) 
> > >> 16,
> >  				drm_rect_width(&plane_state->uapi.dst),
> >  				drm_rect_height(&plane_state-
> > >uapi.dst),
> > -				fb ? fb->format : NULL, need_scaler);
> > +				fb ? fb->format : NULL,
> > +				fb ? fb->modifier : 0,
> > +				need_scaler);
> >  
> >  	if (ret || plane_state->scaler_id < 0)
> >  		return ret;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > b/drivers/gpu/drm/i915/display/intel_display.h
> > index ff496cfbd4ab..0fef9263cddc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -601,6 +601,10 @@ intel_display_capture_error_state(struct
> > drm_i915_private *dev_priv);
> >  void intel_display_print_error_state(struct drm_i915_error_state_buf
> > *e,
> >  				     struct intel_display_error_state
> > *error);
> >  
> > +bool
> > +intel_format_info_is_yuv_semiplanar(const struct drm_format_info
> > *info,
> > +				    uint64_t modifier);
> > +
> >  /* modesetting */
> >  void intel_modeset_init_hw(struct drm_i915_private *i915);
> >  int intel_modeset_init(struct drm_i915_private *i915);
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 67a90059900f..b7f3a1b3358f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -417,7 +417,7 @@ skl_program_scaler(struct intel_plane *plane,
> >  				      0, INT_MAX);
> >  
> >  	/* TODO: handle sub-pixel coordinates */
> > -	if (drm_format_info_is_yuv_semiplanar(fb->format) &&
> > +	if (intel_format_info_is_yuv_semiplanar(fb->format, fb-
> > >modifier) &&
> >  	    !icl_is_hdr_plane(dev_priv, plane->id)) {
> >  		y_hphase = skl_scaler_calc_phase(1, hscale, false);
> >  		y_vphase = skl_scaler_calc_phase(1, vscale, false);
> > @@ -2151,7 +2151,7 @@ static int skl_plane_check_nv12_rotation(const
> > struct intel_plane_state *plane_s
> >  	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> >  
> >  	/* Display WA #1106 */
> > -	if (drm_format_info_is_yuv_semiplanar(fb->format) && src_w & 3
> > &&
> > +	if (intel_format_info_is_yuv_semiplanar(fb->format, fb-
> > >modifier) && src_w & 3 &&
> >  	    (rotation == DRM_MODE_ROTATE_270 ||
> >  	     rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
> >  		DRM_DEBUG_KMS("src width must be multiple of 4 for
> > rotated planar YUV\n");
> > @@ -2171,7 +2171,7 @@ static int skl_plane_max_scale(struct
> > drm_i915_private *dev_priv,
> >  	 * FIXME need to properly check this later.
> >  	 */
> >  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
> > -	    !drm_format_info_is_yuv_semiplanar(fb->format))
> > +	    !intel_format_info_is_yuv_semiplanar(fb->format, fb-
> > >modifier))
> >  		return 0x30000 - 1;
> >  	else
> >  		return 0x20000 - 1;
> > @@ -2233,7 +2233,7 @@ static int skl_plane_check(struct
> > intel_crtc_state *crtc_state,
> >  		plane_state->color_ctl =
> > glk_plane_color_ctl(crtc_state,
> >  							     plane_stat
> > e);
> >  
> > -	if (drm_format_info_is_yuv_semiplanar(fb->format) &&
> > +	if (intel_format_info_is_yuv_semiplanar(fb->format, fb-
> > >modifier) &&
> >  	    icl_is_hdr_plane(dev_priv, plane->id))
> >  		/* Enable and use MPEG-2 chroma siting */
> >  		plane_state->cus_ctl = PLANE_CUS_ENABLE |
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 7cdca06be3bd..31ec82337e4f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4135,7 +4135,7 @@ skl_plane_relative_data_rate(const struct
> > intel_crtc_state *crtc_state,
> >  		return 0;
> >  
> >  	if (color_plane == 1 &&
> > -	    !drm_format_info_is_yuv_semiplanar(fb->format))
> > +	    !intel_format_info_is_yuv_semiplanar(fb->format, fb-
> > >modifier))
> >  		return 0;
> >  
> >  	/*
> > @@ -4559,7 +4559,8 @@ skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> >  	u32 interm_pbpl;
> >  
> >  	/* only planar format has two planes */
> > -	if (color_plane == 1 &&
> > !drm_format_info_is_yuv_semiplanar(format)) {
> > +	if (color_plane == 1 &&
> > +	    !intel_format_info_is_yuv_semiplanar(format, modifier)) {
> >  		DRM_DEBUG_KMS("Non planar format have single plane\n");
> >  		return -EINVAL;
> >  	}
> > @@ -4571,7 +4572,7 @@ skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> >  	wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
> >  	wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  			 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > -	wp->is_planar = drm_format_info_is_yuv_semiplanar(format);
> > +	wp->is_planar = intel_format_info_is_yuv_semiplanar(format,
> > modifier);
> >  
> >  	wp->width = width;
> >  	if (color_plane == 1 && wp->is_planar)
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[Intel-gfx] [PATCH 11/15] drm/framebuffer: Format modifier for Intel Gen-12 media compression

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

v2: Update code comment describing the color plane order for YUV
    semiplanar formats.

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..8bc0b31597d8 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 11/15] drm/framebuffer: Format modifier for Intel Gen-12 media compression

[Kahola, Mika]

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Gen-12 display can decompress surfaces compressed by the media
> engine, add
> a new modifier as the driver needs to know the surface was compressed
> by
> the media or render engine.
> 
> v2: Update code comment describing the color plane order for YUV
>     semiplanar formats.
> 
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h
> index 5ba481f49931..8bc0b31597d8 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -421,6 +421,19 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL,
> 6)
>  
> +/*
> + * Intel color control surfaces (CCS) for Gen-12 media compression
> + *
> + * The main surface is Y-tiled and at plane index 0, the CCS is
> linear and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1
> tiles in
> + * main surface. In other words, 4 bits in CCS map to a main surface
> cache
> + * line pair. The main surface pitch is required to be a multiple of
> four
> + * Y-tile widths. For semi-planar formats like NV12, CCS planes
> follow the
> + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV
> surfaces,
> + * planes 2 and 3 for the respective CCS.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL,
> 7)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized
> macroblocks
>   *
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[PATCH 11/15] drm/framebuffer: Format modifier for Intel Gen-12 media compression

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

v2: Update code comment describing the color plane order for YUV
    semiplanar formats.

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..8bc0b31597d8 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.22.0

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[Intel-gfx] [PATCH 11/15] drm/framebuffer: Format modifier for Intel Gen-12 media compression

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

v2: Update code comment describing the color plane order for YUV
    semiplanar formats.

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..8bc0b31597d8 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.22.0

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[Intel-gfx] [PATCH 12/15] drm/fb: Extend format_info member arrays to handle four planes

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 include/drm/drm_fourcc.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
 		 * triplet @char_per_block, @block_w, @block_h for better
 		 * describing the pixel format.
 		 */
-		u8 cpp[3];
+		u8 cpp[4];
 
 		/**
 		 * @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
 		 * information from their drm_mode_config.get_format_info hook
 		 * if they want the core to be validating the pitch.
 		 */
-		u8 char_per_block[3];
+		u8 char_per_block[4];
 	};
 
 	/**
@@ -113,7 +113,7 @@ struct drm_format_info {
 	 * Block width in pixels, this is intended to be accessed through
 	 * drm_format_info_block_width()
 	 */
-	u8 block_w[3];
+	u8 block_w[4];
 
 	/**
 	 * @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
 	 * Block height in pixels, this is intended to be accessed through
 	 * drm_format_info_block_height()
 	 */
-	u8 block_h[3];
+	u8 block_h[4];
 
 	/** @hsub: Horizontal chroma subsampling factor */
 	u8 hsub;
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 12/15] drm/fb: Extend format_info member arrays to handle four planes

[Kahola, Mika]

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> addfb() uAPI has supported four planes for a while now, make
> format_info
> compatible with that.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  include/drm/drm_fourcc.h | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
> index 306d1efeb5e0..156b122c0ad5 100644
> --- a/include/drm/drm_fourcc.h
> +++ b/include/drm/drm_fourcc.h
> @@ -78,7 +78,7 @@ struct drm_format_info {
>  		 * triplet @char_per_block, @block_w, @block_h for
> better
>  		 * describing the pixel format.
>  		 */
> -		u8 cpp[3];
> +		u8 cpp[4];
>  
>  		/**
>  		 * @char_per_block:
> @@ -104,7 +104,7 @@ struct drm_format_info {
>  		 * information from their
> drm_mode_config.get_format_info hook
>  		 * if they want the core to be validating the pitch.
>  		 */
> -		u8 char_per_block[3];
> +		u8 char_per_block[4];
>  	};
>  
>  	/**
> @@ -113,7 +113,7 @@ struct drm_format_info {
>  	 * Block width in pixels, this is intended to be accessed
> through
>  	 * drm_format_info_block_width()
>  	 */
> -	u8 block_w[3];
> +	u8 block_w[4];
>  
>  	/**
>  	 * @block_h:
> @@ -121,7 +121,7 @@ struct drm_format_info {
>  	 * Block height in pixels, this is intended to be accessed
> through
>  	 * drm_format_info_block_height()
>  	 */
> -	u8 block_h[3];
> +	u8 block_h[4];
>  
>  	/** @hsub: Horizontal chroma subsampling factor */
>  	u8 hsub;
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[PATCH 12/15] drm/fb: Extend format_info member arrays to handle four planes

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 include/drm/drm_fourcc.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
 		 * triplet @char_per_block, @block_w, @block_h for better
 		 * describing the pixel format.
 		 */
-		u8 cpp[3];
+		u8 cpp[4];
 
 		/**
 		 * @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
 		 * information from their drm_mode_config.get_format_info hook
 		 * if they want the core to be validating the pitch.
 		 */
-		u8 char_per_block[3];
+		u8 char_per_block[4];
 	};
 
 	/**
@@ -113,7 +113,7 @@ struct drm_format_info {
 	 * Block width in pixels, this is intended to be accessed through
 	 * drm_format_info_block_width()
 	 */
-	u8 block_w[3];
+	u8 block_w[4];
 
 	/**
 	 * @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
 	 * Block height in pixels, this is intended to be accessed through
 	 * drm_format_info_block_height()
 	 */
-	u8 block_h[3];
+	u8 block_h[4];
 
 	/** @hsub: Horizontal chroma subsampling factor */
 	u8 hsub;
-- 
2.22.0

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[Intel-gfx] [PATCH 12/15] drm/fb: Extend format_info member arrays to handle four planes

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 include/drm/drm_fourcc.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
 		 * triplet @char_per_block, @block_w, @block_h for better
 		 * describing the pixel format.
 		 */
-		u8 cpp[3];
+		u8 cpp[4];
 
 		/**
 		 * @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
 		 * information from their drm_mode_config.get_format_info hook
 		 * if they want the core to be validating the pitch.
 		 */
-		u8 char_per_block[3];
+		u8 char_per_block[4];
 	};
 
 	/**
@@ -113,7 +113,7 @@ struct drm_format_info {
 	 * Block width in pixels, this is intended to be accessed through
 	 * drm_format_info_block_width()
 	 */
-	u8 block_w[3];
+	u8 block_w[4];
 
 	/**
 	 * @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
 	 * Block height in pixels, this is intended to be accessed through
 	 * drm_format_info_block_height()
 	 */
-	u8 block_h[3];
+	u8 block_h[4];
 
 	/** @hsub: Horizontal chroma subsampling factor */
 	u8 hsub;
-- 
2.22.0

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[Intel-gfx] [PATCH 13/15] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not
support media decompression.

v2: Fix checkpatch warnings on code style (Lucas)

From DK:
Separate modifier array for planes that cannot decompress media (Ville)

v3: Support planar formats
v4: Switch plane order
v5:
- Use format block descriptors to get CCS subsampling calculation right
  everywhere.
- Extend the plane state normal view array to accommodate 4 color planes.
- Use helpers to convert between main and CCS planes.

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 180 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_display.h  |   1 +
 .../drm/i915/display/intel_display_types.h    |   6 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  55 ++++--
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 5 files changed, 188 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8b36c33bb63e..1c2becf47bfd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1943,7 +1943,9 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
 
 static bool is_gen12_ccs_modifier(u64 modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+
 }
 
 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
@@ -1976,8 +1978,7 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
 }
 
 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
-static int
-intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
+int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
 {
 	if (is_ccs_modifier(fb->modifier))
 		return main_to_ccs_plane(fb, main_plane);
@@ -2012,6 +2013,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 			return 128;
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		if (is_ccs_plane(fb, color_plane))
 			return 64;
 		/* fall through */
@@ -2152,6 +2154,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 			return 256 * 1024;
 		return 0;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2536,6 +2539,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2587,6 +2591,21 @@ static const struct drm_format_info gen12_ccs_formats[] = {
 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 	  .hsub = 1, .vsub = 1, .has_alpha = true },
+	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
+	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 2, .vsub = 1, .is_yuv = true },
+	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
+	  .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
+	  .hsub = 2, .vsub = 2, .is_yuv = true },
+	{ .format = DRM_FORMAT_P010, .num_planes = 4,
+	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+	  .hsub = 2, .vsub = 2, .is_yuv = true },
+	{ .format = DRM_FORMAT_P012, .num_planes = 4,
+	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+	  .hsub = 2, .vsub = 2, .is_yuv = true },
+	{ .format = DRM_FORMAT_P016, .num_planes = 4,
+	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+	  .hsub = 2, .vsub = 2, .is_yuv = true },
 };
 
 static const struct drm_format_info *
@@ -2613,6 +2632,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 					  ARRAY_SIZE(skl_ccs_formats),
 					  cmd->pixel_format);
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return lookup_format_info(gen12_ccs_formats,
 					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
@@ -2624,6 +2644,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 bool is_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
@@ -2695,7 +2716,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 	}
 
 	tile_width = intel_tile_width_bytes(fb, color_plane);
-	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+	if (is_ccs_modifier(fb->modifier)) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2705,7 +2726,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
 			tile_width *= 4;
 		/*
 		 * The main surface pitch must be padded to a multiple of four
@@ -2827,8 +2848,19 @@ intel_fb_plane_get_subsampling(int *hsub, int *vsub,
 
 	*vsub = 32;
 }
+
+static void
+intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
+{
+	int hsub, vsub;
+
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+	*w = fb->width / hsub;
+	*h = fb->height / vsub;
+}
+
 static int
-intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	int main_plane;
@@ -2836,7 +2868,6 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
 	int tile_width, tile_height;
 	int ccs_x, ccs_y;
 	int main_x, main_y;
-	int ccs_plane = 1;
 
 	if (!is_ccs_plane(fb, ccs_plane))
 		return 0;
@@ -2891,8 +2922,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		int ret;
 
 		cpp = fb->format->cpp[i];
-		width = drm_framebuffer_plane_width(fb->width, fb, i);
-		height = drm_framebuffer_plane_height(fb->height, fb, i);
+		intel_fb_plane_dims(&width, &height, fb, i);
 
 		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
 		if (ret) {
@@ -2901,7 +2931,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			return ret;
 		}
 
-		ret = intel_fb_check_ccs_xy(fb, x, y);
+		ret = intel_fb_check_ccs_xy(fb, i, x, y);
 		if (ret)
 			return ret;
 
@@ -3555,6 +3585,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
 			return 5120;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		/* FIXME AUX plane? */
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
@@ -3614,10 +3645,10 @@ static int icl_max_plane_height(void)
 }
 
 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
-					   int main_x, int main_y, u32 main_offset)
+					   int main_x, int main_y, u32 main_offset,
+					   int ccs_plane)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	int ccs_plane = main_to_ccs_plane(fb, 0);
 	int aux_x = plane_state->color_plane[ccs_plane].x;
 	int aux_y = plane_state->color_plane[ccs_plane].y;
 	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
@@ -3723,7 +3754,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	 * they match with the main surface x/y offsets.
 	 */
 	if (is_ccs_modifier(fb->modifier)) {
-		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset,
+						       aux_plane)) {
 			if (offset == 0)
 				break;
 
@@ -3756,7 +3788,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
-	int max_width = skl_max_plane_width(fb, 1, rotation);
+	int uv_plane = 1;
+	int max_width = skl_max_plane_width(fb, uv_plane, rotation);
 	int max_height = 4096;
 	int x = plane_state->uapi.src.x1 >> 17;
 	int y = plane_state->uapi.src.y1 >> 17;
@@ -3764,8 +3797,9 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 	int h = drm_rect_height(&plane_state->uapi.src) >> 17;
 	u32 offset;
 
-	intel_add_fb_offsets(&x, &y, plane_state, 1);
-	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+	intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
+	offset = intel_plane_compute_aligned_offset(&x, &y,
+						    plane_state, uv_plane);
 
 	/* FIXME not quite sure how/if these apply to the chroma plane */
 	if (w > max_width || h > max_height) {
@@ -3774,9 +3808,39 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 		return -EINVAL;
 	}
 
-	plane_state->color_plane[1].offset = offset;
-	plane_state->color_plane[1].x = x;
-	plane_state->color_plane[1].y = y;
+	if (is_ccs_modifier(fb->modifier)) {
+		int ccs_plane = main_to_ccs_plane(fb, uv_plane);
+		int aux_offset = plane_state->color_plane[ccs_plane].offset;
+		int alignment = intel_surf_alignment(fb, uv_plane);
+
+		if (offset > aux_offset)
+			offset = intel_plane_adjust_aligned_offset(&x, &y,
+								   plane_state,
+								   uv_plane,
+								   offset,
+								   aux_offset & ~(alignment - 1));
+
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
+						       offset, ccs_plane)) {
+			if (offset == 0)
+				break;
+
+			offset = intel_plane_adjust_aligned_offset(&x, &y,
+								   plane_state,
+								   uv_plane,
+								   offset, offset - alignment);
+		}
+
+		if (x != plane_state->color_plane[ccs_plane].x ||
+		    y != plane_state->color_plane[ccs_plane].y) {
+			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
+			return -EINVAL;
+		}
+	}
+
+	plane_state->color_plane[uv_plane].offset = offset;
+	plane_state->color_plane[uv_plane].x = x;
+	plane_state->color_plane[uv_plane].y = y;
 
 	return 0;
 }
@@ -3786,21 +3850,40 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int src_x = plane_state->uapi.src.x1 >> 16;
 	int src_y = plane_state->uapi.src.y1 >> 16;
-	int hsub;
-	int vsub;
-	int x;
-	int y;
 	u32 offset;
+	int ccs_plane;
 
-	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
-	x = src_x / hsub;
-	y = src_y / vsub;
-	intel_add_fb_offsets(&x, &y, plane_state, 1);
-	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+	for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
+		int main_hsub, main_vsub;
+		int hsub, vsub;
+		int x, y;
+
+		if (!is_ccs_plane(fb, ccs_plane))
+			continue;
+
+		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
+					       ccs_to_main_plane(fb, ccs_plane));
+		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
+
+		hsub *= main_hsub;
+		vsub *= main_vsub;
+		x = src_x / hsub;
+		y = src_y / vsub;
 
-	plane_state->color_plane[1].offset = offset;
-	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
-	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
+		intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
+
+		offset = intel_plane_compute_aligned_offset(&x, &y,
+							    plane_state,
+							    ccs_plane);
+
+		plane_state->color_plane[ccs_plane].offset = offset;
+		plane_state->color_plane[ccs_plane].x = (x * hsub +
+							 src_x % hsub) /
+							main_hsub;
+		plane_state->color_plane[ccs_plane].y = (y * vsub +
+							 src_y % vsub) /
+							main_vsub;
+	}
 
 	return 0;
 }
@@ -3809,6 +3892,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int ret;
+	bool needs_aux = false;
 
 	ret = intel_plane_compute_gtt(plane_state);
 	if (ret)
@@ -3818,22 +3902,32 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 		return 0;
 
 	/*
-	 * Handle the AUX surface first since
-	 * the main surface setup depends on it.
+	 * Handle the AUX surface first since the main surface setup depends on
+	 * it.
 	 */
+	if (is_ccs_modifier(fb->modifier)) {
+		needs_aux = true;
+		ret = skl_check_ccs_aux_surface(plane_state);
+		if (ret)
+			return ret;
+	}
+
 	if (intel_format_info_is_yuv_semiplanar(fb->format,
 					        fb->modifier)) {
+		needs_aux = true;
 		ret = skl_check_nv12_aux_surface(plane_state);
 		if (ret)
 			return ret;
-	} else if (is_ccs_modifier(fb->modifier)) {
-		ret = skl_check_ccs_aux_surface(plane_state);
-		if (ret)
-			return ret;
-	} else {
-		plane_state->color_plane[1].offset = ~0xfff;
-		plane_state->color_plane[1].x = 0;
-		plane_state->color_plane[1].y = 0;
+	}
+
+	if (!needs_aux) {
+		int i;
+
+		for (i = 1; i < fb->format->num_planes; i++) {
+			plane_state->color_plane[i].offset = ~0xfff;
+			plane_state->color_plane[i].x = 0;
+			plane_state->color_plane[i].y = 0;
+		}
 	}
 
 	ret = skl_check_main_surface(plane_state);
@@ -4423,6 +4517,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y |
 		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 		       PLANE_CTL_CLEAR_COLOR_DISABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -10165,6 +10261,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
 				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
 				I915_FORMAT_MOD_Y_TILED_CCS;
+		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 0fef9263cddc..b8112340773b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -474,6 +474,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    struct intel_link_m_n *m_n,
 			    bool constant_n, bool fec_enable);
 bool is_ccs_modifier(u64 modifier);
+int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane);
 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..3cdf44fa4164 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -90,8 +90,8 @@ struct intel_framebuffer {
 	/* for each plane in the normal GTT view */
 	struct {
 		unsigned int x, y;
-	} normal[2];
-	/* for each plane in the rotated GTT view */
+	} normal[4];
+	/* for each plane in the rotated GTT view for no-CCS formats */
 	struct {
 		unsigned int x, y;
 		unsigned int pitch; /* pixels */
@@ -555,7 +555,7 @@ struct intel_plane_state {
 		 */
 		u32 stride;
 		int x, y;
-	} color_plane[2];
+	} color_plane[4];
 
 	/* plane control register */
 	u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7f3a1b3358f..be56b6f56411 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -583,15 +583,16 @@ skl_program_plane(struct intel_plane *plane,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
-	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
-	u32 aux_stride = skl_plane_stride(plane_state, 1);
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	int aux_plane = intel_main_to_aux_plane(fb, color_plane);
+	u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
+	u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
 	int crtc_x = plane_state->uapi.dst.x1;
 	int crtc_y = plane_state->uapi.dst.y1;
 	u32 x = plane_state->color_plane[color_plane].x;
 	u32 y = plane_state->color_plane[color_plane].y;
 	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
-	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	u8 alpha = plane_state->hw.alpha >> 8;
 	u32 plane_color_ctl = 0;
 	unsigned long irqflags;
@@ -2106,7 +2107,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2577,7 +2579,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_ccs[] = {
+static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED,
+	I915_FORMAT_MOD_X_TILED,
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
+static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
@@ -2742,10 +2753,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	}
 }
 
+static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
+{
+	return plane_id < PLANE_SPRITE4;
+}
+
 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 					     u32 format, u64 modifier)
 {
+	struct intel_plane *plane = to_intel_plane(_plane);
+
 	switch (modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		if (!gen12_plane_supports_mc_ccs(plane->id))
+			return false;
+		/* fall through */
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2763,11 +2785,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (is_ccs_modifier(modifier))
 			return true;
 		/* fall through */
-	case DRM_FORMAT_RGB565:
-	case DRM_FORMAT_XRGB2101010:
-	case DRM_FORMAT_XBGR2101010:
-	case DRM_FORMAT_ARGB2101010:
-	case DRM_FORMAT_ABGR2101010:
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
@@ -2776,6 +2793,14 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_P010:
 	case DRM_FORMAT_P012:
 	case DRM_FORMAT_P016:
+		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+			return true;
+		/* fall through */
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_XBGR2101010:
+	case DRM_FORMAT_ARGB2101010:
+	case DRM_FORMAT_ABGR2101010:
 	case DRM_FORMAT_XVYU2101010:
 	case DRM_FORMAT_C8:
 	case DRM_FORMAT_XBGR16161616F:
@@ -2909,6 +2934,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
 	}
 }
 
+static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
+{
+	if (gen12_plane_supports_mc_ccs(plane_id))
+		return gen12_plane_format_modifiers_mc_ccs;
+	else
+		return gen12_plane_format_modifiers_rc_ccs;
+}
+
 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, enum plane_id plane_id)
 {
@@ -2974,7 +3007,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 
 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		modifiers = gen12_plane_format_modifiers_ccs;
+		modifiers = gen12_get_plane_modifiers(plane_id);
 		plane_funcs = &gen12_plane_funcs;
 	} else {
 		if (plane->has_ccs)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bbfedeb00b7f..b6dc735e85e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6808,6 +6808,7 @@ enum {
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
+#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
-- 
2.22.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 13/15] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine

[Sripada, Radhakrishna]

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Detect the modifier corresponding to media compression to enable
> display decompression for YUV and xRGB packed formats. A new modifier
> is
> added so that the driver can distinguish between media and render
> compressed buffers. Unlike render decompression, plane 6 and  plane 7
> do not
> support media decompression.
> 
> v2: Fix checkpatch warnings on code style (Lucas)
> 
> From DK:
> Separate modifier array for planes that cannot decompress media
> (Ville)
> 
> v3: Support planar formats
> v4: Switch plane order
> v5:
> - Use format block descriptors to get CCS subsampling calculation
> right
>   everywhere.
> - Extend the plane state normal view array to accommodate 4 color
> planes.
> - Use helpers to convert between main and CCS planes.
> 
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 180 ++++++++++++++
> ----
>  drivers/gpu/drm/i915/display/intel_display.h  |   1 +
>  .../drm/i915/display/intel_display_types.h    |   6 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  55 ++++--
>  drivers/gpu/drm/i915/i915_reg.h               |   1 +
>  5 files changed, 188 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8b36c33bb63e..1c2becf47bfd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1943,7 +1943,9 @@ static bool is_ccs_plane(const struct
> drm_framebuffer *fb, int plane)
>  
>  static bool is_gen12_ccs_modifier(u64 modifier)
>  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> +
>  }
>  
>  static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int
> plane)
> @@ -1976,8 +1978,7 @@ static int ccs_to_main_plane(const struct
> drm_framebuffer *fb, int ccs_plane)
>  }
>  
>  /* Return either the main plane's CCS or - if not a CCS FB - UV
> plane */
> -static int
> -intel_main_to_aux_plane(const struct drm_framebuffer *fb, int
> main_plane)
> +int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int
> main_plane)
>  {
>  	if (is_ccs_modifier(fb->modifier))
>  		return main_to_ccs_plane(fb, main_plane);
> @@ -2012,6 +2013,7 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
>  			return 128;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		if (is_ccs_plane(fb, color_plane))
>  			return 64;
>  		/* fall through */
> @@ -2152,6 +2154,7 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
>  			return 256 * 1024;
>  		return 0;
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return 16 * 1024;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2536,6 +2539,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return I915_TILING_Y;
>  	default:
>  		return I915_TILING_NONE;
> @@ -2587,6 +2591,21 @@ static const struct drm_format_info
> gen12_ccs_formats[] = {
>  	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
>  	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
>  	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
> +	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = {
> 1, 1 },
> +	  .hsub = 2, .vsub = 1, .is_yuv = true },
> +	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
> +	  .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 },
> .block_h = { 1, 1, 1, 1 },
> +	  .hsub = 2, .vsub = 2, .is_yuv = true },
> +	{ .format = DRM_FORMAT_P010, .num_planes = 4,
> +	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 },
> .block_h = { 1, 1, 1, 1 },
> +	  .hsub = 2, .vsub = 2, .is_yuv = true },
> +	{ .format = DRM_FORMAT_P012, .num_planes = 4,
> +	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 },
> .block_h = { 1, 1, 1, 1 },
> +	  .hsub = 2, .vsub = 2, .is_yuv = true },
> +	{ .format = DRM_FORMAT_P016, .num_planes = 4,
> +	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 },
> .block_h = { 1, 1, 1, 1 },
> +	  .hsub = 2, .vsub = 2, .is_yuv = true },
>  };
>  
>  static const struct drm_format_info *
> @@ -2613,6 +2632,7 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
>  					  ARRAY_SIZE(skl_ccs_formats),
>  					  cmd->pixel_format);
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return lookup_format_info(gen12_ccs_formats,
>  					  ARRAY_SIZE(gen12_ccs_formats)
> ,
>  					  cmd->pixel_format);
> @@ -2624,6 +2644,7 @@ intel_get_format_info(const struct
> drm_mode_fb_cmd2 *cmd)
>  bool is_ccs_modifier(u64 modifier)
>  {
>  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
>  	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
> @@ -2695,7 +2716,7 @@ intel_fb_stride_alignment(const struct
> drm_framebuffer *fb, int color_plane)
>  	}
>  
>  	tile_width = intel_tile_width_bytes(fb, color_plane);
> -	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
> +	if (is_ccs_modifier(fb->modifier)) {
>  		/*
>  		 * Display WA #0531: skl,bxt,kbl,glk
>  		 *
> @@ -2705,7 +2726,7 @@ intel_fb_stride_alignment(const struct
> drm_framebuffer *fb, int color_plane)
>  		 * require the entire fb to accommodate that to avoid
>  		 * potential runtime errors at plane configuration
> time.
>  		 */
> -		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
> +		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb-
> >width > 3840)
>  			tile_width *= 4;
>  		/*
>  		 * The main surface pitch must be padded to a multiple
> of four
> @@ -2827,8 +2848,19 @@ intel_fb_plane_get_subsampling(int *hsub, int
> *vsub,
>  
>  	*vsub = 32;
>  }
> +
> +static void
> +intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int
> color_plane)
> +{
> +	int hsub, vsub;
> +
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
> +	*w = fb->width / hsub;
> +	*h = fb->height / vsub;
> +}
> +
>  static int
> -intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int
> x, int y)
>  {
>  	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
>  	int main_plane;
> @@ -2836,7 +2868,6 @@ intel_fb_check_ccs_xy(struct drm_framebuffer
> *fb, int x, int y)
>  	int tile_width, tile_height;
>  	int ccs_x, ccs_y;
>  	int main_x, main_y;
> -	int ccs_plane = 1;
>  
>  	if (!is_ccs_plane(fb, ccs_plane))
>  		return 0;
> @@ -2891,8 +2922,7 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
>  		int ret;
>  
>  		cpp = fb->format->cpp[i];
> -		width = drm_framebuffer_plane_width(fb->width, fb, i);
> -		height = drm_framebuffer_plane_height(fb->height, fb,
> i);
> +		intel_fb_plane_dims(&width, &height, fb, i);
>  
>  		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
>  		if (ret) {
> @@ -2901,7 +2931,7 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
>  			return ret;
>  		}
>  
> -		ret = intel_fb_check_ccs_xy(fb, x, y);
> +		ret = intel_fb_check_ccs_xy(fb, i, x, y);
>  		if (ret)
>  			return ret;
>  
> @@ -3555,6 +3585,7 @@ static int skl_max_plane_width(const struct
> drm_framebuffer *fb,
>  			return 5120;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		/* FIXME AUX plane? */
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Yf_TILED:
> @@ -3614,10 +3645,10 @@ static int icl_max_plane_height(void)
>  }
>  
>  static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> *plane_state,
> -					   int main_x, int main_y, u32
> main_offset)
> +					   int main_x, int main_y, u32
> main_offset,
> +					   int ccs_plane)
>  {
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> -	int ccs_plane = main_to_ccs_plane(fb, 0);
>  	int aux_x = plane_state->color_plane[ccs_plane].x;
>  	int aux_y = plane_state->color_plane[ccs_plane].y;
>  	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
> @@ -3723,7 +3754,8 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
>  	 * they match with the main surface x/y offsets.
>  	 */
>  	if (is_ccs_modifier(fb->modifier)) {
> -		while (!skl_check_main_ccs_coordinates(plane_state, x,
> y, offset)) {
> +		while (!skl_check_main_ccs_coordinates(plane_state, x,
> y, offset,
> +						       aux_plane)) {
>  			if (offset == 0)
>  				break;
>  
> @@ -3756,7 +3788,8 @@ static int skl_check_nv12_aux_surface(struct
> intel_plane_state *plane_state)
>  {
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	unsigned int rotation = plane_state->hw.rotation;
> -	int max_width = skl_max_plane_width(fb, 1, rotation);
> +	int uv_plane = 1;
> +	int max_width = skl_max_plane_width(fb, uv_plane, rotation);
>  	int max_height = 4096;
>  	int x = plane_state->uapi.src.x1 >> 17;
>  	int y = plane_state->uapi.src.y1 >> 17;
> @@ -3764,8 +3797,9 @@ static int skl_check_nv12_aux_surface(struct
> intel_plane_state *plane_state)
>  	int h = drm_rect_height(&plane_state->uapi.src) >> 17;
>  	u32 offset;
>  
> -	intel_add_fb_offsets(&x, &y, plane_state, 1);
> -	offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 1);
> +	intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
> +	offset = intel_plane_compute_aligned_offset(&x, &y,
> +						    plane_state,
> uv_plane);
>  
>  	/* FIXME not quite sure how/if these apply to the chroma plane
> */
>  	if (w > max_width || h > max_height) {
> @@ -3774,9 +3808,39 @@ static int skl_check_nv12_aux_surface(struct
> intel_plane_state *plane_state)
>  		return -EINVAL;
>  	}
>  
> -	plane_state->color_plane[1].offset = offset;
> -	plane_state->color_plane[1].x = x;
> -	plane_state->color_plane[1].y = y;
> +	if (is_ccs_modifier(fb->modifier)) {
> +		int ccs_plane = main_to_ccs_plane(fb, uv_plane);
> +		int aux_offset = plane_state-
> >color_plane[ccs_plane].offset;
> +		int alignment = intel_surf_alignment(fb, uv_plane);
> +
> +		if (offset > aux_offset)
> +			offset = intel_plane_adjust_aligned_offset(&x,
> &y,
> +								   plan
> e_state,
> +								   uv_p
> lane,
> +								   offs
> et,
> +								   aux_
> offset & ~(alignment - 1));
> +
> +		while (!skl_check_main_ccs_coordinates(plane_state, x,
> y,
> +						       offset,
> ccs_plane)) {
> +			if (offset == 0)
> +				break;
> +
> +			offset = intel_plane_adjust_aligned_offset(&x,
> &y,
> +								   plan
> e_state,
> +								   uv_p
> lane,
> +								   offs
> et, offset - alignment);
> +		}
> +
> +		if (x != plane_state->color_plane[ccs_plane].x ||
> +		    y != plane_state->color_plane[ccs_plane].y) {
> +			DRM_DEBUG_KMS("Unable to find suitable display
> surface offset due to CCS\n");
> +			return -EINVAL;
> +		}
> +	}
> +
> +	plane_state->color_plane[uv_plane].offset = offset;
> +	plane_state->color_plane[uv_plane].x = x;
> +	plane_state->color_plane[uv_plane].y = y;
>  
>  	return 0;
>  }
> @@ -3786,21 +3850,40 @@ static int skl_check_ccs_aux_surface(struct
> intel_plane_state *plane_state)
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	int src_x = plane_state->uapi.src.x1 >> 16;
>  	int src_y = plane_state->uapi.src.y1 >> 16;
> -	int hsub;
> -	int vsub;
> -	int x;
> -	int y;
>  	u32 offset;
> +	int ccs_plane;
>  
> -	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
> -	x = src_x / hsub;
> -	y = src_y / vsub;
> -	intel_add_fb_offsets(&x, &y, plane_state, 1);
> -	offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 1);
> +	for (ccs_plane = 0; ccs_plane < fb->format->num_planes;
> ccs_plane++) {
> +		int main_hsub, main_vsub;
> +		int hsub, vsub;
> +		int x, y;
> +
> +		if (!is_ccs_plane(fb, ccs_plane))
> +			continue;
> +
> +		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub,
> fb,
> +					       ccs_to_main_plane(fb,
> ccs_plane));
> +		intel_fb_plane_get_subsampling(&hsub, &vsub, fb,
> ccs_plane);
> +
> +		hsub *= main_hsub;
> +		vsub *= main_vsub;
> +		x = src_x / hsub;
> +		y = src_y / vsub;
>  
> -	plane_state->color_plane[1].offset = offset;
> -	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
> -	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
> +		intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
> +
> +		offset = intel_plane_compute_aligned_offset(&x, &y,
> +							    plane_state
> ,
> +							    ccs_plane);
> +
> +		plane_state->color_plane[ccs_plane].offset = offset;
> +		plane_state->color_plane[ccs_plane].x = (x * hsub +
> +							 src_x % hsub)
> /
> +							main_hsub;
> +		plane_state->color_plane[ccs_plane].y = (y * vsub +
> +							 src_y % vsub)
> /
> +							main_vsub;
> +	}
>  
>  	return 0;
>  }
> @@ -3809,6 +3892,7 @@ int skl_check_plane_surface(struct
> intel_plane_state *plane_state)
>  {
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	int ret;
> +	bool needs_aux = false;
>  
>  	ret = intel_plane_compute_gtt(plane_state);
>  	if (ret)
> @@ -3818,22 +3902,32 @@ int skl_check_plane_surface(struct
> intel_plane_state *plane_state)
>  		return 0;
>  
>  	/*
> -	 * Handle the AUX surface first since
> -	 * the main surface setup depends on it.
> +	 * Handle the AUX surface first since the main surface setup
> depends on
> +	 * it.
>  	 */
> +	if (is_ccs_modifier(fb->modifier)) {
> +		needs_aux = true;
> +		ret = skl_check_ccs_aux_surface(plane_state);
> +		if (ret)
> +			return ret;
> +	}
> +
>  	if (intel_format_info_is_yuv_semiplanar(fb->format,
>  					        fb->modifier)) {
> +		needs_aux = true;
>  		ret = skl_check_nv12_aux_surface(plane_state);
>  		if (ret)
>  			return ret;
> -	} else if (is_ccs_modifier(fb->modifier)) {
> -		ret = skl_check_ccs_aux_surface(plane_state);
> -		if (ret)
> -			return ret;
> -	} else {
> -		plane_state->color_plane[1].offset = ~0xfff;
> -		plane_state->color_plane[1].x = 0;
> -		plane_state->color_plane[1].y = 0;
> +	}
> +
> +	if (!needs_aux) {
> +		int i;
> +
> +		for (i = 1; i < fb->format->num_planes; i++) {
> +			plane_state->color_plane[i].offset = ~0xfff;
> +			plane_state->color_plane[i].x = 0;
> +			plane_state->color_plane[i].y = 0;
> +		}
>  	}
>  
>  	ret = skl_check_main_surface(plane_state);
> @@ -4423,6 +4517,8 @@ static u32 skl_plane_ctl_tiling(u64
> fb_modifier)
>  		return PLANE_CTL_TILED_Y |
>  		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
>  		       PLANE_CTL_CLEAR_COLOR_DISABLE;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		return PLANE_CTL_TILED_Y |
> PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return PLANE_CTL_TILED_YF;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -10165,6 +10261,8 @@ skylake_get_initial_plane_config(struct
> intel_crtc *crtc,
>  			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
>  				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
>  				I915_FORMAT_MOD_Y_TILED_CCS;
> +		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> +			fb->modifier =
> I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
>  		else
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 0fef9263cddc..b8112340773b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -474,6 +474,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
>  			    struct intel_link_m_n *m_n,
>  			    bool constant_n, bool fec_enable);
>  bool is_ccs_modifier(u64 modifier);
> +int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int
> main_plane);
>  void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
>  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  			      u32 pixel_format, u64 modifier);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 83ea04149b77..3cdf44fa4164 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -90,8 +90,8 @@ struct intel_framebuffer {
>  	/* for each plane in the normal GTT view */
>  	struct {
>  		unsigned int x, y;
> -	} normal[2];
> -	/* for each plane in the rotated GTT view */
> +	} normal[4];
> +	/* for each plane in the rotated GTT view for no-CCS formats */
>  	struct {
>  		unsigned int x, y;
>  		unsigned int pitch; /* pixels */
> @@ -555,7 +555,7 @@ struct intel_plane_state {
>  		 */
>  		u32 stride;
>  		int x, y;
> -	} color_plane[2];
> +	} color_plane[4];
>  
>  	/* plane control register */
>  	u32 ctl;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index b7f3a1b3358f..be56b6f56411 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -583,15 +583,16 @@ skl_program_plane(struct intel_plane *plane,
>  	const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
>  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
>  	u32 stride = skl_plane_stride(plane_state, color_plane);
> -	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
> -	u32 aux_stride = skl_plane_stride(plane_state, 1);
> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> +	int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> +	u32 aux_dist = plane_state->color_plane[aux_plane].offset -
> surf_addr;
> +	u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
>  	int crtc_x = plane_state->uapi.dst.x1;
>  	int crtc_y = plane_state->uapi.dst.y1;
>  	u32 x = plane_state->color_plane[color_plane].x;
>  	u32 y = plane_state->color_plane[color_plane].y;
>  	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
>  	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> -	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	u8 alpha = plane_state->hw.alpha >> 8;
>  	u32 plane_color_ctl = 0;
>  	unsigned long irqflags;
> @@ -2106,7 +2107,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> mode\n");
>  		return -EINVAL;
>  	}
> @@ -2577,7 +2579,16 @@ static const u64
> skl_plane_format_modifiers_ccs[] = {
>  	DRM_FORMAT_MOD_INVALID
>  };
>  
> -static const u64 gen12_plane_format_modifiers_ccs[] = {
> +static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> +	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> +	I915_FORMAT_MOD_Y_TILED,
> +	I915_FORMAT_MOD_X_TILED,
> +	DRM_FORMAT_MOD_LINEAR,
> +	DRM_FORMAT_MOD_INVALID
> +};
> +
> +static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
>  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
> @@ -2742,10 +2753,21 @@ static bool
> skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	}
>  }
>  
> +static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
> +{
> +	return plane_id < PLANE_SPRITE4;
> +}
> +
>  static bool gen12_plane_format_mod_supported(struct drm_plane
> *_plane,
>  					     u32 format, u64 modifier)
>  {
> +	struct intel_plane *plane = to_intel_plane(_plane);
> +
>  	switch (modifier) {
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		if (!gen12_plane_supports_mc_ccs(plane->id))
> +			return false;
> +		/* fall through */
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -2763,11 +2785,6 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  		if (is_ccs_modifier(modifier))
>  			return true;
>  		/* fall through */
> -	case DRM_FORMAT_RGB565:
> -	case DRM_FORMAT_XRGB2101010:
> -	case DRM_FORMAT_XBGR2101010:
> -	case DRM_FORMAT_ARGB2101010:
> -	case DRM_FORMAT_ABGR2101010:
>  	case DRM_FORMAT_YUYV:
>  	case DRM_FORMAT_YVYU:
>  	case DRM_FORMAT_UYVY:
> @@ -2776,6 +2793,14 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_P010:
>  	case DRM_FORMAT_P012:
>  	case DRM_FORMAT_P016:
> +		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> +			return true;
> +		/* fall through */
> +	case DRM_FORMAT_RGB565:
> +	case DRM_FORMAT_XRGB2101010:
> +	case DRM_FORMAT_XBGR2101010:
> +	case DRM_FORMAT_ARGB2101010:
> +	case DRM_FORMAT_ABGR2101010:
>  	case DRM_FORMAT_XVYU2101010:
>  	case DRM_FORMAT_C8:
>  	case DRM_FORMAT_XBGR16161616F:
> @@ -2909,6 +2934,14 @@ static const u32 *icl_get_plane_formats(struct
> drm_i915_private *dev_priv,
>  	}
>  }
>  
> +static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
> +{
> +	if (gen12_plane_supports_mc_ccs(plane_id))
> +		return gen12_plane_format_modifiers_mc_ccs;
> +	else
> +		return gen12_plane_format_modifiers_rc_ccs;
> +}
> +
>  static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
>  			      enum pipe pipe, enum plane_id plane_id)
>  {
> @@ -2974,7 +3007,7 @@ skl_universal_plane_create(struct
> drm_i915_private *dev_priv,
>  
>  	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		modifiers = gen12_plane_format_modifiers_ccs;
> +		modifiers = gen12_get_plane_modifiers(plane_id);
>  		plane_funcs = &gen12_plane_funcs;
>  	} else {
>  		if (plane->has_ccs)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index bbfedeb00b7f..b6dc735e85e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6808,6 +6808,7 @@ enum {
>  #define   PLANE_CTL_TILED_Y			(4 << 10)
>  #define   PLANE_CTL_TILED_YF			(5 << 10)
>  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
> +#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /*
> TGL+ */
>  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /*
> Pre-GLK */
>  #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
>  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH v2 13/15] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine

[Imre Deak]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not
support media decompression.

v2: Fix checkpatch warnings on code style (Lucas)

From DK:
Separate modifier array for planes that cannot decompress media (Ville)

v3: Support planar formats
v4: Switch plane order
v5:
- Use format block descriptors to get CCS subsampling calculation right
  everywhere.
- Extend the plane state normal view array to accommodate 4 color planes.
- Use helpers to convert between main and CCS planes.
v6: Add missing packed YUV formats to the MC format list. (Yang)

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Yang A Shi <yang.a.shi@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 184 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_display.h  |   1 +
 .../drm/i915/display/intel_display_types.h    |   6 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  55 ++++--
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 5 files changed, 195 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 433d9aebbf42..27cf901db5d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1943,7 +1943,9 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
 
 static bool is_gen12_ccs_modifier(u64 modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+
 }
 
 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
@@ -1976,8 +1978,7 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
 }
 
 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
-static int
-intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
+int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
 {
 	if (is_ccs_modifier(fb->modifier))
 		return main_to_ccs_plane(fb, main_plane);
@@ -2012,6 +2013,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 			return 128;
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		if (is_ccs_plane(fb, color_plane))
 			return 64;
 		/* fall through */
@@ -2152,6 +2154,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 			return 256 * 1024;
 		return 0;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2536,6 +2539,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2587,6 +2591,30 @@ static const struct drm_format_info gen12_ccs_formats[] = {
 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 	  .hsub = 1, .vsub = 1, .has_alpha = true },
+	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
+	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 2, .vsub = 1, .is_yuv = true },
+	{ .format = DRM_FORMAT_YVYU, .num_planes = 2,
+	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 2, .vsub = 1, .is_yuv = true },
+	{ .format = DRM_FORMAT_UYVY, .num_planes = 2,
+	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 2, .vsub = 1, .is_yuv = true },
+	{ .format = DRM_FORMAT_VYUY, .num_planes = 2,
+	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 2, .vsub = 1, .is_yuv = true },
+	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
+	  .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
+	  .hsub = 2, .vsub = 2, .is_yuv = true },
+	{ .format = DRM_FORMAT_P010, .num_planes = 4,
+	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+	  .hsub = 2, .vsub = 2, .is_yuv = true },
+	{ .format = DRM_FORMAT_P012, .num_planes = 4,
+	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+	  .hsub = 2, .vsub = 2, .is_yuv = true },
+	{ .format = DRM_FORMAT_P016, .num_planes = 4,
+	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+	  .hsub = 2, .vsub = 2, .is_yuv = true },
 };
 
 static const struct drm_format_info *
@@ -2613,6 +2641,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 					  ARRAY_SIZE(skl_ccs_formats),
 					  cmd->pixel_format);
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return lookup_format_info(gen12_ccs_formats,
 					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
@@ -2624,6 +2653,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 bool is_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
@@ -2695,7 +2725,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 	}
 
 	tile_width = intel_tile_width_bytes(fb, color_plane);
-	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+	if (is_ccs_modifier(fb->modifier)) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2705,7 +2735,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
 			tile_width *= 4;
 		/*
 		 * The main surface pitch must be padded to a multiple of four
@@ -2827,6 +2857,17 @@ intel_fb_plane_get_subsampling(int *hsub, int *vsub,
 
 	*vsub = 32;
 }
+
+static void
+intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
+{
+	int hsub, vsub;
+
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+	*w = fb->width / hsub;
+	*h = fb->height / vsub;
+}
+
 static int
 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
 {
@@ -2949,8 +2990,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		int ret;
 
 		cpp = fb->format->cpp[i];
-		width = drm_framebuffer_plane_width(fb->width, fb, i);
-		height = drm_framebuffer_plane_height(fb->height, fb, i);
+		intel_fb_plane_dims(&width, &height, fb, i);
 
 		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
 		if (ret) {
@@ -3585,6 +3625,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
 			return 5120;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		/* FIXME AUX plane? */
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
@@ -3644,10 +3685,10 @@ static int icl_max_plane_height(void)
 }
 
 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
-					   int main_x, int main_y, u32 main_offset)
+					   int main_x, int main_y, u32 main_offset,
+					   int ccs_plane)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	int ccs_plane = main_to_ccs_plane(fb, 0);
 	int aux_x = plane_state->color_plane[ccs_plane].x;
 	int aux_y = plane_state->color_plane[ccs_plane].y;
 	u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
@@ -3753,7 +3794,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	 * they match with the main surface x/y offsets.
 	 */
 	if (is_ccs_modifier(fb->modifier)) {
-		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset,
+						       aux_plane)) {
 			if (offset == 0)
 				break;
 
@@ -3786,7 +3828,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
-	int max_width = skl_max_plane_width(fb, 1, rotation);
+	int uv_plane = 1;
+	int max_width = skl_max_plane_width(fb, uv_plane, rotation);
 	int max_height = 4096;
 	int x = plane_state->uapi.src.x1 >> 17;
 	int y = plane_state->uapi.src.y1 >> 17;
@@ -3794,8 +3837,9 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 	int h = drm_rect_height(&plane_state->uapi.src) >> 17;
 	u32 offset;
 
-	intel_add_fb_offsets(&x, &y, plane_state, 1);
-	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+	intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
+	offset = intel_plane_compute_aligned_offset(&x, &y,
+						    plane_state, uv_plane);
 
 	/* FIXME not quite sure how/if these apply to the chroma plane */
 	if (w > max_width || h > max_height) {
@@ -3804,9 +3848,39 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 		return -EINVAL;
 	}
 
-	plane_state->color_plane[1].offset = offset;
-	plane_state->color_plane[1].x = x;
-	plane_state->color_plane[1].y = y;
+	if (is_ccs_modifier(fb->modifier)) {
+		int ccs_plane = main_to_ccs_plane(fb, uv_plane);
+		int aux_offset = plane_state->color_plane[ccs_plane].offset;
+		int alignment = intel_surf_alignment(fb, uv_plane);
+
+		if (offset > aux_offset)
+			offset = intel_plane_adjust_aligned_offset(&x, &y,
+								   plane_state,
+								   uv_plane,
+								   offset,
+								   aux_offset & ~(alignment - 1));
+
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
+						       offset, ccs_plane)) {
+			if (offset == 0)
+				break;
+
+			offset = intel_plane_adjust_aligned_offset(&x, &y,
+								   plane_state,
+								   uv_plane,
+								   offset, offset - alignment);
+		}
+
+		if (x != plane_state->color_plane[ccs_plane].x ||
+		    y != plane_state->color_plane[ccs_plane].y) {
+			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
+			return -EINVAL;
+		}
+	}
+
+	plane_state->color_plane[uv_plane].offset = offset;
+	plane_state->color_plane[uv_plane].x = x;
+	plane_state->color_plane[uv_plane].y = y;
 
 	return 0;
 }
@@ -3816,21 +3890,40 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int src_x = plane_state->uapi.src.x1 >> 16;
 	int src_y = plane_state->uapi.src.y1 >> 16;
-	int hsub;
-	int vsub;
-	int x;
-	int y;
 	u32 offset;
+	int ccs_plane;
 
-	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
-	x = src_x / hsub;
-	y = src_y / vsub;
-	intel_add_fb_offsets(&x, &y, plane_state, 1);
-	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+	for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
+		int main_hsub, main_vsub;
+		int hsub, vsub;
+		int x, y;
+
+		if (!is_ccs_plane(fb, ccs_plane))
+			continue;
+
+		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
+					       ccs_to_main_plane(fb, ccs_plane));
+		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
+
+		hsub *= main_hsub;
+		vsub *= main_vsub;
+		x = src_x / hsub;
+		y = src_y / vsub;
 
-	plane_state->color_plane[1].offset = offset;
-	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
-	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
+		intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
+
+		offset = intel_plane_compute_aligned_offset(&x, &y,
+							    plane_state,
+							    ccs_plane);
+
+		plane_state->color_plane[ccs_plane].offset = offset;
+		plane_state->color_plane[ccs_plane].x = (x * hsub +
+							 src_x % hsub) /
+							main_hsub;
+		plane_state->color_plane[ccs_plane].y = (y * vsub +
+							 src_y % vsub) /
+							main_vsub;
+	}
 
 	return 0;
 }
@@ -3839,6 +3932,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int ret;
+	bool needs_aux = false;
 
 	ret = intel_plane_compute_gtt(plane_state);
 	if (ret)
@@ -3848,22 +3942,32 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 		return 0;
 
 	/*
-	 * Handle the AUX surface first since
-	 * the main surface setup depends on it.
+	 * Handle the AUX surface first since the main surface setup depends on
+	 * it.
 	 */
+	if (is_ccs_modifier(fb->modifier)) {
+		needs_aux = true;
+		ret = skl_check_ccs_aux_surface(plane_state);
+		if (ret)
+			return ret;
+	}
+
 	if (intel_format_info_is_yuv_semiplanar(fb->format,
 					        fb->modifier)) {
+		needs_aux = true;
 		ret = skl_check_nv12_aux_surface(plane_state);
 		if (ret)
 			return ret;
-	} else if (is_ccs_modifier(fb->modifier)) {
-		ret = skl_check_ccs_aux_surface(plane_state);
-		if (ret)
-			return ret;
-	} else {
-		plane_state->color_plane[1].offset = ~0xfff;
-		plane_state->color_plane[1].x = 0;
-		plane_state->color_plane[1].y = 0;
+	}
+
+	if (!needs_aux) {
+		int i;
+
+		for (i = 1; i < fb->format->num_planes; i++) {
+			plane_state->color_plane[i].offset = ~0xfff;
+			plane_state->color_plane[i].x = 0;
+			plane_state->color_plane[i].y = 0;
+		}
 	}
 
 	ret = skl_check_main_surface(plane_state);
@@ -4453,6 +4557,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y |
 		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 		       PLANE_CTL_CLEAR_COLOR_DISABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -10195,6 +10301,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
 				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
 				I915_FORMAT_MOD_Y_TILED_CCS;
+		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 0fef9263cddc..b8112340773b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -474,6 +474,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    struct intel_link_m_n *m_n,
 			    bool constant_n, bool fec_enable);
 bool is_ccs_modifier(u64 modifier);
+int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane);
 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..3cdf44fa4164 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -90,8 +90,8 @@ struct intel_framebuffer {
 	/* for each plane in the normal GTT view */
 	struct {
 		unsigned int x, y;
-	} normal[2];
-	/* for each plane in the rotated GTT view */
+	} normal[4];
+	/* for each plane in the rotated GTT view for no-CCS formats */
 	struct {
 		unsigned int x, y;
 		unsigned int pitch; /* pixels */
@@ -555,7 +555,7 @@ struct intel_plane_state {
 		 */
 		u32 stride;
 		int x, y;
-	} color_plane[2];
+	} color_plane[4];
 
 	/* plane control register */
 	u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7f3a1b3358f..be56b6f56411 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -583,15 +583,16 @@ skl_program_plane(struct intel_plane *plane,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
-	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
-	u32 aux_stride = skl_plane_stride(plane_state, 1);
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	int aux_plane = intel_main_to_aux_plane(fb, color_plane);
+	u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
+	u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
 	int crtc_x = plane_state->uapi.dst.x1;
 	int crtc_y = plane_state->uapi.dst.y1;
 	u32 x = plane_state->color_plane[color_plane].x;
 	u32 y = plane_state->color_plane[color_plane].y;
 	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
-	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	u8 alpha = plane_state->hw.alpha >> 8;
 	u32 plane_color_ctl = 0;
 	unsigned long irqflags;
@@ -2106,7 +2107,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2577,7 +2579,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_ccs[] = {
+static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED,
+	I915_FORMAT_MOD_X_TILED,
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
+static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
@@ -2742,10 +2753,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	}
 }
 
+static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
+{
+	return plane_id < PLANE_SPRITE4;
+}
+
 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 					     u32 format, u64 modifier)
 {
+	struct intel_plane *plane = to_intel_plane(_plane);
+
 	switch (modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		if (!gen12_plane_supports_mc_ccs(plane->id))
+			return false;
+		/* fall through */
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2763,11 +2785,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (is_ccs_modifier(modifier))
 			return true;
 		/* fall through */
-	case DRM_FORMAT_RGB565:
-	case DRM_FORMAT_XRGB2101010:
-	case DRM_FORMAT_XBGR2101010:
-	case DRM_FORMAT_ARGB2101010:
-	case DRM_FORMAT_ABGR2101010:
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
@@ -2776,6 +2793,14 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_P010:
 	case DRM_FORMAT_P012:
 	case DRM_FORMAT_P016:
+		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+			return true;
+		/* fall through */
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_XBGR2101010:
+	case DRM_FORMAT_ARGB2101010:
+	case DRM_FORMAT_ABGR2101010:
 	case DRM_FORMAT_XVYU2101010:
 	case DRM_FORMAT_C8:
 	case DRM_FORMAT_XBGR16161616F:
@@ -2909,6 +2934,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
 	}
 }
 
+static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
+{
+	if (gen12_plane_supports_mc_ccs(plane_id))
+		return gen12_plane_format_modifiers_mc_ccs;
+	else
+		return gen12_plane_format_modifiers_rc_ccs;
+}
+
 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, enum plane_id plane_id)
 {
@@ -2974,7 +3007,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 
 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		modifiers = gen12_plane_format_modifiers_ccs;
+		modifiers = gen12_get_plane_modifiers(plane_id);
 		plane_funcs = &gen12_plane_funcs;
 	} else {
 		if (plane->has_ccs)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bbfedeb00b7f..b6dc735e85e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6808,6 +6808,7 @@ enum {
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
+#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
-- 
2.22.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 14/15] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

[Imre Deak]

From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.

V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
v6: Documentation Nitpicks(Nanley)

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8bc0b31597d8..1c9c3991cab6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,25 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
 
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 14/15] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

[Kahola, Mika]

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> 
> Gen12 display can decompress surfaces compressed by render engine
> with
> Clear Color, add a new modifier as the driver needs to know the
> surface
> was compressed by render engine.
> 
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
> 
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h
> index 8bc0b31597d8..1c9c3991cab6 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,25 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL,
> 7)
>  
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12
> render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS
> is linear
> + * and at index 1. The clear color is stored at index 2, and the
> pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128
> bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and
> generates
> + * the converted clear color of size 64 bits. The first 32 bits
> store the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher
> Converted
> + * Clear Color value when applicable. The Converted Clear Color
> values are
> + * consumed by the DE. The last 64 bits are used to store Color
> Discard Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS
> cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main
> surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL, 8)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized
> macroblocks
>   *
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[PATCH 14/15] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

[Imre Deak]

From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.

V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
v6: Documentation Nitpicks(Nanley)

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8bc0b31597d8..1c9c3991cab6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,25 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
 
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.22.0

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[Intel-gfx] [PATCH 14/15] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

[Imre Deak]

From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.

V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
v6: Documentation Nitpicks(Nanley)

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8bc0b31597d8..1c9c3991cab6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,25 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
 
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.22.0

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[Intel-gfx] [PATCH 15/15] drm/i915/tgl: Add Clear Color support for TGL Render Decompression

[Imre Deak]

From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.

v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
    plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
v6:
- Use format block descriptors to get the subsampling calculations for
  the CCS surface right.
- Use helpers to convert between main and CCS surfaces.
- Prevent coordinate checks for the CC surface.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com> (v5)
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 67 +++++++++++++++++--
 .../drm/i915/display/intel_display_types.h    |  3 +
 drivers/gpu/drm/i915/display/intel_sprite.c   | 11 ++-
 drivers/gpu/drm/i915/i915_reg.h               | 12 ++++
 4 files changed, 88 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1c2becf47bfd..f264a0792d0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1944,8 +1944,8 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
 static bool is_gen12_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-
 }
 
 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
@@ -1953,6 +1953,12 @@ static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
 	return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
 }
 
+static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
+{
+	return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
+	       plane == 2;
+}
+
 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
 {
 	if (is_ccs_modifier(fb->modifier))
@@ -1974,6 +1980,9 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
 	WARN_ON(!is_ccs_modifier(fb->modifier) ||
 		ccs_plane < fb->format->num_planes / 2);
 
+	if (is_gen12_ccs_cc_plane(fb, ccs_plane))
+		return 0;
+
 	return ccs_plane - fb->format->num_planes / 2;
 }
 
@@ -2013,6 +2022,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 			return 128;
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		if (is_ccs_plane(fb, color_plane))
 			return 64;
@@ -2154,6 +2164,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 			return 256 * 1024;
 		return 0;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
@@ -2539,6 +2550,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
 	default:
@@ -2608,6 +2620,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
 	  .hsub = 2, .vsub = 2, .is_yuv = true },
 };
 
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2636,6 +2667,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 		return lookup_format_info(gen12_ccs_formats,
 					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+		return lookup_format_info(gen12_ccs_cc_formats,
+					  ARRAY_SIZE(gen12_ccs_cc_formats),
+					  cmd->pixel_format);
 	default:
 		return NULL;
 	}
@@ -2644,6 +2679,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 bool is_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
@@ -2869,7 +2905,7 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
 	int ccs_x, ccs_y;
 	int main_x, main_y;
 
-	if (!is_ccs_plane(fb, ccs_plane))
+	if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
 		return 0;
 
 	intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
@@ -2921,6 +2957,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		int x, y;
 		int ret;
 
+		/*
+		 * Plane 2 of Render Compression with Clear Color fb modifier
+		 * is consumed by the driver and not passed to DE. Skip the
+		 * arithmetic related to alignment and offset calculation.
+		 */
+		if (is_gen12_ccs_cc_plane(fb, i)) {
+			if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
+				continue;
+			else
+				return -EINVAL;
+		}
+
 		cpp = fb->format->cpp[i];
 		intel_fb_plane_dims(&width, &height, fb, i);
 
@@ -3858,7 +3906,8 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 		int hsub, vsub;
 		int x, y;
 
-		if (!is_ccs_plane(fb, ccs_plane))
+		if (!is_ccs_plane(fb, ccs_plane) ||
+		    is_gen12_ccs_cc_plane(fb, ccs_plane))
 			continue;
 
 		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
@@ -4512,6 +4561,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return PLANE_CTL_TILED_Y |
@@ -15360,6 +15410,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 
 	plane_state->vma = vma;
 
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
+		u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
+								  fb->offsets[2] >> PAGE_SHIFT));
+
+		plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
+				     | *(ccaddr + CC_VAL_LOWER_OFFSET);
+		kunmap_atomic(ccaddr);
+	}
+
 	return 0;
 }
 
@@ -16651,7 +16710,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			goto err;
 		}
 
-		if (is_gen12_ccs_plane(fb, i)) {
+		if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
 			int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
 
 			if (fb->pitches[i] != ccs_aux_stride) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3cdf44fa4164..ab01349b7273 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -607,6 +607,9 @@ struct intel_plane_state {
 	u32 planar_slave;
 
 	struct drm_intel_sprite_colorkey ckey;
+
+	/* Clear Color Value */
+	u64 ccval;
 };
 
 struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index be56b6f56411..1a7037429d32 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -598,6 +598,7 @@ skl_program_plane(struct intel_plane *plane,
 	unsigned long irqflags;
 	u32 keymsk, keymax;
 	u32 plane_ctl = plane_state->ctl;
+	u64 ccval = plane_state->ccval;
 
 	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
 
@@ -640,6 +641,10 @@ skl_program_plane(struct intel_plane *plane,
 	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
 		icl_program_input_csc(plane, crtc_state, plane_state);
 
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+		intel_uncore_write64_fw(&dev_priv->uncore,
+					PLANE_CC_VAL(pipe, plane_id), ccval);
+
 	skl_write_plane_wm(plane, crtc_state);
 
 	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
@@ -2108,7 +2113,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2582,6 +2588,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2590,6 +2597,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
 
 static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2772,6 +2780,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		break;
 	default:
 		return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b6dc735e85e1..d93451f3d8ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6841,6 +6841,8 @@ enum {
 #define _PLANE_KEYMAX_1_A			0x701a0
 #define _PLANE_KEYMAX_2_A			0x702a0
 #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
+#define _PLANE_CC_VAL_1_A			0x701b4
+#define _PLANE_CC_VAL_2_A			0x702b4
 #define _PLANE_AUX_DIST_1_A			0x701c0
 #define _PLANE_AUX_DIST_2_A			0x702c0
 #define _PLANE_AUX_OFFSET_1_A			0x701c4
@@ -6880,6 +6882,16 @@ enum {
 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
 
+#define _PLANE_CC_VAL_1_B			0x711b4
+#define _PLANE_CC_VAL_2_B			0x712b4
+#define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane)	\
+	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
+#define CC_VAL_LOWER_OFFSET		4
+#define CC_VAL_HIGHER_OFFSET		5
+
 /* Input CSC Register Definitions */
 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
-- 
2.22.0

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Re: [Intel-gfx] [PATCH 15/15] drm/i915/tgl: Add Clear Color support for TGL Render Decompression

[Matt Roper]

On Wed, Dec 18, 2019 at 06:11:05PM +0200, Imre Deak wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> 
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
> user-space through an offset in the GEM BO. Add a new modifier to identify
> and parse new Clear Color information and extend Gen12 render decompression
> functionality to the newly added modifier.
> 
> v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
>     plane config(Matt). Fix Lookup error.
> v3: Fix the panic while running kms_cube
> v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
> v5: Fix typos and wrap comments(Matt)
> v6:
> - Use format block descriptors to get the subsampling calculations for
>   the CCS surface right.
> - Use helpers to convert between main and CCS surfaces.
> - Prevent coordinate checks for the CC surface.

I notice that we're not handling CCS_CC as a case during
skylake_get_initial_plane_config() in this patch.  It's probably very,
very unlikely that we'll ever have any form of compression on a pre-OS
framebuffer; I'm wondering if we should remove the CCS handling we have
there today and just skip framebuffer reconstruction if we see
compression active (either with or without clear color) on a framebuffer
that we're inheriting from the pre-OS software.  But if we keep support
for non-CC compressed framebuffers, we should probably at least add a
case handling CC if we see the registers set that way.  Of course if
that inherited framebuffer is in stolen memory, then we're not going to
be able to grab the page and kmap_atomic() it either.  So probably
easier to reject CCS_CC pre-OS framebuffers rather than trying to copy
the framebuffer to non-stolen memory before use...

Aside from that, I have a couple other comments below, but they're minor
things that you can either ignore or deal with in followup patches, so

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjala <ville.syrjala@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> (v5)
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 67 +++++++++++++++++--
>  .../drm/i915/display/intel_display_types.h    |  3 +
>  drivers/gpu/drm/i915/display/intel_sprite.c   | 11 ++-
>  drivers/gpu/drm/i915/i915_reg.h               | 12 ++++
>  4 files changed, 88 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1c2becf47bfd..f264a0792d0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1944,8 +1944,8 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
>  static bool is_gen12_ccs_modifier(u64 modifier)
>  {
>  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
>  	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> -
>  }
>  
>  static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> @@ -1953,6 +1953,12 @@ static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
>  	return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
>  }
>  
> +static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
> +{
> +	return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
> +	       plane == 2;
> +}
> +
>  static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
>  {
>  	if (is_ccs_modifier(fb->modifier))
> @@ -1974,6 +1980,9 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
>  	WARN_ON(!is_ccs_modifier(fb->modifier) ||
>  		ccs_plane < fb->format->num_planes / 2);
>  
> +	if (is_gen12_ccs_cc_plane(fb, ccs_plane))
> +		return 0;
> +
>  	return ccs_plane - fb->format->num_planes / 2;
>  }
>  

Do we actually wind up ever calling this function with the CC plane?
From what I can see all the callsites are in places where we've already
bailed out if we see we're operating on the CC plane.


> @@ -2013,6 +2022,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  			return 128;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		if (is_ccs_plane(fb, color_plane))
>  			return 64;
> @@ -2154,6 +2164,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>  			return 256 * 1024;
>  		return 0;
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return 16 * 1024;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> @@ -2539,6 +2550,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return I915_TILING_Y;
>  	default:
> @@ -2608,6 +2620,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
>  	  .hsub = 2, .vsub = 2, .is_yuv = true },
>  };
>  
> +/*
> + * Same as gen12_ccs_formats[] above, but with additional surface used
> + * to pass Clear Color information in plane 2 with 64 bits of data.
> + */
> +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> +	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> +	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> +	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> +	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +};
> +
>  static const struct drm_format_info *
>  lookup_format_info(const struct drm_format_info formats[],
>  		   int num_formats, u32 format)
> @@ -2636,6 +2667,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  		return lookup_format_info(gen12_ccs_formats,
>  					  ARRAY_SIZE(gen12_ccs_formats),
>  					  cmd->pixel_format);
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> +		return lookup_format_info(gen12_ccs_cc_formats,
> +					  ARRAY_SIZE(gen12_ccs_cc_formats),
> +					  cmd->pixel_format);
>  	default:
>  		return NULL;
>  	}
> @@ -2644,6 +2679,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  bool is_ccs_modifier(u64 modifier)
>  {
>  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
>  	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
>  	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> @@ -2869,7 +2905,7 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
>  	int ccs_x, ccs_y;
>  	int main_x, main_y;
>  
> -	if (!is_ccs_plane(fb, ccs_plane))
> +	if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
>  		return 0;
>  
>  	intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
> @@ -2921,6 +2957,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		int x, y;
>  		int ret;
>  
> +		/*
> +		 * Plane 2 of Render Compression with Clear Color fb modifier
> +		 * is consumed by the driver and not passed to DE. Skip the
> +		 * arithmetic related to alignment and offset calculation.
> +		 */
> +		if (is_gen12_ccs_cc_plane(fb, i)) {
> +			if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
> +				continue;
> +			else
> +				return -EINVAL;
> +		}
> +
>  		cpp = fb->format->cpp[i];
>  		intel_fb_plane_dims(&width, &height, fb, i);
>  
> @@ -3858,7 +3906,8 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
>  		int hsub, vsub;
>  		int x, y;
>  
> -		if (!is_ccs_plane(fb, ccs_plane))
> +		if (!is_ccs_plane(fb, ccs_plane) ||
> +		    is_gen12_ccs_cc_plane(fb, ccs_plane))
>  			continue;
>  
>  		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
> @@ -4512,6 +4561,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>  	case I915_FORMAT_MOD_Y_TILED:
>  		return PLANE_CTL_TILED_Y;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return PLANE_CTL_TILED_Y |
> @@ -15360,6 +15410,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
>  
>  	plane_state->vma = vma;
>  
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> +		u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> +								  fb->offsets[2] >> PAGE_SHIFT));
> +
> +		plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
> +				     | *(ccaddr + CC_VAL_LOWER_OFFSET);
> +		kunmap_atomic(ccaddr);
> +	}
> +
>  	return 0;

Some of the lines here are long enough that we should probably
split/wrap them differently.

Personally I still feel like describing the CC plane as a C structure
would make it easier to read/understand, even if the kernel driver
doesn't actually use some of the fields in it.  Or at least just mapping
the buffer as a u64* instead of a u32* so that we can read a single
value from it rather than reading the low and high parts separately.


Matt

>  }
>  
> @@ -16651,7 +16710,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  			goto err;
>  		}
>  
> -		if (is_gen12_ccs_plane(fb, i)) {
> +		if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
>  			int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
>  
>  			if (fb->pitches[i] != ccs_aux_stride) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 3cdf44fa4164..ab01349b7273 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -607,6 +607,9 @@ struct intel_plane_state {
>  	u32 planar_slave;
>  
>  	struct drm_intel_sprite_colorkey ckey;
> +
> +	/* Clear Color Value */
> +	u64 ccval;
>  };
>  
>  struct intel_initial_plane_config {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index be56b6f56411..1a7037429d32 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -598,6 +598,7 @@ skl_program_plane(struct intel_plane *plane,
>  	unsigned long irqflags;
>  	u32 keymsk, keymax;
>  	u32 plane_ctl = plane_state->ctl;
> +	u64 ccval = plane_state->ccval;
>  
>  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>  
> @@ -640,6 +641,10 @@ skl_program_plane(struct intel_plane *plane,
>  	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
>  		icl_program_input_csc(plane, crtc_state, plane_state);
>  
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> +		intel_uncore_write64_fw(&dev_priv->uncore,
> +					PLANE_CC_VAL(pipe, plane_id), ccval);
> +
>  	skl_write_plane_wm(plane, crtc_state);
>  
>  	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> @@ -2108,7 +2113,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
>  		return -EINVAL;
>  	}
> @@ -2582,6 +2588,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
>  static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
>  	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
>  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
>  	DRM_FORMAT_MOD_LINEAR,
> @@ -2590,6 +2597,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
>  
>  static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
>  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
>  	DRM_FORMAT_MOD_LINEAR,
> @@ -2772,6 +2780,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		break;
>  	default:
>  		return false;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b6dc735e85e1..d93451f3d8ae 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6841,6 +6841,8 @@ enum {
>  #define _PLANE_KEYMAX_1_A			0x701a0
>  #define _PLANE_KEYMAX_2_A			0x702a0
>  #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
> +#define _PLANE_CC_VAL_1_A			0x701b4
> +#define _PLANE_CC_VAL_2_A			0x702b4
>  #define _PLANE_AUX_DIST_1_A			0x701c0
>  #define _PLANE_AUX_DIST_2_A			0x702c0
>  #define _PLANE_AUX_OFFSET_1_A			0x701c4
> @@ -6880,6 +6882,16 @@ enum {
>  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
>  #define _PLANE_NV12_BUF_CFG_2_A		0x70378
>  
> +#define _PLANE_CC_VAL_1_B			0x711b4
> +#define _PLANE_CC_VAL_2_B			0x712b4
> +#define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
> +#define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
> +#define PLANE_CC_VAL(pipe, plane)	\
> +	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
> +
> +#define CC_VAL_LOWER_OFFSET		4
> +#define CC_VAL_HIGHER_OFFSET		5
> +
>  /* Input CSC Register Definitions */
>  #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
>  #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
> -- 
> 2.22.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 15/15] drm/i915/tgl: Add Clear Color support for TGL Render Decompression

[Imre Deak]

On Fri, Dec 20, 2019 at 02:58:12PM -0800, Matt Roper wrote:
> On Wed, Dec 18, 2019 at 06:11:05PM +0200, Imre Deak wrote:
> > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > 
> > Render Decompression is supported with Y-Tiled main surface. The CCS is
> > linear and has 4 bits of data for each main surface cache line pair, a
> > ratio of 1:256. Additional Clear Color information is passed from the
> > user-space through an offset in the GEM BO. Add a new modifier to identify
> > and parse new Clear Color information and extend Gen12 render decompression
> > functionality to the newly added modifier.
> > 
> > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> >     plane config(Matt). Fix Lookup error.
> > v3: Fix the panic while running kms_cube
> > v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
> > v5: Fix typos and wrap comments(Matt)
> > v6:
> > - Use format block descriptors to get the subsampling calculations for
> >   the CCS surface right.
> > - Use helpers to convert between main and CCS surfaces.
> > - Prevent coordinate checks for the CC surface.
> 
> I notice that we're not handling CCS_CC as a case during
> skylake_get_initial_plane_config() in this patch.  It's probably very,
> very unlikely that we'll ever have any form of compression on a pre-OS
> framebuffer; I'm wondering if we should remove the CCS handling we have
> there today and just skip framebuffer reconstruction if we see
> compression active (either with or without clear color) on a framebuffer
> that we're inheriting from the pre-OS software.  But if we keep support
> for non-CC compressed framebuffers, we should probably at least add a
> case handling CC if we see the registers set that way.  Of course if
> that inherited framebuffer is in stolen memory, then we're not going to
> be able to grab the page and kmap_atomic() it either.  So probably
> easier to reject CCS_CC pre-OS framebuffers rather than trying to copy
> the framebuffer to non-stolen memory before use...

Yea, CCS_CC detection is missing.

In any case all CCS FBs would be rejected later, since the readout and
so also object allocation for any plane other than the first one is
missing.

Not sure either whether these would be ever used by BIOS.

I think for now we should just have CCS_CC also added in
skylake_get_initial_plane_config() and also debug print the modifier
there.

> Aside from that, I have a couple other comments below, but they're minor
> things that you can either ignore or deal with in followup patches, so
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@intel.com>
> > Cc: Shashank Sharma <shashank.sharma@intel.com>
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> (v5)
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 67 +++++++++++++++++--
> >  .../drm/i915/display/intel_display_types.h    |  3 +
> >  drivers/gpu/drm/i915/display/intel_sprite.c   | 11 ++-
> >  drivers/gpu/drm/i915/i915_reg.h               | 12 ++++
> >  4 files changed, 88 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 1c2becf47bfd..f264a0792d0b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1944,8 +1944,8 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> >  static bool is_gen12_ccs_modifier(u64 modifier)
> >  {
> >  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> >  	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> > -
> >  }
> >  
> >  static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > @@ -1953,6 +1953,12 @@ static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> >  	return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
> >  }
> >  
> > +static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
> > +{
> > +	return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
> > +	       plane == 2;
> > +}
> > +
> >  static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
> >  {
> >  	if (is_ccs_modifier(fb->modifier))
> > @@ -1974,6 +1980,9 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
> >  	WARN_ON(!is_ccs_modifier(fb->modifier) ||
> >  		ccs_plane < fb->format->num_planes / 2);
> >  
> > +	if (is_gen12_ccs_cc_plane(fb, ccs_plane))
> > +		return 0;
> > +
> >  	return ccs_plane - fb->format->num_planes / 2;
> >  }
> >  
> 
> Do we actually wind up ever calling this function with the CC plane?
> From what I can see all the callsites are in places where we've already
> bailed out if we see we're operating on the CC plane.

Yea, it's better to not allow using this func on the CC plane, will add
instead a check for that here.

> > @@ -2013,6 +2022,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  			return 128;
> >  		/* fall through */
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  		if (is_ccs_plane(fb, color_plane))
> >  			return 64;
> > @@ -2154,6 +2164,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> >  			return 256 * 1024;
> >  		return 0;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  		return 16 * 1024;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > @@ -2539,6 +2550,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  		return I915_TILING_Y;
> >  	default:
> > @@ -2608,6 +2620,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> >  	  .hsub = 2, .vsub = 2, .is_yuv = true },
> >  };
> >  
> > +/*
> > + * Same as gen12_ccs_formats[] above, but with additional surface used
> > + * to pass Clear Color information in plane 2 with 64 bits of data.
> > + */
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> > +	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > +	  .hsub = 1, .vsub = 1, },
> > +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> > +	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > +	  .hsub = 1, .vsub = 1, },
> > +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> > +	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> > +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> > +	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> > +};
> > +
> >  static const struct drm_format_info *
> >  lookup_format_info(const struct drm_format_info formats[],
> >  		   int num_formats, u32 format)
> > @@ -2636,6 +2667,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> >  		return lookup_format_info(gen12_ccs_formats,
> >  					  ARRAY_SIZE(gen12_ccs_formats),
> >  					  cmd->pixel_format);
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > +		return lookup_format_info(gen12_ccs_cc_formats,
> > +					  ARRAY_SIZE(gen12_ccs_cc_formats),
> > +					  cmd->pixel_format);
> >  	default:
> >  		return NULL;
> >  	}
> > @@ -2644,6 +2679,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> >  bool is_ccs_modifier(u64 modifier)
> >  {
> >  	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> >  	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> >  	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > @@ -2869,7 +2905,7 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
> >  	int ccs_x, ccs_y;
> >  	int main_x, main_y;
> >  
> > -	if (!is_ccs_plane(fb, ccs_plane))
> > +	if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
> >  		return 0;
> >  
> >  	intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
> > @@ -2921,6 +2957,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> >  		int x, y;
> >  		int ret;
> >  
> > +		/*
> > +		 * Plane 2 of Render Compression with Clear Color fb modifier
> > +		 * is consumed by the driver and not passed to DE. Skip the
> > +		 * arithmetic related to alignment and offset calculation.
> > +		 */
> > +		if (is_gen12_ccs_cc_plane(fb, i)) {
> > +			if (IS_ALIGNED(fb->offsets[2], PAGE_SIZE))
> > +				continue;
> > +			else
> > +				return -EINVAL;
> > +		}
> > +
> >  		cpp = fb->format->cpp[i];
> >  		intel_fb_plane_dims(&width, &height, fb, i);
> >  
> > @@ -3858,7 +3906,8 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
> >  		int hsub, vsub;
> >  		int x, y;
> >  
> > -		if (!is_ccs_plane(fb, ccs_plane))
> > +		if (!is_ccs_plane(fb, ccs_plane) ||
> > +		    is_gen12_ccs_cc_plane(fb, ccs_plane))
> >  			continue;
> >  
> >  		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
> > @@ -4512,6 +4561,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  		return PLANE_CTL_TILED_Y;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return PLANE_CTL_TILED_Y |
> > @@ -15360,6 +15410,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
> >  
> >  	plane_state->vma = vma;
> >  
> > +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) {
> > +		u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb),
> > +								  fb->offsets[2] >> PAGE_SHIFT));
> > +
> > +		plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32)
> > +				     | *(ccaddr + CC_VAL_LOWER_OFFSET);
> > +		kunmap_atomic(ccaddr);
> > +	}
> > +
> >  	return 0;
> 
> Some of the lines here are long enough that we should probably
> split/wrap them differently.
> 
> Personally I still feel like describing the CC plane as a C structure
> would make it easier to read/understand, even if the kernel driver
> doesn't actually use some of the fields in it.  Or at least just mapping
> the buffer as a u64* instead of a u32* so that we can read a single
> value from it rather than reading the low and high parts separately.

Ok, will try to improve it.

> 
> 
> Matt
> 
> >  }
> >  
> > @@ -16651,7 +16710,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> >  			goto err;
> >  		}
> >  
> > -		if (is_gen12_ccs_plane(fb, i)) {
> > +		if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
> >  			int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
> >  
> >  			if (fb->pitches[i] != ccs_aux_stride) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 3cdf44fa4164..ab01349b7273 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -607,6 +607,9 @@ struct intel_plane_state {
> >  	u32 planar_slave;
> >  
> >  	struct drm_intel_sprite_colorkey ckey;
> > +
> > +	/* Clear Color Value */
> > +	u64 ccval;
> >  };
> >  
> >  struct intel_initial_plane_config {
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index be56b6f56411..1a7037429d32 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -598,6 +598,7 @@ skl_program_plane(struct intel_plane *plane,
> >  	unsigned long irqflags;
> >  	u32 keymsk, keymax;
> >  	u32 plane_ctl = plane_state->ctl;
> > +	u64 ccval = plane_state->ccval;
> >  
> >  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> >  
> > @@ -640,6 +641,10 @@ skl_program_plane(struct intel_plane *plane,
> >  	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> >  		icl_program_input_csc(plane, crtc_state, plane_state);
> >  
> > +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> > +		intel_uncore_write64_fw(&dev_priv->uncore,
> > +					PLANE_CC_VAL(pipe, plane_id), ccval);
> > +
> >  	skl_write_plane_wm(plane, crtc_state);
> >  
> >  	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
> > @@ -2108,7 +2113,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> >  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> >  		return -EINVAL;
> >  	}
> > @@ -2582,6 +2588,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
> >  static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> >  	I915_FORMAT_MOD_Y_TILED,
> >  	I915_FORMAT_MOD_X_TILED,
> >  	DRM_FORMAT_MOD_LINEAR,
> > @@ -2590,6 +2597,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> >  
> >  static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> >  	I915_FORMAT_MOD_Y_TILED,
> >  	I915_FORMAT_MOD_X_TILED,
> >  	DRM_FORMAT_MOD_LINEAR,
> > @@ -2772,6 +2780,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  	case I915_FORMAT_MOD_X_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		break;
> >  	default:
> >  		return false;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b6dc735e85e1..d93451f3d8ae 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6841,6 +6841,8 @@ enum {
> >  #define _PLANE_KEYMAX_1_A			0x701a0
> >  #define _PLANE_KEYMAX_2_A			0x702a0
> >  #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
> > +#define _PLANE_CC_VAL_1_A			0x701b4
> > +#define _PLANE_CC_VAL_2_A			0x702b4
> >  #define _PLANE_AUX_DIST_1_A			0x701c0
> >  #define _PLANE_AUX_DIST_2_A			0x702c0
> >  #define _PLANE_AUX_OFFSET_1_A			0x701c4
> > @@ -6880,6 +6882,16 @@ enum {
> >  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
> >  #define _PLANE_NV12_BUF_CFG_2_A		0x70378
> >  
> > +#define _PLANE_CC_VAL_1_B			0x711b4
> > +#define _PLANE_CC_VAL_2_B			0x712b4
> > +#define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
> > +#define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
> > +#define PLANE_CC_VAL(pipe, plane)	\
> > +	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
> > +
> > +#define CC_VAL_LOWER_OFFSET		4
> > +#define CC_VAL_HIGHER_OFFSET		5
> > +
> >  /* Input CSC Register Definitions */
> >  #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
> >  #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
> > -- 
> > 2.22.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Render/media decompression support (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Render/media decompression support (rev2)
URL   : https://patchwork.freedesktop.org/series/71125/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
20f56e60829c drm/framebuffer: Format modifier for Intel Gen-12 render compression
23ba997a14b1 drm/i915: Use intel_tile_height() instead of re-implementing
1d89d4a9f731 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
efa1d8e8a1af drm/i915: Extract framebufer CCS offset checks into a function
8648416c288f drm/i915: Add helpers to select correct ccs/aux planes
81a7b00d91e6 drm/i915/tgl: Gen-12 render decompression
-:287: ERROR:CODE_INDENT: code indent should use tabs where possible
#287: FILE: drivers/gpu/drm/i915/display/intel_display.c:2802:
+^I        drm_format_info_block_width(fb->format, main_plane);$

total: 1 errors, 0 warnings, 0 checks, 434 lines checked
82ec90bd848a drm/i915/tgl: Make sure FBs have a correct CCS plane stride
136d04c5ec63 drm/i915: Skip rotated offset adjustment for unsupported modifiers
e528f5592152 drm/i915: Make sure Y slave planes get all the required state
10830ae44aa5 drm/i915: Make sure CCS YUV semiplanar format checks work
-:54: ERROR:CODE_INDENT: code indent should use tabs where possible
#54: FILE: drivers/gpu/drm/i915/display/intel_display.c:3825:
+^I^I^I^I^I        fb->modifier)) {$

-:54: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#54: FILE: drivers/gpu/drm/i915/display/intel_display.c:3825:
+	if (intel_format_info_is_yuv_semiplanar(fb->format,
+					        fb->modifier)) {

-:64: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t'
#64: FILE: drivers/gpu/drm/i915/display/intel_display.c:5755:
+		  uint64_t modifier, bool need_scaler)

total: 1 errors, 0 warnings, 2 checks, 142 lines checked
4d6d5ce67a4f drm/framebuffer: Format modifier for Intel Gen-12 media compression
3afe4941ecb1 drm/fb: Extend format_info member arrays to handle four planes
cd33cb3884df drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not

-:111: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#111: FILE: drivers/gpu/drm/i915/display/intel_display.c:2635:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

total: 0 errors, 2 warnings, 0 checks, 487 lines checked
5a820e552d62 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
210d9ea8c440 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
-:304: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#304: FILE: drivers/gpu/drm/i915/i915_reg.h:6889:
+#define PLANE_CC_VAL(pipe, plane)	\
+	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))

total: 0 errors, 0 warnings, 1 checks, 238 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: Render/media decompression support (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Render/media decompression support (rev2)
URL   : https://patchwork.freedesktop.org/series/71125/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7599 -> Patchwork_15830
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15830 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15830, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15830:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - fi-hsw-peppy:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-blb-e6850:       [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-blb-e6850/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-blb-e6850/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-u2:          [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-glk-dsi:         [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-pnv-d510:        [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-x1275:       [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-apl-guc:         [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-kefka:       [PASS][15] -> [FAIL][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-5557u:       [PASS][17] -> [FAIL][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6770hq:      [PASS][19] -> [FAIL][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-tgl-y:           [PASS][21] -> [FAIL][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-tgl-y/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-tgl-y/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6600u:       NOTRUN -> [FAIL][23]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-guc:         [PASS][24] -> [FAIL][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-nick:        [PASS][26] -> [FAIL][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-bsw-nick/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-bsw-nick/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-8809g:       [PASS][28] -> [FAIL][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-lmem:        [PASS][30] -> [FAIL][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-r:           [PASS][32] -> [FAIL][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cml-u2:          [PASS][34] -> [FAIL][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-n2820:       NOTRUN -> [FAIL][36]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-guc:         [PASS][37] -> [FAIL][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-icl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-icl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bxt-dsi:         [PASS][39] -> [FAIL][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-j1900:       [PASS][41] -> [FAIL][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-4770:        [PASS][43] -> [FAIL][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-guc:         [PASS][45] -> [FAIL][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-whl-u:           [PASS][47] -> [FAIL][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-u3:          [PASS][49] -> [FAIL][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-icl-u3/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-icl-u3/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-guc:         [PASS][51] -> [FAIL][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-n3050:       [PASS][53] -> [FAIL][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ivb-3770:        [PASS][55] -> [FAIL][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ilk-650:         [PASS][57] -> [FAIL][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-elk-e7500:       [PASS][59] -> [FAIL][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8700k:       [PASS][61] -> [FAIL][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-y:           [PASS][63] -> [FAIL][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-icl-y/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-icl-y/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-4770r:       [PASS][65] -> [FAIL][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-hsw-4770r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-hsw-4770r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
Known issues
------------

  Here are the changes found in Patchwork_15830 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][67] -> [FAIL][68] ([i915#178])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [PASS][69] -> [DMESG-FAIL][70] ([i915#770])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-hsw-4770r/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-byt-j1900:       [PASS][71] -> [INCOMPLETE][72] ([i915#45])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-n2820:       [TIMEOUT][73] ([i915#816]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-byt-n2820/igt@gem_close_race@basic-threads.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-byt-n2820/igt@gem_close_race@basic-threads.html

  * igt@gem_exec_gttfill@basic:
    - {fi-tgl-u}:         [INCOMPLETE][75] ([fdo#111593]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-tgl-u/igt@gem_exec_gttfill@basic.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-tgl-u/igt@gem_exec_gttfill@basic.html

  * igt@i915_selftest@live_blt:
    - fi-ivb-3770:        [DMESG-FAIL][77] ([i915#725]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-ivb-3770/igt@i915_selftest@live_blt.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-ivb-3770/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-8700k:       [INCOMPLETE][79] ([i915#424]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-kbl-x1275:       [DMESG-WARN][81] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][82] ([fdo#107139] / [i915#62] / [i915#92])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][83] ([i915#725]) -> [DMESG-FAIL][84] ([i915#770])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-hsw-4770/igt@i915_selftest@live_blt.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - fi-kbl-x1275:       [DMESG-WARN][85] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][86] ([i915#62] / [i915#92]) +4 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-x1275:       [DMESG-WARN][87] ([i915#62] / [i915#92]) -> [DMESG-WARN][88] ([i915#62] / [i915#92] / [i915#95]) +7 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7599/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
  [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
  [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (48 -> 40)
------------------------------

  Additional (1): fi-skl-6600u 
  Missing    (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bwr-2160 fi-gdg-551 fi-byt-clapper fi-bdw-samus fi-snb-2600 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7599 -> Patchwork_15830

  CI-20190529: 20190529
  CI_DRM_7599: 03dfaf2e5f39b632d0187544f3c988b8596f11b0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15830: 210d9ea8c440bfc29b443a3af46f937662264594 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

210d9ea8c440 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
5a820e552d62 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
cd33cb3884df drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
3afe4941ecb1 drm/fb: Extend format_info member arrays to handle four planes
4d6d5ce67a4f drm/framebuffer: Format modifier for Intel Gen-12 media compression
10830ae44aa5 drm/i915: Make sure CCS YUV semiplanar format checks work
e528f5592152 drm/i915: Make sure Y slave planes get all the required state
136d04c5ec63 drm/i915: Skip rotated offset adjustment for unsupported modifiers
82ec90bd848a drm/i915/tgl: Make sure FBs have a correct CCS plane stride
81a7b00d91e6 drm/i915/tgl: Gen-12 render decompression
8648416c288f drm/i915: Add helpers to select correct ccs/aux planes
efa1d8e8a1af drm/i915: Extract framebufer CCS offset checks into a function
1d89d4a9f731 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
23ba997a14b1 drm/i915: Use intel_tile_height() instead of re-implementing
20f56e60829c drm/framebuffer: Format modifier for Intel Gen-12 render compression

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15830/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Render/media decompression support (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Render/media decompression support (rev3)
URL   : https://patchwork.freedesktop.org/series/71125/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0db89922ad4d drm/framebuffer: Format modifier for Intel Gen-12 render compression
fdc1e07ba896 drm/i915: Use intel_tile_height() instead of re-implementing
ed420ff5d644 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
6dfdc0daaf3f drm/i915: Extract framebufer CCS offset checks into a function
a5ee2996f222 drm/i915: Add helpers to select correct ccs/aux planes
0754fb06980e drm/i915/tgl: Gen-12 render decompression
-:287: ERROR:CODE_INDENT: code indent should use tabs where possible
#287: FILE: drivers/gpu/drm/i915/display/intel_display.c:2802:
+^I        drm_format_info_block_width(fb->format, main_plane);$

total: 1 errors, 0 warnings, 0 checks, 434 lines checked
9e84b5f36583 drm/i915/tgl: Make sure FBs have a correct CCS plane stride
fe895b490e63 drm/i915: Skip rotated offset adjustment for unsupported modifiers
5f3205fa6fef drm/i915: Make sure Y slave planes get all the required state
586b5fcb3735 drm/i915: Make sure CCS YUV semiplanar format checks work
-:54: ERROR:CODE_INDENT: code indent should use tabs where possible
#54: FILE: drivers/gpu/drm/i915/display/intel_display.c:3856:
+^I^I^I^I^I        fb->modifier)) {$

-:54: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#54: FILE: drivers/gpu/drm/i915/display/intel_display.c:3856:
+	if (intel_format_info_is_yuv_semiplanar(fb->format,
+					        fb->modifier)) {

-:64: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t'
#64: FILE: drivers/gpu/drm/i915/display/intel_display.c:5786:
+		  uint64_t modifier, bool need_scaler)

total: 1 errors, 0 warnings, 2 checks, 142 lines checked
740c4f7ff980 drm/framebuffer: Format modifier for Intel Gen-12 media compression
b816e143d098 drm/fb: Extend format_info member arrays to handle four planes
2add322e7188 drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not

-:111: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#111: FILE: drivers/gpu/drm/i915/display/intel_display.c:2635:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

total: 0 errors, 2 warnings, 0 checks, 487 lines checked
ffc858def370 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
d3ec1213283b drm/i915/tgl: Add Clear Color support for TGL Render Decompression
-:304: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#304: FILE: drivers/gpu/drm/i915/i915_reg.h:6889:
+#define PLANE_CC_VAL(pipe, plane)	\
+	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))

total: 0 errors, 0 warnings, 1 checks, 238 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Render/media decompression support (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Render/media decompression support (rev3)
URL   : https://patchwork.freedesktop.org/series/71125/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7601 -> Patchwork_15836
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/index.html

Known issues
------------

  Here are the changes found in Patchwork_15836 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-j1900:       [PASS][1] -> [TIMEOUT][2] ([i915#816])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/fi-byt-j1900/igt@gem_close_race@basic-threads.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/fi-byt-j1900/igt@gem_close_race@basic-threads.html
    - fi-byt-n2820:       [PASS][3] -> [TIMEOUT][4] ([i915#816])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/fi-byt-n2820/igt@gem_close_race@basic-threads.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/fi-byt-n2820/igt@gem_close_race@basic-threads.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][5] -> [FAIL][6] ([fdo#111096] / [i915#323])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-hsw-4770:        [SKIP][7] ([fdo#109271]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
    - fi-icl-u3:          [DMESG-WARN][9] ([i915#109]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/fi-icl-u3/igt@i915_pm_rpm@module-reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/fi-icl-u3/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][11] ([i915#553] / [i915#725]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/fi-hsw-4770/igt@i915_selftest@live_blt.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - fi-kbl-x1275:       [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - fi-kbl-x1275:       [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +10 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (44 -> 39)
------------------------------

  Additional (5): fi-hsw-4770r fi-bsw-n3050 fi-ivb-3770 fi-snb-2600 fi-kbl-r 
  Missing    (10): fi-ilk-m540 fi-skl-6770hq fi-byt-squawks fi-ilk-650 fi-ctg-p8600 fi-bsw-kefka fi-tgl-y fi-byt-clapper fi-bsw-nick fi-skl-6600u 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7601 -> Patchwork_15836

  CI-20190529: 20190529
  CI_DRM_7601: ae3554cfc3c170d7eab0229497d7b1d10256038f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15836: d3ec1213283ba267c5f08ed430a9d1f234651d2c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d3ec1213283b drm/i915/tgl: Add Clear Color support for TGL Render Decompression
ffc858def370 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
2add322e7188 drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
b816e143d098 drm/fb: Extend format_info member arrays to handle four planes
740c4f7ff980 drm/framebuffer: Format modifier for Intel Gen-12 media compression
586b5fcb3735 drm/i915: Make sure CCS YUV semiplanar format checks work
5f3205fa6fef drm/i915: Make sure Y slave planes get all the required state
fe895b490e63 drm/i915: Skip rotated offset adjustment for unsupported modifiers
9e84b5f36583 drm/i915/tgl: Make sure FBs have a correct CCS plane stride
0754fb06980e drm/i915/tgl: Gen-12 render decompression
a5ee2996f222 drm/i915: Add helpers to select correct ccs/aux planes
6dfdc0daaf3f drm/i915: Extract framebufer CCS offset checks into a function
ed420ff5d644 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
fdc1e07ba896 drm/i915: Use intel_tile_height() instead of re-implementing
0db89922ad4d drm/framebuffer: Format modifier for Intel Gen-12 render compression

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Render/media decompression support (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Render/media decompression support (rev10)
URL   : https://patchwork.freedesktop.org/series/71125/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0e244fde713c drm/framebuffer: Format modifier for Intel Gen-12 render compression
b8b5d1fe8a14 drm/i915: Use intel_tile_height() instead of re-implementing
cfb29f3dfc82 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
302b5a034ca3 drm/i915: Extract framebufer CCS offset checks into a function
9c5b00d5c04f drm/i915: Add helpers to select correct ccs/aux planes
5b81b67242e0 drm/i915/tgl: Gen-12 render decompression
31001f05269d drm/i915/tgl: Make sure FBs have a correct CCS plane stride
bc4f1cd5e087 drm/i915: Skip rotated offset adjustment for unsupported modifiers
38863af06562 drm/i915: Make sure Y slave planes get all the required state
a3117f225e10 drm/i915: Make sure CCS YUV semiplanar format checks work
-:55: ERROR:CODE_INDENT: code indent should use tabs where possible
#55: FILE: drivers/gpu/drm/i915/display/intel_display.c:3855:
+^I^I^I^I^I        fb->modifier)) {$

-:55: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#55: FILE: drivers/gpu/drm/i915/display/intel_display.c:3855:
+	if (intel_format_info_is_yuv_semiplanar(fb->format,
+					        fb->modifier)) {

-:65: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t'
#65: FILE: drivers/gpu/drm/i915/display/intel_display.c:5785:
+		  uint64_t modifier, bool need_scaler)

total: 1 errors, 0 warnings, 2 checks, 142 lines checked
428f9f32c6f5 drm/framebuffer: Format modifier for Intel Gen-12 media compression
78444dfcb223 drm/fb: Extend format_info member arrays to handle four planes
e9bbc97aba9f drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not

-:124: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#124: FILE: drivers/gpu/drm/i915/display/intel_display.c:2644:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

total: 0 errors, 2 warnings, 0 checks, 478 lines checked
8420af3f7552 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
64e5f7fd003b drm/i915/tgl: Add Clear Color support for TGL Render Decompression
-:304: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#304: FILE: drivers/gpu/drm/i915/i915_reg.h:6889:
+#define PLANE_CC_VAL(pipe, plane)	\
+	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))

total: 0 errors, 0 warnings, 1 checks, 238 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Render/media decompression support (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Render/media decompression support (rev10)
URL   : https://patchwork.freedesktop.org/series/71125/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7612 -> Patchwork_15859
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/index.html

Known issues
------------

  Here are the changes found in Patchwork_15859 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-j1900:       [PASS][1] -> [TIMEOUT][2] ([i915#816])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/fi-byt-j1900/igt@gem_close_race@basic-threads.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/fi-byt-j1900/igt@gem_close_race@basic-threads.html
    - fi-byt-n2820:       [PASS][3] -> [TIMEOUT][4] ([i915#816])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/fi-byt-n2820/igt@gem_close_race@basic-threads.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/fi-byt-n2820/igt@gem_close_race@basic-threads.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [PASS][5] -> [DMESG-FAIL][6] ([i915#770])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/fi-hsw-4770r/igt@i915_selftest@live_blt.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][7] ([i915#725]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/fi-hsw-4770/igt@i915_selftest@live_blt.html

  
#### Warnings ####

  * igt@i915_module_load@reload:
    - fi-icl-u2:          [DMESG-WARN][9] ([i915#109] / [i915#289]) -> [DMESG-WARN][10] ([i915#289])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/fi-icl-u2/igt@i915_module_load@reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/fi-icl-u2/igt@i915_module_load@reload.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-kbl-x1275:       [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
    - fi-kbl-x1275:       [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/fi-kbl-x1275/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/fi-kbl-x1275/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (49 -> 34)
------------------------------

  Additional (2): fi-skl-guc fi-cfl-guc 
  Missing    (17): fi-ilk-m540 fi-bdw-samus fi-bdw-5557u fi-kbl-7560u fi-hsw-4200u fi-hsw-peppy fi-glk-dsi fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-blb-e6850 fi-tgl-y fi-byt-clapper fi-bsw-nick fi-skl-6600u fi-kbl-r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7612 -> Patchwork_15859

  CI-20190529: 20190529
  CI_DRM_7612: d8427504d16e1aa87eab972f812c02478522bd70 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15859: 64e5f7fd003bf2907733d63def8aeccf77297e40 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

64e5f7fd003b drm/i915/tgl: Add Clear Color support for TGL Render Decompression
8420af3f7552 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
e9bbc97aba9f drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
78444dfcb223 drm/fb: Extend format_info member arrays to handle four planes
428f9f32c6f5 drm/framebuffer: Format modifier for Intel Gen-12 media compression
a3117f225e10 drm/i915: Make sure CCS YUV semiplanar format checks work
38863af06562 drm/i915: Make sure Y slave planes get all the required state
bc4f1cd5e087 drm/i915: Skip rotated offset adjustment for unsupported modifiers
31001f05269d drm/i915/tgl: Make sure FBs have a correct CCS plane stride
5b81b67242e0 drm/i915/tgl: Gen-12 render decompression
9c5b00d5c04f drm/i915: Add helpers to select correct ccs/aux planes
302b5a034ca3 drm/i915: Extract framebufer CCS offset checks into a function
cfb29f3dfc82 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
b8b5d1fe8a14 drm/i915: Use intel_tile_height() instead of re-implementing
0e244fde713c drm/framebuffer: Format modifier for Intel Gen-12 render compression

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Render/media decompression support (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Render/media decompression support (rev3)
URL   : https://patchwork.freedesktop.org/series/71125/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7601_full -> Patchwork_15836_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15836_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15836_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15836_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-tglb:         [PASS][1] -> [FAIL][2] +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  
#### Warnings ####

  * igt@runner@aborted:
    - shard-apl:          [FAIL][3] ([i915#716]) -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@runner@aborted.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl6/igt@runner@aborted.html

  
New tests
---------

  New tests have been introduced between CI_DRM_7601_full and Patchwork_15836_full:

### New Piglit tests (1) ###

  * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_vec3_array3-position-double_dmat2_array2:
    - Statuses : 1 fail(s)
    - Exec time: [0.16] s

  

Known issues
------------

  Here are the changes found in Patchwork_15836_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-tglb:         [PASS][5] -> [INCOMPLETE][6] ([i915#456])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_ctx_persistence@rcs0-mixed-process:
    - shard-apl:          [PASS][7] -> [FAIL][8] ([i915#679])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl8/igt@gem_ctx_persistence@rcs0-mixed-process.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl3/igt@gem_ctx_persistence@rcs0-mixed-process.html

  * igt@gem_ctx_shared@exec-shared-gtt-bsd:
    - shard-kbl:          [PASS][9] -> [FAIL][10] ([i915#616])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl4/igt@gem_ctx_shared@exec-shared-gtt-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl4/igt@gem_ctx_shared@exec-shared-gtt-bsd.html

  * igt@gem_exec_reloc@basic-cpu-gtt-active:
    - shard-skl:          [PASS][11] -> [DMESG-WARN][12] ([i915#109]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl5/igt@gem_exec_reloc@basic-cpu-gtt-active.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl7/igt@gem_exec_reloc@basic-cpu-gtt-active.html

  * igt@gem_exec_schedule@smoketest-vebox:
    - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([i915#707])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@gem_exec_schedule@smoketest-vebox.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/igt@gem_exec_schedule@smoketest-vebox.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-hsw:          [PASS][15] -> [FAIL][16] ([i915#520])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][17] -> [FAIL][18] ([i915#644])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [PASS][19] -> [INCOMPLETE][20] ([i915#69])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl4/igt@gem_softpin@noreloc-s3.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl9/igt@gem_softpin@noreloc-s3.html

  * igt@gem_sync@basic-many-each:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([i915#472] / [i915#707])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@gem_sync@basic-many-each.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@gem_sync@basic-many-each.html

  * igt@gem_sync@basic-store-each:
    - shard-tglb:         [PASS][23] -> [INCOMPLETE][24] ([i915#435] / [i915#472])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@gem_sync@basic-store-each.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/igt@gem_sync@basic-store-each.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([i915#456] / [i915#460]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@i915_pm_rpm@system-suspend-modeset.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([i915#54])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#79])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-tglb:         [PASS][33] -> [FAIL][34] ([i915#49])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-tglb:         [PASS][35] -> [DMESG-WARN][36] ([i915#766])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [PASS][37] -> [DMESG-WARN][38] ([i915#180]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-tglb:         [PASS][39] -> [INCOMPLETE][40] ([i915#667])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][41] -> [FAIL][42] ([fdo#108145])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@prime_vgem@basic-sync-default:
    - shard-apl:          [PASS][43] -> [INCOMPLETE][44] ([fdo#103927] / [i915#409])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl3/igt@prime_vgem@basic-sync-default.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl6/igt@prime_vgem@basic-sync-default.html

  
#### Possible fixes ####

  * igt@gem_ctx_shared@q-smoketest-vebox:
    - shard-tglb:         [INCOMPLETE][45] ([fdo#111735]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb9/igt@gem_ctx_shared@q-smoketest-vebox.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@gem_ctx_shared@q-smoketest-vebox.html

  * igt@gem_eio@kms:
    - shard-snb:          [INCOMPLETE][47] ([i915#82]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-snb6/igt@gem_eio@kms.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-snb7/igt@gem_eio@kms.html

  * igt@gem_exec_flush@basic-batch-kernel-default-uc:
    - shard-hsw:          [INCOMPLETE][49] ([i915#61]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-hsw2/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-hsw1/igt@gem_exec_flush@basic-batch-kernel-default-uc.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [INCOMPLETE][51] ([i915#456] / [i915#472]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@gem_exec_suspend@basic-s0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-kbl:          [FAIL][53] ([i915#644]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * {igt@gen9_exec_parse@allowed-single}:
    - shard-apl:          [DMESG-WARN][55] ([i915#716]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@gen9_exec_parse@allowed-single.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl2/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_selftest@live_requests:
    - shard-tglb:         [INCOMPLETE][57] ([fdo#112057]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@i915_selftest@live_requests.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/igt@i915_selftest@live_requests.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl4/igt@i915_suspend@sysfs-reader.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl4/igt@i915_suspend@sysfs-reader.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo:
    - shard-tglb:         [SKIP][61] ([i915#400]) -> [PASS][62] +19 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_ccs@pipe-b-ccs-on-another-bo.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/igt@kms_ccs@pipe-b-ccs-on-another-bo.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
    - shard-skl:          [FAIL][65] ([i915#54]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [INCOMPLETE][67] ([i915#435] / [i915#456] / [i915#460]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-apl:          [FAIL][69] ([i915#79]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl8/igt@kms_flip@flip-vs-expired-vblank.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl2/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [INCOMPLETE][71] ([i915#221]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl9/igt@kms_flip@flip-vs-suspend.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglb:         [INCOMPLETE][73] ([i915#474] / [i915#667]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-tglb:         [FAIL][75] ([i915#49]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
    - shard-tglb:         [INCOMPLETE][77] ([i915#435] / [i915#667]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-tglb:         [INCOMPLETE][79] ([i915#456] / [i915#460]) -> [PASS][80] +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@perf@oa-exponents:
    - shard-kbl:          [INCOMPLETE][81] ([fdo#103665]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl7/igt@perf@oa-exponents.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl3/igt@perf@oa-exponents.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-nonpriv:
    - shard-tglb:         [SKIP][83] ([fdo#111912] / [fdo#112080]) -> [SKIP][84] ([fdo#112080])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@gem_ctx_isolation@vcs2-nonpriv.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@gem_ctx_isolation@vcs2-nonpriv.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - shard-snb:          [INCOMPLETE][85] ([i915#82]) -> [SKIP][86] ([fdo#109271])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-snb6/igt@i915_pm_rpm@modeset-non-lpsp.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-snb1/igt@i915_pm_rpm@modeset-non-lpsp.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#112057]: https://bugs.freedesktop.org/show_bug.cgi?id=112057
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
  [i915#400]: https://gitlab.freedesktop.org/drm/intel/issues/400
  [i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
  [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
  [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
  [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#616]: https://gitlab.freedesktop.org/drm/intel/issues/616
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
  [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#766]: https://gitlab.freedesktop.org/drm/intel/issues/766
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7601 -> Patchwork_15836

  CI-20190529: 20190529
  CI_DRM_7601: ae3554cfc3c170d7eab0229497d7b1d10256038f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15836: d3ec1213283ba267c5f08ed430a9d1f234651d2c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Render/media decompression support (rev3)

[Imre Deak]

On Fri, Dec 20, 2019 at 01:12:51PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/tgl: Render/media decompression support (rev3)
> URL   : https://patchwork.freedesktop.org/series/71125/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_7601_full -> Patchwork_15836_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_15836_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_15836_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
>
>   Here are the unknown changes that may have been introduced in Patchwork_15836_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
>     - shard-tglb:         [PASS][1] -> [FAIL][2] +2 similar issues
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

This is expected as IGT can't handle yet YUV CCS surfaces. I've sent a
patch to skip this part of the test:
https://patchwork.freedesktop.org/series/71214/

>   
> #### Warnings ####
> 
>   * igt@runner@aborted:
>     - shard-apl:          [FAIL][3] ([i915#716]) -> [FAIL][4]
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@runner@aborted.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl6/igt@runner@aborted.html

Can't see how this can be related, GEN9 should not be affected by the
patches.
It looks like
https://gitlab.freedesktop.org/drm/intel/issues/409

> 
>   
> New tests
> ---------
> 
>   New tests have been introduced between CI_DRM_7601_full and Patchwork_15836_full:
> 
> ### New Piglit tests (1) ###
> 
>   * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_vec3_array3-position-double_dmat2_array2:
>     - Statuses : 1 fail(s)
>     - Exec time: [0.16] s
> 
>   
> 
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_15836_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_ctx_isolation@vcs0-s3:
>     - shard-tglb:         [PASS][5] -> [INCOMPLETE][6] ([i915#456])
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html
> 
>   * igt@gem_ctx_persistence@rcs0-mixed-process:
>     - shard-apl:          [PASS][7] -> [FAIL][8] ([i915#679])
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl8/igt@gem_ctx_persistence@rcs0-mixed-process.html
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl3/igt@gem_ctx_persistence@rcs0-mixed-process.html
> 
>   * igt@gem_ctx_shared@exec-shared-gtt-bsd:
>     - shard-kbl:          [PASS][9] -> [FAIL][10] ([i915#616])
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl4/igt@gem_ctx_shared@exec-shared-gtt-bsd.html
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl4/igt@gem_ctx_shared@exec-shared-gtt-bsd.html
> 
>   * igt@gem_exec_reloc@basic-cpu-gtt-active:
>     - shard-skl:          [PASS][11] -> [DMESG-WARN][12] ([i915#109]) +1 similar issue
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl5/igt@gem_exec_reloc@basic-cpu-gtt-active.html
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl7/igt@gem_exec_reloc@basic-cpu-gtt-active.html
> 
>   * igt@gem_exec_schedule@smoketest-vebox:
>     - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([i915#707])
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@gem_exec_schedule@smoketest-vebox.html
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/igt@gem_exec_schedule@smoketest-vebox.html
> 
>   * igt@gem_persistent_relocs@forked-interruptible-thrashing:
>     - shard-hsw:          [PASS][15] -> [FAIL][16] ([i915#520])
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
> 
>   * igt@gem_ppgtt@flink-and-close-vma-leak:
>     - shard-glk:          [PASS][17] -> [FAIL][18] ([i915#644])
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
> 
>   * igt@gem_softpin@noreloc-s3:
>     - shard-skl:          [PASS][19] -> [INCOMPLETE][20] ([i915#69])
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl4/igt@gem_softpin@noreloc-s3.html
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl9/igt@gem_softpin@noreloc-s3.html
> 
>   * igt@gem_sync@basic-many-each:
>     - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([i915#472] / [i915#707])
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@gem_sync@basic-many-each.html
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@gem_sync@basic-many-each.html
> 
>   * igt@gem_sync@basic-store-each:
>     - shard-tglb:         [PASS][23] -> [INCOMPLETE][24] ([i915#435] / [i915#472])
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@gem_sync@basic-store-each.html
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/igt@gem_sync@basic-store-each.html
> 
>   * igt@i915_pm_rpm@system-suspend-modeset:
>     - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([i915#456] / [i915#460]) +2 similar issues
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@i915_pm_rpm@system-suspend-modeset.html
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/igt@i915_pm_rpm@system-suspend-modeset.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding:
>     - shard-skl:          [PASS][27] -> [FAIL][28] ([i915#54])
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-suspend:
>     - shard-kbl:          [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank:
>     - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#79])
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
>     - shard-tglb:         [PASS][33] -> [FAIL][34] ([i915#49])
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-rte:
>     - shard-tglb:         [PASS][35] -> [DMESG-WARN][36] ([i915#766])
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-suspend:
>     - shard-apl:          [PASS][37] -> [DMESG-WARN][38] ([i915#180]) +1 similar issue
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
> 
>   * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
>     - shard-tglb:         [PASS][39] -> [INCOMPLETE][40] ([i915#667])
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
> 
>   * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
>     - shard-skl:          [PASS][41] -> [FAIL][42] ([fdo#108145])
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
> 
>   * igt@prime_vgem@basic-sync-default:
>     - shard-apl:          [PASS][43] -> [INCOMPLETE][44] ([fdo#103927] / [i915#409])
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl3/igt@prime_vgem@basic-sync-default.html
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl6/igt@prime_vgem@basic-sync-default.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_ctx_shared@q-smoketest-vebox:
>     - shard-tglb:         [INCOMPLETE][45] ([fdo#111735]) -> [PASS][46]
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb9/igt@gem_ctx_shared@q-smoketest-vebox.html
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@gem_ctx_shared@q-smoketest-vebox.html
> 
>   * igt@gem_eio@kms:
>     - shard-snb:          [INCOMPLETE][47] ([i915#82]) -> [PASS][48]
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-snb6/igt@gem_eio@kms.html
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-snb7/igt@gem_eio@kms.html
> 
>   * igt@gem_exec_flush@basic-batch-kernel-default-uc:
>     - shard-hsw:          [INCOMPLETE][49] ([i915#61]) -> [PASS][50]
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-hsw2/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-hsw1/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
> 
>   * igt@gem_exec_suspend@basic-s0:
>     - shard-tglb:         [INCOMPLETE][51] ([i915#456] / [i915#472]) -> [PASS][52]
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@gem_exec_suspend@basic-s0.html
>    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/igt@gem_exec_suspend@basic-s0.html
> 
>   * igt@gem_ppgtt@flink-and-close-vma-leak:
>     - shard-kbl:          [FAIL][53] ([i915#644]) -> [PASS][54]
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
>    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
> 
>   * {igt@gen9_exec_parse@allowed-single}:
>     - shard-apl:          [DMESG-WARN][55] ([i915#716]) -> [PASS][56]
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@gen9_exec_parse@allowed-single.html
>    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl2/igt@gen9_exec_parse@allowed-single.html
> 
>   * igt@i915_selftest@live_requests:
>     - shard-tglb:         [INCOMPLETE][57] ([fdo#112057]) -> [PASS][58]
>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@i915_selftest@live_requests.html
>    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/igt@i915_selftest@live_requests.html
> 
>   * igt@i915_suspend@sysfs-reader:
>     - shard-apl:          [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +2 similar issues
>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl4/igt@i915_suspend@sysfs-reader.html
>    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl4/igt@i915_suspend@sysfs-reader.html
> 
>   * igt@kms_ccs@pipe-b-ccs-on-another-bo:
>     - shard-tglb:         [SKIP][61] ([i915#400]) -> [PASS][62] +19 similar issues
>    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_ccs@pipe-b-ccs-on-another-bo.html
>    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/igt@kms_ccs@pipe-b-ccs-on-another-bo.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-suspend:
>     - shard-kbl:          [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +2 similar issues
>    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
>     - shard-skl:          [FAIL][65] ([i915#54]) -> [PASS][66]
>    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
>    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
> 
>   * igt@kms_fbcon_fbt@fbc-suspend:
>     - shard-tglb:         [INCOMPLETE][67] ([i915#435] / [i915#456] / [i915#460]) -> [PASS][68]
>    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html
>    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank:
>     - shard-apl:          [FAIL][69] ([i915#79]) -> [PASS][70]
>    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl8/igt@kms_flip@flip-vs-expired-vblank.html
>    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl2/igt@kms_flip@flip-vs-expired-vblank.html
> 
>   * igt@kms_flip@flip-vs-suspend:
>     - shard-skl:          [INCOMPLETE][71] ([i915#221]) -> [PASS][72]
>    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl9/igt@kms_flip@flip-vs-suspend.html
>    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl6/igt@kms_flip@flip-vs-suspend.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
>     - shard-tglb:         [INCOMPLETE][73] ([i915#474] / [i915#667]) -> [PASS][74]
>    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html
>    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
>     - shard-tglb:         [FAIL][75] ([i915#49]) -> [PASS][76]
>    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
>    [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
> 
>   * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
>     - shard-tglb:         [INCOMPLETE][77] ([i915#435] / [i915#667]) -> [PASS][78]
>    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
>    [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
>     - shard-tglb:         [INCOMPLETE][79] ([i915#456] / [i915#460]) -> [PASS][80] +2 similar issues
>    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
>    [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
> 
>   * igt@perf@oa-exponents:
>     - shard-kbl:          [INCOMPLETE][81] ([fdo#103665]) -> [PASS][82]
>    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl7/igt@perf@oa-exponents.html
>    [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl3/igt@perf@oa-exponents.html
> 
>   
> #### Warnings ####
> 
>   * igt@gem_ctx_isolation@vcs2-nonpriv:
>     - shard-tglb:         [SKIP][83] ([fdo#111912] / [fdo#112080]) -> [SKIP][84] ([fdo#112080])
>    [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@gem_ctx_isolation@vcs2-nonpriv.html
>    [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@gem_ctx_isolation@vcs2-nonpriv.html
> 
>   * igt@i915_pm_rpm@modeset-non-lpsp:
>     - shard-snb:          [INCOMPLETE][85] ([i915#82]) -> [SKIP][86] ([fdo#109271])
>    [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-snb6/igt@i915_pm_rpm@modeset-non-lpsp.html
>    [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-snb1/igt@i915_pm_rpm@modeset-non-lpsp.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
>   [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
>   [fdo#112057]: https://bugs.freedesktop.org/show_bug.cgi?id=112057
>   [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
>   [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
>   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
>   [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
>   [i915#400]: https://gitlab.freedesktop.org/drm/intel/issues/400
>   [i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
>   [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
>   [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
>   [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
>   [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
>   [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
>   [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
>   [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520
>   [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
>   [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
>   [i915#616]: https://gitlab.freedesktop.org/drm/intel/issues/616
>   [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
>   [i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
>   [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
>   [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
>   [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
>   [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
>   [i915#766]: https://gitlab.freedesktop.org/drm/intel/issues/766
>   [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>   [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
> 
> 
> Participating hosts (11 -> 11)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * Linux: CI_DRM_7601 -> Patchwork_15836
> 
>   CI-20190529: 20190529
>   CI_DRM_7601: ae3554cfc3c170d7eab0229497d7b1d10256038f @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_15836: d3ec1213283ba267c5f08ed430a9d1f234651d2c @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/index.html
_______________________________________________
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Render/media decompression support (rev3)

[Vudum, Lakshminarayana]

Imre, Acknowledged and re-reported.
https://patchwork.freedesktop.org/series/71125/

Lakshmi.
-----Original Message-----
From: Imre Deak <imre.deak@intel.com> 
Sent: Friday, December 20, 2019 5:32 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/tgl: Render/media decompression support (rev3)

On Fri, Dec 20, 2019 at 01:12:51PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/tgl: Render/media decompression support (rev3)
> URL   : https://patchwork.freedesktop.org/series/71125/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_7601_full -> Patchwork_15836_full 
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_15836_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_15836_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
>
>   Here are the unknown changes that may have been introduced in Patchwork_15836_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
>     - shard-tglb:         [PASS][1] -> [FAIL][2] +2 similar issues
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
>    [2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/i
> gt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

This is expected as IGT can't handle yet YUV CCS surfaces. I've sent a patch to skip this part of the test:
https://patchwork.freedesktop.org/series/71214/

>   
> #### Warnings ####
> 
>   * igt@runner@aborted:
>     - shard-apl:          [FAIL][3] ([i915#716]) -> [FAIL][4]
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@runner@aborted.html
>    [4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl6/ig
> t@runner@aborted.html

Can't see how this can be related, GEN9 should not be affected by the patches.
It looks like
https://gitlab.freedesktop.org/drm/intel/issues/409

> 
>   
> New tests
> ---------
> 
>   New tests have been introduced between CI_DRM_7601_full and Patchwork_15836_full:
> 
> ### New Piglit tests (1) ###
> 
>   * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_vec3_array3-position-double_dmat2_array2:
>     - Statuses : 1 fail(s)
>     - Exec time: [0.16] s
> 
>   
> 
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_15836_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_ctx_isolation@vcs0-s3:
>     - shard-tglb:         [PASS][5] -> [INCOMPLETE][6] ([i915#456])
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html
>    [6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/i
> gt@gem_ctx_isolation@vcs0-s3.html
> 
>   * igt@gem_ctx_persistence@rcs0-mixed-process:
>     - shard-apl:          [PASS][7] -> [FAIL][8] ([i915#679])
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl8/igt@gem_ctx_persistence@rcs0-mixed-process.html
>    [8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl3/ig
> t@gem_ctx_persistence@rcs0-mixed-process.html
> 
>   * igt@gem_ctx_shared@exec-shared-gtt-bsd:
>     - shard-kbl:          [PASS][9] -> [FAIL][10] ([i915#616])
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl4/igt@gem_ctx_shared@exec-shared-gtt-bsd.html
>    [10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl4/ig
> t@gem_ctx_shared@exec-shared-gtt-bsd.html
> 
>   * igt@gem_exec_reloc@basic-cpu-gtt-active:
>     - shard-skl:          [PASS][11] -> [DMESG-WARN][12] ([i915#109]) +1 similar issue
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl5/igt@gem_exec_reloc@basic-cpu-gtt-active.html
>    [12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl7/ig
> t@gem_exec_reloc@basic-cpu-gtt-active.html
> 
>   * igt@gem_exec_schedule@smoketest-vebox:
>     - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([i915#707])
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@gem_exec_schedule@smoketest-vebox.html
>    [14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/i
> gt@gem_exec_schedule@smoketest-vebox.html
> 
>   * igt@gem_persistent_relocs@forked-interruptible-thrashing:
>     - shard-hsw:          [PASS][15] -> [FAIL][16] ([i915#520])
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
>    [16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-hsw2/ig
> t@gem_persistent_relocs@forked-interruptible-thrashing.html
> 
>   * igt@gem_ppgtt@flink-and-close-vma-leak:
>     - shard-glk:          [PASS][17] -> [FAIL][18] ([i915#644])
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
>    [18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-glk7/ig
> t@gem_ppgtt@flink-and-close-vma-leak.html
> 
>   * igt@gem_softpin@noreloc-s3:
>     - shard-skl:          [PASS][19] -> [INCOMPLETE][20] ([i915#69])
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl4/igt@gem_softpin@noreloc-s3.html
>    [20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl9/ig
> t@gem_softpin@noreloc-s3.html
> 
>   * igt@gem_sync@basic-many-each:
>     - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([i915#472] / [i915#707])
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@gem_sync@basic-many-each.html
>    [22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/i
> gt@gem_sync@basic-many-each.html
> 
>   * igt@gem_sync@basic-store-each:
>     - shard-tglb:         [PASS][23] -> [INCOMPLETE][24] ([i915#435] / [i915#472])
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@gem_sync@basic-store-each.html
>    [24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/i
> gt@gem_sync@basic-store-each.html
> 
>   * igt@i915_pm_rpm@system-suspend-modeset:
>     - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([i915#456] / [i915#460]) +2 similar issues
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@i915_pm_rpm@system-suspend-modeset.html
>    [26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/i
> gt@i915_pm_rpm@system-suspend-modeset.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding:
>     - shard-skl:          [PASS][27] -> [FAIL][28] ([i915#54])
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html
>    [28]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl1/ig
> t@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-suspend:
>     - shard-kbl:          [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>    [30]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl6/ig
> t@kms_cursor_crc@pipe-c-cursor-suspend.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank:
>     - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#79])
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
>    [32]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl5/ig
> t@kms_flip@flip-vs-expired-vblank.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
>     - shard-tglb:         [PASS][33] -> [FAIL][34] ([i915#49])
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
>    [34]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/i
> gt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-rte:
>     - shard-tglb:         [PASS][35] -> [DMESG-WARN][36] ([i915#766])
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
>    [36]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/i
> gt@kms_frontbuffer_tracking@fbc-1p-rte.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-suspend:
>     - shard-apl:          [PASS][37] -> [DMESG-WARN][38] ([i915#180]) +1 similar issue
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
>    [38]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl4/ig
> t@kms_frontbuffer_tracking@fbc-suspend.html
> 
>   * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
>     - shard-tglb:         [PASS][39] -> [INCOMPLETE][40] ([i915#667])
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
>    [40]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/i
> gt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
> 
>   * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
>     - shard-skl:          [PASS][41] -> [FAIL][42] ([fdo#108145])
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
>    [42]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl5/ig
> t@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
> 
>   * igt@prime_vgem@basic-sync-default:
>     - shard-apl:          [PASS][43] -> [INCOMPLETE][44] ([fdo#103927] / [i915#409])
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl3/igt@prime_vgem@basic-sync-default.html
>    [44]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl6/ig
> t@prime_vgem@basic-sync-default.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_ctx_shared@q-smoketest-vebox:
>     - shard-tglb:         [INCOMPLETE][45] ([fdo#111735]) -> [PASS][46]
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb9/igt@gem_ctx_shared@q-smoketest-vebox.html
>    [46]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/i
> gt@gem_ctx_shared@q-smoketest-vebox.html
> 
>   * igt@gem_eio@kms:
>     - shard-snb:          [INCOMPLETE][47] ([i915#82]) -> [PASS][48]
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-snb6/igt@gem_eio@kms.html
>    [48]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-snb7/ig
> t@gem_eio@kms.html
> 
>   * igt@gem_exec_flush@basic-batch-kernel-default-uc:
>     - shard-hsw:          [INCOMPLETE][49] ([i915#61]) -> [PASS][50]
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-hsw2/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
>    [50]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-hsw1/ig
> t@gem_exec_flush@basic-batch-kernel-default-uc.html
> 
>   * igt@gem_exec_suspend@basic-s0:
>     - shard-tglb:         [INCOMPLETE][51] ([i915#456] / [i915#472]) -> [PASS][52]
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@gem_exec_suspend@basic-s0.html
>    [52]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/i
> gt@gem_exec_suspend@basic-s0.html
> 
>   * igt@gem_ppgtt@flink-and-close-vma-leak:
>     - shard-kbl:          [FAIL][53] ([i915#644]) -> [PASS][54]
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
>    [54]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl3/ig
> t@gem_ppgtt@flink-and-close-vma-leak.html
> 
>   * {igt@gen9_exec_parse@allowed-single}:
>     - shard-apl:          [DMESG-WARN][55] ([i915#716]) -> [PASS][56]
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@gen9_exec_parse@allowed-single.html
>    [56]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl2/ig
> t@gen9_exec_parse@allowed-single.html
> 
>   * igt@i915_selftest@live_requests:
>     - shard-tglb:         [INCOMPLETE][57] ([fdo#112057]) -> [PASS][58]
>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@i915_selftest@live_requests.html
>    [58]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/i
> gt@i915_selftest@live_requests.html
> 
>   * igt@i915_suspend@sysfs-reader:
>     - shard-apl:          [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +2 similar issues
>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl4/igt@i915_suspend@sysfs-reader.html
>    [60]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl4/ig
> t@i915_suspend@sysfs-reader.html
> 
>   * igt@kms_ccs@pipe-b-ccs-on-another-bo:
>     - shard-tglb:         [SKIP][61] ([i915#400]) -> [PASS][62] +19 similar issues
>    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_ccs@pipe-b-ccs-on-another-bo.html
>    [62]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/i
> gt@kms_ccs@pipe-b-ccs-on-another-bo.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-suspend:
>     - shard-kbl:          [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +2 similar issues
>    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>    [64]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl6/ig
> t@kms_cursor_crc@pipe-a-cursor-suspend.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
>     - shard-skl:          [FAIL][65] ([i915#54]) -> [PASS][66]
>    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
>    [66]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl10/i
> gt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
> 
>   * igt@kms_fbcon_fbt@fbc-suspend:
>     - shard-tglb:         [INCOMPLETE][67] ([i915#435] / [i915#456] / [i915#460]) -> [PASS][68]
>    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html
>    [68]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/i
> gt@kms_fbcon_fbt@fbc-suspend.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank:
>     - shard-apl:          [FAIL][69] ([i915#79]) -> [PASS][70]
>    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl8/igt@kms_flip@flip-vs-expired-vblank.html
>    [70]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl2/ig
> t@kms_flip@flip-vs-expired-vblank.html
> 
>   * igt@kms_flip@flip-vs-suspend:
>     - shard-skl:          [INCOMPLETE][71] ([i915#221]) -> [PASS][72]
>    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl9/igt@kms_flip@flip-vs-suspend.html
>    [72]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl6/ig
> t@kms_flip@flip-vs-suspend.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
>     - shard-tglb:         [INCOMPLETE][73] ([i915#474] / [i915#667]) -> [PASS][74]
>    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html
>    [74]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb1/i
> gt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.ht
> ml
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
>     - shard-tglb:         [FAIL][75] ([i915#49]) -> [PASS][76]
>    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
>    [76]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/i
> gt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
> 
>   * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
>     - shard-tglb:         [INCOMPLETE][77] ([i915#435] / [i915#667]) -> [PASS][78]
>    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
>    [78]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb4/i
> gt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
>     - shard-tglb:         [INCOMPLETE][79] ([i915#456] / [i915#460]) -> [PASS][80] +2 similar issues
>    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
>    [80]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/i
> gt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
> 
>   * igt@perf@oa-exponents:
>     - shard-kbl:          [INCOMPLETE][81] ([fdo#103665]) -> [PASS][82]
>    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl7/igt@perf@oa-exponents.html
>    [82]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl3/ig
> t@perf@oa-exponents.html
> 
>   
> #### Warnings ####
> 
>   * igt@gem_ctx_isolation@vcs2-nonpriv:
>     - shard-tglb:         [SKIP][83] ([fdo#111912] / [fdo#112080]) -> [SKIP][84] ([fdo#112080])
>    [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@gem_ctx_isolation@vcs2-nonpriv.html
>    [84]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/i
> gt@gem_ctx_isolation@vcs2-nonpriv.html
> 
>   * igt@i915_pm_rpm@modeset-non-lpsp:
>     - shard-snb:          [INCOMPLETE][85] ([i915#82]) -> [SKIP][86] ([fdo#109271])
>    [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-snb6/igt@i915_pm_rpm@modeset-non-lpsp.html
>    [86]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-snb1/ig
> t@i915_pm_rpm@modeset-non-lpsp.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
>   [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
>   [fdo#112057]: https://bugs.freedesktop.org/show_bug.cgi?id=112057
>   [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
>   [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
>   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
>   [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
>   [i915#400]: https://gitlab.freedesktop.org/drm/intel/issues/400
>   [i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
>   [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
>   [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
>   [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
>   [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
>   [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
>   [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
>   [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520
>   [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
>   [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
>   [i915#616]: https://gitlab.freedesktop.org/drm/intel/issues/616
>   [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
>   [i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
>   [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
>   [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
>   [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
>   [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
>   [i915#766]: https://gitlab.freedesktop.org/drm/intel/issues/766
>   [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>   [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
> 
> 
> Participating hosts (11 -> 11)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>   * CI: CI-20190529 -> None
>   * Linux: CI_DRM_7601 -> Patchwork_15836
> 
>   CI-20190529: 20190529
>   CI_DRM_7601: ae3554cfc3c170d7eab0229497d7b1d10256038f @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_15836: d3ec1213283ba267c5f08ed430a9d1f234651d2c @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
> git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/index.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Render/media decompression support (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Render/media decompression support (rev3)
URL   : https://patchwork.freedesktop.org/series/71125/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7601_full -> Patchwork_15836_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15836_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15836_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15836_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane@pixel-format-pipe-d-planes:
    - shard-tglb:         [PASS][1] -> [FAIL][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb7/igt@kms_plane@pixel-format-pipe-d-planes.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@kms_plane@pixel-format-pipe-d-planes.html

  
New tests
---------

  New tests have been introduced between CI_DRM_7601_full and Patchwork_15836_full:

### New Piglit tests (1) ###

  * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_vec3_array3-position-double_dmat2_array2:
    - Statuses : 1 fail(s)
    - Exec time: [0.16] s

  

Known issues
------------

  Here are the changes found in Patchwork_15836_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-tglb:         [PASS][3] -> [INCOMPLETE][4] ([i915#456])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_ctx_persistence@rcs0-mixed-process:
    - shard-apl:          [PASS][5] -> [FAIL][6] ([i915#679])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl8/igt@gem_ctx_persistence@rcs0-mixed-process.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl3/igt@gem_ctx_persistence@rcs0-mixed-process.html

  * igt@gem_ctx_shared@exec-shared-gtt-bsd:
    - shard-kbl:          [PASS][7] -> [FAIL][8] ([i915#616])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl4/igt@gem_ctx_shared@exec-shared-gtt-bsd.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl4/igt@gem_ctx_shared@exec-shared-gtt-bsd.html

  * igt@gem_exec_reloc@basic-cpu-gtt-active:
    - shard-skl:          [PASS][9] -> [DMESG-WARN][10] ([i915#109]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl5/igt@gem_exec_reloc@basic-cpu-gtt-active.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl7/igt@gem_exec_reloc@basic-cpu-gtt-active.html

  * igt@gem_exec_schedule@smoketest-vebox:
    - shard-tglb:         [PASS][11] -> [INCOMPLETE][12] ([i915#707])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@gem_exec_schedule@smoketest-vebox.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/igt@gem_exec_schedule@smoketest-vebox.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-hsw:          [PASS][13] -> [FAIL][14] ([i915#520])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#644])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [PASS][17] -> [INCOMPLETE][18] ([i915#69])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl4/igt@gem_softpin@noreloc-s3.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl9/igt@gem_softpin@noreloc-s3.html

  * igt@gem_sync@basic-many-each:
    - shard-tglb:         [PASS][19] -> [INCOMPLETE][20] ([i915#472] / [i915#707])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@gem_sync@basic-many-each.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@gem_sync@basic-many-each.html

  * igt@gem_sync@basic-store-each:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([i915#435] / [i915#472])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@gem_sync@basic-store-each.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/igt@gem_sync@basic-store-each.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-tglb:         [PASS][23] -> [INCOMPLETE][24] ([i915#456] / [i915#460]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@i915_pm_rpm@system-suspend-modeset.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb3/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([i915#54])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-64x64-sliding.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][29] -> [FAIL][30] ([i915#79])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-tglb:         [PASS][31] -> [FAIL][32] ([i915#49])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-tglb:         [PASS][33] -> [DMESG-WARN][34] ([i915#766])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-tglb:         [PASS][37] -> [INCOMPLETE][38] ([i915#667])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-tglb:         [PASS][39] -> [FAIL][40] ([i915#871])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][41] -> [FAIL][42] ([fdo#108145])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@prime_vgem@basic-sync-default:
    - shard-apl:          [PASS][43] -> [INCOMPLETE][44] ([fdo#103927] / [i915#409])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl3/igt@prime_vgem@basic-sync-default.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl6/igt@prime_vgem@basic-sync-default.html

  
#### Possible fixes ####

  * igt@gem_ctx_shared@q-smoketest-vebox:
    - shard-tglb:         [INCOMPLETE][45] ([fdo#111735]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb9/igt@gem_ctx_shared@q-smoketest-vebox.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb5/igt@gem_ctx_shared@q-smoketest-vebox.html

  * igt@gem_eio@kms:
    - shard-snb:          [INCOMPLETE][47] ([i915#82]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-snb6/igt@gem_eio@kms.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-snb7/igt@gem_eio@kms.html

  * igt@gem_exec_flush@basic-batch-kernel-default-uc:
    - shard-hsw:          [INCOMPLETE][49] ([i915#61]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-hsw2/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-hsw1/igt@gem_exec_flush@basic-batch-kernel-default-uc.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [INCOMPLETE][51] ([i915#456] / [i915#472]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@gem_exec_suspend@basic-s0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-kbl:          [FAIL][53] ([i915#644]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * {igt@gen9_exec_parse@allowed-single}:
    - shard-apl:          [DMESG-WARN][55] ([i915#716]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@gen9_exec_parse@allowed-single.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl2/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_selftest@live_requests:
    - shard-tglb:         [INCOMPLETE][57] ([fdo#112057]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@i915_selftest@live_requests.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb2/igt@i915_selftest@live_requests.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl4/igt@i915_suspend@sysfs-reader.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl4/igt@i915_suspend@sysfs-reader.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo:
    - shard-tglb:         [SKIP][61] ([i915#400]) -> [PASS][62] +19 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_ccs@pipe-b-ccs-on-another-bo.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb7/igt@kms_ccs@pipe-b-ccs-on-another-bo.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
    - shard-skl:          [FAIL][65] ([i915#54]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [INCOMPLETE][67] ([i915#435] / [i915#456] / [i915#460]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-apl:          [FAIL][69] ([i915#79]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl8/igt@kms_flip@flip-vs-expired-vblank.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl2/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [INCOMPLETE][71] ([i915#221]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-skl9/igt@kms_flip@flip-vs-suspend.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-skl6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglb:         [INCOMPLETE][73] ([i915#474] / [i915#667]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-tglb:         [FAIL][75] ([i915#49]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
    - shard-tglb:         [INCOMPLETE][77] ([i915#435] / [i915#667]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-tglb:         [INCOMPLETE][79] ([i915#456] / [i915#460]) -> [PASS][80] +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@perf@oa-exponents:
    - shard-kbl:          [INCOMPLETE][81] ([fdo#103665]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-kbl7/igt@perf@oa-exponents.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-kbl3/igt@perf@oa-exponents.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-nonpriv:
    - shard-tglb:         [SKIP][83] ([fdo#111912] / [fdo#112080]) -> [SKIP][84] ([fdo#112080])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-tglb5/igt@gem_ctx_isolation@vcs2-nonpriv.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-tglb9/igt@gem_ctx_isolation@vcs2-nonpriv.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - shard-snb:          [INCOMPLETE][85] ([i915#82]) -> [SKIP][86] ([fdo#109271])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-snb6/igt@i915_pm_rpm@modeset-non-lpsp.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-snb1/igt@i915_pm_rpm@modeset-non-lpsp.html

  * igt@runner@aborted:
    - shard-apl:          [FAIL][87] ([i915#716]) -> [FAIL][88] ([i915#409])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7601/shard-apl7/igt@runner@aborted.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/shard-apl6/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#112057]: https://bugs.freedesktop.org/show_bug.cgi?id=112057
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
  [i915#400]: https://gitlab.freedesktop.org/drm/intel/issues/400
  [i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
  [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
  [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
  [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#616]: https://gitlab.freedesktop.org/drm/intel/issues/616
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
  [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#766]: https://gitlab.freedesktop.org/drm/intel/issues/766
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#871]: https://gitlab.freedesktop.org/drm/intel/issues/871


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7601 -> Patchwork_15836

  CI-20190529: 20190529
  CI_DRM_7601: ae3554cfc3c170d7eab0229497d7b1d10256038f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15836: d3ec1213283ba267c5f08ed430a9d1f234651d2c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15836/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Render/media decompression support (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Render/media decompression support (rev10)
URL   : https://patchwork.freedesktop.org/series/71125/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7612_full -> Patchwork_15859_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15859_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15859_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15859_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-tglb:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb1/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb2/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html

  
Known issues
------------

  Here are the changes found in Patchwork_15859_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#112080]) +5 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb4/igt@gem_busy@busy-vcs1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb6/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb8/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_persistence@vecs0-mixed-process:
    - shard-apl:          [PASS][7] -> [FAIL][8] ([i915#679])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-apl7/igt@gem_ctx_persistence@vecs0-mixed-process.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-apl6/igt@gem_ctx_persistence@vecs0-mixed-process.html

  * igt@gem_exec_parallel@vcs1:
    - shard-tglb:         [PASS][9] -> [INCOMPLETE][10] ([fdo#111593])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb9/igt@gem_exec_parallel@vcs1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb4/igt@gem_exec_parallel@vcs1.html

  * igt@gem_exec_reloc@basic-gtt-read-active:
    - shard-skl:          [PASS][11] -> [DMESG-WARN][12] ([i915#109]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl10/igt@gem_exec_reloc@basic-gtt-read-active.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl1/igt@gem_exec_reloc@basic-gtt-read-active.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#109276]) +15 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb6/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#112146]) +5 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb5/igt@gem_exec_schedule@reorder-wide-bsd.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_exec_schedule@smoketest-vebox:
    - shard-tglb:         [PASS][17] -> [INCOMPLETE][18] ([i915#707])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb2/igt@gem_exec_schedule@smoketest-vebox.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb4/igt@gem_exec_schedule@smoketest-vebox.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-kbl1/igt@gem_exec_suspend@basic-s3.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-kbl1/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([i915#644])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_sync@basic-all:
    - shard-tglb:         [PASS][23] -> [INCOMPLETE][24] ([i915#470] / [i915#472])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb9/igt@gem_sync@basic-all.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb4/igt@gem_sync@basic-all.html

  * igt@gem_sync@basic-store-each:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([i915#435] / [i915#472])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb1/igt@gem_sync@basic-store-each.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb7/igt@gem_sync@basic-store-each.html

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-skl:          [PASS][27] -> [INCOMPLETE][28] ([i915#69])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl4/igt@i915_pm_backlight@fade_with_suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl5/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][29] -> [INCOMPLETE][30] ([i915#140])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][31] -> [FAIL][32] ([i915#454])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb2/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@gem-mmap-cpu:
    - shard-apl:          [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-apl3/igt@i915_pm_rpm@gem-mmap-cpu.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-apl2/igt@i915_pm_rpm@gem-mmap-cpu.html

  * igt@i915_suspend@debugfs-reader:
    - shard-tglb:         [PASS][35] -> [INCOMPLETE][36] ([i915#456] / [i915#460])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb6/igt@i915_suspend@debugfs-reader.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb2/igt@i915_suspend@debugfs-reader.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
    - shard-skl:          [PASS][37] -> [FAIL][38] ([i915#54]) +3 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][39] -> [FAIL][40] ([i915#79])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-tglb:         [PASS][41] -> [FAIL][42] ([i915#49])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-tglb:         [PASS][43] -> [INCOMPLETE][44] ([i915#667])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [PASS][45] -> [SKIP][46] ([fdo#109441])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb2/igt@kms_psr@psr2_dpms.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb8/igt@kms_psr@psr2_dpms.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-glk:          [PASS][47] -> [DMESG-FAIL][48] ([i915#118] / [i915#95])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-glk8/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-glk9/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +5 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-apl4/igt@gem_ctx_isolation@bcs0-s3.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-apl4/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +4 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-kbl6/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-tglb:         [INCOMPLETE][53] ([i915#456]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb2/igt@gem_ctx_isolation@vcs0-s3.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-none:
    - shard-iclb:         [SKIP][55] ([fdo#109276] / [fdo#112080]) -> [PASS][56] +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb6/igt@gem_ctx_isolation@vcs1-none.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb2/igt@gem_ctx_isolation@vcs1-none.html

  * igt@gem_ctx_persistence@vcs0-mixed-process:
    - shard-glk:          [FAIL][57] ([i915#679]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-glk4/igt@gem_ctx_persistence@vcs0-mixed-process.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-glk9/igt@gem_ctx_persistence@vcs0-mixed-process.html

  * igt@gem_ctx_shared@q-smoketest-vebox:
    - shard-tglb:         [INCOMPLETE][59] ([fdo#111735]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb3/igt@gem_ctx_shared@q-smoketest-vebox.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb3/igt@gem_ctx_shared@q-smoketest-vebox.html

  * igt@gem_exec_reuse@single:
    - shard-tglb:         [INCOMPLETE][61] ([i915#435]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb6/igt@gem_exec_reuse@single.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb5/igt@gem_exec_reuse@single.html

  * igt@gem_exec_schedule@fifo-bsd1:
    - shard-iclb:         [SKIP][63] ([fdo#109276]) -> [PASS][64] +10 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb8/igt@gem_exec_schedule@fifo-bsd1.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb2/igt@gem_exec_schedule@fifo-bsd1.html

  * {igt@gem_exec_schedule@pi-distinct-iova-bsd}:
    - shard-iclb:         [SKIP][65] ([i915#677]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb4/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb5/igt@gem_exec_schedule@pi-distinct-iova-bsd.html

  * igt@gem_exec_schedule@wide-bsd:
    - shard-iclb:         [SKIP][67] ([fdo#112146]) -> [PASS][68] +3 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb5/igt@gem_exec_schedule@wide-bsd.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [INCOMPLETE][69] ([i915#456] / [i915#472]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb7/igt@gem_exec_suspend@basic-s0.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb6/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-glk:          [TIMEOUT][71] ([i915#530]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-glk7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-glk8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-tglb:         [INCOMPLETE][73] ([i915#456] / [i915#460]) -> [PASS][74] +3 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb4/igt@gem_workarounds@suspend-resume-context.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb5/igt@gem_workarounds@suspend-resume-context.html

  * {igt@gen9_exec_parse@allowed-single}:
    - shard-skl:          [DMESG-WARN][75] ([i915#716]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl4/igt@gen9_exec_parse@allowed-single.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl4/igt@gen9_exec_parse@allowed-single.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo:
    - shard-tglb:         [SKIP][77] ([i915#400]) -> [PASS][78] +13 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb7/igt@kms_ccs@pipe-b-ccs-on-another-bo.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb9/igt@kms_ccs@pipe-b-ccs-on-another-bo.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x256-random:
    - shard-snb:          [SKIP][79] ([fdo#109271]) -> [PASS][80] +3 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-snb6/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-snb1/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
    - shard-skl:          [FAIL][81] ([i915#54]) -> [PASS][82] +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled:
    - shard-skl:          [FAIL][83] ([i915#52] / [i915#54]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-glk:          [FAIL][85] ([i915#79]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][87] ([i915#49]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-tglb:         [DMESG-WARN][89] ([i915#766]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [INCOMPLETE][91] ([fdo#103665]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-skl:          [DMESG-WARN][93] ([i915#109]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl4/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl4/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][95] ([fdo#108145]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][97] ([fdo#108145] / [i915#265]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-skl:          [DMESG-WARN][99] ([IGT#6]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-skl1/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-skl9/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [SKIP][101] ([fdo#109441]) -> [PASS][102] +4 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_psr@psr2_suspend:
    - shard-tglb:         [DMESG-WARN][103] ([i915#402]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb4/igt@kms_psr@psr2_suspend.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb5/igt@kms_psr@psr2_suspend.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-tglb:         [INCOMPLETE][105] ([i915#460]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  * igt@perf_pmu@busy-no-semaphores-vcs1:
    - shard-iclb:         [SKIP][107] ([fdo#112080]) -> [PASS][108] +9 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [SKIP][109] ([fdo#109276] / [fdo#112080]) -> [FAIL][110] ([IGT#28])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [FAIL][111] ([i915#454]) -> [SKIP][112] ([i915#468])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-tglb7/igt@i915_pm_dc@dc6-dpms.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_selftest@mock_requests:
    - shard-iclb:         [DMESG-WARN][113] -> [INCOMPLETE][114] ([i915#140])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7612/shard-iclb6/igt@i915_selftest@mock_requests.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/shard-iclb2/igt@i915_selftest@mock_requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
  [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#400]: https://gitlab.freedesktop.org/drm/intel/issues/400
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
  [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#766]: https://gitlab.freedesktop.org/drm/intel/issues/766
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 10)
------------------------------

  Missing    (1): pig-hsw-4770r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7612 -> Patchwork_15859

  CI-20190529: 20190529
  CI_DRM_7612: d8427504d16e1aa87eab972f812c02478522bd70 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5351: e7fdcef72d1d6b3bb9f3003bbc37571959e6e8bb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15859: 64e5f7fd003bf2907733d63def8aeccf77297e40 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15859/index.html
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