[ath9k-devel] interrupt handling (ar9002/ar9003): why is BCNMISC checked before ISR_RAC ?

* [ath9k-devel] interrupt handling (ar9002/ar9003): why is BCNMISC checked before ISR_RAC ?
@ 2011-09-12  4:26 Adrian Chadd
  2011-09-12  9:03 ` [ath9k-devel] 回复: " 李建真
  0 siblings, 1 reply; 2+ messages in thread
From: Adrian Chadd @ 2011-09-12  4:26 UTC (permalink / raw)
  To: ath9k-devel

Hi all,

I have a few questions about the interrupt handling in ath9k (since
FreeBSD's interrupt code is much the same.)

Why is it that the BCNMISC flag in AR_ISR is checked in the AR_ISR
read, -before- the AR_ISR_RAC register is read?
Isn't it possible that there's a subtle race condition here, where
reading AR_ISR for the BCNMISC flag will return 0, or some bits in
AR_ISR_S2 are 0, but the condition that triggers them happens between
the reads there, and the subsequent read from AR_ISR_RAC? (which then
atomically copies them to _S registers and 0's the status registers?)

Second question: why is there ATH9K_HW_CAP_RAC_SUPPORTED ?

It's set for the AR9300_20 and later. The AR9002 routines don't even
use that bit - they always use AR_ISR_RAC and the _S shadow registers.
Is it something that doesn't exist for AR9300 1.0 ? (is that even
public?)

Thanks,

Adrian

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