* [PATCH 01/11] arm: arm926ej-s: start.S: port save_boot_params support from armv7 code
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
@ 2022-01-05 0:34 ` Jesse Taube
2022-01-21 1:57 ` Andre Przywara
2022-01-05 0:34 ` [PATCH 02/11] arm: arm926ej-s: add sunxi code Jesse Taube
` (10 subsequent siblings)
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:34 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
The ARMv7 start code has support for saving some boot params at the
entry point, which is used by some SoCs to return to BROM.
Port this to ARM926EJ-S start code.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
arch/arm/cpu/arm926ejs/start.S | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 0afcc47aad..aca7793c57 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -17,6 +17,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
+#include <linux/linkage.h>
/*
*************************************************************************
@@ -32,8 +33,13 @@
*/
.globl reset
+ .globl save_boot_params_ret
+ .type save_boot_params_ret,%function
reset:
+ /* Allow the board to save important registers */
+ b save_boot_params
+save_boot_params_ret:
/*
* set the cpu to SVC32 mode
*/
@@ -110,3 +116,16 @@ flush_dcache:
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+
+/*************************************************************************
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+ * __attribute__((weak));
+ *
+ * Stack pointer is not yet initialized at this moment
+ * Don't save anything to stack even if compiled with -O0
+ *
+ *************************************************************************/
+WEAK(save_boot_params)
+ b save_boot_params_ret /* back to my caller */
+ENDPROC(save_boot_params)
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 01/11] arm: arm926ej-s: start.S: port save_boot_params support from armv7 code
2022-01-05 0:34 ` [PATCH 01/11] arm: arm926ej-s: start.S: port save_boot_params support from armv7 code Jesse Taube
@ 2022-01-21 1:57 ` Andre Przywara
0 siblings, 0 replies; 43+ messages in thread
From: Andre Przywara @ 2022-01-21 1:57 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On Tue, 4 Jan 2022 19:34:58 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi,
> From: Icenowy Zheng <icenowy@aosc.io>
>
> The ARMv7 start code has support for saving some boot params at the
> entry point, which is used by some SoCs to return to BROM.
>
> Port this to ARM926EJ-S start code.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
> arch/arm/cpu/arm926ejs/start.S | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
> index 0afcc47aad..aca7793c57 100644
> --- a/arch/arm/cpu/arm926ejs/start.S
> +++ b/arch/arm/cpu/arm926ejs/start.S
> @@ -17,6 +17,7 @@
> #include <asm-offsets.h>
> #include <config.h>
> #include <common.h>
> +#include <linux/linkage.h>
>
> /*
> *************************************************************************
> @@ -32,8 +33,13 @@
> */
>
> .globl reset
> + .globl save_boot_params_ret
> + .type save_boot_params_ret,%function
>
> reset:
> + /* Allow the board to save important registers */
> + b save_boot_params
> +save_boot_params_ret:
> /*
> * set the cpu to SVC32 mode
> */
> @@ -110,3 +116,16 @@ flush_dcache:
> #endif
> mov pc, lr /* back to my caller */
> #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
> +
> +/*************************************************************************
> + *
> + * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
> + * __attribute__((weak));
> + *
> + * Stack pointer is not yet initialized at this moment
> + * Don't save anything to stack even if compiled with -O0
> + *
> + *************************************************************************/
> +WEAK(save_boot_params)
> + b save_boot_params_ret /* back to my caller */
> +ENDPROC(save_boot_params)
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 02/11] arm: arm926ej-s: add sunxi code
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
2022-01-05 0:34 ` [PATCH 01/11] arm: arm926ej-s: start.S: port save_boot_params support from armv7 code Jesse Taube
@ 2022-01-05 0:34 ` Jesse Taube
2022-01-21 2:25 ` Andre Przywara
2022-01-05 0:35 ` [PATCH 03/11] dt-bindings: clock: Add initial suniv headers Jesse Taube
` (9 subsequent siblings)
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:34 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
Some Allwinner SoCs use ARM926EJ-S core.
Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
arch/arm/cpu/arm926ejs/Makefile | 1 +
arch/arm/cpu/arm926ejs/sunxi/Makefile | 15 +++
arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 +
arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 37 ++++++
arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S | 67 +++++++++++
arch/arm/cpu/arm926ejs/sunxi/start.c | 1 +
arch/arm/cpu/arm926ejs/sunxi/timer.c | 114 +++++++++++++++++++
arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 62 ++++++++++
8 files changed, 303 insertions(+)
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/start.c
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/timer.c
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index b901b7c5c9..7f1436d76e 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -15,6 +15,7 @@ endif
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
# some files can only build in ARM or THUMB2, not THUMB1
diff --git a/arch/arm/cpu/arm926ejs/sunxi/Makefile b/arch/arm/cpu/arm926ejs/sunxi/Makefile
new file mode 100644
index 0000000000..894c461c50
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+#
+# Based on some other Makefile
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y += timer.o
+obj-y += lowlevel_init.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += fel_utils.o
+CFLAGS_fel_utils.o := -marm
+endif
diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk b/arch/arm/cpu/arm926ejs/sunxi/config.mk
new file mode 100644
index 0000000000..76ffec9df6
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk
@@ -0,0 +1,6 @@
+# Build a combined spl + u-boot image
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+ALL-y += u-boot-sunxi-with-spl.bin
+endif
+endif
diff --git a/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
new file mode 100644
index 0000000000..0997a2dc65
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Utility functions for FEL mode.
+ *
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+ ldr r0, =fel_stash
+ str sp, [r0, #0]
+ str lr, [r0, #4]
+ mrs lr, cpsr @ Read CPSR
+ str lr, [r0, #8]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
+ str lr, [r0, #12]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
+ str lr, [r0, #16]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(return_to_fel)
+ mov sp, r0
+ mov lr, r1
+ ldr r0, =fel_stash
+ ldr r1, [r0, #16]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
+ ldr r1, [r0, #12]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
+ ldr r1, [r0, #8]
+ msr cpsr, r1 @ Write CPSR
+ bx lr
+ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
new file mode 100644
index 0000000000..db09bcc4d0
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * A lowlevel_init function that sets up the stack to call a C function to
+ * perform further init.
+ *
+ * Based on lowlevel_init.S in armv7 directory, which is:
+ * (C) Copyright 2010 Texas Instruments, <www.ti.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+.pushsection .text.s_init, "ax"
+WEAK(s_init)
+ bx lr
+ENDPROC(s_init)
+.popsection
+
+.pushsection .text.lowlevel_init, "ax"
+WEAK(lowlevel_init)
+ /*
+ * Setup a temporary stack. Global data is not available yet.
+ */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+ ldr sp, =CONFIG_SPL_STACK
+#else
+ ldr sp, =CONFIG_SYS_INIT_SP_ADDR
+#endif
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+#ifdef CONFIG_SPL_DM
+ mov r9, #0
+#else
+ /*
+ * Set up global data for boards that still need it. This will be
+ * removed soon.
+ */
+#ifdef CONFIG_SPL_BUILD
+ ldr r9, =gdata
+#else
+ sub sp, sp, #GD_SIZE
+ bic sp, sp, #7
+ mov r9, sp
+#endif
+#endif
+ /*
+ * Save the old lr(passed in ip) and the current lr to stack
+ */
+ push {ip, lr}
+
+ /*
+ * Call the very early init function. This should do only the
+ * absolute bare minimum to get started. It should not:
+ *
+ * - set up DRAM
+ * - use global_data
+ * - clear BSS
+ * - try to start a console
+ *
+ * For boards with SPL this should be empty since SPL can do all of
+ * this init in the SPL board_init_f() function which is called
+ * immediately after this.
+ */
+ bl s_init
+ pop {ip, pc}
+ENDPROC(lowlevel_init)
+.popsection
diff --git a/arch/arm/cpu/arm926ejs/sunxi/start.c b/arch/arm/cpu/arm926ejs/sunxi/start.c
new file mode 100644
index 0000000000..6b392fa835
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/start.c
@@ -0,0 +1 @@
+/* Intentionally empty. Only needed to get FEL SPL link line right */
diff --git a/arch/arm/cpu/arm926ejs/sunxi/timer.c b/arch/arm/cpu/arm926ejs/sunxi/timer.c
new file mode 100644
index 0000000000..e624174581
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/timer.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_MODE (0x0 << 7) /* continuous mode */
+#define TIMER_DIV (0x0 << 4) /* pre scale 1 */
+#define TIMER_SRC (0x1 << 2) /* osc24m */
+#define TIMER_RELOAD (0x1 << 1) /* reload internal value */
+#define TIMER_EN (0x1 << 0) /* enable timer */
+
+#define TIMER_CLOCK (24 * 1000 * 1000)
+#define COUNT_TO_USEC(x) ((x) / 24)
+#define USEC_TO_COUNT(x) ((x) * 24)
+#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
+#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+#define TIMER_NUM 0 /* we use timer 0 */
+
+/* read the 32-bit timer */
+static ulong read_timer(void)
+{
+ struct sunxi_timer_reg *timers =
+ (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+ struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
+
+ /*
+ * The hardware timer counts down, therefore we invert to
+ * produce an incrementing timer.
+ */
+ return ~readl(&timer->val);
+}
+
+/* init timer register */
+int timer_init(void)
+{
+ struct sunxi_timer_reg *timers =
+ (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+ struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
+
+ writel(TIMER_LOAD_VAL, &timer->inter);
+ writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
+ &timer->ctl);
+
+ return 0;
+}
+
+ulong get_timer_masked(void)
+{
+ /* current tick value */
+ ulong now = TICKS_TO_HZ(read_timer());
+
+ if (now >= gd->arch.lastinc) { /* normal (non rollover) */
+ gd->arch.tbl += (now - gd->arch.lastinc);
+ } else {
+ /* rollover */
+ gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
+ - gd->arch.lastinc) + now;
+ }
+ gd->arch.lastinc = now;
+
+ return gd->arch.tbl;
+}
+
+/* timer without interrupts */
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+ long tmo = USEC_TO_COUNT(usec);
+ ulong now, last = read_timer();
+
+ while (tmo > 0) {
+ now = read_timer();
+ if (now > last) /* normal (non rollover) */
+ tmo -= now - last;
+ else /* rollover */
+ tmo -= TIMER_LOAD_VAL - last + now;
+ last = now;
+ }
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
new file mode 100644
index 0000000000..048aab788a
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds:
+ *
+ * (C) Copyright 2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Based on omap-common/u-boot-spl.lds:
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ */
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ arch/arm/cpu/arm926ejs/start.o (.text)
+ *(.text*)
+ } > .sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } > .sram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } > .sdram
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 02/11] arm: arm926ej-s: add sunxi code
2022-01-05 0:34 ` [PATCH 02/11] arm: arm926ej-s: add sunxi code Jesse Taube
@ 2022-01-21 2:25 ` Andre Przywara
2022-01-21 3:16 ` Jesse Taube
0 siblings, 1 reply; 43+ messages in thread
From: Andre Przywara @ 2022-01-21 2:25 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On Tue, 4 Jan 2022 19:34:59 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi,
> From: Icenowy Zheng <icenowy@aosc.io>
>
> Some Allwinner SoCs use ARM926EJ-S core.
>
> Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> arch/arm/cpu/arm926ejs/Makefile | 1 +
> arch/arm/cpu/arm926ejs/sunxi/Makefile | 15 +++
> arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 +
> arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 37 ++++++
> arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S | 67 +++++++++++
> arch/arm/cpu/arm926ejs/sunxi/start.c | 1 +
> arch/arm/cpu/arm926ejs/sunxi/timer.c | 114 +++++++++++++++++++
> arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 62 ++++++++++
> 8 files changed, 303 insertions(+)
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/start.c
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/timer.c
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
>
> diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
> index b901b7c5c9..7f1436d76e 100644
> --- a/arch/arm/cpu/arm926ejs/Makefile
> +++ b/arch/arm/cpu/arm926ejs/Makefile
> @@ -15,6 +15,7 @@ endif
> obj-$(CONFIG_MX27) += mx27/
> obj-$(if $(filter mxs,$(SOC)),y) += mxs/
> obj-$(if $(filter spear,$(SOC)),y) += spear/
> +obj-$(CONFIG_ARCH_SUNXI) += sunxi/
>
> # some files can only build in ARM or THUMB2, not THUMB1
>
> diff --git a/arch/arm/cpu/arm926ejs/sunxi/Makefile b/arch/arm/cpu/arm926ejs/sunxi/Makefile
> new file mode 100644
> index 0000000000..894c461c50
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/sunxi/Makefile
> @@ -0,0 +1,15 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
> +#
> +# Based on some other Makefile
> +# (C) Copyright 2000-2003
> +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Please remove this heritage. I appreciate the effort to give credit,
but for a trivial Makefile stub (which even differs significantly) this
is surely overkill.
Just one line with some current copyright should be enough.
> +
> +obj-y += timer.o
> +obj-y += lowlevel_init.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += fel_utils.o
> +CFLAGS_fel_utils.o := -marm
> +endif
> diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk b/arch/arm/cpu/arm926ejs/sunxi/config.mk
> new file mode 100644
> index 0000000000..76ffec9df6
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk
> @@ -0,0 +1,6 @@
> +# Build a combined spl + u-boot image
> +ifdef CONFIG_SPL
> +ifndef CONFIG_SPL_BUILD
> +ALL-y += u-boot-sunxi-with-spl.bin
> +endif
> +endif
> diff --git a/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
> new file mode 100644
> index 0000000000..0997a2dc65
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Utility functions for FEL mode.
> + *
> + * Copyright (c) 2015 Google, Inc
> + */
> +
> +#include <asm-offsets.h>
> +#include <config.h>
> +#include <asm/system.h>
> +#include <linux/linkage.h>
> +
> +ENTRY(save_boot_params)
> + ldr r0, =fel_stash
> + str sp, [r0, #0]
> + str lr, [r0, #4]
> + mrs lr, cpsr @ Read CPSR
> + str lr, [r0, #8]
> + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
> + str lr, [r0, #12]
> + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
> + str lr, [r0, #16]
This is the very same register twice, also written to the wrong offset.
Please remove the last two lines.
Yes, this is a bug in armv7/sunxi/fel_utils.S as well, I will send a
fix.
> + b save_boot_params_ret
> +ENDPROC(save_boot_params)
> +
> +ENTRY(return_to_fel)
> + mov sp, r0
> + mov lr, r1
> + ldr r0, =fel_stash
> + ldr r1, [r0, #16]
> + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
Same here, those two lines can be removed.
> + ldr r1, [r0, #12]
> + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
> + ldr r1, [r0, #8]
> + msr cpsr, r1 @ Write CPSR
> + bx lr
> +ENDPROC(return_to_fel)
> diff --git a/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
> new file mode 100644
> index 0000000000..db09bcc4d0
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
> @@ -0,0 +1,67 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * A lowlevel_init function that sets up the stack to call a C function to
> + * perform further init.
> + *
> + * Based on lowlevel_init.S in armv7 directory, which is:
> + * (C) Copyright 2010 Texas Instruments, <www.ti.com>
> + */
> +
> +#include <asm-offsets.h>
> +#include <config.h>
> +#include <linux/linkage.h>
> +
> +.pushsection .text.s_init, "ax"
> +WEAK(s_init)
> + bx lr
> +ENDPROC(s_init)
> +.popsection
I would say we don't need this weak stub. In contrast to armv7, we are
the only user of this file, and s_init should be provided by
arch/arm/mach-sunxi/board.c.
In general the toplevel README seems to deprecate lowlevel_init, but
this probably needs some fixing in the other sunxi code first.
> +
> +.pushsection .text.lowlevel_init, "ax"
> +WEAK(lowlevel_init)
> + /*
> + * Setup a temporary stack. Global data is not available yet.
> + */
> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
> + ldr sp, =CONFIG_SPL_STACK
> +#else
> + ldr sp, =CONFIG_SYS_INIT_SP_ADDR
> +#endif
> + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
> +#ifdef CONFIG_SPL_DM
> + mov r9, #0
> +#else
We probably don't need this SPL_DM part?
> + /*
> + * Set up global data for boards that still need it. This will be
> + * removed soon.
> + */
> +#ifdef CONFIG_SPL_BUILD
> + ldr r9, =gdata
> +#else
> + sub sp, sp, #GD_SIZE
> + bic sp, sp, #7
> + mov r9, sp
> +#endif
> +#endif
> + /*
> + * Save the old lr(passed in ip) and the current lr to stack
> + */
> + push {ip, lr}
> +
> + /*
> + * Call the very early init function. This should do only the
> + * absolute bare minimum to get started. It should not:
> + *
> + * - set up DRAM
> + * - use global_data
> + * - clear BSS
> + * - try to start a console
> + *
> + * For boards with SPL this should be empty since SPL can do all of
> + * this init in the SPL board_init_f() function which is called
> + * immediately after this.
> + */
Yeah, this (copied) comments seems to suggest we are somewhat off here.
But I think we rely on board.c:s_init() too much to easily remove this.
So for the sake of not blocking this I am willing to keep this part for
now.
> + bl s_init
> + pop {ip, pc}
> +ENDPROC(lowlevel_init)
> +.popsection
> diff --git a/arch/arm/cpu/arm926ejs/sunxi/start.c b/arch/arm/cpu/arm926ejs/sunxi/start.c
> new file mode 100644
> index 0000000000..6b392fa835
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/sunxi/start.c
> @@ -0,0 +1 @@
> +/* Intentionally empty. Only needed to get FEL SPL link line right */
> diff --git a/arch/arm/cpu/arm926ejs/sunxi/timer.c b/arch/arm/cpu/arm926ejs/sunxi/timer.c
> new file mode 100644
> index 0000000000..e624174581
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/sunxi/timer.c
I don't see immediately why the original file lives in
arch/arm/cpu/armv7/sunxi/timer.c. Can we move that to
arch/arm/mach-sunxi or board/sunxi, then just not compile it for arm64?
Because otherwise this looks identical to its donor, minus some smaller
(but good) cleanups.
So I'm curious if we can move and then reuse the original file.
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: (GPL-2.0+)
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/timer.h>
> +#include <asm/global_data.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define TIMER_MODE (0x0 << 7) /* continuous mode */
> +#define TIMER_DIV (0x0 << 4) /* pre scale 1 */
> +#define TIMER_SRC (0x1 << 2) /* osc24m */
> +#define TIMER_RELOAD (0x1 << 1) /* reload internal value */
> +#define TIMER_EN (0x1 << 0) /* enable timer */
> +
> +#define TIMER_CLOCK (24 * 1000 * 1000)
> +#define COUNT_TO_USEC(x) ((x) / 24)
> +#define USEC_TO_COUNT(x) ((x) * 24)
> +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
> +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
> +
> +#define TIMER_LOAD_VAL 0xffffffff
> +
> +#define TIMER_NUM 0 /* we use timer 0 */
> +
> +/* read the 32-bit timer */
> +static ulong read_timer(void)
> +{
> + struct sunxi_timer_reg *timers =
> + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
> + struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
> +
> + /*
> + * The hardware timer counts down, therefore we invert to
> + * produce an incrementing timer.
> + */
> + return ~readl(&timer->val);
> +}
> +
> +/* init timer register */
> +int timer_init(void)
> +{
> + struct sunxi_timer_reg *timers =
> + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
> + struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
> +
> + writel(TIMER_LOAD_VAL, &timer->inter);
> + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
> + &timer->ctl);
> +
> + return 0;
> +}
> +
> +ulong get_timer_masked(void)
Any reason you lost the static here?
> +{
> + /* current tick value */
> + ulong now = TICKS_TO_HZ(read_timer());
> +
> + if (now >= gd->arch.lastinc) { /* normal (non rollover) */
> + gd->arch.tbl += (now - gd->arch.lastinc);
> + } else {
> + /* rollover */
> + gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
> + - gd->arch.lastinc) + now;
> + }
> + gd->arch.lastinc = now;
> +
> + return gd->arch.tbl;
> +}
> +
> +/* timer without interrupts */
> +ulong get_timer(ulong base)
> +{
> + return get_timer_masked() - base;
> +}
> +
> +/* delay x useconds */
> +void __udelay(unsigned long usec)
> +{
> + long tmo = USEC_TO_COUNT(usec);
> + ulong now, last = read_timer();
> +
> + while (tmo > 0) {
> + now = read_timer();
> + if (now > last) /* normal (non rollover) */
> + tmo -= now - last;
> + else /* rollover */
> + tmo -= TIMER_LOAD_VAL - last + now;
> + last = now;
> + }
> +}
> +
> +/*
> + * This function is derived from PowerPC code (read timebase as long long).
> + * On ARM it just returns the timer value.
> + */
> +unsigned long long get_ticks(void)
> +{
> + return get_timer(0);
> +}
> +
> +/*
> + * This function is derived from PowerPC code (timebase clock frequency).
> + * On ARM it returns the number of timer ticks per second.
> + */
> +ulong get_tbclk(void)
> +{
> + return CONFIG_SYS_HZ;
> +}
> diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
> new file mode 100644
> index 0000000000..048aab788a
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
> @@ -0,0 +1,62 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2018
> + * Icenowy Zheng <icenowy@aosc.io>
> + *
> + * Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds:
> + *
> + * (C) Copyright 2012
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Tom Cubie <tangliang@allwinnertech.com>
> + *
I think that's enough history at this point ...
> + * Based on omap-common/u-boot-spl.lds:
> + *
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
> + *
> + * (C) Copyright 2010
> + * Texas Instruments, <www.ti.com>
> + * Aneesh V <aneesh@ti.com>
> + */
> +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
> + LENGTH = CONFIG_SPL_MAX_SIZE }
> +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
> + LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
> +
> +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> +OUTPUT_ARCH(arm)
> +ENTRY(_start)
> +SECTIONS
> +{
> + .text :
> + {
> + __start = .;
> + *(.vectors)
> + arch/arm/cpu/arm926ejs/start.o (.text)
Do we actually need this, if it's empty? Isn't that file just to
satisfy the needs of the generic linker scripts?
Cheers,
Andre.
> + *(.text*)
> + } > .sram
> +
> + . = ALIGN(4);
> + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
> +
> + . = ALIGN(4);
> + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
> +
> + . = ALIGN(4);
> + .u_boot_list : {
> + KEEP(*(SORT(.u_boot_list*)));
> + } > .sram
> +
> + . = ALIGN(4);
> + __image_copy_end = .;
> + _end = .;
> +
> + .bss :
> + {
> + . = ALIGN(4);
> + __bss_start = .;
> + *(.bss*)
> + . = ALIGN(4);
> + __bss_end = .;
> + } > .sdram
> +}
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 02/11] arm: arm926ej-s: add sunxi code
2022-01-21 2:25 ` Andre Przywara
@ 2022-01-21 3:16 ` Jesse Taube
2022-01-24 1:45 ` Andre Przywara
0 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-21 3:16 UTC (permalink / raw)
To: Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On 1/20/22 21:25, Andre Przywara wrote:
> On Tue, 4 Jan 2022 19:34:59 -0500
> Jesse Taube <mr.bossman075@gmail.com> wrote:
>
> Hi,
>
>> From: Icenowy Zheng <icenowy@aosc.io>
>>
>> Some Allwinner SoCs use ARM926EJ-S core.
>>
>> Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>> ---
>> arch/arm/cpu/arm926ejs/Makefile | 1 +
>> arch/arm/cpu/arm926ejs/sunxi/Makefile | 15 +++
>> arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 +
>> arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 37 ++++++
>> arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S | 67 +++++++++++
>> arch/arm/cpu/arm926ejs/sunxi/start.c | 1 +
>> arch/arm/cpu/arm926ejs/sunxi/timer.c | 114 +++++++++++++++++++
>> arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 62 ++++++++++
>> 8 files changed, 303 insertions(+)
>> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile
>> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk
>> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
>> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
>> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/start.c
>> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/timer.c
>> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
>>
>> diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
>> index b901b7c5c9..7f1436d76e 100644
>> --- a/arch/arm/cpu/arm926ejs/Makefile
>> +++ b/arch/arm/cpu/arm926ejs/Makefile
>> @@ -15,6 +15,7 @@ endif
>> obj-$(CONFIG_MX27) += mx27/
>> obj-$(if $(filter mxs,$(SOC)),y) += mxs/
>> obj-$(if $(filter spear,$(SOC)),y) += spear/
>> +obj-$(CONFIG_ARCH_SUNXI) += sunxi/
>>
>> # some files can only build in ARM or THUMB2, not THUMB1
>>
>> diff --git a/arch/arm/cpu/arm926ejs/sunxi/Makefile b/arch/arm/cpu/arm926ejs/sunxi/Makefile
>> new file mode 100644
>> index 0000000000..894c461c50
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/sunxi/Makefile
>> @@ -0,0 +1,15 @@
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
>> +#
>> +# Based on some other Makefile
>> +# (C) Copyright 2000-2003
>> +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
>
> Please remove this heritage. I appreciate the effort to give credit,
> but for a trivial Makefile stub (which even differs significantly) this
> is surely overkill.
> Just one line with some current copyright should be enough.
>
Fixed.
>> +
>> +obj-y += timer.o
>> +obj-y += lowlevel_init.o
>> +
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y += fel_utils.o
>> +CFLAGS_fel_utils.o := -marm
>> +endif
>> diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk b/arch/arm/cpu/arm926ejs/sunxi/config.mk
>> new file mode 100644
>> index 0000000000..76ffec9df6
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk
>> @@ -0,0 +1,6 @@
>> +# Build a combined spl + u-boot image
>> +ifdef CONFIG_SPL
>> +ifndef CONFIG_SPL_BUILD
>> +ALL-y += u-boot-sunxi-with-spl.bin
>> +endif
>> +endif
>> diff --git a/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
>> new file mode 100644
>> index 0000000000..0997a2dc65
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
>> @@ -0,0 +1,37 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Utility functions for FEL mode.
>> + *
>> + * Copyright (c) 2015 Google, Inc
>> + */
>> +
>> +#include <asm-offsets.h>
>> +#include <config.h>
>> +#include <asm/system.h>
>> +#include <linux/linkage.h>
>> +
>> +ENTRY(save_boot_params)
>> + ldr r0, =fel_stash
>> + str sp, [r0, #0]
>> + str lr, [r0, #4]
>> + mrs lr, cpsr @ Read CPSR
>> + str lr, [r0, #8]
>> + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
>> + str lr, [r0, #12]
>> + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
>> + str lr, [r0, #16]
>
> This is the very same register twice, also written to the wrong offset.
> Please remove the last two lines.
> Yes, this is a bug in armv7/sunxi/fel_utils.S as well, I will send a
> fix.
Please CC me.
>
>> + b save_boot_params_ret
>> +ENDPROC(save_boot_params)
>> +
>> +ENTRY(return_to_fel)
>> + mov sp, r0
>> + mov lr, r1
>> + ldr r0, =fel_stash
>> + ldr r1, [r0, #16]
>> + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
>
> Same here, those two lines can be removed.
>
>> + ldr r1, [r0, #12]
>> + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
>> + ldr r1, [r0, #8]
>> + msr cpsr, r1 @ Write CPSR
>> + bx lr
>> +ENDPROC(return_to_fel)
>> diff --git a/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
>> new file mode 100644
>> index 0000000000..db09bcc4d0
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
>> @@ -0,0 +1,67 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * A lowlevel_init function that sets up the stack to call a C function to
>> + * perform further init.
>> + *
>> + * Based on lowlevel_init.S in armv7 directory, which is:
>> + * (C) Copyright 2010 Texas Instruments, <www.ti.com>
>> + */
>> +
>> +#include <asm-offsets.h>
>> +#include <config.h>
>> +#include <linux/linkage.h>
>> +
>> +.pushsection .text.s_init, "ax"
>> +WEAK(s_init)
>> + bx lr
>> +ENDPROC(s_init)
>> +.popsection
>
> I would say we don't need this weak stub. In contrast to armv7, we are
> the only user of this file, and s_init should be provided by
> arch/arm/mach-sunxi/board.c.
>
> In general the toplevel README seems to deprecate lowlevel_init, but
> this probably needs some fixing in the other sunxi code first.
I removed it its defined in board like you said.
>> +
>> +.pushsection .text.lowlevel_init, "ax"
>> +WEAK(lowlevel_init)
>> + /*
>> + * Setup a temporary stack. Global data is not available yet.
>> + */
>> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
>> + ldr sp, =CONFIG_SPL_STACK
>> +#else
>> + ldr sp, =CONFIG_SYS_INIT_SP_ADDR
>> +#endif
>> + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
>> +#ifdef CONFIG_SPL_DM
>> + mov r9, #0
>> +#else
>
> We probably don't need this SPL_DM part?
Hmmmmm you are right im assuiming this got copied from somewhere. I
replaced the ifdef with `mov r9, #0`.
>
>> + /*
>> + * Set up global data for boards that still need it. This will be
>> + * removed soon.
>> + */
>> +#ifdef CONFIG_SPL_BUILD
>> + ldr r9, =gdata
>> +#else
>> + sub sp, sp, #GD_SIZE
>> + bic sp, sp, #7
>> + mov r9, sp
>> +#endif
>> +#endif
>> + /*
>> + * Save the old lr(passed in ip) and the current lr to stack
>> + */
>> + push {ip, lr}
>> +
>> + /*
>> + * Call the very early init function. This should do only the
>> + * absolute bare minimum to get started. It should not:
>> + *
>> + * - set up DRAM
>> + * - use global_data
>> + * - clear BSS
>> + * - try to start a console
>> + *
>> + * For boards with SPL this should be empty since SPL can do all of
>> + * this init in the SPL board_init_f() function which is called
>> + * immediately after this.
>> + */
>
> Yeah, this (copied) comments seems to suggest we are somewhat off here.
> But I think we rely on board.c:s_init() too much to easily remove this.
>
> So for the sake of not blocking this I am willing to keep this part for
> now.
Much apretiated!
>
>> + bl s_init
>> + pop {ip, pc}
>> +ENDPROC(lowlevel_init)
>> +.popsection
>> diff --git a/arch/arm/cpu/arm926ejs/sunxi/start.c b/arch/arm/cpu/arm926ejs/sunxi/start.c
>> new file mode 100644
>> index 0000000000..6b392fa835
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/sunxi/start.c
>> @@ -0,0 +1 @@
>> +/* Intentionally empty. Only needed to get FEL SPL link line right */
>> diff --git a/arch/arm/cpu/arm926ejs/sunxi/timer.c b/arch/arm/cpu/arm926ejs/sunxi/timer.c
>> new file mode 100644
>> index 0000000000..e624174581
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/sunxi/timer.c
>
> I don't see immediately why the original file lives in
> arch/arm/cpu/armv7/sunxi/timer.c. Can we move that to
> arch/arm/mach-sunxi or board/sunxi, then just not compile it for arm64?
> Because otherwise this looks identical to its donor, minus some smaller
> (but good) cleanups.
> So I'm curious if we can move and then reuse the original file.
I will try thanks for the pointer.
>
>> @@ -0,0 +1,114 @@
>> +// SPDX-License-Identifier: (GPL-2.0+)
>> +/*
>> + * (C) Copyright 2007-2011
>> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
>> + * Tom Cubie <tangliang@allwinnertech.com>
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/timer.h>
>> +#include <asm/global_data.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define TIMER_MODE (0x0 << 7) /* continuous mode */
>> +#define TIMER_DIV (0x0 << 4) /* pre scale 1 */
>> +#define TIMER_SRC (0x1 << 2) /* osc24m */
>> +#define TIMER_RELOAD (0x1 << 1) /* reload internal value */
>> +#define TIMER_EN (0x1 << 0) /* enable timer */
>> +
>> +#define TIMER_CLOCK (24 * 1000 * 1000)
>> +#define COUNT_TO_USEC(x) ((x) / 24)
>> +#define USEC_TO_COUNT(x) ((x) * 24)
>> +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
>> +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
>> +
>> +#define TIMER_LOAD_VAL 0xffffffff
>> +
>> +#define TIMER_NUM 0 /* we use timer 0 */
>> +
>> +/* read the 32-bit timer */
>> +static ulong read_timer(void)
>> +{
>> + struct sunxi_timer_reg *timers =
>> + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
>> + struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
>> +
>> + /*
>> + * The hardware timer counts down, therefore we invert to
>> + * produce an incrementing timer.
>> + */
>> + return ~readl(&timer->val);
>> +}
>> +
>> +/* init timer register */
>> +int timer_init(void)
>> +{
>> + struct sunxi_timer_reg *timers =
>> + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
>> + struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
>> +
>> + writel(TIMER_LOAD_VAL, &timer->inter);
>> + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
>> + &timer->ctl);
>> +
>> + return 0;
>> +}
>> +
>> +ulong get_timer_masked(void)
>
> Any reason you lost the static here?
No, presumibly becuse it got changed sence 2018.
>
>> +{
>> + /* current tick value */
>> + ulong now = TICKS_TO_HZ(read_timer());
>> +
>> + if (now >= gd->arch.lastinc) { /* normal (non rollover) */
>> + gd->arch.tbl += (now - gd->arch.lastinc);
>> + } else {
>> + /* rollover */
>> + gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
>> + - gd->arch.lastinc) + now;
>> + }
>> + gd->arch.lastinc = now;
>> +
>> + return gd->arch.tbl;
>> +}
>> +
>> +/* timer without interrupts */
>> +ulong get_timer(ulong base)
>> +{
>> + return get_timer_masked() - base;
>> +}
>> +
>> +/* delay x useconds */
>> +void __udelay(unsigned long usec)
>> +{
>> + long tmo = USEC_TO_COUNT(usec);
>> + ulong now, last = read_timer();
>> +
>> + while (tmo > 0) {
>> + now = read_timer();
>> + if (now > last) /* normal (non rollover) */
>> + tmo -= now - last;
>> + else /* rollover */
>> + tmo -= TIMER_LOAD_VAL - last + now;
>> + last = now;
>> + }
>> +}
>> +
>> +/*
>> + * This function is derived from PowerPC code (read timebase as long long).
>> + * On ARM it just returns the timer value.
>> + */
>> +unsigned long long get_ticks(void)
>> +{
>> + return get_timer(0);
>> +}
>> +
>> +/*
>> + * This function is derived from PowerPC code (timebase clock frequency).
>> + * On ARM it returns the number of timer ticks per second.
>> + */
>> +ulong get_tbclk(void)
>> +{
>> + return CONFIG_SYS_HZ;
>> +}
>> diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
>> new file mode 100644
>> index 0000000000..048aab788a
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
>> @@ -0,0 +1,62 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * (C) Copyright 2018
>> + * Icenowy Zheng <icenowy@aosc.io>
>> + *
>> + * Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds:
>> + *
>> + * (C) Copyright 2012
>> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
>> + * Tom Cubie <tangliang@allwinnertech.com>
>> + *
>
> I think that's enough history at this point ...
LOL I'll fix this, I think Icenowy wanted to make licencing clear.
>
>> + * Based on omap-common/u-boot-spl.lds:
>> + *
>> + * (C) Copyright 2002
>> + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
>> + *
>> + * (C) Copyright 2010
>> + * Texas Instruments, <www.ti.com>
>> + * Aneesh V <aneesh@ti.com>
>> + */
>> +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
>> + LENGTH = CONFIG_SPL_MAX_SIZE }
>> +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
>> + LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
>> +
>> +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
>> +OUTPUT_ARCH(arm)
>> +ENTRY(_start)
>> +SECTIONS
>> +{
>> + .text :
>> + {
>> + __start = .;
>> + *(.vectors)
>> + arch/arm/cpu/arm926ejs/start.o (.text)
>
> Do we actually need this, if it's empty? Isn't that file just to
> satisfy the needs of the generic linker scripts?
>
Nope I droped it and the file.
I'm impresesd with how fast you reviewd this one thanks for the
feedback. You don't have to review patch 6 unless its okay that dram
isnt using device tree, I think it should use it so thats on my todo list.
Thanks,
Jesse Taube
> Cheers,
> Andre.
>
>> + *(.text*)
>> + } > .sram
>> +
>> + . = ALIGN(4);
>> + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
>> +
>> + . = ALIGN(4);
>> + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
>> +
>> + . = ALIGN(4);
>> + .u_boot_list : {
>> + KEEP(*(SORT(.u_boot_list*)));
>> + } > .sram
>> +
>> + . = ALIGN(4);
>> + __image_copy_end = .;
>> + _end = .;
>> +
>> + .bss :
>> + {
>> + . = ALIGN(4);
>> + __bss_start = .;
>> + *(.bss*)
>> + . = ALIGN(4);
>> + __bss_end = .;
>> + } > .sdram
>> +}
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 02/11] arm: arm926ej-s: add sunxi code
2022-01-21 3:16 ` Jesse Taube
@ 2022-01-24 1:45 ` Andre Przywara
0 siblings, 0 replies; 43+ messages in thread
From: Andre Przywara @ 2022-01-24 1:45 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On Thu, 20 Jan 2022 22:16:41 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi Jesse,
> On 1/20/22 21:25, Andre Przywara wrote:
> > On Tue, 4 Jan 2022 19:34:59 -0500
> > Jesse Taube <mr.bossman075@gmail.com> wrote:
> >
> > Hi,
> >
> >> From: Icenowy Zheng <icenowy@aosc.io>
> >>
> >> Some Allwinner SoCs use ARM926EJ-S core.
> >>
> >> Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> >> ---
> >> arch/arm/cpu/arm926ejs/Makefile | 1 +
> >> arch/arm/cpu/arm926ejs/sunxi/Makefile | 15 +++
> >> arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 +
> >> arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 37 ++++++
> >> arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S | 67 +++++++++++
> >> arch/arm/cpu/arm926ejs/sunxi/start.c | 1 +
> >> arch/arm/cpu/arm926ejs/sunxi/timer.c | 114 +++++++++++++++++++
> >> arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 62 ++++++++++
> >> 8 files changed, 303 insertions(+)
> >> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile
> >> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk
> >> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
> >> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
> >> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/start.c
> >> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/timer.c
> >> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
> >>
> >> diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
> >> index b901b7c5c9..7f1436d76e 100644
> >> --- a/arch/arm/cpu/arm926ejs/Makefile
> >> +++ b/arch/arm/cpu/arm926ejs/Makefile
> >> @@ -15,6 +15,7 @@ endif
> >> obj-$(CONFIG_MX27) += mx27/
> >> obj-$(if $(filter mxs,$(SOC)),y) += mxs/
> >> obj-$(if $(filter spear,$(SOC)),y) += spear/
> >> +obj-$(CONFIG_ARCH_SUNXI) += sunxi/
> >>
> >> # some files can only build in ARM or THUMB2, not THUMB1
> >>
> >> diff --git a/arch/arm/cpu/arm926ejs/sunxi/Makefile b/arch/arm/cpu/arm926ejs/sunxi/Makefile
> >> new file mode 100644
> >> index 0000000000..894c461c50
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/arm926ejs/sunxi/Makefile
> >> @@ -0,0 +1,15 @@
> >> +# SPDX-License-Identifier: GPL-2.0+
> >> +#
> >> +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
> >> +#
> >> +# Based on some other Makefile
> >> +# (C) Copyright 2000-2003
> >> +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
> >
> > Please remove this heritage. I appreciate the effort to give credit,
> > but for a trivial Makefile stub (which even differs significantly) this
> > is surely overkill.
> > Just one line with some current copyright should be enough.
> >
> Fixed.
> >> +
> >> +obj-y += timer.o
> >> +obj-y += lowlevel_init.o
> >> +
> >> +ifdef CONFIG_SPL_BUILD
> >> +obj-y += fel_utils.o
> >> +CFLAGS_fel_utils.o := -marm
> >> +endif
> >> diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk b/arch/arm/cpu/arm926ejs/sunxi/config.mk
> >> new file mode 100644
> >> index 0000000000..76ffec9df6
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk
> >> @@ -0,0 +1,6 @@
> >> +# Build a combined spl + u-boot image
> >> +ifdef CONFIG_SPL
> >> +ifndef CONFIG_SPL_BUILD
> >> +ALL-y += u-boot-sunxi-with-spl.bin
> >> +endif
> >> +endif
> >> diff --git a/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
> >> new file mode 100644
> >> index 0000000000..0997a2dc65
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
> >> @@ -0,0 +1,37 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * Utility functions for FEL mode.
> >> + *
> >> + * Copyright (c) 2015 Google, Inc
> >> + */
> >> +
> >> +#include <asm-offsets.h>
> >> +#include <config.h>
> >> +#include <asm/system.h>
> >> +#include <linux/linkage.h>
> >> +
> >> +ENTRY(save_boot_params)
> >> + ldr r0, =fel_stash
> >> + str sp, [r0, #0]
> >> + str lr, [r0, #4]
> >> + mrs lr, cpsr @ Read CPSR
> >> + str lr, [r0, #8]
> >> + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
> >> + str lr, [r0, #12]
> >> + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
> >> + str lr, [r0, #16]
> >
> > This is the very same register twice, also written to the wrong offset.
> > Please remove the last two lines.
> > Yes, this is a bug in armv7/sunxi/fel_utils.S as well, I will send a
> > fix.
> Please CC me.
> >
> >> + b save_boot_params_ret
> >> +ENDPROC(save_boot_params)
> >> +
> >> +ENTRY(return_to_fel)
> >> + mov sp, r0
> >> + mov lr, r1
> >> + ldr r0, =fel_stash
> >> + ldr r1, [r0, #16]
> >> + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
> >
> > Same here, those two lines can be removed.
> >
> >> + ldr r1, [r0, #12]
> >> + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
> >> + ldr r1, [r0, #8]
> >> + msr cpsr, r1 @ Write CPSR
> >> + bx lr
> >> +ENDPROC(return_to_fel)
> >> diff --git a/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
> >> new file mode 100644
> >> index 0000000000..db09bcc4d0
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
> >> @@ -0,0 +1,67 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * A lowlevel_init function that sets up the stack to call a C function to
> >> + * perform further init.
> >> + *
> >> + * Based on lowlevel_init.S in armv7 directory, which is:
> >> + * (C) Copyright 2010 Texas Instruments, <www.ti.com>
> >> + */
> >> +
> >> +#include <asm-offsets.h>
> >> +#include <config.h>
> >> +#include <linux/linkage.h>
> >> +
> >> +.pushsection .text.s_init, "ax"
> >> +WEAK(s_init)
> >> + bx lr
> >> +ENDPROC(s_init)
> >> +.popsection
> >
> > I would say we don't need this weak stub. In contrast to armv7, we are
> > the only user of this file, and s_init should be provided by
> > arch/arm/mach-sunxi/board.c.
> >
> > In general the toplevel README seems to deprecate lowlevel_init, but
> > this probably needs some fixing in the other sunxi code first.
> I removed it its defined in board like you said.
> >> +
> >> +.pushsection .text.lowlevel_init, "ax"
> >> +WEAK(lowlevel_init)
> >> + /*
> >> + * Setup a temporary stack. Global data is not available yet.
> >> + */
> >> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
> >> + ldr sp, =CONFIG_SPL_STACK
> >> +#else
> >> + ldr sp, =CONFIG_SYS_INIT_SP_ADDR
> >> +#endif
> >> + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
> >> +#ifdef CONFIG_SPL_DM
> >> + mov r9, #0
> >> +#else
> >
> > We probably don't need this SPL_DM part?
> Hmmmmm you are right im assuiming this got copied from somewhere. I
> replaced the ifdef with `mov r9, #0`.
Well, we don't define SPL_DM, and probably will never do. Setting r9 to
0 does not make much sense, since we overwrite it below. So remove all
three lines and the corresponding #endif below.
But ...
> >
> >> + /*
> >> + * Set up global data for boards that still need it. This will be
> >> + * removed soon.
> >> + */
> >> +#ifdef CONFIG_SPL_BUILD
> >> + ldr r9, =gdata
> >> +#else
> >> + sub sp, sp, #GD_SIZE
> >> + bic sp, sp, #7
> >> + mov r9, sp
> >> +#endif
> >> +#endif
> >> + /*
> >> + * Save the old lr(passed in ip) and the current lr to stack
> >> + */
> >> + push {ip, lr}
> >> +
> >> + /*
> >> + * Call the very early init function. This should do only the
> >> + * absolute bare minimum to get started. It should not:
> >> + *
> >> + * - set up DRAM
> >> + * - use global_data
> >> + * - clear BSS
> >> + * - try to start a console
> >> + *
> >> + * For boards with SPL this should be empty since SPL can do all of
> >> + * this init in the SPL board_init_f() function which is called
> >> + * immediately after this.
> >> + */
> >
> > Yeah, this (copied) comments seems to suggest we are somewhat off here.
> > But I think we rely on board.c:s_init() too much to easily remove this.
> >
> > So for the sake of not blocking this I am willing to keep this part for
> > now.
> Much apretiated!
Actually I had a look, and I was able to remove the need for
lowlevel_init from sunxi altogether (in arch/.../board.c), basically by
moving the code to board_init_f() and filling the gaps. So we don't need
to copy this whole function here at all. I am not sure those patches
make it in time, though (need some more testing), so we might just go
with this (fixed) patch here, and remove lowlevel_init later.
> >
> >> + bl s_init
> >> + pop {ip, pc}
> >> +ENDPROC(lowlevel_init)
> >> +.popsection
> >> diff --git a/arch/arm/cpu/arm926ejs/sunxi/start.c b/arch/arm/cpu/arm926ejs/sunxi/start.c
> >> new file mode 100644
> >> index 0000000000..6b392fa835
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/arm926ejs/sunxi/start.c
> >> @@ -0,0 +1 @@
> >> +/* Intentionally empty. Only needed to get FEL SPL link line right */
> >> diff --git a/arch/arm/cpu/arm926ejs/sunxi/timer.c b/arch/arm/cpu/arm926ejs/sunxi/timer.c
> >> new file mode 100644
> >> index 0000000000..e624174581
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/arm926ejs/sunxi/timer.c
> >
> > I don't see immediately why the original file lives in
> > arch/arm/cpu/armv7/sunxi/timer.c. Can we move that to
> > arch/arm/mach-sunxi or board/sunxi, then just not compile it for arm64?
> > Because otherwise this looks identical to its donor, minus some smaller
> > (but good) cleanups.
> > So I'm curious if we can move and then reuse the original file.
> I will try thanks for the pointer.
> >
> >> @@ -0,0 +1,114 @@
> >> +// SPDX-License-Identifier: (GPL-2.0+)
> >> +/*
> >> + * (C) Copyright 2007-2011
> >> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> >> + * Tom Cubie <tangliang@allwinnertech.com>
> >> + */
> >> +
> >> +#include <common.h>
> >> +#include <asm/io.h>
> >> +#include <asm/arch/timer.h>
> >> +#include <asm/global_data.h>
> >> +
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +
> >> +#define TIMER_MODE (0x0 << 7) /* continuous mode */
> >> +#define TIMER_DIV (0x0 << 4) /* pre scale 1 */
> >> +#define TIMER_SRC (0x1 << 2) /* osc24m */
> >> +#define TIMER_RELOAD (0x1 << 1) /* reload internal value */
> >> +#define TIMER_EN (0x1 << 0) /* enable timer */
> >> +
> >> +#define TIMER_CLOCK (24 * 1000 * 1000)
> >> +#define COUNT_TO_USEC(x) ((x) / 24)
> >> +#define USEC_TO_COUNT(x) ((x) * 24)
> >> +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
> >> +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
> >> +
> >> +#define TIMER_LOAD_VAL 0xffffffff
> >> +
> >> +#define TIMER_NUM 0 /* we use timer 0 */
> >> +
> >> +/* read the 32-bit timer */
> >> +static ulong read_timer(void)
> >> +{
> >> + struct sunxi_timer_reg *timers =
> >> + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
> >> + struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
> >> +
> >> + /*
> >> + * The hardware timer counts down, therefore we invert to
> >> + * produce an incrementing timer.
> >> + */
> >> + return ~readl(&timer->val);
> >> +}
> >> +
> >> +/* init timer register */
> >> +int timer_init(void)
> >> +{
> >> + struct sunxi_timer_reg *timers =
> >> + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
> >> + struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
> >> +
> >> + writel(TIMER_LOAD_VAL, &timer->inter);
> >> + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
> >> + &timer->ctl);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +ulong get_timer_masked(void)
> >
> > Any reason you lost the static here?
> No, presumibly becuse it got changed sence 2018.
> >
> >> +{
> >> + /* current tick value */
> >> + ulong now = TICKS_TO_HZ(read_timer());
> >> +
> >> + if (now >= gd->arch.lastinc) { /* normal (non rollover) */
> >> + gd->arch.tbl += (now - gd->arch.lastinc);
> >> + } else {
> >> + /* rollover */
> >> + gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
> >> + - gd->arch.lastinc) + now;
> >> + }
> >> + gd->arch.lastinc = now;
> >> +
> >> + return gd->arch.tbl;
> >> +}
> >> +
> >> +/* timer without interrupts */
> >> +ulong get_timer(ulong base)
> >> +{
> >> + return get_timer_masked() - base;
> >> +}
> >> +
> >> +/* delay x useconds */
> >> +void __udelay(unsigned long usec)
> >> +{
> >> + long tmo = USEC_TO_COUNT(usec);
> >> + ulong now, last = read_timer();
> >> +
> >> + while (tmo > 0) {
> >> + now = read_timer();
> >> + if (now > last) /* normal (non rollover) */
> >> + tmo -= now - last;
> >> + else /* rollover */
> >> + tmo -= TIMER_LOAD_VAL - last + now;
> >> + last = now;
> >> + }
> >> +}
> >> +
> >> +/*
> >> + * This function is derived from PowerPC code (read timebase as long long).
> >> + * On ARM it just returns the timer value.
> >> + */
> >> +unsigned long long get_ticks(void)
> >> +{
> >> + return get_timer(0);
> >> +}
> >> +
> >> +/*
> >> + * This function is derived from PowerPC code (timebase clock frequency).
> >> + * On ARM it returns the number of timer ticks per second.
> >> + */
> >> +ulong get_tbclk(void)
> >> +{
> >> + return CONFIG_SYS_HZ;
> >> +}
> >> diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
> >> new file mode 100644
> >> index 0000000000..048aab788a
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
> >> @@ -0,0 +1,62 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * (C) Copyright 2018
> >> + * Icenowy Zheng <icenowy@aosc.io>
> >> + *
> >> + * Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds:
> >> + *
> >> + * (C) Copyright 2012
> >> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> >> + * Tom Cubie <tangliang@allwinnertech.com>
> >> + *
> >
> > I think that's enough history at this point ...
> LOL I'll fix this, I think Icenowy wanted to make licencing clear.
Well, the licensing is covered by the initial line, the copyright just
means who needs to file the lawsuit in case someone violates the GPL ;-)
It's nice to give credit, but how much copyright-able material there is
in a linker script is somewhat debatable ;-)
> >
> >> + * Based on omap-common/u-boot-spl.lds:
> >> + *
> >> + * (C) Copyright 2002
> >> + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
> >> + *
> >> + * (C) Copyright 2010
> >> + * Texas Instruments, <www.ti.com>
> >> + * Aneesh V <aneesh@ti.com>
> >> + */
> >> +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
> >> + LENGTH = CONFIG_SPL_MAX_SIZE }
> >> +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
> >> + LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
> >> +
> >> +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> >> +OUTPUT_ARCH(arm)
> >> +ENTRY(_start)
> >> +SECTIONS
> >> +{
> >> + .text :
> >> + {
> >> + __start = .;
> >> + *(.vectors)
> >> + arch/arm/cpu/arm926ejs/start.o (.text)
> >
> > Do we actually need this, if it's empty? Isn't that file just to
> > satisfy the needs of the generic linker scripts?
> >
> Nope I droped it and the file.
>
> I'm impresesd with how fast you reviewd this one thanks for the
> feedback. You don't have to review patch 6 unless its okay that dram
> isnt using device tree, I think it should use it so thats on my todo list.
No, don't bother, adding DT and/or DM to the SPL is not going to happen
anytime soon - it just complicated things for no real benefit. You can
check what it takes to move that code to drivers/ram/sunxi, though. I
think I moved one DRAM driver to boards/sunxi as an experiment before,
and that worked rather smoothly, so we might then move the other
drivers as well (though that doesn't really improve anything).
Cheers,
Andre
>
> Thanks,
> Jesse Taube
> > Cheers,
> > Andre.
> >
> >> + *(.text*)
> >> + } > .sram
> >> +
> >> + . = ALIGN(4);
> >> + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
> >> +
> >> + . = ALIGN(4);
> >> + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
> >> +
> >> + . = ALIGN(4);
> >> + .u_boot_list : {
> >> + KEEP(*(SORT(.u_boot_list*)));
> >> + } > .sram
> >> +
> >> + . = ALIGN(4);
> >> + __image_copy_end = .;
> >> + _end = .;
> >> +
> >> + .bss :
> >> + {
> >> + . = ALIGN(4);
> >> + __bss_start = .;
> >> + *(.bss*)
> >> + . = ALIGN(4);
> >> + __bss_end = .;
> >> + } > .sdram
> >> +}
> >
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 03/11] dt-bindings: clock: Add initial suniv headers
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
2022-01-05 0:34 ` [PATCH 01/11] arm: arm926ej-s: start.S: port save_boot_params support from armv7 code Jesse Taube
2022-01-05 0:34 ` [PATCH 02/11] arm: arm926ej-s: add sunxi code Jesse Taube
@ 2022-01-05 0:35 ` Jesse Taube
2022-01-21 1:57 ` Andre Przywara
2022-01-05 0:35 ` [PATCH 04/11] dt-bindings: reset: " Jesse Taube
` (8 subsequent siblings)
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:35 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
This commit introduces suniv dt-bindings headers needed for
device tree files.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
include/dt-bindings/clock/suniv-ccu.h | 68 +++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 include/dt-bindings/clock/suniv-ccu.h
diff --git a/include/dt-bindings/clock/suniv-ccu.h b/include/dt-bindings/clock/suniv-ccu.h
new file mode 100644
index 0000000000..83d3c18ac0
--- /dev/null
+++ b/include/dt-bindings/clock/suniv-ccu.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUNIV_H_
+#define _DT_BINDINGS_CLK_SUNIV_H_
+
+#define CLK_CPU 11
+
+#define CLK_BUS_MMC0 14
+#define CLK_BUS_MMC1 15
+#define CLK_BUS_DRAM 16
+#define CLK_BUS_SPI0 17
+#define CLK_BUS_SPI1 18
+#define CLK_BUS_OTG 19
+#define CLK_BUS_VE 20
+#define CLK_BUS_LCD 21
+#define CLK_BUS_DEINTERLACE 22
+#define CLK_BUS_CSI 23
+#define CLK_BUS_TVD 24
+#define CLK_BUS_TVE 25
+#define CLK_BUS_DE_BE 26
+#define CLK_BUS_DE_FE 27
+#define CLK_BUS_CODEC 28
+#define CLK_BUS_SPDIF 29
+#define CLK_BUS_IR 30
+#define CLK_BUS_RSB 31
+#define CLK_BUS_I2S0 32
+#define CLK_BUS_I2C0 33
+#define CLK_BUS_I2C1 34
+#define CLK_BUS_I2C2 35
+#define CLK_BUS_PIO 36
+#define CLK_BUS_UART0 37
+#define CLK_BUS_UART1 38
+#define CLK_BUS_UART2 39
+
+#define CLK_MMC0 40
+#define CLK_MMC0_SAMPLE 41
+#define CLK_MMC0_OUTPUT 42
+#define CLK_MMC1 43
+#define CLK_MMC1_SAMPLE 44
+#define CLK_MMC1_OUTPUT 45
+#define CLK_I2S 46
+#define CLK_SPDIF 47
+
+#define CLK_USB_PHY0 48
+
+#define CLK_DRAM_VE 49
+#define CLK_DRAM_CSI 50
+#define CLK_DRAM_DEINTERLACE 51
+#define CLK_DRAM_TVD 52
+#define CLK_DRAM_DE_FE 53
+#define CLK_DRAM_DE_BE 54
+
+#define CLK_DE_BE 55
+#define CLK_DE_FE 56
+#define CLK_TCON 57
+#define CLK_DEINTERLACE 58
+#define CLK_TVE2_CLK 59
+#define CLK_TVE1_CLK 60
+#define CLK_TVD 61
+#define CLK_CSI 62
+#define CLK_VE 63
+#define CLK_CODEC 64
+#define CLK_AVS 65
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 03/11] dt-bindings: clock: Add initial suniv headers
2022-01-05 0:35 ` [PATCH 03/11] dt-bindings: clock: Add initial suniv headers Jesse Taube
@ 2022-01-21 1:57 ` Andre Przywara
0 siblings, 0 replies; 43+ messages in thread
From: Andre Przywara @ 2022-01-21 1:57 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On Tue, 4 Jan 2022 19:35:00 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
> From: Icenowy Zheng <icenowy@aosc.io>
>
> This commit introduces suniv dt-bindings headers needed for
> device tree files.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
This seems to be some old copy, it doesn't match with what's in the
Linux kernel (different name, plus clock IDs off-by-one).
Please use a verbatim copy (under the same name) from the Linux kernel.
Cheers,
Andre
> ---
> include/dt-bindings/clock/suniv-ccu.h | 68 +++++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 include/dt-bindings/clock/suniv-ccu.h
>
> diff --git a/include/dt-bindings/clock/suniv-ccu.h b/include/dt-bindings/clock/suniv-ccu.h
> new file mode 100644
> index 0000000000..83d3c18ac0
> --- /dev/null
> +++ b/include/dt-bindings/clock/suniv-ccu.h
> @@ -0,0 +1,68 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
> +/*
> + * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SUNIV_H_
> +#define _DT_BINDINGS_CLK_SUNIV_H_
> +
> +#define CLK_CPU 11
> +
> +#define CLK_BUS_MMC0 14
> +#define CLK_BUS_MMC1 15
> +#define CLK_BUS_DRAM 16
> +#define CLK_BUS_SPI0 17
> +#define CLK_BUS_SPI1 18
> +#define CLK_BUS_OTG 19
> +#define CLK_BUS_VE 20
> +#define CLK_BUS_LCD 21
> +#define CLK_BUS_DEINTERLACE 22
> +#define CLK_BUS_CSI 23
> +#define CLK_BUS_TVD 24
> +#define CLK_BUS_TVE 25
> +#define CLK_BUS_DE_BE 26
> +#define CLK_BUS_DE_FE 27
> +#define CLK_BUS_CODEC 28
> +#define CLK_BUS_SPDIF 29
> +#define CLK_BUS_IR 30
> +#define CLK_BUS_RSB 31
> +#define CLK_BUS_I2S0 32
> +#define CLK_BUS_I2C0 33
> +#define CLK_BUS_I2C1 34
> +#define CLK_BUS_I2C2 35
> +#define CLK_BUS_PIO 36
> +#define CLK_BUS_UART0 37
> +#define CLK_BUS_UART1 38
> +#define CLK_BUS_UART2 39
> +
> +#define CLK_MMC0 40
> +#define CLK_MMC0_SAMPLE 41
> +#define CLK_MMC0_OUTPUT 42
> +#define CLK_MMC1 43
> +#define CLK_MMC1_SAMPLE 44
> +#define CLK_MMC1_OUTPUT 45
> +#define CLK_I2S 46
> +#define CLK_SPDIF 47
> +
> +#define CLK_USB_PHY0 48
> +
> +#define CLK_DRAM_VE 49
> +#define CLK_DRAM_CSI 50
> +#define CLK_DRAM_DEINTERLACE 51
> +#define CLK_DRAM_TVD 52
> +#define CLK_DRAM_DE_FE 53
> +#define CLK_DRAM_DE_BE 54
> +
> +#define CLK_DE_BE 55
> +#define CLK_DE_FE 56
> +#define CLK_TCON 57
> +#define CLK_DEINTERLACE 58
> +#define CLK_TVE2_CLK 59
> +#define CLK_TVE1_CLK 60
> +#define CLK_TVD 61
> +#define CLK_CSI 62
> +#define CLK_VE 63
> +#define CLK_CODEC 64
> +#define CLK_AVS 65
> +
> +#endif
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 04/11] dt-bindings: reset: Add initial suniv headers
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
` (2 preceding siblings ...)
2022-01-05 0:35 ` [PATCH 03/11] dt-bindings: clock: Add initial suniv headers Jesse Taube
@ 2022-01-05 0:35 ` Jesse Taube
2022-01-21 1:58 ` Andre Przywara
2022-01-05 0:35 ` [PATCH 05/11] ARM: sunxi: Add support for F1C100s Jesse Taube
` (7 subsequent siblings)
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:35 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
This commit introduces suniv dt-bindings headers
needed for device tree files.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
include/dt-bindings/reset/suniv-ccu.h | 36 +++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 include/dt-bindings/reset/suniv-ccu.h
diff --git a/include/dt-bindings/reset/suniv-ccu.h b/include/dt-bindings/reset/suniv-ccu.h
new file mode 100644
index 0000000000..d556a8dba0
--- /dev/null
+++ b/include/dt-bindings/reset/suniv-ccu.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUNIV_H_
+#define _DT_BINDINGS_RST_SUNIV_H_
+
+#define RST_USB_PHY0 0
+#define RST_BUS_MMC0 1
+#define RST_BUS_MMC1 2
+#define RST_BUS_DRAM 3
+#define RST_BUS_SPI0 4
+#define RST_BUS_SPI1 5
+#define RST_BUS_OTG 6
+#define RST_BUS_VE 7
+#define RST_BUS_LCD 8
+#define RST_BUS_DEINTERLACE 9
+#define RST_BUS_CSI 10
+#define RST_BUS_TVD 11
+#define RST_BUS_TVE 12
+#define RST_BUS_DE_BE 13
+#define RST_BUS_DE_FE 14
+#define RST_BUS_CODEC 15
+#define RST_BUS_SPDIF 16
+#define RST_BUS_IR 17
+#define RST_BUS_RSB 18
+#define RST_BUS_I2S0 19
+#define RST_BUS_I2C0 20
+#define RST_BUS_I2C1 21
+#define RST_BUS_I2C2 22
+#define RST_BUS_UART0 23
+#define RST_BUS_UART1 24
+#define RST_BUS_UART2 25
+
+#endif /* _DT_BINDINGS_RST_SUNIV_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 04/11] dt-bindings: reset: Add initial suniv headers
2022-01-05 0:35 ` [PATCH 04/11] dt-bindings: reset: " Jesse Taube
@ 2022-01-21 1:58 ` Andre Przywara
0 siblings, 0 replies; 43+ messages in thread
From: Andre Przywara @ 2022-01-21 1:58 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On Tue, 4 Jan 2022 19:35:01 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
> From: Icenowy Zheng <icenowy@aosc.io>
>
> This commit introduces suniv dt-bindings headers
> needed for device tree files.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
This seems to be some old copy, it doesn't match with what's in the
Linux kernel (different name, plus clock IDs off-by-one).
Please use a verbatim copy (under the same name) from the Linux kernel.
Cheers,
Andre
> ---
> include/dt-bindings/reset/suniv-ccu.h | 36 +++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 include/dt-bindings/reset/suniv-ccu.h
>
> diff --git a/include/dt-bindings/reset/suniv-ccu.h b/include/dt-bindings/reset/suniv-ccu.h
> new file mode 100644
> index 0000000000..d556a8dba0
> --- /dev/null
> +++ b/include/dt-bindings/reset/suniv-ccu.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
> +/*
> + * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +#ifndef _DT_BINDINGS_RST_SUNIV_H_
> +#define _DT_BINDINGS_RST_SUNIV_H_
> +
> +#define RST_USB_PHY0 0
> +#define RST_BUS_MMC0 1
> +#define RST_BUS_MMC1 2
> +#define RST_BUS_DRAM 3
> +#define RST_BUS_SPI0 4
> +#define RST_BUS_SPI1 5
> +#define RST_BUS_OTG 6
> +#define RST_BUS_VE 7
> +#define RST_BUS_LCD 8
> +#define RST_BUS_DEINTERLACE 9
> +#define RST_BUS_CSI 10
> +#define RST_BUS_TVD 11
> +#define RST_BUS_TVE 12
> +#define RST_BUS_DE_BE 13
> +#define RST_BUS_DE_FE 14
> +#define RST_BUS_CODEC 15
> +#define RST_BUS_SPDIF 16
> +#define RST_BUS_IR 17
> +#define RST_BUS_RSB 18
> +#define RST_BUS_I2S0 19
> +#define RST_BUS_I2C0 20
> +#define RST_BUS_I2C1 21
> +#define RST_BUS_I2C2 22
> +#define RST_BUS_UART0 23
> +#define RST_BUS_UART1 24
> +#define RST_BUS_UART2 25
> +
> +#endif /* _DT_BINDINGS_RST_SUNIV_H_ */
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 05/11] ARM: sunxi: Add support for F1C100s
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
` (3 preceding siblings ...)
2022-01-05 0:35 ` [PATCH 04/11] dt-bindings: reset: " Jesse Taube
@ 2022-01-05 0:35 ` Jesse Taube
2022-01-26 2:05 ` Andre Przywara
2022-01-05 0:35 ` [PATCH 06/11] sunxi: Add F1C100s DRAM initial support Jesse Taube
` (6 subsequent siblings)
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:35 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
This patch aims to add header files for the F1C100s.
The header files included add support for gpio, dram and clocks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 25 +++++++++++++++++++
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 ++++++
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
4 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index cbbe5c7a1e..2cfd540742 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -19,7 +19,7 @@
#elif defined(CONFIG_SUN50I_GEN_H6)
#include <asm/arch/clock_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
- defined(CONFIG_MACH_SUN50I)
+ defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
#include <asm/arch/clock_sun6i.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/clock_sun9i.h>
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index ee387127f3..5ecdf58bd5 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -168,6 +168,14 @@ struct sunxi_ccm_reg {
u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */
};
+/* apb1 bit field */
+#ifdef CONFIG_MACH_SUNIV
+#define APB1_GATE_UART_SHIFT (20)
+#define APB1_GATE_UART_MASK (0x7 << APB1_GATE_UART_SHIFT)
+#define APB1_GATE_TWI_SHIFT (16)
+#define APB1_GATE_TWI_MASK (0x7 << APB1_GATE_TWI_SHIFT)
+#endif
+
/* apb2 bit field */
#define APB2_CLK_SRC_LOSC (0x0 << 24)
#define APB2_CLK_SRC_OSC24M (0x1 << 24)
@@ -226,7 +234,12 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
+#if !defined(CONFIG_MACH_SUNIV)
#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
+#else
+/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */
+#define PLL6_CFG_DEFAULT 0x90041800
+#endif
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
@@ -310,6 +323,8 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_USB0 25
#define AHB_GATE_OFFSET_SATA 24
#endif
+#define AHB_GATE_OFFSET_SPI1 21
+#define AHB_GATE_OFFSET_SPI0 20
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_NAND0 13
@@ -458,6 +473,8 @@ struct sunxi_ccm_reg {
#ifdef CONFIG_MACH_SUN8I_R40
#define AHB_RESET_OFFSET_SATA 24
#endif
+#define AHB_RESET_OFFSET_SPI1 21
+#define AHB_RESET_OFFSET_SPI0 20
#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11
@@ -488,6 +505,14 @@ struct sunxi_ccm_reg {
#define AHB_RESET_OFFSET_EPHY 2
#define AHB_RESET_OFFSET_LVDS 0
+/* apb1 reset */
+#ifdef CONFIG_MACH_SUNIV
+#define APB1_RESET_UART_SHIFT (20)
+#define APB1_RESET_UART_MASK (0x7 << APB1_RESET_UART_SHIFT)
+#define APB1_RESET_TWI_SHIFT (16)
+#define APB1_RESET_TWI_MASK (0x7 << APB1_RESET_TWI_SHIFT)
+#endif
+
/* apb2 reset */
#define APB2_RESET_UART_SHIFT (16)
#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index d4c795d89c..83178dd5c8 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -122,6 +122,12 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_SJTAG_BASE 0x01c23c00
+#ifdef CONFIG_MACH_SUNIV
+#define SUNXI_UART0_BASE 0x01c25000
+#define SUNXI_UART1_BASE 0x01c25400
+#define SUNXI_UART2_BASE 0x01c25800
+#endif
+
#define SUNXI_TP_BASE 0x01c25000
#define SUNXI_PMU_BASE 0x01c25400
@@ -129,9 +135,11 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_CPUCFG_BASE 0x01c25c00
#endif
+#ifndef CONFIG_MACH_SUNIV
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
#define SUNXI_UART2_BASE 0x01c28800
+#endif
#define SUNXI_UART3_BASE 0x01c28c00
#define SUNXI_UART4_BASE 0x01c29000
#define SUNXI_UART5_BASE 0x01c29400
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f3ab1aea0e..ced69f7dd4 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -165,6 +165,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPD_LVDS0 3
#define SUNXI_GPD_PWM 2
+#define SUNIV_GPE_UART0 5
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI2 3
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 05/11] ARM: sunxi: Add support for F1C100s
2022-01-05 0:35 ` [PATCH 05/11] ARM: sunxi: Add support for F1C100s Jesse Taube
@ 2022-01-26 2:05 ` Andre Przywara
2022-01-26 4:53 ` Jesse Taube
0 siblings, 1 reply; 43+ messages in thread
From: Andre Przywara @ 2022-01-26 2:05 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
On Tue, 4 Jan 2022 19:35:02 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi,
can you please change the subject, to maybe mention clocks? Reads
rather generic as is.
> From: Icenowy Zheng <icenowy@aosc.io>
>
> This patch aims to add header files for the F1C100s.
> The header files included add support for gpio, dram and clocks.
This looks to be about clocks and UARTs only?
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 25 +++++++++++++++++++
> arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 ++++++
> arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
> 4 files changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
> index cbbe5c7a1e..2cfd540742 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
> @@ -19,7 +19,7 @@
> #elif defined(CONFIG_SUN50I_GEN_H6)
> #include <asm/arch/clock_sun50i_h6.h>
> #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
> - defined(CONFIG_MACH_SUN50I)
> + defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
> #include <asm/arch/clock_sun6i.h>
> #elif defined(CONFIG_MACH_SUN9I)
> #include <asm/arch/clock_sun9i.h>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index ee387127f3..5ecdf58bd5 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -168,6 +168,14 @@ struct sunxi_ccm_reg {
> u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */
> };
>
> +/* apb1 bit field */
> +#ifdef CONFIG_MACH_SUNIV
> +#define APB1_GATE_UART_SHIFT (20)
> +#define APB1_GATE_UART_MASK (0x7 << APB1_GATE_UART_SHIFT)
> +#define APB1_GATE_TWI_SHIFT (16)
> +#define APB1_GATE_TWI_MASK (0x7 << APB1_GATE_TWI_SHIFT)
The values match the user manual, but I don't see the *_MASK values used
anywhere. Please just drop them.
> +#endif
> +
> /* apb2 bit field */
> #define APB2_CLK_SRC_LOSC (0x0 << 24)
> #define APB2_CLK_SRC_OSC24M (0x1 << 24)
> @@ -226,7 +234,12 @@ struct sunxi_ccm_reg {
> #define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
> #define CCM_PLL5_CTRL_EN (0x1 << 31)
>
> +#if !defined(CONFIG_MACH_SUNIV)
> #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
> +#else
> +/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */
> +#define PLL6_CFG_DEFAULT 0x90041800
The manual says that bit 0 resets to 1, as in the other SoCs. It just
seems to affect the "back door clock output", so we should leave it as
1.
> +#endif
>
> #define CCM_PLL6_CTRL_N_SHIFT 8
> #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
> @@ -310,6 +323,8 @@ struct sunxi_ccm_reg {
> #define AHB_GATE_OFFSET_USB0 25
> #define AHB_GATE_OFFSET_SATA 24
> #endif
> +#define AHB_GATE_OFFSET_SPI1 21
> +#define AHB_GATE_OFFSET_SPI0 20
I think this is legacy, we don't need this anymore with the DM clock
driver we use in the SPI driver. The SPL SPI is separate anyway.
Please just drop.
> #define AHB_GATE_OFFSET_MCTL 14
> #define AHB_GATE_OFFSET_GMAC 17
> #define AHB_GATE_OFFSET_NAND0 13
> @@ -458,6 +473,8 @@ struct sunxi_ccm_reg {
> #ifdef CONFIG_MACH_SUN8I_R40
> #define AHB_RESET_OFFSET_SATA 24
> #endif
> +#define AHB_RESET_OFFSET_SPI1 21
> +#define AHB_RESET_OFFSET_SPI0 20
Same here, I don't see that used anywhere.
> #define AHB_RESET_OFFSET_GMAC 17
> #define AHB_RESET_OFFSET_MCTL 14
> #define AHB_RESET_OFFSET_MMC3 11
> @@ -488,6 +505,14 @@ struct sunxi_ccm_reg {
> #define AHB_RESET_OFFSET_EPHY 2
> #define AHB_RESET_OFFSET_LVDS 0
>
> +/* apb1 reset */
> +#ifdef CONFIG_MACH_SUNIV
> +#define APB1_RESET_UART_SHIFT (20)
> +#define APB1_RESET_UART_MASK (0x7 << APB1_RESET_UART_SHIFT)
> +#define APB1_RESET_TWI_SHIFT (16)
> +#define APB1_RESET_TWI_MASK (0x7 << APB1_RESET_TWI_SHIFT)
> +#endif
> +
> /* apb2 reset */
> #define APB2_RESET_UART_SHIFT (16)
> #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> index d4c795d89c..83178dd5c8 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> @@ -122,6 +122,12 @@ defined(CONFIG_MACH_SUN50I)
>
> #define SUNXI_SJTAG_BASE 0x01c23c00
>
> +#ifdef CONFIG_MACH_SUNIV
> +#define SUNXI_UART0_BASE 0x01c25000
> +#define SUNXI_UART1_BASE 0x01c25400
> +#define SUNXI_UART2_BASE 0x01c25800
> +#endif
That should be moved down and merged into the other chunk below.
Rest looks alright.
Cheers,
Andre
> +
> #define SUNXI_TP_BASE 0x01c25000
> #define SUNXI_PMU_BASE 0x01c25400
>
> @@ -129,9 +135,11 @@ defined(CONFIG_MACH_SUN50I)
> #define SUNXI_CPUCFG_BASE 0x01c25c00
> #endif
>
> +#ifndef CONFIG_MACH_SUNIV
> #define SUNXI_UART0_BASE 0x01c28000
> #define SUNXI_UART1_BASE 0x01c28400
> #define SUNXI_UART2_BASE 0x01c28800
> +#endif
> #define SUNXI_UART3_BASE 0x01c28c00
> #define SUNXI_UART4_BASE 0x01c29000
> #define SUNXI_UART5_BASE 0x01c29400
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index f3ab1aea0e..ced69f7dd4 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -165,6 +165,7 @@ enum sunxi_gpio_number {
> #define SUNXI_GPD_LVDS0 3
> #define SUNXI_GPD_PWM 2
>
> +#define SUNIV_GPE_UART0 5
> #define SUN8I_GPE_TWI2 3
> #define SUN50I_GPE_TWI2 3
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 05/11] ARM: sunxi: Add support for F1C100s
2022-01-26 2:05 ` Andre Przywara
@ 2022-01-26 4:53 ` Jesse Taube
2022-01-26 10:08 ` Andre Przywara
0 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-26 4:53 UTC (permalink / raw)
To: Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
On 1/25/22 21:05, Andre Przywara wrote:
> On Tue, 4 Jan 2022 19:35:02 -0500
> Jesse Taube <mr.bossman075@gmail.com> wrote:
>
> Hi,
>
> can you please change the subject, to maybe mention clocks? Reads
> rather generic as is.
>
>> From: Icenowy Zheng <icenowy@aosc.io>
>>
>> This patch aims to add header files for the F1C100s.
>> The header files included add support for gpio, dram and clocks.
>
> This looks to be about clocks and UARTs only?
>
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>> ---
>> arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
>> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 25 +++++++++++++++++++
>> arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 ++++++
>> arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
>> 4 files changed, 35 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
>> index cbbe5c7a1e..2cfd540742 100644
>> --- a/arch/arm/include/asm/arch-sunxi/clock.h
>> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
>> @@ -19,7 +19,7 @@
>> #elif defined(CONFIG_SUN50I_GEN_H6)
>> #include <asm/arch/clock_sun50i_h6.h>
>> #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
>> - defined(CONFIG_MACH_SUN50I)
>> + defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
>> #include <asm/arch/clock_sun6i.h>
>> #elif defined(CONFIG_MACH_SUN9I)
>> #include <asm/arch/clock_sun9i.h>
>> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
>> index ee387127f3..5ecdf58bd5 100644
>> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
>> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
>> @@ -168,6 +168,14 @@ struct sunxi_ccm_reg {
>> u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */
>> };
>>
>> +/* apb1 bit field */
>> +#ifdef CONFIG_MACH_SUNIV
>> +#define APB1_GATE_UART_SHIFT (20)
>> +#define APB1_GATE_UART_MASK (0x7 << APB1_GATE_UART_SHIFT)
>> +#define APB1_GATE_TWI_SHIFT (16)
>> +#define APB1_GATE_TWI_MASK (0x7 << APB1_GATE_TWI_SHIFT)
>
> The values match the user manual, but I don't see the *_MASK values used
> anywhere. Please just drop them.
>
>> +#endif
>> +
>> /* apb2 bit field */
>> #define APB2_CLK_SRC_LOSC (0x0 << 24)
>> #define APB2_CLK_SRC_OSC24M (0x1 << 24)
>> @@ -226,7 +234,12 @@ struct sunxi_ccm_reg {
>> #define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
>> #define CCM_PLL5_CTRL_EN (0x1 << 31)
>>
>> +#if !defined(CONFIG_MACH_SUNIV)
>> #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
>> +#else
>> +/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */
>> +#define PLL6_CFG_DEFAULT 0x90041800
>
> The manual says that bit 0 resets to 1, as in the other SoCs. It just
> seems to affect the "back door clock output", so we should leave it as
> 1.
Uh I don't understand.
>> +#endif
>>
>> #define CCM_PLL6_CTRL_N_SHIFT 8
>> #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
>> @@ -310,6 +323,8 @@ struct sunxi_ccm_reg {
>> #define AHB_GATE_OFFSET_USB0 25
>> #define AHB_GATE_OFFSET_SATA 24
>> #endif
>> +#define AHB_GATE_OFFSET_SPI1 21
>> +#define AHB_GATE_OFFSET_SPI0 20
>
> I think this is legacy, we don't need this anymore with the DM clock
> driver we use in the SPI driver. The SPL SPI is separate anyway.
> Please just drop.
>
>> #define AHB_GATE_OFFSET_MCTL 14
>> #define AHB_GATE_OFFSET_GMAC 17
>> #define AHB_GATE_OFFSET_NAND0 13
>> @@ -458,6 +473,8 @@ struct sunxi_ccm_reg {
>> #ifdef CONFIG_MACH_SUN8I_R40
>> #define AHB_RESET_OFFSET_SATA 24
>> #endif
>> +#define AHB_RESET_OFFSET_SPI1 21
>> +#define AHB_RESET_OFFSET_SPI0 20
>
> Same here, I don't see that used anywhere.
>
>> #define AHB_RESET_OFFSET_GMAC 17
>> #define AHB_RESET_OFFSET_MCTL 14
>> #define AHB_RESET_OFFSET_MMC3 11
>> @@ -488,6 +505,14 @@ struct sunxi_ccm_reg {
>> #define AHB_RESET_OFFSET_EPHY 2
>> #define AHB_RESET_OFFSET_LVDS 0
>>
>> +/* apb1 reset */
>> +#ifdef CONFIG_MACH_SUNIV
>> +#define APB1_RESET_UART_SHIFT (20)
>> +#define APB1_RESET_UART_MASK (0x7 << APB1_RESET_UART_SHIFT)
>> +#define APB1_RESET_TWI_SHIFT (16)
>> +#define APB1_RESET_TWI_MASK (0x7 << APB1_RESET_TWI_SHIFT)
>> +#endif
>> +
>> /* apb2 reset */
>> #define APB2_RESET_UART_SHIFT (16)
>> #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
>> index d4c795d89c..83178dd5c8 100644
>> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
>> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
>> @@ -122,6 +122,12 @@ defined(CONFIG_MACH_SUN50I)
>>
>> #define SUNXI_SJTAG_BASE 0x01c23c00
>>
>> +#ifdef CONFIG_MACH_SUNIV
>> +#define SUNXI_UART0_BASE 0x01c25000
>> +#define SUNXI_UART1_BASE 0x01c25400
>> +#define SUNXI_UART2_BASE 0x01c25800
>> +#endif
>
> That should be moved down and merged into the other chunk below.
>
> Rest looks alright.
>
> Cheers,
> Andre
>
>
>> +
>> #define SUNXI_TP_BASE 0x01c25000
>> #define SUNXI_PMU_BASE 0x01c25400
>>
>> @@ -129,9 +135,11 @@ defined(CONFIG_MACH_SUN50I)
>> #define SUNXI_CPUCFG_BASE 0x01c25c00
>> #endif
>>
>> +#ifndef CONFIG_MACH_SUNIV
>> #define SUNXI_UART0_BASE 0x01c28000
>> #define SUNXI_UART1_BASE 0x01c28400
>> #define SUNXI_UART2_BASE 0x01c28800
>> +#endif
>> #define SUNXI_UART3_BASE 0x01c28c00
>> #define SUNXI_UART4_BASE 0x01c29000
>> #define SUNXI_UART5_BASE 0x01c29400
>> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
>> index f3ab1aea0e..ced69f7dd4 100644
>> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
>> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
>> @@ -165,6 +165,7 @@ enum sunxi_gpio_number {
>> #define SUNXI_GPD_LVDS0 3
>> #define SUNXI_GPD_PWM 2
>>
>> +#define SUNIV_GPE_UART0 5
>> #define SUN8I_GPE_TWI2 3
>> #define SUN50I_GPE_TWI2 3
>>
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 05/11] ARM: sunxi: Add support for F1C100s
2022-01-26 4:53 ` Jesse Taube
@ 2022-01-26 10:08 ` Andre Przywara
0 siblings, 0 replies; 43+ messages in thread
From: Andre Przywara @ 2022-01-26 10:08 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
On Tue, 25 Jan 2022 23:53:27 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi Jesse,
> On 1/25/22 21:05, Andre Przywara wrote:
> > On Tue, 4 Jan 2022 19:35:02 -0500
> > Jesse Taube <mr.bossman075@gmail.com> wrote:
> >
> > Hi,
> >
> > can you please change the subject, to maybe mention clocks? Reads
> > rather generic as is.
> >
> >> From: Icenowy Zheng <icenowy@aosc.io>
> >>
> >> This patch aims to add header files for the F1C100s.
> >> The header files included add support for gpio, dram and clocks.
> >
> > This looks to be about clocks and UARTs only?
> >
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> >> ---
> >> arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
> >> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 25 +++++++++++++++++++
> >> arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 ++++++
> >> arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
> >> 4 files changed, 35 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
> >> index cbbe5c7a1e..2cfd540742 100644
> >> --- a/arch/arm/include/asm/arch-sunxi/clock.h
> >> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
> >> @@ -19,7 +19,7 @@
> >> #elif defined(CONFIG_SUN50I_GEN_H6)
> >> #include <asm/arch/clock_sun50i_h6.h>
> >> #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
> >> - defined(CONFIG_MACH_SUN50I)
> >> + defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
> >> #include <asm/arch/clock_sun6i.h>
> >> #elif defined(CONFIG_MACH_SUN9I)
> >> #include <asm/arch/clock_sun9i.h>
> >> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> >> index ee387127f3..5ecdf58bd5 100644
> >> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> >> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> >> @@ -168,6 +168,14 @@ struct sunxi_ccm_reg {
> >> u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */
> >> };
> >>
> >> +/* apb1 bit field */
> >> +#ifdef CONFIG_MACH_SUNIV
> >> +#define APB1_GATE_UART_SHIFT (20)
> >> +#define APB1_GATE_UART_MASK (0x7 << APB1_GATE_UART_SHIFT)
> >> +#define APB1_GATE_TWI_SHIFT (16)
> >> +#define APB1_GATE_TWI_MASK (0x7 << APB1_GATE_TWI_SHIFT)
> >
> > The values match the user manual, but I don't see the *_MASK values used
> > anywhere. Please just drop them.
> >
> >> +#endif
> >> +
> >> /* apb2 bit field */
> >> #define APB2_CLK_SRC_LOSC (0x0 << 24)
> >> #define APB2_CLK_SRC_OSC24M (0x1 << 24)
> >> @@ -226,7 +234,12 @@ struct sunxi_ccm_reg {
> >> #define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
> >> #define CCM_PLL5_CTRL_EN (0x1 << 31)
> >>
> >> +#if !defined(CONFIG_MACH_SUNIV)
> >> #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
> >> +#else
> >> +/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */
> >> +#define PLL6_CFG_DEFAULT 0x90041800
> >
> > The manual says that bit 0 resets to 1, as in the other SoCs. It just
> > seems to affect the "back door clock output", so we should leave it as
> > 1.
>
> Uh I don't understand.
If you look at the description of the PLL_PERIPH register (@0x28) in the
CCU section of the F1C200s user manual, you will find that bits 1:0 are
defaulting to 0x1, the same as for the other SoCs handled in this file.
The description says that this affects the "PLL_PERIPH back door clock
output" and is for debug only, which tells me that we should leave it
alone, as we do on the other SoCs. So the value should read 0x90041801.
Cheers,
Andre
>
> >> +#endif
> >>
> >> #define CCM_PLL6_CTRL_N_SHIFT 8
> >> #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
> >> @@ -310,6 +323,8 @@ struct sunxi_ccm_reg {
> >> #define AHB_GATE_OFFSET_USB0 25
> >> #define AHB_GATE_OFFSET_SATA 24
> >> #endif
> >> +#define AHB_GATE_OFFSET_SPI1 21
> >> +#define AHB_GATE_OFFSET_SPI0 20
> >
> > I think this is legacy, we don't need this anymore with the DM clock
> > driver we use in the SPI driver. The SPL SPI is separate anyway.
> > Please just drop.
> >
> >> #define AHB_GATE_OFFSET_MCTL 14
> >> #define AHB_GATE_OFFSET_GMAC 17
> >> #define AHB_GATE_OFFSET_NAND0 13
> >> @@ -458,6 +473,8 @@ struct sunxi_ccm_reg {
> >> #ifdef CONFIG_MACH_SUN8I_R40
> >> #define AHB_RESET_OFFSET_SATA 24
> >> #endif
> >> +#define AHB_RESET_OFFSET_SPI1 21
> >> +#define AHB_RESET_OFFSET_SPI0 20
> >
> > Same here, I don't see that used anywhere.
> >
> >> #define AHB_RESET_OFFSET_GMAC 17
> >> #define AHB_RESET_OFFSET_MCTL 14
> >> #define AHB_RESET_OFFSET_MMC3 11
> >> @@ -488,6 +505,14 @@ struct sunxi_ccm_reg {
> >> #define AHB_RESET_OFFSET_EPHY 2
> >> #define AHB_RESET_OFFSET_LVDS 0
> >>
> >> +/* apb1 reset */
> >> +#ifdef CONFIG_MACH_SUNIV
> >> +#define APB1_RESET_UART_SHIFT (20)
> >> +#define APB1_RESET_UART_MASK (0x7 << APB1_RESET_UART_SHIFT)
> >> +#define APB1_RESET_TWI_SHIFT (16)
> >> +#define APB1_RESET_TWI_MASK (0x7 << APB1_RESET_TWI_SHIFT)
> >> +#endif
> >> +
> >> /* apb2 reset */
> >> #define APB2_RESET_UART_SHIFT (16)
> >> #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
> >> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> >> index d4c795d89c..83178dd5c8 100644
> >> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> >> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> >> @@ -122,6 +122,12 @@ defined(CONFIG_MACH_SUN50I)
> >>
> >> #define SUNXI_SJTAG_BASE 0x01c23c00
> >>
> >> +#ifdef CONFIG_MACH_SUNIV
> >> +#define SUNXI_UART0_BASE 0x01c25000
> >> +#define SUNXI_UART1_BASE 0x01c25400
> >> +#define SUNXI_UART2_BASE 0x01c25800
> >> +#endif
> >
> > That should be moved down and merged into the other chunk below.
> >
> > Rest looks alright.
> >
> > Cheers,
> > Andre
> >
> >
> >> +
> >> #define SUNXI_TP_BASE 0x01c25000
> >> #define SUNXI_PMU_BASE 0x01c25400
> >>
> >> @@ -129,9 +135,11 @@ defined(CONFIG_MACH_SUN50I)
> >> #define SUNXI_CPUCFG_BASE 0x01c25c00
> >> #endif
> >>
> >> +#ifndef CONFIG_MACH_SUNIV
> >> #define SUNXI_UART0_BASE 0x01c28000
> >> #define SUNXI_UART1_BASE 0x01c28400
> >> #define SUNXI_UART2_BASE 0x01c28800
> >> +#endif
> >> #define SUNXI_UART3_BASE 0x01c28c00
> >> #define SUNXI_UART4_BASE 0x01c29000
> >> #define SUNXI_UART5_BASE 0x01c29400
> >> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> >> index f3ab1aea0e..ced69f7dd4 100644
> >> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> >> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> >> @@ -165,6 +165,7 @@ enum sunxi_gpio_number {
> >> #define SUNXI_GPD_LVDS0 3
> >> #define SUNXI_GPD_PWM 2
> >>
> >> +#define SUNIV_GPE_UART0 5
> >> #define SUN8I_GPE_TWI2 3
> >> #define SUN50I_GPE_TWI2 3
> >>
> >
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 06/11] sunxi: Add F1C100s DRAM initial support
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
` (4 preceding siblings ...)
2022-01-05 0:35 ` [PATCH 05/11] ARM: sunxi: Add support for F1C100s Jesse Taube
@ 2022-01-05 0:35 ` Jesse Taube
2022-01-05 0:35 ` [PATCH 07/11] sunxi: board: Add support for SUNIV Jesse Taube
` (5 subsequent siblings)
11 siblings, 0 replies; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:35 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
Add support for F1C100s internal dram controller.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
arch/arm/include/asm/arch-sunxi/dram.h | 2 +
arch/arm/include/asm/arch-sunxi/dram_suniv.h | 46 ++
arch/arm/mach-sunxi/Makefile | 2 +
arch/arm/mach-sunxi/dram_helpers.c | 4 +
arch/arm/mach-sunxi/dram_suniv.c | 420 +++++++++++++++++++
5 files changed, 474 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_suniv.h
create mode 100644 arch/arm/mach-sunxi/dram_suniv.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index c3b3e1f512..682daae6b1 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -31,6 +31,8 @@
#include <asm/arch/dram_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN50I_H616)
#include <asm/arch/dram_sun50i_h616.h>
+#elif defined(CONFIG_MACH_SUNIV)
+#include <asm/arch/dram_suniv.h>
#else
#include <asm/arch/dram_sun4i.h>
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_suniv.h b/arch/arm/include/asm/arch-sunxi/dram_suniv.h
new file mode 100644
index 0000000000..6f4c0512d6
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_suniv.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * suniv DRAM controller register definition
+ *
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on xboot's arch/arm32/mach-f1c100s/sys-dram.c, which is:
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ */
+
+#define PIO_SDRAM_DRV (0x2c0)
+#define PIO_SDRAM_PULL (0x2c4)
+
+#define DRAM_SCONR (0x00)
+#define DRAM_STMG0R (0x04)
+#define DRAM_STMG1R (0x08)
+#define DRAM_SCTLR (0x0c)
+#define DRAM_SREFR (0x10)
+#define DRAM_SEXTMR (0x14)
+#define DRAM_DDLYR (0x24)
+#define DRAM_DADRR (0x28)
+#define DRAM_DVALR (0x2c)
+#define DRAM_DRPTR0 (0x30)
+#define DRAM_DRPTR1 (0x34)
+#define DRAM_DRPTR2 (0x38)
+#define DRAM_DRPTR3 (0x3c)
+#define DRAM_SEFR (0x40)
+#define DRAM_MAE (0x44)
+#define DRAM_ASPR (0x48)
+#define DRAM_SDLY0 (0x4C)
+#define DRAM_SDLY1 (0x50)
+#define DRAM_SDLY2 (0x54)
+#define DRAM_MCR0 (0x100)
+#define DRAM_MCR1 (0x104)
+#define DRAM_MCR2 (0x108)
+#define DRAM_MCR3 (0x10c)
+#define DRAM_MCR4 (0x110)
+#define DRAM_MCR5 (0x114)
+#define DRAM_MCR6 (0x118)
+#define DRAM_MCR7 (0x11c)
+#define DRAM_MCR8 (0x120)
+#define DRAM_MCR9 (0x124)
+#define DRAM_MCR10 (0x128)
+#define DRAM_MCR11 (0x12c)
+#define DRAM_BWCR (0x140)
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 5d3fd70f74..42e76d4328 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y += dram_helpers.o
obj-y += pinmux.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
+obj-$(CONFIG_MACH_SUNIV) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
@@ -27,6 +28,7 @@ obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
obj-$(CONFIG_SUN50I_GEN_H6) += clock_sun50i_h6.o
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o
obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o
obj-$(CONFIG_DRAM_SUN8I_A23) += dram_sun8i_a23.o
diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index 520b597fcc..2c873192e6 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -26,7 +26,10 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val)
/*
* Test if memory at offset offset matches memory at begin of DRAM
+ *
+ * Note: dsb() is not available on ARMv5 in Thumb mode
*/
+#ifndef CONFIG_MACH_SUNIV
bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
@@ -37,3 +40,4 @@ bool mctl_mem_matches(u32 offset)
return readl(CONFIG_SYS_SDRAM_BASE) ==
readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
}
+#endif
diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c
new file mode 100644
index 0000000000..56c2d557ff
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_suniv.c
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * suniv DRAM initialization
+ *
+ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on xboot's arch/arm32/mach-f1c100s/sys-dram.c, which is:
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/gpio.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <hang.h>
+
+#define SDR_T_CAS (0x2)
+#define SDR_T_RAS (0x8)
+#define SDR_T_RCD (0x3)
+#define SDR_T_RP (0x3)
+#define SDR_T_WR (0x3)
+#define SDR_T_RFC (0xd)
+#define SDR_T_XSR (0xf9)
+#define SDR_T_RC (0xb)
+#define SDR_T_INIT (0x8)
+#define SDR_T_INIT_REF (0x7)
+#define SDR_T_WTR (0x2)
+#define SDR_T_RRD (0x2)
+#define SDR_T_XP (0x0)
+
+enum dram_type {
+ DRAM_TYPE_SDR = 0,
+ DRAM_TYPE_DDR = 1,
+ /* Not supported yet. */
+ DRAM_TYPE_MDDR = 2,
+};
+
+struct dram_para {
+ u32 size; /* dram size (unit: MByte) */
+ u32 clk; /* dram work clock (unit: MHz) */
+ u32 access_mode; /* 0: interleave mode 1: sequence mode */
+ u32 cs_num; /* dram chip count 1: one chip 2: two chip */
+ u32 ddr8_remap; /* for 8bits data width DDR 0: normal 1: 8bits */
+ enum dram_type sdr_ddr;
+ u32 bwidth; /* dram bus width */
+ u32 col_width; /* column address width */
+ u32 row_width; /* row address width */
+ u32 bank_size; /* dram bank count */
+ u32 cas; /* dram cas */
+};
+
+struct dram_para suniv_dram_para = {
+ .size = 32,
+ .clk = 156,
+ .access_mode = 1,
+ .cs_num = 1,
+ .ddr8_remap = 0,
+ .sdr_ddr = DRAM_TYPE_DDR,
+ .bwidth = 16,
+ .col_width = 10,
+ .row_width = 13,
+ .bank_size = 4,
+ .cas = 0x3,
+};
+
+static int dram_initial(void)
+{
+ unsigned int time = 0xffffff;
+
+ setbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR, 0x1);
+ while ((readl(SUNXI_DRAMC_BASE + DRAM_SCTLR) & 0x1) && time--) {
+ if (time == 0)
+ return 0;
+ }
+ return 1;
+}
+
+static int dram_delay_scan(void)
+{
+ unsigned int time = 0xffffff;
+
+ setbits_le32(SUNXI_DRAMC_BASE + DRAM_DDLYR, 0x1);
+ while ((readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) & 0x1) && time--) {
+ if (time == 0)
+ return 0;
+ }
+ return 1;
+}
+
+static void dram_set_autofresh_cycle(u32 clk)
+{
+ u32 val = 0;
+ u32 row = 0;
+ u32 temp = 0;
+
+ row = readl(SUNXI_DRAMC_BASE + DRAM_SCONR);
+ row &= 0x1e0;
+ row >>= 0x5;
+
+ if (row == 0xc) {
+ if (clk >= 1000000) {
+ temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
+ while (temp >= (10000000 >> 6)) {
+ temp -= (10000000 >> 6);
+ val++;
+ }
+ } else {
+ val = (clk * 499) >> 6;
+ }
+ } else if (row == 0xb) {
+ if (clk >= 1000000) {
+ temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
+ while (temp >= (10000000 >> 7)) {
+ temp -= (10000000 >> 7);
+ val++;
+ }
+ } else {
+ val = (clk * 499) >> 5;
+ }
+ }
+ writel(val, SUNXI_DRAMC_BASE + DRAM_SREFR);
+}
+
+static int dram_para_setup(struct dram_para *para)
+{
+ u32 val = 0;
+
+ val = (para->ddr8_remap) | (0x1 << 1) |
+ ((para->bank_size >> 2) << 3) |
+ ((para->cs_num >> 1) << 4) |
+ ((para->row_width - 1) << 5) |
+ ((para->col_width - 1) << 9) |
+ ((para->sdr_ddr ? (para->bwidth >> 4) : (para->bwidth >> 5)) << 13) |
+ (para->access_mode << 15) |
+ (para->sdr_ddr << 16);
+
+ writel(val, SUNXI_DRAMC_BASE + DRAM_SCONR);
+ setbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR, 0x1 << 19);
+ return dram_initial();
+}
+
+static u32 dram_check_delay(u32 bwidth)
+{
+ u32 dsize;
+ int i, j;
+ u32 num = 0;
+ u32 dflag = 0;
+
+ dsize = ((bwidth == 16) ? 4 : 2);
+ for (i = 0; i < dsize; i++) {
+ if (i == 0)
+ dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR0);
+ else if (i == 1)
+ dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR1);
+ else if (i == 2)
+ dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR2);
+ else if (i == 3)
+ dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR3);
+
+ for (j = 0; j < 32; j++) {
+ if (dflag & 0x1)
+ num++;
+ dflag >>= 1;
+ }
+ }
+ return num;
+}
+
+static int sdr_readpipe_scan(void)
+{
+ u32 k = 0;
+
+ for (k = 0; k < 32; k++)
+ writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k);
+ for (k = 0; k < 32; k++) {
+ if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k)
+ return 0;
+ }
+ return 1;
+}
+
+static u32 sdr_readpipe_select(void)
+{
+ u32 value = 0;
+ u32 i = 0;
+
+ for (i = 0; i < 8; i++) {
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, i << 6);
+ if (sdr_readpipe_scan()) {
+ value = i;
+ return value;
+ }
+ }
+ return value;
+}
+
+static u32 dram_check_type(struct dram_para *para)
+{
+ u32 times = 0;
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, i << 6);
+ dram_delay_scan();
+ if (readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) & 0x30)
+ times++;
+ }
+
+ if (times == 8) {
+ para->sdr_ddr = DRAM_TYPE_SDR;
+ return 0;
+ }
+ para->sdr_ddr = DRAM_TYPE_DDR;
+ return 1;
+}
+
+static u32 dram_scan_readpipe(struct dram_para *para)
+{
+ u32 rp_best = 0, rp_val = 0;
+ u32 readpipe[8];
+ int i;
+
+ if (para->sdr_ddr == DRAM_TYPE_DDR) {
+ for (i = 0; i < 8; i++) {
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, i << 6);
+ dram_delay_scan();
+ readpipe[i] = 0;
+ if ((((readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) >> 4) & 0x3) == 0x0) &&
+ (((readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) >> 4) & 0x1) == 0x0))
+ readpipe[i] = dram_check_delay(para->bwidth);
+ if (rp_val < readpipe[i]) {
+ rp_val = readpipe[i];
+ rp_best = i;
+ }
+ }
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, rp_best << 6);
+ dram_delay_scan();
+ } else {
+ clrbits_le32(SUNXI_DRAMC_BASE + DRAM_SCONR,
+ (0x1 << 16) | (0x3 << 13));
+ rp_best = sdr_readpipe_select();
+ clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
+ 0x7 << 6, rp_best << 6);
+ }
+ return 0;
+}
+
+static u32 dram_get_dram_size(struct dram_para *para)
+{
+ u32 colflag = 10, rowflag = 13;
+ u32 val1 = 0;
+ u32 count = 0;
+ u32 addr1, addr2;
+ int i;
+
+ para->col_width = colflag;
+ para->row_width = rowflag;
+ dram_para_setup(para);
+ dram_scan_readpipe(para);
+ for (i = 0; i < 32; i++) {
+ *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
+ *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
+ }
+ for (i = 0; i < 32; i++) {
+ val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i));
+ if (val1 == 0x22)
+ count++;
+ }
+ if (count == 32)
+ colflag = 9;
+ else
+ colflag = 10;
+ count = 0;
+ para->col_width = colflag;
+ para->row_width = rowflag;
+ dram_para_setup(para);
+ if (colflag == 10) {
+ addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000;
+ addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000;
+ } else {
+ addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000;
+ addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000;
+ }
+ for (i = 0; i < 32; i++) {
+ *((u8 *)(addr1 + i)) = 0x33;
+ *((u8 *)(addr2 + i)) = 0x44;
+ }
+ for (i = 0; i < 32; i++) {
+ val1 = *((u8 *)(addr1 + i));
+ if (val1 == 0x44)
+ count++;
+ }
+ if (count == 32)
+ rowflag = 12;
+ else
+ rowflag = 13;
+ para->col_width = colflag;
+ para->row_width = rowflag;
+ if (para->row_width != 13)
+ para->size = 16;
+ else if (para->col_width == 10)
+ para->size = 64;
+ else
+ para->size = 32;
+ dram_set_autofresh_cycle(para->clk);
+ para->access_mode = 0;
+ dram_para_setup(para);
+
+ return 0;
+}
+
+static void simple_dram_check(void)
+{
+ volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE;
+ int i;
+
+ for (i = 0; i < 0x40; i++)
+ dram[i] = i;
+
+ for (i = 0; i < 0x40; i++) {
+ if (dram[i] != i) {
+ printf("DRAM initialization failed: dram[0x%x] != 0x%x.", i, dram[i]);
+ hang();
+ }
+ }
+
+ for (i = 0; i < 0x10000; i += 0x40)
+ dram[i] = i;
+
+ for (i = 0; i < 0x10000; i += 0x40) {
+ if (dram[i] != i) {
+ printf("DRAM initialization failed: dram[0x%x] != 0x%x.", i, dram[i]);
+ hang();
+ }
+ }
+}
+
+static void do_dram_init(struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ u32 val;
+ u8 m; /* PLL_DDR clock factor */
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(3), 0x7);
+ mdelay(5);
+ /* TODO: dig out what's them... some analog register? */
+ if ((para->cas >> 3) & 0x1)
+ setbits_le32(SUNXI_PIO_BASE + 0x2c4, (0x1 << 23) | (0x20 << 17));
+
+ if (para->clk >= 144 && para->clk <= 180)
+ writel(0xaaa, SUNXI_PIO_BASE + 0x2c0);
+ if (para->clk >= 180)
+ writel(0xfff, SUNXI_PIO_BASE + 0x2c0);
+
+ if (para->cas & BIT(4))
+ writel(0xd1303333, &ccm->pll5_pattern_cfg);
+ else if (para->cas & BIT(5))
+ writel(0xcce06666, &ccm->pll5_pattern_cfg);
+ else if (para->cas & BIT(6))
+ writel(0xc8909999, &ccm->pll5_pattern_cfg);
+ else if (para->cas & BIT(7))
+ writel(0xc440cccc, &ccm->pll5_pattern_cfg);
+
+ if (para->clk <= 96)
+ m = 2;
+ else
+ m = 1;
+
+ val = CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+ CCM_PLL5_CTRL_N((para->clk * 2) / (24 / m)) |
+ CCM_PLL5_CTRL_K(1) | CCM_PLL5_CTRL_M(m);
+ if (para->cas & GENMASK(7, 4))
+ val |= CCM_PLL5_CTRL_SIGMA_DELTA_EN;
+ writel(val, &ccm->pll5_cfg);
+ setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_UPD);
+ mctl_await_completion(&ccm->pll5_cfg, BIT(28), BIT(28));
+ mdelay(5);
+
+ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_MCTL));
+ clrbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_RESET_OFFSET_MCTL));
+ udelay(50);
+ setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_RESET_OFFSET_MCTL));
+
+ clrsetbits_le32(SUNXI_PIO_BASE + 0x2c4, (1 << 16),
+ ((para->sdr_ddr == DRAM_TYPE_DDR) << 16));
+
+ val = (SDR_T_CAS << 0) | (SDR_T_RAS << 3) | (SDR_T_RCD << 7) |
+ (SDR_T_RP << 10) | (SDR_T_WR << 13) | (SDR_T_RFC << 15) |
+ (SDR_T_XSR << 19) | (SDR_T_RC << 28);
+ writel(val, SUNXI_DRAMC_BASE + DRAM_STMG0R);
+ val = (SDR_T_INIT << 0) | (SDR_T_INIT_REF << 16) | (SDR_T_WTR << 20) |
+ (SDR_T_RRD << 22) | (SDR_T_XP << 25);
+ writel(val, SUNXI_DRAMC_BASE + DRAM_STMG1R);
+ dram_para_setup(para);
+ dram_check_type(para);
+
+ clrsetbits_le32(SUNXI_PIO_BASE + 0x2c4, (1 << 16),
+ ((para->sdr_ddr == DRAM_TYPE_DDR) << 16));
+
+ dram_set_autofresh_cycle(para->clk);
+ dram_scan_readpipe(para);
+ dram_get_dram_size(para);
+ simple_dram_check();
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ do_dram_init(&suniv_dram_para);
+
+ return suniv_dram_para.size * 1024 * 1024;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH 07/11] sunxi: board: Add support for SUNIV
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
` (5 preceding siblings ...)
2022-01-05 0:35 ` [PATCH 06/11] sunxi: Add F1C100s DRAM initial support Jesse Taube
@ 2022-01-05 0:35 ` Jesse Taube
2022-01-21 1:58 ` Andre Przywara
2022-01-05 0:35 ` [PATCH 08/11] configs: sunxi: Add common SUNIV header Jesse Taube
` (4 subsequent siblings)
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:35 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
Generic Timer Extension is not available on SUNIV.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
board/sunxi/board.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 2790a0f9e8..59eb195c26 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -197,7 +197,7 @@ int board_init(void)
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
-#ifndef CONFIG_ARM64
+#if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
debug("id_pfr1: 0x%08x\n", id_pfr1);
/* Generic Timer Extension available? */
@@ -224,7 +224,7 @@ int board_init(void)
#endif
}
}
-#endif /* !CONFIG_ARM64 */
+#endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
ret = axp_gpio_init();
if (ret)
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 07/11] sunxi: board: Add support for SUNIV
2022-01-05 0:35 ` [PATCH 07/11] sunxi: board: Add support for SUNIV Jesse Taube
@ 2022-01-21 1:58 ` Andre Przywara
0 siblings, 0 replies; 43+ messages in thread
From: Andre Przywara @ 2022-01-21 1:58 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
On Tue, 4 Jan 2022 19:35:04 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi,
> From: Icenowy Zheng <icenowy@aosc.io>
>
> Generic Timer Extension is not available on SUNIV.
Well, that, plus there are no ID registers with which we could query
this. But that has the same effect, so:
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
> board/sunxi/board.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 2790a0f9e8..59eb195c26 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -197,7 +197,7 @@ int board_init(void)
>
> gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
>
> -#ifndef CONFIG_ARM64
> +#if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
> asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
> debug("id_pfr1: 0x%08x\n", id_pfr1);
> /* Generic Timer Extension available? */
> @@ -224,7 +224,7 @@ int board_init(void)
> #endif
> }
> }
> -#endif /* !CONFIG_ARM64 */
> +#endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
>
> ret = axp_gpio_init();
> if (ret)
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 08/11] configs: sunxi: Add common SUNIV header
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
` (6 preceding siblings ...)
2022-01-05 0:35 ` [PATCH 07/11] sunxi: board: Add support for SUNIV Jesse Taube
@ 2022-01-05 0:35 ` Jesse Taube
2022-01-26 2:07 ` Andre Przywara
2022-01-05 0:35 ` [PATCH 09/11] sunxi: Add support for SUNIV architecture Jesse Taube
` (3 subsequent siblings)
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:35 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
Adds support for SUNIV and the F1C100s.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
include/configs/suniv.h | 14 +++++++
include/configs/sunxi-common.h | 67 ++++++++++++++++++++++++----------
2 files changed, 62 insertions(+), 19 deletions(-)
create mode 100644 include/configs/suniv.h
diff --git a/include/configs/suniv.h b/include/configs/suniv.h
new file mode 100644
index 0000000000..6118cd5e1a
--- /dev/null
+++ b/include/configs/suniv.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for new Allwinner F-series (suniv) CPU
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 7260eb72a4..62004a09c1 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -22,7 +22,12 @@
/* Serial & console */
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
+#ifndef CONFIG_MACH_SUNIV
#define CONFIG_SYS_NS16550_CLK 24000000
+#else
+/* suniv doesn't have apb2 and uart is connected to apb1 */
+#define CONFIG_SYS_NS16550_CLK 100000000
+#endif
#ifndef CONFIG_DM_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE -4
# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
@@ -49,6 +54,16 @@
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
+#elif defined(CONFIG_MACH_SUNIV)
+#define SDRAM_OFFSET(x) 0x8##x
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
+/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
+ * since it needs to fit in with the other values. By also #defining it
+ * we get warnings if the Kconfig value mismatches.
+ */
+#define CONFIG_SPL_STACK_R_ADDR 0x81e00000
+#define CONFIG_SPL_BSS_START_ADDR 0x81f80000
#else
#define SDRAM_OFFSET(x) 0x4##x
#define CONFIG_SYS_SDRAM_BASE 0x40000000
@@ -109,6 +124,8 @@
#endif
#define CONFIG_SYS_MMC_MAX_DEVICE 4
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_SECT_SIZE 0x1000
#endif
/*
@@ -187,32 +204,44 @@
#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000))
#else
-/*
- * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
- * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
- * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end.
- */
-#ifndef CONFIG_MACH_SUN8I_V3S
-#define BOOTM_SIZE __stringify(0xa000000)
-#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
-#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
-#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
-#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
-#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000))
-#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000))
-#else
+#if defined(CONFIG_MACH_SUN8I_V3S)
/*
* 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
* 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
* 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end.
*/
-#define BOOTM_SIZE __stringify(0x2e00000)
-#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000))
-#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000))
-#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000))
-#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000))
+#define BOOTM_SIZE __stringify(0x2e00000)
+#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000))
+#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000))
+#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000))
#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000))
#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000))
+#elif defined(CONFIG_MACH_SUNIV)
+/*
+ * 32M RAM minus 1MB heap + 8MB for u-boot, stack, fb, etc.
+ * 8M uncompressed kernel, 4M compressed kernel, 512K fdt,
+ * 512K script, 512K pxe and the ramdisk at the end.
+ */
+#define BOOTM_SIZE __stringify(0x1700000)
+#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0500000))
+#define FDT_ADDR_R __stringify(SDRAM_OFFSET(0C00000))
+#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(0C50000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(0D00000))
+#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(0D50000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(0D60000))
+#else
+/*
+ * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
+ * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end.
+ */
+#define BOOTM_SIZE __stringify(0xa000000)
+#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
+#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
+#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
+#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000))
#endif
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 08/11] configs: sunxi: Add common SUNIV header
2022-01-05 0:35 ` [PATCH 08/11] configs: sunxi: Add common SUNIV header Jesse Taube
@ 2022-01-26 2:07 ` Andre Przywara
0 siblings, 0 replies; 43+ messages in thread
From: Andre Przywara @ 2022-01-26 2:07 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
On Tue, 4 Jan 2022 19:35:05 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi,
> From: Icenowy Zheng <icenowy@aosc.io>
>
> Adds support for SUNIV and the F1C100s.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> include/configs/suniv.h | 14 +++++++
> include/configs/sunxi-common.h | 67 ++++++++++++++++++++++++----------
> 2 files changed, 62 insertions(+), 19 deletions(-)
> create mode 100644 include/configs/suniv.h
>
> diff --git a/include/configs/suniv.h b/include/configs/suniv.h
> new file mode 100644
> index 0000000000..6118cd5e1a
> --- /dev/null
> +++ b/include/configs/suniv.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Configuration settings for new Allwinner F-series (suniv) CPU
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * Include common sunxi configuration where most the settings are
> + */
> +#include <configs/sunxi-common.h>
> +
> +#endif /* __CONFIG_H */
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 7260eb72a4..62004a09c1 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -22,7 +22,12 @@
> /* Serial & console */
> #define CONFIG_SYS_NS16550_SERIAL
> /* ns16550 reg in the low bits of cpu reg */
> +#ifndef CONFIG_MACH_SUNIV
Can you flip this around to avoid the negative logic?
> #define CONFIG_SYS_NS16550_CLK 24000000
> +#else
> +/* suniv doesn't have apb2 and uart is connected to apb1 */
> +#define CONFIG_SYS_NS16550_CLK 100000000
> +#endif
> #ifndef CONFIG_DM_SERIAL
> # define CONFIG_SYS_NS16550_REG_SIZE -4
> # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
> @@ -49,6 +54,16 @@
> * since it needs to fit in with the other values. By also #defining it
> * we get warnings if the Kconfig value mismatches. */
> #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
> +#elif defined(CONFIG_MACH_SUNIV)
> +#define SDRAM_OFFSET(x) 0x8##x
> +#define CONFIG_SYS_SDRAM_BASE 0x80000000
> +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
I am not sure this actually works? SYS_LOAD_ADDR lives in /Kconfig, you
would need to add a line there.
> +/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
> + * since it needs to fit in with the other values. By also #defining it
> + * we get warnings if the Kconfig value mismatches.
> + */
> +#define CONFIG_SPL_STACK_R_ADDR 0x81e00000
> +#define CONFIG_SPL_BSS_START_ADDR 0x81f80000
> #else
> #define SDRAM_OFFSET(x) 0x4##x
> #define CONFIG_SYS_SDRAM_BASE 0x40000000
> @@ -109,6 +124,8 @@
> #endif
>
> #define CONFIG_SYS_MMC_MAX_DEVICE 4
> +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
> +#define CONFIG_ENV_SECT_SIZE 0x1000
This lives in Kconfig, and should not be needed anyway. I think this
gets covered by my SPI fix series? Please remove those two lines.
> #endif
>
> /*
> @@ -187,32 +204,44 @@
> #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000))
>
> #else
> -/*
> - * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
> - * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
> - * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end.
> - */
> -#ifndef CONFIG_MACH_SUN8I_V3S
> -#define BOOTM_SIZE __stringify(0xa000000)
> -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
> -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
> -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
> -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
> -#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000))
> -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000))
> -#else
> +#if defined(CONFIG_MACH_SUN8I_V3S)
Please merge this with the #else above into an #elif.
> /*
> * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
> * 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
> * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end.
> */
> -#define BOOTM_SIZE __stringify(0x2e00000)
> -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000))
> -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000))
> -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000))
> -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000))
> +#define BOOTM_SIZE __stringify(0x2e00000)
> +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000))
> +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000))
> +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000))
This part should vanish: the alignment is off, and PXEFILE_ADDR_R got
dropped. I guess a rebase artefact ...
> #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000))
> #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000))
> +#elif defined(CONFIG_MACH_SUNIV)
Please add an empty line above that one, to separate the SoC classes.
> +/*
> + * 32M RAM minus 1MB heap + 8MB for u-boot, stack, fb, etc.
> + * 8M uncompressed kernel, 4M compressed kernel, 512K fdt,
> + * 512K script, 512K pxe and the ramdisk at the end.
This comment does not match the values below (which are also not
vertically aligned to the rest, as above).
compressed kernel is 7M, 320K fdt, 707K script, 320K PXE, 64K dt
overlay.
I suggest to swap the script and PXE sizes.
> + */
> +#define BOOTM_SIZE __stringify(0x1700000)
> +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0500000))
> +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(0C00000))
> +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(0C50000))
> +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(0D00000))
> +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(0D50000))
> +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(0D60000))
> +#else
Same here, an empty line above, so that it reads
...
< previous definitions>
<empty line>
#elif/#else
/*
* comment ....
...
> +/*
> + * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
> + * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
> + * 1M script, 1M pxe and the ramdisk at the end.
> + */
> +#define BOOTM_SIZE __stringify(0xa000000)
> +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
> +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
> +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
> +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
> +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000))
> +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000))
Again, this breaks the vertical alignment. Ideally it would vanish from
the diff.
Cheers,
Andre
> #endif
> #endif
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
` (7 preceding siblings ...)
2022-01-05 0:35 ` [PATCH 08/11] configs: sunxi: Add common SUNIV header Jesse Taube
@ 2022-01-05 0:35 ` Jesse Taube
2022-01-26 14:13 ` Andre Przywara
2022-01-05 0:35 ` [PATCH 10/11] ARM: dts: suniv: Add device tree files for F1C100s Jesse Taube
` (2 subsequent siblings)
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:35 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
Add support for the suniv architecture, which is newer ARM9 SoCs by
Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
sun6i.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
arch/arm/mach-sunxi/Kconfig | 16 +++++++++--
arch/arm/mach-sunxi/board.c | 31 +++++++++++++++++++--
arch/arm/mach-sunxi/clock.c | 3 +-
arch/arm/mach-sunxi/clock_sun6i.c | 46 ++++++++++++++++++++++++++++++-
arch/arm/mach-sunxi/cpu_info.c | 2 ++
5 files changed, 91 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 2c18cf02d1..9bb7717731 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,7 +1,8 @@
if ARCH_SUNXI
config SPL_LDSCRIPT
- default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
+ default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
+ default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 && !MACH_SUNIV
config IDENT_STRING
default " Allwinner Technology"
@@ -183,6 +184,12 @@ choice
prompt "Sunxi SoC Variant"
optional
+config MACH_SUNIV
+ bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
+ select CPU_ARM926EJS
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
config MACH_SUN4I
bool "sun4i (Allwinner A10)"
select CPU_V7A
@@ -587,6 +594,7 @@ config DRAM_ODT_CORRECTION
endif
config SYS_CLK_FREQ
+ default 408000000 if MACH_SUNIV
default 1008000000 if MACH_SUN4I
default 1008000000 if MACH_SUN5I
default 1008000000 if MACH_SUN6I
@@ -598,6 +606,7 @@ config SYS_CLK_FREQ
default 1008000000 if MACH_SUN50I_H616
config SYS_CONFIG_NAME
+ default "suniv" if MACH_SUNIV
default "sun4i" if MACH_SUN4I
default "sun5i" if MACH_SUN5I
default "sun6i" if MACH_SUN6I
@@ -805,7 +814,7 @@ config VIDEO_SUNXI
config VIDEO_HDMI
bool "HDMI output support"
- depends on VIDEO_SUNXI && !MACH_SUN8I
+ depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
default y
---help---
Say Y here to add support for outputting video over HDMI.
@@ -1005,6 +1014,7 @@ config GMAC_TX_DELAY
Set the GMAC Transmit Clock Delay Chain value.
config SPL_STACK_R_ADDR
+ default 0x81e00000 if MACH_SUNIV
default 0x4fe00000 if MACH_SUN4I
default 0x4fe00000 if MACH_SUN5I
default 0x4fe00000 if MACH_SUN6I
@@ -1016,7 +1026,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 3ef179742c..2fee86b49b 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -86,7 +86,8 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
-#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
+#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \
+ defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
@@ -94,6 +95,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40))
@@ -219,7 +224,8 @@ void s_init(void)
/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
#endif
-#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
+#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) && \
+ !defined(CONFIG_MACH_SUNIV)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
@@ -328,10 +334,31 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
return sector;
}
+#ifndef CONFIG_MACH_SUNIV
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
+#else
+/*
+ * suniv BROM do not pass the boot media type to SPL, so we try with the
+ * boot sequence in BROM: mmc0->spinor->fail.
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+ * See the comments above in sunxi_get_boot_device() for information
+ * about FEL boot.
+ */
+ if (!is_boot0_magic(SPL_ADDR + 4)) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+}
+#endif
void board_init_f(ulong dummy)
{
diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
index de7e875298..da3a0eb058 100644
--- a/arch/arm/mach-sunxi/clock.c
+++ b/arch/arm/mach-sunxi/clock.c
@@ -35,7 +35,8 @@ int clock_init(void)
}
/* These functions are shared between various SoCs so put them here. */
-#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I && \
+ !defined CONFIG_MACH_SUNIV
int clock_twi_onoff(int port, int state)
{
struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 8e84062bd7..b0b3ea4d30 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -23,7 +23,8 @@ void clock_init_safe(void)
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \
+ !defined(CONFIG_MACH_SUNIV)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
@@ -49,9 +50,11 @@ void clock_init_safe(void)
writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+#ifndef CONFIG_MACH_SUNIV
writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
if (IS_ENABLED(CONFIG_MACH_SUN6I))
writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+#endif
#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
@@ -87,6 +90,7 @@ void clock_init_uart(void)
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#ifndef CONFIG_MACH_SUNIV
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
APB2_CLK_RATE_N_1|
@@ -102,6 +106,24 @@ void clock_init_uart(void)
setbits_le32(&ccm->apb2_reset_cfg,
1 << (APB2_RESET_UART_SHIFT +
CONFIG_CONS_INDEX - 1));
+#else
+ /* suniv doesn't have apb2, so uart clock source is apb1 */
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+ while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
+ ;
+
+ writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->apb1_reset_cfg,
+ 1 << (APB1_RESET_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+#endif
#else
/* enable R_PIO and R_UART clocks, and de-assert resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
@@ -125,10 +147,15 @@ void clock_set_pll1(unsigned int clk)
}
/* Switch to 24MHz clock while changing PLL1 */
+#ifndef CONFIG_MACH_SUNIV
writel(AXI_DIV_3 << AXI_DIV_SHIFT |
ATB_DIV_2 << ATB_DIV_SHIFT |
CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
&ccm->cpu_axi_cfg);
+#else
+ writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+#endif
/*
* sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
@@ -137,13 +164,26 @@ void clock_set_pll1(unsigned int clk)
writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
+#ifndef CONFIG_MACH_SUNIV
sdelay(200);
+#else
+ /* ARM926EJ-S code does not have sdelay */
+ volatile int i = 200;
+
+ while (i > 0)
+ i--;
+#endif
/* Switch CPU to PLL1 */
+#ifndef CONFIG_MACH_SUNIV
writel(AXI_DIV_3 << AXI_DIV_SHIFT |
ATB_DIV_2 << ATB_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_axi_cfg);
+#else
+ writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+#endif
}
#endif
@@ -317,7 +357,11 @@ unsigned int clock_get_pll6(void)
uint32_t rval = readl(&ccm->pll6_cfg);
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+#ifndef CONFIG_MACH_SUNIV
return 24000000 * n * k / 2;
+#else
+ return 24000000 * n * k;
+#endif
}
unsigned int clock_get_mipi_pll(void)
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index ba33ef2430..7eef178859 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -57,6 +57,8 @@ int print_cpuinfo(void)
{
#ifdef CONFIG_MACH_SUN4I
puts("CPU: Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_MACH_SUNIV
+ puts("CPU: Allwinner F Series (SUNIV)\n");
#elif defined CONFIG_MACH_SUN5I
u32 val = readl(SUNXI_SID_BASE + 0x08);
switch ((val >> 12) & 0xf) {
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-05 0:35 ` [PATCH 09/11] sunxi: Add support for SUNIV architecture Jesse Taube
@ 2022-01-26 14:13 ` Andre Przywara
2022-01-26 14:38 ` Jesse Taube
0 siblings, 1 reply; 43+ messages in thread
From: Andre Przywara @ 2022-01-26 14:13 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On Tue, 4 Jan 2022 19:35:06 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi Jesse,
I was checking some bits and pieces here, so sorry for the delay. I saw
your v2, and will review that ASAP, so that we get one step closer. Please
don't send a v3 before that.
If you have some time, can you also meanwhile check if this series is
bisectable, meaning that every patch compiles? I have the feeling there is
something off, but didn't check it. Pick an H3 and an A64 board, and
compile it after each patch. I can do this as well, if you don't find the
time for this.
In general I am tempted to merge this still in this cycle, since we don't
have other big changes, but we would need to settle this by early next
week then.
See below for more work ;-) (Sorry!)
> From: Icenowy Zheng <icenowy@aosc.io>
>
> Add support for the suniv architecture, which is newer ARM9 SoCs by
> Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
> sun6i.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> arch/arm/mach-sunxi/Kconfig | 16 +++++++++--
> arch/arm/mach-sunxi/board.c | 31 +++++++++++++++++++--
> arch/arm/mach-sunxi/clock.c | 3 +-
> arch/arm/mach-sunxi/clock_sun6i.c | 46 ++++++++++++++++++++++++++++++-
> arch/arm/mach-sunxi/cpu_info.c | 2 ++
> 5 files changed, 91 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 2c18cf02d1..9bb7717731 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -1,7 +1,8 @@
> if ARCH_SUNXI
>
> config SPL_LDSCRIPT
> - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
> + default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
> + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 && !MACH_SUNIV
>
> config IDENT_STRING
> default " Allwinner Technology"
> @@ -183,6 +184,12 @@ choice
> prompt "Sunxi SoC Variant"
> optional
>
> +config MACH_SUNIV
> + bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
> + select CPU_ARM926EJS
> + select SUNXI_GEN_SUN6I
> + select SUPPORT_SPL
> +
> config MACH_SUN4I
> bool "sun4i (Allwinner A10)"
> select CPU_V7A
> @@ -587,6 +594,7 @@ config DRAM_ODT_CORRECTION
> endif
>
> config SYS_CLK_FREQ
> + default 408000000 if MACH_SUNIV
> default 1008000000 if MACH_SUN4I
> default 1008000000 if MACH_SUN5I
> default 1008000000 if MACH_SUN6I
> @@ -598,6 +606,7 @@ config SYS_CLK_FREQ
> default 1008000000 if MACH_SUN50I_H616
>
> config SYS_CONFIG_NAME
> + default "suniv" if MACH_SUNIV
> default "sun4i" if MACH_SUN4I
> default "sun5i" if MACH_SUN5I
> default "sun6i" if MACH_SUN6I
> @@ -805,7 +814,7 @@ config VIDEO_SUNXI
>
> config VIDEO_HDMI
> bool "HDMI output support"
> - depends on VIDEO_SUNXI && !MACH_SUN8I
> + depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
> default y
> ---help---
> Say Y here to add support for outputting video over HDMI.
> @@ -1005,6 +1014,7 @@ config GMAC_TX_DELAY
> Set the GMAC Transmit Clock Delay Chain value.
>
> config SPL_STACK_R_ADDR
> + default 0x81e00000 if MACH_SUNIV
> default 0x4fe00000 if MACH_SUN4I
> default 0x4fe00000 if MACH_SUN5I
> default 0x4fe00000 if MACH_SUN6I
> @@ -1016,7 +1026,7 @@ config SPL_STACK_R_ADDR
>
> config SPL_SPI_SUNXI
> bool "Support for SPI Flash on Allwinner SoCs in SPL"
> - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
> + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV
I think this is premature without the corresponding patch to
spl_spi_sunxi.c.
> help
> Enable support for SPI Flash. This option allows SPL to read from
> sunxi SPI Flash. It uses the same method as the boot ROM, so does
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index 3ef179742c..2fee86b49b 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -86,7 +86,8 @@ static int gpio_init(void)
> sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
> sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
> #endif
> -#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
> +#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \
> + defined(CONFIG_MACH_SUNIV)
> sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
> #else
> @@ -94,6 +95,10 @@ static int gpio_init(void)
> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
> #endif
> sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
> + sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
> + sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
> + sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
> #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
> defined(CONFIG_MACH_SUN7I) || \
> defined(CONFIG_MACH_SUN8I_R40))
> @@ -219,7 +224,8 @@ void s_init(void)
> /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
> #endif
>
> -#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
> +#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) && \
> + !defined(CONFIG_MACH_SUNIV)
That looks correct for now, but should become obsolete with my
lowlevel_init cleanup series.
> /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
> asm volatile(
> "mrc p15, 0, r0, c1, c0, 1\n"
> @@ -328,10 +334,31 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
> return sector;
> }
>
> +#ifndef CONFIG_MACH_SUNIV
Can you please flip this around to avoid the negative logic?
> u32 spl_boot_device(void)
> {
> return sunxi_get_boot_device();
> }
> +#else
> +/*
> + * suniv BROM do not pass the boot media type to SPL, so we try with the
> + * boot sequence in BROM: mmc0->spinor->fail.
> + */
> +void board_boot_order(u32 *spl_boot_list)
> +{
> + /*
> + * See the comments above in sunxi_get_boot_device() for information
> + * about FEL boot.
> + */
> + if (!is_boot0_magic(SPL_ADDR + 4)) {
> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
> + return;
> + }
> +
> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
So does that mean that it tries MMC first, even when booted via SPI? So if
there is a *non*-bootable microSD card in, it will read something from
sector 80, and will execute that if this is a FIT or legacy image?
I wonder if we actually have some indication of SPI booting, for instance
the pinmux or clock settings?
Otherwise we would really need to mimic the BROM, and read and verify the
eGON header again, to be reliable.
I might be talked into ignoring this issue for now, if there will be a fix
patch later on.
> + spl_boot_list[1] = BOOT_DEVICE_SPI;
> +}
> +#endif
>
> void board_init_f(ulong dummy)
> {
> diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
> index de7e875298..da3a0eb058 100644
> --- a/arch/arm/mach-sunxi/clock.c
> +++ b/arch/arm/mach-sunxi/clock.c
> @@ -35,7 +35,8 @@ int clock_init(void)
> }
>
> /* These functions are shared between various SoCs so put them here. */
> -#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
> +#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I && \
> + !defined CONFIG_MACH_SUNIV
> int clock_twi_onoff(int port, int state)
> {
> struct sunxi_ccm_reg *const ccm =
> diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
> index 8e84062bd7..b0b3ea4d30 100644
> --- a/arch/arm/mach-sunxi/clock_sun6i.c
> +++ b/arch/arm/mach-sunxi/clock_sun6i.c
> @@ -23,7 +23,8 @@ void clock_init_safe(void)
> struct sunxi_ccm_reg * const ccm =
> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>
> -#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
> +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \
> + !defined(CONFIG_MACH_SUNIV)
> struct sunxi_prcm_reg * const prcm =
> (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>
> @@ -49,9 +50,11 @@ void clock_init_safe(void)
>
> writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
>
> +#ifndef CONFIG_MACH_SUNIV
> writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
> if (IS_ENABLED(CONFIG_MACH_SUN6I))
> writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
> +#endif
>
> #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
> setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
> @@ -87,6 +90,7 @@ void clock_init_uart(void)
> struct sunxi_ccm_reg *const ccm =
> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>
> +#ifndef CONFIG_MACH_SUNIV
Please again negate and swap the branches.
> /* uart clock source is apb2 */
> writel(APB2_CLK_SRC_OSC24M|
> APB2_CLK_RATE_N_1|
> @@ -102,6 +106,24 @@ void clock_init_uart(void)
> setbits_le32(&ccm->apb2_reset_cfg,
> 1 << (APB2_RESET_UART_SHIFT +
> CONFIG_CONS_INDEX - 1));
> +#else
> + /* suniv doesn't have apb2, so uart clock source is apb1 */
> + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
> + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
> + ;
> +
> + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
This is done is clock_init_safe() already, which is called before
clock_init_uart(). I feel we should drop it here, not only because
touching a PLL again might cause problems.
> +
> + /* open the clock for uart */
> + setbits_le32(&ccm->apb1_gate,
> + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
> + CONFIG_CONS_INDEX - 1));
> +
> + /* deassert uart reset */
> + setbits_le32(&ccm->apb1_reset_cfg,
> + 1 << (APB1_RESET_UART_SHIFT +
> + CONFIG_CONS_INDEX - 1));
> +#endif
> #else
> /* enable R_PIO and R_UART clocks, and de-assert resets */
> prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
> @@ -125,10 +147,15 @@ void clock_set_pll1(unsigned int clk)
> }
>
> /* Switch to 24MHz clock while changing PLL1 */
> +#ifndef CONFIG_MACH_SUNIV
Same negation here. And can you please turn those preprocessor guards into
if (IS_ENABLED(CONFIG_MACH_SUNIV)) ...
where applicable? That's always preferred, if all symbols used inside both
branches are defined in either case, as in here, for instance.
As the compiler will see that it's a compile-time constant, it will remove
the non-applicable branch. So the effect on the code is mostly the same,
but both branches are "compile-tested" and it's more readable, as the
nesting is done properly.
> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
> ATB_DIV_2 << ATB_DIV_SHIFT |
> CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
> &ccm->cpu_axi_cfg);
> +#else
> + writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
> + &ccm->cpu_axi_cfg);
> +#endif
>
> /*
> * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
> @@ -137,13 +164,26 @@ void clock_set_pll1(unsigned int clk)
> writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
> CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
> CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
> +#ifndef CONFIG_MACH_SUNIV
Guess ...
> sdelay(200);
> +#else
> + /* ARM926EJ-S code does not have sdelay */
I wonder if we should just copy a definition of it to
arch/arm/cpu/arm926ejs. The ARMv7 assembly should just work.
> + volatile int i = 200;
> +
> + while (i > 0)
> + i--;
> +#endif
>
> /* Switch CPU to PLL1 */
> +#ifndef CONFIG_MACH_SUNIV
Negate and if(IS_ENABLED(...)), please.
> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
> ATB_DIV_2 << ATB_DIV_SHIFT |
> CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
> &ccm->cpu_axi_cfg);
> +#else
> + writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
> + &ccm->cpu_axi_cfg);
> +#endif
> }
> #endif
>
> @@ -317,7 +357,11 @@ unsigned int clock_get_pll6(void)
> uint32_t rval = readl(&ccm->pll6_cfg);
> int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
> int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
> +#ifndef CONFIG_MACH_SUNIV
Negate and if(IS_ENABLED(...)), please.
> return 24000000 * n * k / 2;
> +#else
> + return 24000000 * n * k;
> +#endif
> }
This whole file is admittedly quite messy. We should be able to move the
video clocks out here and into our DM clock driver, but this is
non-trivial, I believe, so I won't ask you doing this ;-)
Cheers,
Andre
>
> unsigned int clock_get_mipi_pll(void)
> diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
> index ba33ef2430..7eef178859 100644
> --- a/arch/arm/mach-sunxi/cpu_info.c
> +++ b/arch/arm/mach-sunxi/cpu_info.c
> @@ -57,6 +57,8 @@ int print_cpuinfo(void)
> {
> #ifdef CONFIG_MACH_SUN4I
> puts("CPU: Allwinner A10 (SUN4I)\n");
> +#elif defined CONFIG_MACH_SUNIV
> + puts("CPU: Allwinner F Series (SUNIV)\n");
> #elif defined CONFIG_MACH_SUN5I
> u32 val = readl(SUNXI_SID_BASE + 0x08);
> switch ((val >> 12) & 0xf) {
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-26 14:13 ` Andre Przywara
@ 2022-01-26 14:38 ` Jesse Taube
2022-01-29 3:21 ` Jesse Taube
0 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-26 14:38 UTC (permalink / raw)
To: Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On 1/26/22 09:13, Andre Przywara wrote:
> On Tue, 4 Jan 2022 19:35:06 -0500
> Jesse Taube <mr.bossman075@gmail.com> wrote:
>
> Hi Jesse,
>
> I was checking some bits and pieces here, so sorry for the delay. I saw
> your v2, and will review that ASAP, so that we get one step closer. Please
> don't send a v3 before that.
>
> If you have some time, can you also meanwhile check if this series is
> bisectable, meaning that every patch compiles? I have the feeling there is
> something off, but didn't check it. Pick an H3 and an A64 board, and
> compile it after each patch. I can do this as well, if you don't find the
> time for this.
I didnt check for bisectability but i did order the patches to avoid it.
>
> In general I am tempted to merge this still in this cycle, since we don't
> have other big changes, but we would need to settle this by early next
> week then.
>
> See below for more work ;-) (Sorry!)
Its okay.
>
>> From: Icenowy Zheng <icenowy@aosc.io>
>>
>> Add support for the suniv architecture, which is newer ARM9 SoCs by
>> Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
>> sun6i.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>> ---
>> arch/arm/mach-sunxi/Kconfig | 16 +++++++++--
>> arch/arm/mach-sunxi/board.c | 31 +++++++++++++++++++--
>> arch/arm/mach-sunxi/clock.c | 3 +-
>> arch/arm/mach-sunxi/clock_sun6i.c | 46 ++++++++++++++++++++++++++++++-
>> arch/arm/mach-sunxi/cpu_info.c | 2 ++
>> 5 files changed, 91 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
>> index 2c18cf02d1..9bb7717731 100644
>> --- a/arch/arm/mach-sunxi/Kconfig
>> +++ b/arch/arm/mach-sunxi/Kconfig
>> @@ -1,7 +1,8 @@
>> if ARCH_SUNXI
>>
>> config SPL_LDSCRIPT
>> - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
>> + default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
>> + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 && !MACH_SUNIV
>>
>> config IDENT_STRING
>> default " Allwinner Technology"
>> @@ -183,6 +184,12 @@ choice
>> prompt "Sunxi SoC Variant"
>> optional
>>
>> +config MACH_SUNIV
>> + bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
>> + select CPU_ARM926EJS
>> + select SUNXI_GEN_SUN6I
>> + select SUPPORT_SPL
>> +
>> config MACH_SUN4I
>> bool "sun4i (Allwinner A10)"
>> select CPU_V7A
>> @@ -587,6 +594,7 @@ config DRAM_ODT_CORRECTION
>> endif
>>
>> config SYS_CLK_FREQ
>> + default 408000000 if MACH_SUNIV
>> default 1008000000 if MACH_SUN4I
>> default 1008000000 if MACH_SUN5I
>> default 1008000000 if MACH_SUN6I
>> @@ -598,6 +606,7 @@ config SYS_CLK_FREQ
>> default 1008000000 if MACH_SUN50I_H616
>>
>> config SYS_CONFIG_NAME
>> + default "suniv" if MACH_SUNIV
>> default "sun4i" if MACH_SUN4I
>> default "sun5i" if MACH_SUN5I
>> default "sun6i" if MACH_SUN6I
>> @@ -805,7 +814,7 @@ config VIDEO_SUNXI
>>
>> config VIDEO_HDMI
>> bool "HDMI output support"
>> - depends on VIDEO_SUNXI && !MACH_SUN8I
>> + depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
>> default y
>> ---help---
>> Say Y here to add support for outputting video over HDMI.
>> @@ -1005,6 +1014,7 @@ config GMAC_TX_DELAY
>> Set the GMAC Transmit Clock Delay Chain value.
>>
>> config SPL_STACK_R_ADDR
>> + default 0x81e00000 if MACH_SUNIV
>> default 0x4fe00000 if MACH_SUN4I
>> default 0x4fe00000 if MACH_SUN5I
>> default 0x4fe00000 if MACH_SUN6I
>> @@ -1016,7 +1026,7 @@ config SPL_STACK_R_ADDR
>>
>> config SPL_SPI_SUNXI
>> bool "Support for SPI Flash on Allwinner SoCs in SPL"
>> - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
>> + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV
>
> I think this is premature without the corresponding patch to
> spl_spi_sunxi.c.
Ill look into this.
>
>> help
>> Enable support for SPI Flash. This option allows SPL to read from
>> sunxi SPI Flash. It uses the same method as the boot ROM, so does
>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
>> index 3ef179742c..2fee86b49b 100644
>> --- a/arch/arm/mach-sunxi/board.c
>> +++ b/arch/arm/mach-sunxi/board.c
>> @@ -86,7 +86,8 @@ static int gpio_init(void)
>> sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
>> sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
>> #endif
>> -#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
>> +#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \
>> + defined(CONFIG_MACH_SUNIV)
>> sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
>> #else
>> @@ -94,6 +95,10 @@ static int gpio_init(void)
>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
>> #endif
>> sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
>> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
>> + sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
>> #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
>> defined(CONFIG_MACH_SUN7I) || \
>> defined(CONFIG_MACH_SUN8I_R40))
>> @@ -219,7 +224,8 @@ void s_init(void)
>> /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
>> #endif
>>
>> -#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
>> +#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) && \
>> + !defined(CONFIG_MACH_SUNIV)
>
> That looks correct for now, but should become obsolete with my
> lowlevel_init cleanup series.
Yes in V2 i fix this line, but it breaks compiling without your patch.
Idk if you want a bad compile or a bad merge.
>
>> /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
>> asm volatile(
>> "mrc p15, 0, r0, c1, c0, 1\n"
>> @@ -328,10 +334,31 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
>> return sector;
>> }
>>
>> +#ifndef CONFIG_MACH_SUNIV
>
> Can you please flip this around to avoid the negative logic?
Ah yes i will.
>
>> u32 spl_boot_device(void)
>> {
>> return sunxi_get_boot_device();
>> }
>> +#else
>> +/*
>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>> + * boot sequence in BROM: mmc0->spinor->fail.
>> + */
>> +void board_boot_order(u32 *spl_boot_list)
>> +{
>> + /*
>> + * See the comments above in sunxi_get_boot_device() for information
>> + * about FEL boot.
>> + */
>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>> + return;
>> + }
>> +
>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>
> So does that mean that it tries MMC first, even when booted via SPI? So if
> there is a *non*-bootable microSD card in, it will read something from
> sector 80, and will execute that if this is a FIT or legacy image?
yes
>
> I wonder if we actually have some indication of SPI booting, for instance
> the pinmux or clock settings?
> Otherwise we would really need to mimic the BROM, and read and verify the
> eGON header again, to be reliable.
HMM this should be fixed thx for pointing this out.
>
> I might be talked into ignoring this issue for now, if there will be a fix
> patch later on.
>
>> + spl_boot_list[1] = BOOT_DEVICE_SPI;
>> +}
>> +#endif
>>
>> void board_init_f(ulong dummy)
>> {
>> diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
>> index de7e875298..da3a0eb058 100644
>> --- a/arch/arm/mach-sunxi/clock.c
>> +++ b/arch/arm/mach-sunxi/clock.c
>> @@ -35,7 +35,8 @@ int clock_init(void)
>> }
>>
>> /* These functions are shared between various SoCs so put them here. */
>> -#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
>> +#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I && \
>> + !defined CONFIG_MACH_SUNIV
>> int clock_twi_onoff(int port, int state)
>> {
>> struct sunxi_ccm_reg *const ccm =
>> diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
>> index 8e84062bd7..b0b3ea4d30 100644
>> --- a/arch/arm/mach-sunxi/clock_sun6i.c
>> +++ b/arch/arm/mach-sunxi/clock_sun6i.c
>> @@ -23,7 +23,8 @@ void clock_init_safe(void)
>> struct sunxi_ccm_reg * const ccm =
>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>
>> -#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
>> +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \
>> + !defined(CONFIG_MACH_SUNIV)
>> struct sunxi_prcm_reg * const prcm =
>> (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>>
>> @@ -49,9 +50,11 @@ void clock_init_safe(void)
>>
>> writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
>>
>> +#ifndef CONFIG_MACH_SUNIV
>> writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
>> if (IS_ENABLED(CONFIG_MACH_SUN6I))
>> writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
>> +#endif
>>
>> #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
>> setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
>> @@ -87,6 +90,7 @@ void clock_init_uart(void)
>> struct sunxi_ccm_reg *const ccm =
>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>
>> +#ifndef CONFIG_MACH_SUNIV
>
> Please again negate and swap the branches.
>
>> /* uart clock source is apb2 */
>> writel(APB2_CLK_SRC_OSC24M|
>> APB2_CLK_RATE_N_1|
>> @@ -102,6 +106,24 @@ void clock_init_uart(void)
>> setbits_le32(&ccm->apb2_reset_cfg,
>> 1 << (APB2_RESET_UART_SHIFT +
>> CONFIG_CONS_INDEX - 1));
>> +#else
>> + /* suniv doesn't have apb2, so uart clock source is apb1 */
>> + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
>> + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
>> + ;
>> +
>> + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
>
> This is done is clock_init_safe() already, which is called before
> clock_init_uart(). I feel we should drop it here, not only because
> touching a PLL again might cause problems.
Okay.
>
>> +
>> + /* open the clock for uart */
>> + setbits_le32(&ccm->apb1_gate,
>> + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
>> + CONFIG_CONS_INDEX - 1));
>> +
>> + /* deassert uart reset */
>> + setbits_le32(&ccm->apb1_reset_cfg,
>> + 1 << (APB1_RESET_UART_SHIFT +
>> + CONFIG_CONS_INDEX - 1));
>> +#endif
>> #else
>> /* enable R_PIO and R_UART clocks, and de-assert resets */
>> prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
>> @@ -125,10 +147,15 @@ void clock_set_pll1(unsigned int clk)
>> }
>>
>> /* Switch to 24MHz clock while changing PLL1 */
>> +#ifndef CONFIG_MACH_SUNIV
>
> Same negation here. And can you please turn those preprocessor guards into
> if (IS_ENABLED(CONFIG_MACH_SUNIV)) ...
> where applicable? That's always preferred, if all symbols used inside both
> branches are defined in either case, as in here, for instance.
> As the compiler will see that it's a compile-time constant, it will remove
> the non-applicable branch. So the effect on the code is mostly the same,
> but both branches are "compile-tested" and it's more readable, as the
> nesting is done properly.
>
>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
>> ATB_DIV_2 << ATB_DIV_SHIFT |
>> CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
>> &ccm->cpu_axi_cfg);
>> +#else
>> + writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
>> + &ccm->cpu_axi_cfg);
>> +#endif
>>
>> /*
>> * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
>> @@ -137,13 +164,26 @@ void clock_set_pll1(unsigned int clk)
>> writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
>> CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
>> CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
>> +#ifndef CONFIG_MACH_SUNIV
>
> Guess ...
Sorry i didnt think it would be too bit a problem.
>
>> sdelay(200);
>> +#else
>> + /* ARM926EJ-S code does not have sdelay */
>
> I wonder if we should just copy a definition of it to
> arch/arm/cpu/arm926ejs. The ARMv7 assembly should just work.
I will try. if it doesnt work i will add.
>> + volatile int i = 200;
>> +
>> + while (i > 0)
>> + i--;
>> +#endif
>>
>> /* Switch CPU to PLL1 */
>> +#ifndef CONFIG_MACH_SUNIV
>
> Negate and if(IS_ENABLED(...)), please.
>
>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
>> ATB_DIV_2 << ATB_DIV_SHIFT |
>> CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
>> &ccm->cpu_axi_cfg);
>> +#else
>> + writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
>> + &ccm->cpu_axi_cfg);
>> +#endif
>> }
>> #endif
>>
>> @@ -317,7 +357,11 @@ unsigned int clock_get_pll6(void)
>> uint32_t rval = readl(&ccm->pll6_cfg);
>> int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
>> int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
>> +#ifndef CONFIG_MACH_SUNIV
>
> Negate and if(IS_ENABLED(...)), please.
>
>> return 24000000 * n * k / 2;
>> +#else
>> + return 24000000 * n * k;
>> +#endif
>> }
>
> This whole file is admittedly quite messy. We should be able to move the
> video clocks out here and into our DM clock driver, but this is
> non-trivial, I believe, so I won't ask you doing this ;-)
Ah yes I was changing all the added ifdefs to ifs then I noticed that
there where alreay ifdefs everywhere so i didnt change it. I will
continue with it.
>
> Cheers,
> Andre
>
>>
>> unsigned int clock_get_mipi_pll(void)
>> diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
>> index ba33ef2430..7eef178859 100644
>> --- a/arch/arm/mach-sunxi/cpu_info.c
>> +++ b/arch/arm/mach-sunxi/cpu_info.c
>> @@ -57,6 +57,8 @@ int print_cpuinfo(void)
>> {
>> #ifdef CONFIG_MACH_SUN4I
>> puts("CPU: Allwinner A10 (SUN4I)\n");
>> +#elif defined CONFIG_MACH_SUNIV
>> + puts("CPU: Allwinner F Series (SUNIV)\n");
>> #elif defined CONFIG_MACH_SUN5I
>> u32 val = readl(SUNXI_SID_BASE + 0x08);
>> switch ((val >> 12) & 0xf) {
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-26 14:38 ` Jesse Taube
@ 2022-01-29 3:21 ` Jesse Taube
2022-01-29 11:51 ` Andre Przywara
0 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-29 3:21 UTC (permalink / raw)
To: Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On 1/26/22 09:38, Jesse Taube wrote:
>
>
> On 1/26/22 09:13, Andre Przywara wrote:
>> On Tue, 4 Jan 2022 19:35:06 -0500
>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>
>> Hi Jesse,
>>
>> I was checking some bits and pieces here, so sorry for the delay. I saw
>> your v2, and will review that ASAP, so that we get one step closer. Please
>> don't send a v3 before that.
>>
>> If you have some time, can you also meanwhile check if this series is
>> bisectable, meaning that every patch compiles? I have the feeling there is
>> something off, but didn't check it. Pick an H3 and an A64 board, and
>> compile it after each patch. I can do this as well, if you don't find the
>> time for this.
> I didnt check for bisectability but i did order the patches to avoid it.
>>
>> In general I am tempted to merge this still in this cycle, since we don't
>> have other big changes, but we would need to settle this by early next
>> week then.
>>
>> See below for more work ;-) (Sorry!)
> Its okay.
>>
>>> From: Icenowy Zheng <icenowy@aosc.io>
>>>
>>> Add support for the suniv architecture, which is newer ARM9 SoCs by
>>> Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
>>> sun6i.
>>>
>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>>> ---
>>> arch/arm/mach-sunxi/Kconfig | 16 +++++++++--
>>> arch/arm/mach-sunxi/board.c | 31 +++++++++++++++++++--
>>> arch/arm/mach-sunxi/clock.c | 3 +-
>>> arch/arm/mach-sunxi/clock_sun6i.c | 46 ++++++++++++++++++++++++++++++-
>>> arch/arm/mach-sunxi/cpu_info.c | 2 ++
>>> 5 files changed, 91 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
>>> index 2c18cf02d1..9bb7717731 100644
>>> --- a/arch/arm/mach-sunxi/Kconfig
>>> +++ b/arch/arm/mach-sunxi/Kconfig
>>> @@ -1,7 +1,8 @@
>>> if ARCH_SUNXI
>>>
>>> config SPL_LDSCRIPT
>>> - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
>>> + default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
>>> + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 && !MACH_SUNIV
>>>
>>> config IDENT_STRING
>>> default " Allwinner Technology"
>>> @@ -183,6 +184,12 @@ choice
>>> prompt "Sunxi SoC Variant"
>>> optional
>>>
>>> +config MACH_SUNIV
>>> + bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
>>> + select CPU_ARM926EJS
>>> + select SUNXI_GEN_SUN6I
>>> + select SUPPORT_SPL
>>> +
>>> config MACH_SUN4I
>>> bool "sun4i (Allwinner A10)"
>>> select CPU_V7A
>>> @@ -587,6 +594,7 @@ config DRAM_ODT_CORRECTION
>>> endif
>>>
>>> config SYS_CLK_FREQ
>>> + default 408000000 if MACH_SUNIV
>>> default 1008000000 if MACH_SUN4I
>>> default 1008000000 if MACH_SUN5I
>>> default 1008000000 if MACH_SUN6I
>>> @@ -598,6 +606,7 @@ config SYS_CLK_FREQ
>>> default 1008000000 if MACH_SUN50I_H616
>>>
>>> config SYS_CONFIG_NAME
>>> + default "suniv" if MACH_SUNIV
>>> default "sun4i" if MACH_SUN4I
>>> default "sun5i" if MACH_SUN5I
>>> default "sun6i" if MACH_SUN6I
>>> @@ -805,7 +814,7 @@ config VIDEO_SUNXI
>>>
>>> config VIDEO_HDMI
>>> bool "HDMI output support"
>>> - depends on VIDEO_SUNXI && !MACH_SUN8I
>>> + depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
>>> default y
>>> ---help---
>>> Say Y here to add support for outputting video over HDMI.
>>> @@ -1005,6 +1014,7 @@ config GMAC_TX_DELAY
>>> Set the GMAC Transmit Clock Delay Chain value.
>>>
>>> config SPL_STACK_R_ADDR
>>> + default 0x81e00000 if MACH_SUNIV
>>> default 0x4fe00000 if MACH_SUN4I
>>> default 0x4fe00000 if MACH_SUN5I
>>> default 0x4fe00000 if MACH_SUN6I
>>> @@ -1016,7 +1026,7 @@ config SPL_STACK_R_ADDR
>>>
>>> config SPL_SPI_SUNXI
>>> bool "Support for SPI Flash on Allwinner SoCs in SPL"
>>> - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
>>> + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV
>>
>> I think this is premature without the corresponding patch to
>> spl_spi_sunxi.c.
> Ill look into this.
>>
>>> help
>>> Enable support for SPI Flash. This option allows SPL to read from
>>> sunxi SPI Flash. It uses the same method as the boot ROM, so does
>>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
>>> index 3ef179742c..2fee86b49b 100644
>>> --- a/arch/arm/mach-sunxi/board.c
>>> +++ b/arch/arm/mach-sunxi/board.c
>>> @@ -86,7 +86,8 @@ static int gpio_init(void)
>>> sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
>>> sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
>>> #endif
>>> -#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
>>> +#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \
>>> + defined(CONFIG_MACH_SUNIV)
>>> sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
>>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
>>> #else
>>> @@ -94,6 +95,10 @@ static int gpio_init(void)
>>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
>>> #endif
>>> sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
>>> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
>>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
>>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
>>> + sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
>>> #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
>>> defined(CONFIG_MACH_SUN7I) || \
>>> defined(CONFIG_MACH_SUN8I_R40))
>>> @@ -219,7 +224,8 @@ void s_init(void)
>>> /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
>>> #endif
>>>
>>> -#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
>>> +#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) && \
>>> + !defined(CONFIG_MACH_SUNIV)
>>
>> That looks correct for now, but should become obsolete with my
>> lowlevel_init cleanup series.
> Yes in V2 i fix this line, but it breaks compiling without your patch.
> Idk if you want a bad compile or a bad merge.
>>
>>> /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
>>> asm volatile(
>>> "mrc p15, 0, r0, c1, c0, 1\n"
>>> @@ -328,10 +334,31 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
>>> return sector;
>>> }
>>>
>>> +#ifndef CONFIG_MACH_SUNIV
>>
>> Can you please flip this around to avoid the negative logic?
> Ah yes i will.
>>
>>> u32 spl_boot_device(void)
>>> {
>>> return sunxi_get_boot_device();
>>> }
>>> +#else
>>> +/*
>>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>>> + * boot sequence in BROM: mmc0->spinor->fail.
>>> + */
>>> +void board_boot_order(u32 *spl_boot_list)
>>> +{
>>> + /*
>>> + * See the comments above in sunxi_get_boot_device() for information
>>> + * about FEL boot.
>>> + */
>>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>>> + return;
>>> + }
>>> +
>>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>>
>> So does that mean that it tries MMC first, even when booted via SPI? So if
>> there is a *non*-bootable microSD card in, it will read something from
>> sector 80, and will execute that if this is a FIT or legacy image?
> yes
Uh sorry to bother you again but I cant seem to find a way to find where
the bootrom got the spl. I could check other periphirals like pinmux. I
could also just have it configured at build. Are both these options
okay? I will try to find a way to find the boot device at runtime first.
Also in my next patch i added spi boot for the spl. I also have a patch
for DT spi driver, but I didn't add it to v3.
thank you,
Jesse Taube
>>
>> I wonder if we actually have some indication of SPI booting, for instance
>> the pinmux or clock settings?
>> Otherwise we would really need to mimic the BROM, and read and verify the
>> eGON header again, to be reliable.
> HMM this should be fixed thx for pointing this out.
>>
>> I might be talked into ignoring this issue for now, if there will be a fix
>> patch later on.
>>
>>> + spl_boot_list[1] = BOOT_DEVICE_SPI;
>>> +}
>>> +#endif
>>>
>>> void board_init_f(ulong dummy)
>>> {
>>> diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
>>> index de7e875298..da3a0eb058 100644
>>> --- a/arch/arm/mach-sunxi/clock.c
>>> +++ b/arch/arm/mach-sunxi/clock.c
>>> @@ -35,7 +35,8 @@ int clock_init(void)
>>> }
>>>
>>> /* These functions are shared between various SoCs so put them here. */
>>> -#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
>>> +#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I && \
>>> + !defined CONFIG_MACH_SUNIV
>>> int clock_twi_onoff(int port, int state)
>>> {
>>> struct sunxi_ccm_reg *const ccm =
>>> diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
>>> index 8e84062bd7..b0b3ea4d30 100644
>>> --- a/arch/arm/mach-sunxi/clock_sun6i.c
>>> +++ b/arch/arm/mach-sunxi/clock_sun6i.c
>>> @@ -23,7 +23,8 @@ void clock_init_safe(void)
>>> struct sunxi_ccm_reg * const ccm =
>>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>>
>>> -#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
>>> +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \
>>> + !defined(CONFIG_MACH_SUNIV)
>>> struct sunxi_prcm_reg * const prcm =
>>> (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>>>
>>> @@ -49,9 +50,11 @@ void clock_init_safe(void)
>>>
>>> writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
>>>
>>> +#ifndef CONFIG_MACH_SUNIV
>>> writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
>>> if (IS_ENABLED(CONFIG_MACH_SUN6I))
>>> writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
>>> +#endif
>>>
>>> #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
>>> setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
>>> @@ -87,6 +90,7 @@ void clock_init_uart(void)
>>> struct sunxi_ccm_reg *const ccm =
>>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>>
>>> +#ifndef CONFIG_MACH_SUNIV
>>
>> Please again negate and swap the branches.
>>
>>> /* uart clock source is apb2 */
>>> writel(APB2_CLK_SRC_OSC24M|
>>> APB2_CLK_RATE_N_1|
>>> @@ -102,6 +106,24 @@ void clock_init_uart(void)
>>> setbits_le32(&ccm->apb2_reset_cfg,
>>> 1 << (APB2_RESET_UART_SHIFT +
>>> CONFIG_CONS_INDEX - 1));
>>> +#else
>>> + /* suniv doesn't have apb2, so uart clock source is apb1 */
>>> + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
>>> + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
>>> + ;
>>> +
>>> + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
>>
>> This is done is clock_init_safe() already, which is called before
>> clock_init_uart(). I feel we should drop it here, not only because
>> touching a PLL again might cause problems.
> Okay.
>>
>>> +
>>> + /* open the clock for uart */
>>> + setbits_le32(&ccm->apb1_gate,
>>> + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
>>> + CONFIG_CONS_INDEX - 1));
>>> +
>>> + /* deassert uart reset */
>>> + setbits_le32(&ccm->apb1_reset_cfg,
>>> + 1 << (APB1_RESET_UART_SHIFT +
>>> + CONFIG_CONS_INDEX - 1));
>>> +#endif
>>> #else
>>> /* enable R_PIO and R_UART clocks, and de-assert resets */
>>> prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
>>> @@ -125,10 +147,15 @@ void clock_set_pll1(unsigned int clk)
>>> }
>>>
>>> /* Switch to 24MHz clock while changing PLL1 */
>>> +#ifndef CONFIG_MACH_SUNIV
>>
>> Same negation here. And can you please turn those preprocessor guards into
>> if (IS_ENABLED(CONFIG_MACH_SUNIV)) ...
>> where applicable? That's always preferred, if all symbols used inside both
>> branches are defined in either case, as in here, for instance.
>> As the compiler will see that it's a compile-time constant, it will remove
>> the non-applicable branch. So the effect on the code is mostly the same,
>> but both branches are "compile-tested" and it's more readable, as the
>> nesting is done properly.
>>
>>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
>>> ATB_DIV_2 << ATB_DIV_SHIFT |
>>> CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
>>> &ccm->cpu_axi_cfg);
>>> +#else
>>> + writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
>>> + &ccm->cpu_axi_cfg);
>>> +#endif
>>>
>>> /*
>>> * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
>>> @@ -137,13 +164,26 @@ void clock_set_pll1(unsigned int clk)
>>> writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
>>> CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
>>> CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
>>> +#ifndef CONFIG_MACH_SUNIV
>>
>> Guess ...
> Sorry i didnt think it would be too bit a problem.
>>
>>> sdelay(200);
>>> +#else
>>> + /* ARM926EJ-S code does not have sdelay */
>>
>> I wonder if we should just copy a definition of it to
>> arch/arm/cpu/arm926ejs. The ARMv7 assembly should just work.
> I will try. if it doesnt work i will add.
>>> + volatile int i = 200;
>>> +
>>> + while (i > 0)
>>> + i--;
>>> +#endif
>>>
>>> /* Switch CPU to PLL1 */
>>> +#ifndef CONFIG_MACH_SUNIV
>>
>> Negate and if(IS_ENABLED(...)), please.
>>
>>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
>>> ATB_DIV_2 << ATB_DIV_SHIFT |
>>> CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
>>> &ccm->cpu_axi_cfg);
>>> +#else
>>> + writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
>>> + &ccm->cpu_axi_cfg);
>>> +#endif
>>> }
>>> #endif
>>>
>>> @@ -317,7 +357,11 @@ unsigned int clock_get_pll6(void)
>>> uint32_t rval = readl(&ccm->pll6_cfg);
>>> int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
>>> int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
>>> +#ifndef CONFIG_MACH_SUNIV
>>
>> Negate and if(IS_ENABLED(...)), please.
>>
>>> return 24000000 * n * k / 2;
>>> +#else
>>> + return 24000000 * n * k;
>>> +#endif
>>> }
>>
>> This whole file is admittedly quite messy. We should be able to move the
>> video clocks out here and into our DM clock driver, but this is
>> non-trivial, I believe, so I won't ask you doing this ;-)
> Ah yes I was changing all the added ifdefs to ifs then I noticed that
> there where alreay ifdefs everywhere so i didnt change it. I will
> continue with it.
>>
>> Cheers,
>> Andre
>>
>>>
>>> unsigned int clock_get_mipi_pll(void)
>>> diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
>>> index ba33ef2430..7eef178859 100644
>>> --- a/arch/arm/mach-sunxi/cpu_info.c
>>> +++ b/arch/arm/mach-sunxi/cpu_info.c
>>> @@ -57,6 +57,8 @@ int print_cpuinfo(void)
>>> {
>>> #ifdef CONFIG_MACH_SUN4I
>>> puts("CPU: Allwinner A10 (SUN4I)\n");
>>> +#elif defined CONFIG_MACH_SUNIV
>>> + puts("CPU: Allwinner F Series (SUNIV)\n");
>>> #elif defined CONFIG_MACH_SUN5I
>>> u32 val = readl(SUNXI_SID_BASE + 0x08);
>>> switch ((val >> 12) & 0xf) {
>>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-29 3:21 ` Jesse Taube
@ 2022-01-29 11:51 ` Andre Przywara
2022-01-29 19:24 ` Jesse Taube
2022-01-29 20:59 ` Samuel Holland
0 siblings, 2 replies; 43+ messages in thread
From: Andre Przywara @ 2022-01-29 11:51 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On Fri, 28 Jan 2022 22:21:28 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
> On 1/26/22 09:38, Jesse Taube wrote:
> >
> >
> > On 1/26/22 09:13, Andre Przywara wrote:
> >> On Tue, 4 Jan 2022 19:35:06 -0500
> >> Jesse Taube <mr.bossman075@gmail.com> wrote:
> >>
> >> Hi Jesse,
> >>
> >> I was checking some bits and pieces here, so sorry for the delay. I saw
> >> your v2, and will review that ASAP, so that we get one step closer. Please
> >> don't send a v3 before that.
> >>
> >> If you have some time, can you also meanwhile check if this series is
> >> bisectable, meaning that every patch compiles? I have the feeling there is
> >> something off, but didn't check it. Pick an H3 and an A64 board, and
> >> compile it after each patch. I can do this as well, if you don't find the
> >> time for this.
> > I didnt check for bisectability but i did order the patches to avoid it.
> >>
> >> In general I am tempted to merge this still in this cycle, since we don't
> >> have other big changes, but we would need to settle this by early next
> >> week then.
> >>
> >> See below for more work ;-) (Sorry!)
> > Its okay.
> >>
> >>> From: Icenowy Zheng <icenowy@aosc.io>
> >>>
> >>> Add support for the suniv architecture, which is newer ARM9 SoCs by
> >>> Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
> >>> sun6i.
> >>>
> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> >>> ---
> >>> arch/arm/mach-sunxi/Kconfig | 16 +++++++++--
> >>> arch/arm/mach-sunxi/board.c | 31 +++++++++++++++++++--
> >>> arch/arm/mach-sunxi/clock.c | 3 +-
> >>> arch/arm/mach-sunxi/clock_sun6i.c | 46 ++++++++++++++++++++++++++++++-
> >>> arch/arm/mach-sunxi/cpu_info.c | 2 ++
> >>> 5 files changed, 91 insertions(+), 7 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> >>> index 2c18cf02d1..9bb7717731 100644
> >>> --- a/arch/arm/mach-sunxi/Kconfig
> >>> +++ b/arch/arm/mach-sunxi/Kconfig
> >>> @@ -1,7 +1,8 @@
> >>> if ARCH_SUNXI
> >>>
> >>> config SPL_LDSCRIPT
> >>> - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
> >>> + default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
> >>> + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 && !MACH_SUNIV
> >>>
> >>> config IDENT_STRING
> >>> default " Allwinner Technology"
> >>> @@ -183,6 +184,12 @@ choice
> >>> prompt "Sunxi SoC Variant"
> >>> optional
> >>>
> >>> +config MACH_SUNIV
> >>> + bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
> >>> + select CPU_ARM926EJS
> >>> + select SUNXI_GEN_SUN6I
> >>> + select SUPPORT_SPL
> >>> +
> >>> config MACH_SUN4I
> >>> bool "sun4i (Allwinner A10)"
> >>> select CPU_V7A
> >>> @@ -587,6 +594,7 @@ config DRAM_ODT_CORRECTION
> >>> endif
> >>>
> >>> config SYS_CLK_FREQ
> >>> + default 408000000 if MACH_SUNIV
> >>> default 1008000000 if MACH_SUN4I
> >>> default 1008000000 if MACH_SUN5I
> >>> default 1008000000 if MACH_SUN6I
> >>> @@ -598,6 +606,7 @@ config SYS_CLK_FREQ
> >>> default 1008000000 if MACH_SUN50I_H616
> >>>
> >>> config SYS_CONFIG_NAME
> >>> + default "suniv" if MACH_SUNIV
> >>> default "sun4i" if MACH_SUN4I
> >>> default "sun5i" if MACH_SUN5I
> >>> default "sun6i" if MACH_SUN6I
> >>> @@ -805,7 +814,7 @@ config VIDEO_SUNXI
> >>>
> >>> config VIDEO_HDMI
> >>> bool "HDMI output support"
> >>> - depends on VIDEO_SUNXI && !MACH_SUN8I
> >>> + depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
> >>> default y
> >>> ---help---
> >>> Say Y here to add support for outputting video over HDMI.
> >>> @@ -1005,6 +1014,7 @@ config GMAC_TX_DELAY
> >>> Set the GMAC Transmit Clock Delay Chain value.
> >>>
> >>> config SPL_STACK_R_ADDR
> >>> + default 0x81e00000 if MACH_SUNIV
> >>> default 0x4fe00000 if MACH_SUN4I
> >>> default 0x4fe00000 if MACH_SUN5I
> >>> default 0x4fe00000 if MACH_SUN6I
> >>> @@ -1016,7 +1026,7 @@ config SPL_STACK_R_ADDR
> >>>
> >>> config SPL_SPI_SUNXI
> >>> bool "Support for SPI Flash on Allwinner SoCs in SPL"
> >>> - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
> >>> + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV
> >>
> >> I think this is premature without the corresponding patch to
> >> spl_spi_sunxi.c.
> > Ill look into this.
> >>
> >>> help
> >>> Enable support for SPI Flash. This option allows SPL to read from
> >>> sunxi SPI Flash. It uses the same method as the boot ROM, so does
> >>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> >>> index 3ef179742c..2fee86b49b 100644
> >>> --- a/arch/arm/mach-sunxi/board.c
> >>> +++ b/arch/arm/mach-sunxi/board.c
> >>> @@ -86,7 +86,8 @@ static int gpio_init(void)
> >>> sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
> >>> sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
> >>> #endif
> >>> -#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
> >>> +#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \
> >>> + defined(CONFIG_MACH_SUNIV)
> >>> sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
> >>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
> >>> #else
> >>> @@ -94,6 +95,10 @@ static int gpio_init(void)
> >>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
> >>> #endif
> >>> sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
> >>> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
> >>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
> >>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
> >>> + sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
> >>> #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
> >>> defined(CONFIG_MACH_SUN7I) || \
> >>> defined(CONFIG_MACH_SUN8I_R40))
> >>> @@ -219,7 +224,8 @@ void s_init(void)
> >>> /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
> >>> #endif
> >>>
> >>> -#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
> >>> +#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) && \
> >>> + !defined(CONFIG_MACH_SUNIV)
> >>
> >> That looks correct for now, but should become obsolete with my
> >> lowlevel_init cleanup series.
> > Yes in V2 i fix this line, but it breaks compiling without your patch.
> > Idk if you want a bad compile or a bad merge.
> >>
> >>> /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
> >>> asm volatile(
> >>> "mrc p15, 0, r0, c1, c0, 1\n"
> >>> @@ -328,10 +334,31 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
> >>> return sector;
> >>> }
> >>>
> >>> +#ifndef CONFIG_MACH_SUNIV
> >>
> >> Can you please flip this around to avoid the negative logic?
> > Ah yes i will.
> >>
> >>> u32 spl_boot_device(void)
> >>> {
> >>> return sunxi_get_boot_device();
> >>> }
> >>> +#else
> >>> +/*
> >>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
> >>> + * boot sequence in BROM: mmc0->spinor->fail.
> >>> + */
> >>> +void board_boot_order(u32 *spl_boot_list)
> >>> +{
> >>> + /*
> >>> + * See the comments above in sunxi_get_boot_device() for information
> >>> + * about FEL boot.
> >>> + */
> >>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
> >>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
> >>> + return;
> >>> + }
> >>> +
> >>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
> >>
> >> So does that mean that it tries MMC first, even when booted via SPI? So if
> >> there is a *non*-bootable microSD card in, it will read something from
> >> sector 80, and will execute that if this is a FIT or legacy image?
> > yes
> Uh sorry to bother you again but I cant seem to find a way to find where
> the bootrom got the spl. I could check other periphirals like pinmux. I
> could also just have it configured at build. Are both these options
> okay? I will try to find a way to find the boot device at runtime first.
Don't bother for this version, it's fine as it is now, we can refine
this later. It's only a problem if there is a non-valid SPL, but a
valid U-Boot proper legacy image on the SD card.
I don't want to have a build time option, we try to keep a single image
for all boot sources.
So eventually I'd prefer the pinmux/clock check, since that's cheaper.
The alternative would be to read the SPL (again), check for a valid
header and verify the checksum. You can look at this for inspiration:
https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przywara@arm.com/
> Also in my next patch i added spi boot for the spl. I also have a patch
> for DT spi driver, but I didn't add it to v3.
Please stay with the number and scope of the patches as we have it at
the moment. You can send the SPL SPI and DT SPI as follow-up patches,
and we can take them later.
For now I want to get the basic support in, even if that means FEL
only. Otherwise it becomes an issue of herding cats, with constant
rebase burden.
Cheers,
Andre
> thank you,
> Jesse Taube
> >>
> >> I wonder if we actually have some indication of SPI booting, for instance
> >> the pinmux or clock settings?
> >> Otherwise we would really need to mimic the BROM, and read and verify the
> >> eGON header again, to be reliable.
> > HMM this should be fixed thx for pointing this out.
> >>
> >> I might be talked into ignoring this issue for now, if there will be a fix
> >> patch later on.
> >>
> >>> + spl_boot_list[1] = BOOT_DEVICE_SPI;
> >>> +}
> >>> +#endif
> >>>
> >>> void board_init_f(ulong dummy)
> >>> {
> >>> diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
> >>> index de7e875298..da3a0eb058 100644
> >>> --- a/arch/arm/mach-sunxi/clock.c
> >>> +++ b/arch/arm/mach-sunxi/clock.c
> >>> @@ -35,7 +35,8 @@ int clock_init(void)
> >>> }
> >>>
> >>> /* These functions are shared between various SoCs so put them here. */
> >>> -#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
> >>> +#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I && \
> >>> + !defined CONFIG_MACH_SUNIV
> >>> int clock_twi_onoff(int port, int state)
> >>> {
> >>> struct sunxi_ccm_reg *const ccm =
> >>> diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
> >>> index 8e84062bd7..b0b3ea4d30 100644
> >>> --- a/arch/arm/mach-sunxi/clock_sun6i.c
> >>> +++ b/arch/arm/mach-sunxi/clock_sun6i.c
> >>> @@ -23,7 +23,8 @@ void clock_init_safe(void)
> >>> struct sunxi_ccm_reg * const ccm =
> >>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> >>>
> >>> -#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
> >>> +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \
> >>> + !defined(CONFIG_MACH_SUNIV)
> >>> struct sunxi_prcm_reg * const prcm =
> >>> (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
> >>>
> >>> @@ -49,9 +50,11 @@ void clock_init_safe(void)
> >>>
> >>> writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
> >>>
> >>> +#ifndef CONFIG_MACH_SUNIV
> >>> writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
> >>> if (IS_ENABLED(CONFIG_MACH_SUN6I))
> >>> writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
> >>> +#endif
> >>>
> >>> #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
> >>> setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
> >>> @@ -87,6 +90,7 @@ void clock_init_uart(void)
> >>> struct sunxi_ccm_reg *const ccm =
> >>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> >>>
> >>> +#ifndef CONFIG_MACH_SUNIV
> >>
> >> Please again negate and swap the branches.
> >>
> >>> /* uart clock source is apb2 */
> >>> writel(APB2_CLK_SRC_OSC24M|
> >>> APB2_CLK_RATE_N_1|
> >>> @@ -102,6 +106,24 @@ void clock_init_uart(void)
> >>> setbits_le32(&ccm->apb2_reset_cfg,
> >>> 1 << (APB2_RESET_UART_SHIFT +
> >>> CONFIG_CONS_INDEX - 1));
> >>> +#else
> >>> + /* suniv doesn't have apb2, so uart clock source is apb1 */
> >>> + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
> >>> + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
> >>> + ;
> >>> +
> >>> + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
> >>
> >> This is done is clock_init_safe() already, which is called before
> >> clock_init_uart(). I feel we should drop it here, not only because
> >> touching a PLL again might cause problems.
> > Okay.
> >>
> >>> +
> >>> + /* open the clock for uart */
> >>> + setbits_le32(&ccm->apb1_gate,
> >>> + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
> >>> + CONFIG_CONS_INDEX - 1));
> >>> +
> >>> + /* deassert uart reset */
> >>> + setbits_le32(&ccm->apb1_reset_cfg,
> >>> + 1 << (APB1_RESET_UART_SHIFT +
> >>> + CONFIG_CONS_INDEX - 1));
> >>> +#endif
> >>> #else
> >>> /* enable R_PIO and R_UART clocks, and de-assert resets */
> >>> prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
> >>> @@ -125,10 +147,15 @@ void clock_set_pll1(unsigned int clk)
> >>> }
> >>>
> >>> /* Switch to 24MHz clock while changing PLL1 */
> >>> +#ifndef CONFIG_MACH_SUNIV
> >>
> >> Same negation here. And can you please turn those preprocessor guards into
> >> if (IS_ENABLED(CONFIG_MACH_SUNIV)) ...
> >> where applicable? That's always preferred, if all symbols used inside both
> >> branches are defined in either case, as in here, for instance.
> >> As the compiler will see that it's a compile-time constant, it will remove
> >> the non-applicable branch. So the effect on the code is mostly the same,
> >> but both branches are "compile-tested" and it's more readable, as the
> >> nesting is done properly.
> >>
> >>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
> >>> ATB_DIV_2 << ATB_DIV_SHIFT |
> >>> CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
> >>> &ccm->cpu_axi_cfg);
> >>> +#else
> >>> + writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
> >>> + &ccm->cpu_axi_cfg);
> >>> +#endif
> >>>
> >>> /*
> >>> * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
> >>> @@ -137,13 +164,26 @@ void clock_set_pll1(unsigned int clk)
> >>> writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
> >>> CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
> >>> CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
> >>> +#ifndef CONFIG_MACH_SUNIV
> >>
> >> Guess ...
> > Sorry i didnt think it would be too bit a problem.
> >>
> >>> sdelay(200);
> >>> +#else
> >>> + /* ARM926EJ-S code does not have sdelay */
> >>
> >> I wonder if we should just copy a definition of it to
> >> arch/arm/cpu/arm926ejs. The ARMv7 assembly should just work.
> > I will try. if it doesnt work i will add.
> >>> + volatile int i = 200;
> >>> +
> >>> + while (i > 0)
> >>> + i--;
> >>> +#endif
> >>>
> >>> /* Switch CPU to PLL1 */
> >>> +#ifndef CONFIG_MACH_SUNIV
> >>
> >> Negate and if(IS_ENABLED(...)), please.
> >>
> >>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
> >>> ATB_DIV_2 << ATB_DIV_SHIFT |
> >>> CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
> >>> &ccm->cpu_axi_cfg);
> >>> +#else
> >>> + writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
> >>> + &ccm->cpu_axi_cfg);
> >>> +#endif
> >>> }
> >>> #endif
> >>>
> >>> @@ -317,7 +357,11 @@ unsigned int clock_get_pll6(void)
> >>> uint32_t rval = readl(&ccm->pll6_cfg);
> >>> int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
> >>> int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
> >>> +#ifndef CONFIG_MACH_SUNIV
> >>
> >> Negate and if(IS_ENABLED(...)), please.
> >>
> >>> return 24000000 * n * k / 2;
> >>> +#else
> >>> + return 24000000 * n * k;
> >>> +#endif
> >>> }
> >>
> >> This whole file is admittedly quite messy. We should be able to move the
> >> video clocks out here and into our DM clock driver, but this is
> >> non-trivial, I believe, so I won't ask you doing this ;-)
> > Ah yes I was changing all the added ifdefs to ifs then I noticed that
> > there where alreay ifdefs everywhere so i didnt change it. I will
> > continue with it.
> >>
> >> Cheers,
> >> Andre
> >>
> >>>
> >>> unsigned int clock_get_mipi_pll(void)
> >>> diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
> >>> index ba33ef2430..7eef178859 100644
> >>> --- a/arch/arm/mach-sunxi/cpu_info.c
> >>> +++ b/arch/arm/mach-sunxi/cpu_info.c
> >>> @@ -57,6 +57,8 @@ int print_cpuinfo(void)
> >>> {
> >>> #ifdef CONFIG_MACH_SUN4I
> >>> puts("CPU: Allwinner A10 (SUN4I)\n");
> >>> +#elif defined CONFIG_MACH_SUNIV
> >>> + puts("CPU: Allwinner F Series (SUNIV)\n");
> >>> #elif defined CONFIG_MACH_SUN5I
> >>> u32 val = readl(SUNXI_SID_BASE + 0x08);
> >>> switch ((val >> 12) & 0xf) {
> >>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-29 11:51 ` Andre Przywara
@ 2022-01-29 19:24 ` Jesse Taube
2022-01-29 20:44 ` Giulio Benetti
2022-01-29 20:59 ` Samuel Holland
1 sibling, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-29 19:24 UTC (permalink / raw)
To: Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On 1/29/22 06:51, Andre Przywara wrote:
> On Fri, 28 Jan 2022 22:21:28 -0500
> Jesse Taube <mr.bossman075@gmail.com> wrote:
>
>> On 1/26/22 09:38, Jesse Taube wrote:
>>>
>>>
>>> On 1/26/22 09:13, Andre Przywara wrote:
>>>> On Tue, 4 Jan 2022 19:35:06 -0500
>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>
>>>> Hi Jesse,
>>>>
>>>> I was checking some bits and pieces here, so sorry for the delay. I saw
>>>> your v2, and will review that ASAP, so that we get one step closer. Please
>>>> don't send a v3 before that.
>>>>
>>>> If you have some time, can you also meanwhile check if this series is
>>>> bisectable, meaning that every patch compiles? I have the feeling there is
>>>> something off, but didn't check it. Pick an H3 and an A64 board, and
>>>> compile it after each patch. I can do this as well, if you don't find the
>>>> time for this.
>>> I didnt check for bisectability but i did order the patches to avoid it.
>>>>
>>>> In general I am tempted to merge this still in this cycle, since we don't
>>>> have other big changes, but we would need to settle this by early next
>>>> week then.
>>>>
>>>> See below for more work ;-) (Sorry!)
>>> Its okay.
>>>>
>>>>> From: Icenowy Zheng <icenowy@aosc.io>
>>>>>
>>>>> Add support for the suniv architecture, which is newer ARM9 SoCs by
>>>>> Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
>>>>> sun6i.
>>>>>
>>>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>>>>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>>>>> ---
>>>>> arch/arm/mach-sunxi/Kconfig | 16 +++++++++--
>>>>> arch/arm/mach-sunxi/board.c | 31 +++++++++++++++++++--
>>>>> arch/arm/mach-sunxi/clock.c | 3 +-
>>>>> arch/arm/mach-sunxi/clock_sun6i.c | 46 ++++++++++++++++++++++++++++++-
>>>>> arch/arm/mach-sunxi/cpu_info.c | 2 ++
>>>>> 5 files changed, 91 insertions(+), 7 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
>>>>> index 2c18cf02d1..9bb7717731 100644
>>>>> --- a/arch/arm/mach-sunxi/Kconfig
>>>>> +++ b/arch/arm/mach-sunxi/Kconfig
>>>>> @@ -1,7 +1,8 @@
>>>>> if ARCH_SUNXI
>>>>>
>>>>> config SPL_LDSCRIPT
>>>>> - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
>>>>> + default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
>>>>> + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 && !MACH_SUNIV
>>>>>
>>>>> config IDENT_STRING
>>>>> default " Allwinner Technology"
>>>>> @@ -183,6 +184,12 @@ choice
>>>>> prompt "Sunxi SoC Variant"
>>>>> optional
>>>>>
>>>>> +config MACH_SUNIV
>>>>> + bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
>>>>> + select CPU_ARM926EJS
>>>>> + select SUNXI_GEN_SUN6I
>>>>> + select SUPPORT_SPL
>>>>> +
>>>>> config MACH_SUN4I
>>>>> bool "sun4i (Allwinner A10)"
>>>>> select CPU_V7A
>>>>> @@ -587,6 +594,7 @@ config DRAM_ODT_CORRECTION
>>>>> endif
>>>>>
>>>>> config SYS_CLK_FREQ
>>>>> + default 408000000 if MACH_SUNIV
>>>>> default 1008000000 if MACH_SUN4I
>>>>> default 1008000000 if MACH_SUN5I
>>>>> default 1008000000 if MACH_SUN6I
>>>>> @@ -598,6 +606,7 @@ config SYS_CLK_FREQ
>>>>> default 1008000000 if MACH_SUN50I_H616
>>>>>
>>>>> config SYS_CONFIG_NAME
>>>>> + default "suniv" if MACH_SUNIV
>>>>> default "sun4i" if MACH_SUN4I
>>>>> default "sun5i" if MACH_SUN5I
>>>>> default "sun6i" if MACH_SUN6I
>>>>> @@ -805,7 +814,7 @@ config VIDEO_SUNXI
>>>>>
>>>>> config VIDEO_HDMI
>>>>> bool "HDMI output support"
>>>>> - depends on VIDEO_SUNXI && !MACH_SUN8I
>>>>> + depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
>>>>> default y
>>>>> ---help---
>>>>> Say Y here to add support for outputting video over HDMI.
>>>>> @@ -1005,6 +1014,7 @@ config GMAC_TX_DELAY
>>>>> Set the GMAC Transmit Clock Delay Chain value.
>>>>>
>>>>> config SPL_STACK_R_ADDR
>>>>> + default 0x81e00000 if MACH_SUNIV
>>>>> default 0x4fe00000 if MACH_SUN4I
>>>>> default 0x4fe00000 if MACH_SUN5I
>>>>> default 0x4fe00000 if MACH_SUN6I
>>>>> @@ -1016,7 +1026,7 @@ config SPL_STACK_R_ADDR
>>>>>
>>>>> config SPL_SPI_SUNXI
>>>>> bool "Support for SPI Flash on Allwinner SoCs in SPL"
>>>>> - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
>>>>> + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV
>>>>
>>>> I think this is premature without the corresponding patch to
>>>> spl_spi_sunxi.c.
>>> Ill look into this.
>>>>
>>>>> help
>>>>> Enable support for SPI Flash. This option allows SPL to read from
>>>>> sunxi SPI Flash. It uses the same method as the boot ROM, so does
>>>>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
>>>>> index 3ef179742c..2fee86b49b 100644
>>>>> --- a/arch/arm/mach-sunxi/board.c
>>>>> +++ b/arch/arm/mach-sunxi/board.c
>>>>> @@ -86,7 +86,8 @@ static int gpio_init(void)
>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
>>>>> #endif
>>>>> -#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
>>>>> +#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \
>>>>> + defined(CONFIG_MACH_SUNIV)
>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
>>>>> #else
>>>>> @@ -94,6 +95,10 @@ static int gpio_init(void)
>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
>>>>> #endif
>>>>> sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
>>>>> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
>>>>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
>>>>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
>>>>> + sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
>>>>> #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
>>>>> defined(CONFIG_MACH_SUN7I) || \
>>>>> defined(CONFIG_MACH_SUN8I_R40))
>>>>> @@ -219,7 +224,8 @@ void s_init(void)
>>>>> /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
>>>>> #endif
>>>>>
>>>>> -#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
>>>>> +#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) && \
>>>>> + !defined(CONFIG_MACH_SUNIV)
>>>>
>>>> That looks correct for now, but should become obsolete with my
>>>> lowlevel_init cleanup series.
>>> Yes in V2 i fix this line, but it breaks compiling without your patch.
>>> Idk if you want a bad compile or a bad merge.
>>>>
>>>>> /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
>>>>> asm volatile(
>>>>> "mrc p15, 0, r0, c1, c0, 1\n"
>>>>> @@ -328,10 +334,31 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
>>>>> return sector;
>>>>> }
>>>>>
>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>
>>>> Can you please flip this around to avoid the negative logic?
>>> Ah yes i will.
>>>>
>>>>> u32 spl_boot_device(void)
>>>>> {
>>>>> return sunxi_get_boot_device();
>>>>> }
>>>>> +#else
>>>>> +/*
>>>>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>>>>> + * boot sequence in BROM: mmc0->spinor->fail.
>>>>> + */
>>>>> +void board_boot_order(u32 *spl_boot_list)
>>>>> +{
>>>>> + /*
>>>>> + * See the comments above in sunxi_get_boot_device() for information
>>>>> + * about FEL boot.
>>>>> + */
>>>>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>>>>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>>>>> + return;
>>>>> + }
>>>>> +
>>>>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>>>>
>>>> So does that mean that it tries MMC first, even when booted via SPI? So if
>>>> there is a *non*-bootable microSD card in, it will read something from
>>>> sector 80, and will execute that if this is a FIT or legacy image?
>>> yes
>> Uh sorry to bother you again but I cant seem to find a way to find where
>> the bootrom got the spl. I could check other periphirals like pinmux. I
>> could also just have it configured at build. Are both these options
>> okay? I will try to find a way to find the boot device at runtime first.
>
> Don't bother for this version, it's fine as it is now, we can refine
> this later. It's only a problem if there is a non-valid SPL, but a
> valid U-Boot proper legacy image on the SD card.
> I don't want to have a build time option, we try to keep a single image
> for all boot sources.
Ah the boot source is in R2 when save_boot_params is called.
I dont know how i would add it though.
> So eventually I'd prefer the pinmux/clock check, since that's cheaper.
> The alternative would be to read the SPL (again), check for a valid
> header and verify the checksum. You can look at this for inspiration:
> https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przywara@arm.com/
>
>> Also in my next patch i added spi boot for the spl. I also have a patch
>> for DT spi driver, but I didn't add it to v3.
>
> Please stay with the number and scope of the patches as we have it at
> the moment. You can send the SPL SPI and DT SPI as follow-up patches,
> and we can take them later.
> For now I want to get the basic support in, even if that means FEL
> only. Otherwise it becomes an issue of herding cats, with constant
> rebase burden.
>
> Cheers,
> Andre
>
>> thank you,
>> Jesse Taube
>>>>
>>>> I wonder if we actually have some indication of SPI booting, for instance
>>>> the pinmux or clock settings?
>>>> Otherwise we would really need to mimic the BROM, and read and verify the
>>>> eGON header again, to be reliable.
>>> HMM this should be fixed thx for pointing this out.
>>>>
>>>> I might be talked into ignoring this issue for now, if there will be a fix
>>>> patch later on.
>>>>
>>>>> + spl_boot_list[1] = BOOT_DEVICE_SPI;
>>>>> +}
>>>>> +#endif
>>>>>
>>>>> void board_init_f(ulong dummy)
>>>>> {
>>>>> diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
>>>>> index de7e875298..da3a0eb058 100644
>>>>> --- a/arch/arm/mach-sunxi/clock.c
>>>>> +++ b/arch/arm/mach-sunxi/clock.c
>>>>> @@ -35,7 +35,8 @@ int clock_init(void)
>>>>> }
>>>>>
>>>>> /* These functions are shared between various SoCs so put them here. */
>>>>> -#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
>>>>> +#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I && \
>>>>> + !defined CONFIG_MACH_SUNIV
>>>>> int clock_twi_onoff(int port, int state)
>>>>> {
>>>>> struct sunxi_ccm_reg *const ccm =
>>>>> diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
>>>>> index 8e84062bd7..b0b3ea4d30 100644
>>>>> --- a/arch/arm/mach-sunxi/clock_sun6i.c
>>>>> +++ b/arch/arm/mach-sunxi/clock_sun6i.c
>>>>> @@ -23,7 +23,8 @@ void clock_init_safe(void)
>>>>> struct sunxi_ccm_reg * const ccm =
>>>>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>>>>
>>>>> -#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
>>>>> +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \
>>>>> + !defined(CONFIG_MACH_SUNIV)
>>>>> struct sunxi_prcm_reg * const prcm =
>>>>> (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>>>>>
>>>>> @@ -49,9 +50,11 @@ void clock_init_safe(void)
>>>>>
>>>>> writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
>>>>>
>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>> writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
>>>>> if (IS_ENABLED(CONFIG_MACH_SUN6I))
>>>>> writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
>>>>> +#endif
>>>>>
>>>>> #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
>>>>> setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
>>>>> @@ -87,6 +90,7 @@ void clock_init_uart(void)
>>>>> struct sunxi_ccm_reg *const ccm =
>>>>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>>>>
>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>
>>>> Please again negate and swap the branches.
>>>>
>>>>> /* uart clock source is apb2 */
>>>>> writel(APB2_CLK_SRC_OSC24M|
>>>>> APB2_CLK_RATE_N_1|
>>>>> @@ -102,6 +106,24 @@ void clock_init_uart(void)
>>>>> setbits_le32(&ccm->apb2_reset_cfg,
>>>>> 1 << (APB2_RESET_UART_SHIFT +
>>>>> CONFIG_CONS_INDEX - 1));
>>>>> +#else
>>>>> + /* suniv doesn't have apb2, so uart clock source is apb1 */
>>>>> + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
>>>>> + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
>>>>> + ;
>>>>> +
>>>>> + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
>>>>
>>>> This is done is clock_init_safe() already, which is called before
>>>> clock_init_uart(). I feel we should drop it here, not only because
>>>> touching a PLL again might cause problems.
>>> Okay.
>>>>
>>>>> +
>>>>> + /* open the clock for uart */
>>>>> + setbits_le32(&ccm->apb1_gate,
>>>>> + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
>>>>> + CONFIG_CONS_INDEX - 1));
>>>>> +
>>>>> + /* deassert uart reset */
>>>>> + setbits_le32(&ccm->apb1_reset_cfg,
>>>>> + 1 << (APB1_RESET_UART_SHIFT +
>>>>> + CONFIG_CONS_INDEX - 1));
>>>>> +#endif
>>>>> #else
>>>>> /* enable R_PIO and R_UART clocks, and de-assert resets */
>>>>> prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
>>>>> @@ -125,10 +147,15 @@ void clock_set_pll1(unsigned int clk)
>>>>> }
>>>>>
>>>>> /* Switch to 24MHz clock while changing PLL1 */
>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>
>>>> Same negation here. And can you please turn those preprocessor guards into
>>>> if (IS_ENABLED(CONFIG_MACH_SUNIV)) ...
>>>> where applicable? That's always preferred, if all symbols used inside both
>>>> branches are defined in either case, as in here, for instance.
>>>> As the compiler will see that it's a compile-time constant, it will remove
>>>> the non-applicable branch. So the effect on the code is mostly the same,
>>>> but both branches are "compile-tested" and it's more readable, as the
>>>> nesting is done properly.
>>>>
>>>>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
>>>>> ATB_DIV_2 << ATB_DIV_SHIFT |
>>>>> CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
>>>>> &ccm->cpu_axi_cfg);
>>>>> +#else
>>>>> + writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
>>>>> + &ccm->cpu_axi_cfg);
>>>>> +#endif
>>>>>
>>>>> /*
>>>>> * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
>>>>> @@ -137,13 +164,26 @@ void clock_set_pll1(unsigned int clk)
>>>>> writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
>>>>> CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
>>>>> CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>
>>>> Guess ...
>>> Sorry i didnt think it would be too bit a problem.
>>>>
>>>>> sdelay(200);
>>>>> +#else
>>>>> + /* ARM926EJ-S code does not have sdelay */
>>>>
>>>> I wonder if we should just copy a definition of it to
>>>> arch/arm/cpu/arm926ejs. The ARMv7 assembly should just work.
>>> I will try. if it doesnt work i will add.
>>>>> + volatile int i = 200;
>>>>> +
>>>>> + while (i > 0)
>>>>> + i--;
>>>>> +#endif
>>>>>
>>>>> /* Switch CPU to PLL1 */
>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>
>>>> Negate and if(IS_ENABLED(...)), please.
>>>>
>>>>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
>>>>> ATB_DIV_2 << ATB_DIV_SHIFT |
>>>>> CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
>>>>> &ccm->cpu_axi_cfg);
>>>>> +#else
>>>>> + writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
>>>>> + &ccm->cpu_axi_cfg);
>>>>> +#endif
>>>>> }
>>>>> #endif
>>>>>
>>>>> @@ -317,7 +357,11 @@ unsigned int clock_get_pll6(void)
>>>>> uint32_t rval = readl(&ccm->pll6_cfg);
>>>>> int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
>>>>> int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>
>>>> Negate and if(IS_ENABLED(...)), please.
>>>>
>>>>> return 24000000 * n * k / 2;
>>>>> +#else
>>>>> + return 24000000 * n * k;
>>>>> +#endif
>>>>> }
>>>>
>>>> This whole file is admittedly quite messy. We should be able to move the
>>>> video clocks out here and into our DM clock driver, but this is
>>>> non-trivial, I believe, so I won't ask you doing this ;-)
>>> Ah yes I was changing all the added ifdefs to ifs then I noticed that
>>> there where alreay ifdefs everywhere so i didnt change it. I will
>>> continue with it.
>>>>
>>>> Cheers,
>>>> Andre
>>>>
>>>>>
>>>>> unsigned int clock_get_mipi_pll(void)
>>>>> diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
>>>>> index ba33ef2430..7eef178859 100644
>>>>> --- a/arch/arm/mach-sunxi/cpu_info.c
>>>>> +++ b/arch/arm/mach-sunxi/cpu_info.c
>>>>> @@ -57,6 +57,8 @@ int print_cpuinfo(void)
>>>>> {
>>>>> #ifdef CONFIG_MACH_SUN4I
>>>>> puts("CPU: Allwinner A10 (SUN4I)\n");
>>>>> +#elif defined CONFIG_MACH_SUNIV
>>>>> + puts("CPU: Allwinner F Series (SUNIV)\n");
>>>>> #elif defined CONFIG_MACH_SUN5I
>>>>> u32 val = readl(SUNXI_SID_BASE + 0x08);
>>>>> switch ((val >> 12) & 0xf) {
>>>>
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-29 19:24 ` Jesse Taube
@ 2022-01-29 20:44 ` Giulio Benetti
0 siblings, 0 replies; 43+ messages in thread
From: Giulio Benetti @ 2022-01-29 20:44 UTC (permalink / raw)
To: Jesse Taube
Cc: Andre Przywara, u-boot, jagan, hdegoede, sjg, icenowy,
marek.behun, festevam, narmstrong, tharvey, christianshewitt,
pbrobinson, jernej.skrabec, hs, samuel, arnaud.ferraris,
thirtythreeforty, Chris Morgan
Hi Jesse, Andre, All,
> Il giorno 29 gen 2022, alle ore 20:24, Jesse Taube <mr.bossman075@gmail.com> ha scritto:
>
>
>
>> On 1/29/22 06:51, Andre Przywara wrote:
>>> On Fri, 28 Jan 2022 22:21:28 -0500
>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>> On 1/26/22 09:38, Jesse Taube wrote:
>>>>
>>>>
>>>> On 1/26/22 09:13, Andre Przywara wrote:
>>>>> On Tue, 4 Jan 2022 19:35:06 -0500
>>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>>
>>>>> Hi Jesse,
>>>>>
>>>>> I was checking some bits and pieces here, so sorry for the delay. I saw
>>>>> your v2, and will review that ASAP, so that we get one step closer. Please
>>>>> don't send a v3 before that.
>>>>>
>>>>> If you have some time, can you also meanwhile check if this series is
>>>>> bisectable, meaning that every patch compiles? I have the feeling there is
>>>>> something off, but didn't check it. Pick an H3 and an A64 board, and
>>>>> compile it after each patch. I can do this as well, if you don't find the
>>>>> time for this.
>>>> I didnt check for bisectability but i did order the patches to avoid it.
>>>>>
>>>>> In general I am tempted to merge this still in this cycle, since we don't
>>>>> have other big changes, but we would need to settle this by early next
>>>>> week then.
>>>>>
>>>>> See below for more work ;-) (Sorry!)
>>>> Its okay.
>>>>>
>>>>>> From: Icenowy Zheng <icenowy@aosc.io>
>>>>>>
>>>>>> Add support for the suniv architecture, which is newer ARM9 SoCs by
>>>>>> Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
>>>>>> sun6i.
>>>>>>
>>>>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>>>>>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>>>>>> ---
>>>>>> arch/arm/mach-sunxi/Kconfig | 16 +++++++++--
>>>>>> arch/arm/mach-sunxi/board.c | 31 +++++++++++++++++++--
>>>>>> arch/arm/mach-sunxi/clock.c | 3 +-
>>>>>> arch/arm/mach-sunxi/clock_sun6i.c | 46 ++++++++++++++++++++++++++++++-
>>>>>> arch/arm/mach-sunxi/cpu_info.c | 2 ++
>>>>>> 5 files changed, 91 insertions(+), 7 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
>>>>>> index 2c18cf02d1..9bb7717731 100644
>>>>>> --- a/arch/arm/mach-sunxi/Kconfig
>>>>>> +++ b/arch/arm/mach-sunxi/Kconfig
>>>>>> @@ -1,7 +1,8 @@
>>>>>> if ARCH_SUNXI
>>>>>> config SPL_LDSCRIPT
>>>>>> - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
>>>>>> + default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
>>>>>> + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 && !MACH_SUNIV
>>>>>> config IDENT_STRING
>>>>>> default " Allwinner Technology"
>>>>>> @@ -183,6 +184,12 @@ choice
>>>>>> prompt "Sunxi SoC Variant"
>>>>>> optional
>>>>>> +config MACH_SUNIV
>>>>>> + bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
>>>>>> + select CPU_ARM926EJS
>>>>>> + select SUNXI_GEN_SUN6I
>>>>>> + select SUPPORT_SPL
>>>>>> +
>>>>>> config MACH_SUN4I
>>>>>> bool "sun4i (Allwinner A10)"
>>>>>> select CPU_V7A
>>>>>> @@ -587,6 +594,7 @@ config DRAM_ODT_CORRECTION
>>>>>> endif
>>>>>> config SYS_CLK_FREQ
>>>>>> + default 408000000 if MACH_SUNIV
>>>>>> default 1008000000 if MACH_SUN4I
>>>>>> default 1008000000 if MACH_SUN5I
>>>>>> default 1008000000 if MACH_SUN6I
>>>>>> @@ -598,6 +606,7 @@ config SYS_CLK_FREQ
>>>>>> default 1008000000 if MACH_SUN50I_H616
>>>>>> config SYS_CONFIG_NAME
>>>>>> + default "suniv" if MACH_SUNIV
>>>>>> default "sun4i" if MACH_SUN4I
>>>>>> default "sun5i" if MACH_SUN5I
>>>>>> default "sun6i" if MACH_SUN6I
>>>>>> @@ -805,7 +814,7 @@ config VIDEO_SUNXI
>>>>>> config VIDEO_HDMI
>>>>>> bool "HDMI output support"
>>>>>> - depends on VIDEO_SUNXI && !MACH_SUN8I
>>>>>> + depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
>>>>>> default y
>>>>>> ---help---
>>>>>> Say Y here to add support for outputting video over HDMI.
>>>>>> @@ -1005,6 +1014,7 @@ config GMAC_TX_DELAY
>>>>>> Set the GMAC Transmit Clock Delay Chain value.
>>>>>> config SPL_STACK_R_ADDR
>>>>>> + default 0x81e00000 if MACH_SUNIV
>>>>>> default 0x4fe00000 if MACH_SUN4I
>>>>>> default 0x4fe00000 if MACH_SUN5I
>>>>>> default 0x4fe00000 if MACH_SUN6I
>>>>>> @@ -1016,7 +1026,7 @@ config SPL_STACK_R_ADDR
>>>>>> config SPL_SPI_SUNXI
>>>>>> bool "Support for SPI Flash on Allwinner SoCs in SPL"
>>>>>> - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
>>>>>> + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV
>>>>>
>>>>> I think this is premature without the corresponding patch to
>>>>> spl_spi_sunxi.c.
>>>> Ill look into this.
>>>>>
>>>>>> help
>>>>>> Enable support for SPI Flash. This option allows SPL to read from
>>>>>> sunxi SPI Flash. It uses the same method as the boot ROM, so does
>>>>>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
>>>>>> index 3ef179742c..2fee86b49b 100644
>>>>>> --- a/arch/arm/mach-sunxi/board.c
>>>>>> +++ b/arch/arm/mach-sunxi/board.c
>>>>>> @@ -86,7 +86,8 @@ static int gpio_init(void)
>>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
>>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
>>>>>> #endif
>>>>>> -#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
>>>>>> +#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \
>>>>>> + defined(CONFIG_MACH_SUNIV)
>>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
>>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
>>>>>> #else
>>>>>> @@ -94,6 +95,10 @@ static int gpio_init(void)
>>>>>> sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
>>>>>> #endif
>>>>>> sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
>>>>>> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
>>>>>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
>>>>>> + sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
>>>>>> + sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
>>>>>> #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
>>>>>> defined(CONFIG_MACH_SUN7I) || \
>>>>>> defined(CONFIG_MACH_SUN8I_R40))
>>>>>> @@ -219,7 +224,8 @@ void s_init(void)
>>>>>> /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
>>>>>> #endif
>>>>>> -#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
>>>>>> +#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) && \
>>>>>> + !defined(CONFIG_MACH_SUNIV)
>>>>>
>>>>> That looks correct for now, but should become obsolete with my
>>>>> lowlevel_init cleanup series.
>>>> Yes in V2 i fix this line, but it breaks compiling without your patch.
>>>> Idk if you want a bad compile or a bad merge.
>>>>>
>>>>>> /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
>>>>>> asm volatile(
>>>>>> "mrc p15, 0, r0, c1, c0, 1\n"
>>>>>> @@ -328,10 +334,31 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
>>>>>> return sector;
>>>>>> }
>>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>>
>>>>> Can you please flip this around to avoid the negative logic?
>>>> Ah yes i will.
>>>>>
>>>>>> u32 spl_boot_device(void)
>>>>>> {
>>>>>> return sunxi_get_boot_device();
>>>>>> }
>>>>>> +#else
>>>>>> +/*
>>>>>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>>>>>> + * boot sequence in BROM: mmc0->spinor->fail.
>>>>>> + */
>>>>>> +void board_boot_order(u32 *spl_boot_list)
>>>>>> +{
>>>>>> + /*
>>>>>> + * See the comments above in sunxi_get_boot_device() for information
>>>>>> + * about FEL boot.
>>>>>> + */
>>>>>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>>>>>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>>>>>> + return;
>>>>>> + }
>>>>>> +
>>>>>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>>>>>
>>>>> So does that mean that it tries MMC first, even when booted via SPI? So if
>>>>> there is a *non*-bootable microSD card in, it will read something from
>>>>> sector 80, and will execute that if this is a FIT or legacy image?
>>>> yes
>>> Uh sorry to bother you again but I cant seem to find a way to find where
>>> the bootrom got the spl. I could check other periphirals like pinmux. I
>>> could also just have it configured at build. Are both these options
>>> okay? I will try to find a way to find the boot device at runtime first.
>> Don't bother for this version, it's fine as it is now, we can refine
>> this later. It's only a problem if there is a non-valid SPL, but a
>> valid U-Boot proper legacy image on the SD card.
>> I don't want to have a build time option, we try to keep a single image
>> for all boot sources.
> Ah the boot source is in R2 when save_boot_params is called.
> I dont know how i would add it though.
save_boot_params is called at the very beginning:
https://elixir.bootlin.com/u-boot/latest/source/arch/arm/cpu/armv7/start.S#L39
So maybe that is something left from BROM after running.
Are the values present in R2 compatible to the ones used from sunxi?
We could add a global variable in start.S to save the value and use it later in the code to know
the media we’re booting from.
Best regards
—-
Giulio Benetti
Benetti Engineering sas
>> So eventually I'd prefer the pinmux/clock check, since that's cheaper.
>> The alternative would be to read the SPL (again), check for a valid
>> header and verify the checksum. You can look at this for inspiration:
>> https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przywara@arm.com/
>>> Also in my next patch i added spi boot for the spl. I also have a patch
>>> for DT spi driver, but I didn't add it to v3.
>> Please stay with the number and scope of the patches as we have it at
>> the moment. You can send the SPL SPI and DT SPI as follow-up patches,
>> and we can take them later.
>> For now I want to get the basic support in, even if that means FEL
>> only. Otherwise it becomes an issue of herding cats, with constant
>> rebase burden.
>> Cheers,
>> Andre
>>> thank you,
>>> Jesse Taube
>>>>>
>>>>> I wonder if we actually have some indication of SPI booting, for instance
>>>>> the pinmux or clock settings?
>>>>> Otherwise we would really need to mimic the BROM, and read and verify the
>>>>> eGON header again, to be reliable.
>>>> HMM this should be fixed thx for pointing this out.
>>>>>
>>>>> I might be talked into ignoring this issue for now, if there will be a fix
>>>>> patch later on.
>>>>>
>>>>>> + spl_boot_list[1] = BOOT_DEVICE_SPI;
>>>>>> +}
>>>>>> +#endif
>>>>>> void board_init_f(ulong dummy)
>>>>>> {
>>>>>> diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
>>>>>> index de7e875298..da3a0eb058 100644
>>>>>> --- a/arch/arm/mach-sunxi/clock.c
>>>>>> +++ b/arch/arm/mach-sunxi/clock.c
>>>>>> @@ -35,7 +35,8 @@ int clock_init(void)
>>>>>> }
>>>>>> /* These functions are shared between various SoCs so put them here. */
>>>>>> -#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
>>>>>> +#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I && \
>>>>>> + !defined CONFIG_MACH_SUNIV
>>>>>> int clock_twi_onoff(int port, int state)
>>>>>> {
>>>>>> struct sunxi_ccm_reg *const ccm =
>>>>>> diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
>>>>>> index 8e84062bd7..b0b3ea4d30 100644
>>>>>> --- a/arch/arm/mach-sunxi/clock_sun6i.c
>>>>>> +++ b/arch/arm/mach-sunxi/clock_sun6i.c
>>>>>> @@ -23,7 +23,8 @@ void clock_init_safe(void)
>>>>>> struct sunxi_ccm_reg * const ccm =
>>>>>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>>>>> -#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
>>>>>> +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \
>>>>>> + !defined(CONFIG_MACH_SUNIV)
>>>>>> struct sunxi_prcm_reg * const prcm =
>>>>>> (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>>>>>> @@ -49,9 +50,11 @@ void clock_init_safe(void)
>>>>>> writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
>>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>>> writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
>>>>>> if (IS_ENABLED(CONFIG_MACH_SUN6I))
>>>>>> writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
>>>>>> +#endif
>>>>>> #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
>>>>>> setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
>>>>>> @@ -87,6 +90,7 @@ void clock_init_uart(void)
>>>>>> struct sunxi_ccm_reg *const ccm =
>>>>>> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>>
>>>>> Please again negate and swap the branches.
>>>>>
>>>>>> /* uart clock source is apb2 */
>>>>>> writel(APB2_CLK_SRC_OSC24M|
>>>>>> APB2_CLK_RATE_N_1|
>>>>>> @@ -102,6 +106,24 @@ void clock_init_uart(void)
>>>>>> setbits_le32(&ccm->apb2_reset_cfg,
>>>>>> 1 << (APB2_RESET_UART_SHIFT +
>>>>>> CONFIG_CONS_INDEX - 1));
>>>>>> +#else
>>>>>> + /* suniv doesn't have apb2, so uart clock source is apb1 */
>>>>>> + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
>>>>>> + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
>>>>>> + ;
>>>>>> +
>>>>>> + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
>>>>>
>>>>> This is done is clock_init_safe() already, which is called before
>>>>> clock_init_uart(). I feel we should drop it here, not only because
>>>>> touching a PLL again might cause problems.
>>>> Okay.
>>>>>
>>>>>> +
>>>>>> + /* open the clock for uart */
>>>>>> + setbits_le32(&ccm->apb1_gate,
>>>>>> + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
>>>>>> + CONFIG_CONS_INDEX - 1));
>>>>>> +
>>>>>> + /* deassert uart reset */
>>>>>> + setbits_le32(&ccm->apb1_reset_cfg,
>>>>>> + 1 << (APB1_RESET_UART_SHIFT +
>>>>>> + CONFIG_CONS_INDEX - 1));
>>>>>> +#endif
>>>>>> #else
>>>>>> /* enable R_PIO and R_UART clocks, and de-assert resets */
>>>>>> prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
>>>>>> @@ -125,10 +147,15 @@ void clock_set_pll1(unsigned int clk)
>>>>>> }
>>>>>> /* Switch to 24MHz clock while changing PLL1 */
>>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>>
>>>>> Same negation here. And can you please turn those preprocessor guards into
>>>>> if (IS_ENABLED(CONFIG_MACH_SUNIV)) ...
>>>>> where applicable? That's always preferred, if all symbols used inside both
>>>>> branches are defined in either case, as in here, for instance.
>>>>> As the compiler will see that it's a compile-time constant, it will remove
>>>>> the non-applicable branch. So the effect on the code is mostly the same,
>>>>> but both branches are "compile-tested" and it's more readable, as the
>>>>> nesting is done properly.
>>>>>
>>>>>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
>>>>>> ATB_DIV_2 << ATB_DIV_SHIFT |
>>>>>> CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
>>>>>> &ccm->cpu_axi_cfg);
>>>>>> +#else
>>>>>> + writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
>>>>>> + &ccm->cpu_axi_cfg);
>>>>>> +#endif
>>>>>> /*
>>>>>> * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
>>>>>> @@ -137,13 +164,26 @@ void clock_set_pll1(unsigned int clk)
>>>>>> writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
>>>>>> CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
>>>>>> CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
>>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>>
>>>>> Guess ...
>>>> Sorry i didnt think it would be too bit a problem.
>>>>>
>>>>>> sdelay(200);
>>>>>> +#else
>>>>>> + /* ARM926EJ-S code does not have sdelay */
>>>>>
>>>>> I wonder if we should just copy a definition of it to
>>>>> arch/arm/cpu/arm926ejs. The ARMv7 assembly should just work.
>>>> I will try. if it doesnt work i will add.
>>>>>> + volatile int i = 200;
>>>>>> +
>>>>>> + while (i > 0)
>>>>>> + i--;
>>>>>> +#endif
>>>>>> /* Switch CPU to PLL1 */
>>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>>
>>>>> Negate and if(IS_ENABLED(...)), please.
>>>>>
>>>>>> writel(AXI_DIV_3 << AXI_DIV_SHIFT |
>>>>>> ATB_DIV_2 << ATB_DIV_SHIFT |
>>>>>> CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
>>>>>> &ccm->cpu_axi_cfg);
>>>>>> +#else
>>>>>> + writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
>>>>>> + &ccm->cpu_axi_cfg);
>>>>>> +#endif
>>>>>> }
>>>>>> #endif
>>>>>> @@ -317,7 +357,11 @@ unsigned int clock_get_pll6(void)
>>>>>> uint32_t rval = readl(&ccm->pll6_cfg);
>>>>>> int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
>>>>>> int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
>>>>>> +#ifndef CONFIG_MACH_SUNIV
>>>>>
>>>>> Negate and if(IS_ENABLED(...)), please.
>>>>>
>>>>>> return 24000000 * n * k / 2;
>>>>>> +#else
>>>>>> + return 24000000 * n * k;
>>>>>> +#endif
>>>>>> }
>>>>>
>>>>> This whole file is admittedly quite messy. We should be able to move the
>>>>> video clocks out here and into our DM clock driver, but this is
>>>>> non-trivial, I believe, so I won't ask you doing this ;-)
>>>> Ah yes I was changing all the added ifdefs to ifs then I noticed that
>>>> there where alreay ifdefs everywhere so i didnt change it. I will
>>>> continue with it.
>>>>>
>>>>> Cheers,
>>>>> Andre
>>>>>
>>>>>> unsigned int clock_get_mipi_pll(void)
>>>>>> diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
>>>>>> index ba33ef2430..7eef178859 100644
>>>>>> --- a/arch/arm/mach-sunxi/cpu_info.c
>>>>>> +++ b/arch/arm/mach-sunxi/cpu_info.c
>>>>>> @@ -57,6 +57,8 @@ int print_cpuinfo(void)
>>>>>> {
>>>>>> #ifdef CONFIG_MACH_SUN4I
>>>>>> puts("CPU: Allwinner A10 (SUN4I)\n");
>>>>>> +#elif defined CONFIG_MACH_SUNIV
>>>>>> + puts("CPU: Allwinner F Series (SUNIV)\n");
>>>>>> #elif defined CONFIG_MACH_SUN5I
>>>>>> u32 val = readl(SUNXI_SID_BASE + 0x08);
>>>>>> switch ((val >> 12) & 0xf) {
>>>>>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-29 11:51 ` Andre Przywara
2022-01-29 19:24 ` Jesse Taube
@ 2022-01-29 20:59 ` Samuel Holland
2022-01-29 21:05 ` Jesse Taube
1 sibling, 1 reply; 43+ messages in thread
From: Samuel Holland @ 2022-01-29 20:59 UTC (permalink / raw)
To: Andre Przywara, Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On 1/29/22 5:51 AM, Andre Przywara wrote:
> On Fri, 28 Jan 2022 22:21:28 -0500
> Jesse Taube <mr.bossman075@gmail.com> wrote:
>> On 1/26/22 09:38, Jesse Taube wrote:
>>> On 1/26/22 09:13, Andre Przywara wrote:
>>>> On Tue, 4 Jan 2022 19:35:06 -0500
>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>
>>>>> u32 spl_boot_device(void)
>>>>> {
>>>>> return sunxi_get_boot_device();
>>>>> }
>>>>> +#else
>>>>> +/*
>>>>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>>>>> + * boot sequence in BROM: mmc0->spinor->fail.
>>>>> + */
>>>>> +void board_boot_order(u32 *spl_boot_list)
>>>>> +{
>>>>> + /*
>>>>> + * See the comments above in sunxi_get_boot_device() for information
>>>>> + * about FEL boot.
>>>>> + */
>>>>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>>>>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>>>>> + return;
>>>>> + }
>>>>> +
>>>>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>>>>
>>>> So does that mean that it tries MMC first, even when booted via SPI? So if
>>>> there is a *non*-bootable microSD card in, it will read something from
>>>> sector 80, and will execute that if this is a FIT or legacy image?
>>> yes
>> Uh sorry to bother you again but I cant seem to find a way to find where
>> the bootrom got the spl. I could check other periphirals like pinmux. I
>> could also just have it configured at build. Are both these options
>> okay? I will try to find a way to find the boot device at runtime first.
>
> Don't bother for this version, it's fine as it is now, we can refine
> this later. It's only a problem if there is a non-valid SPL, but a
> valid U-Boot proper legacy image on the SD card.
> I don't want to have a build time option, we try to keep a single image
> for all boot sources.
> So eventually I'd prefer the pinmux/clock check, since that's cheaper.
> The alternative would be to read the SPL (again), check for a valid
> header and verify the checksum. You can look at this for inspiration:
> https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przywara@arm.com/
I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
it loaded SPL from, or make any other changes to the loaded eGON image. The boot
ROM also completely cleans up its clock and pinctrl changes, regardless of the
success/failure of a specific boot device.
There's a function which loads some value to r2, but that gets called before the
"load eGON from storage" functions, so r2 will be clobbered.
So as far as I can tell, the only way to determine the boot device, other than
reimplementing the BROM in SPL, is to look at the return address on the top of
the BROM's stack. These are the possible values (in order of execution):
0xffff40f8: mmc0
0xffff4114: spi0 NAND
0xffff4130: spi0 NOR
0xffff4150: mmc1
Regards,
Samuel
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-29 20:59 ` Samuel Holland
@ 2022-01-29 21:05 ` Jesse Taube
2022-01-29 21:18 ` Giulio Benetti
2022-01-29 21:19 ` Jesse Taube
0 siblings, 2 replies; 43+ messages in thread
From: Jesse Taube @ 2022-01-29 21:05 UTC (permalink / raw)
To: Samuel Holland, Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On 1/29/22 15:59, Samuel Holland wrote:
> On 1/29/22 5:51 AM, Andre Przywara wrote:
>> On Fri, 28 Jan 2022 22:21:28 -0500
>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>> On 1/26/22 09:38, Jesse Taube wrote:
>>>> On 1/26/22 09:13, Andre Przywara wrote:
>>>>> On Tue, 4 Jan 2022 19:35:06 -0500
>>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>>
>>>>>> u32 spl_boot_device(void)
>>>>>> {
>>>>>> return sunxi_get_boot_device();
>>>>>> }
>>>>>> +#else
>>>>>> +/*
>>>>>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>>>>>> + * boot sequence in BROM: mmc0->spinor->fail.
>>>>>> + */
>>>>>> +void board_boot_order(u32 *spl_boot_list)
>>>>>> +{
>>>>>> + /*
>>>>>> + * See the comments above in sunxi_get_boot_device() for information
>>>>>> + * about FEL boot.
>>>>>> + */
>>>>>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>>>>>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>>>>>> + return;
>>>>>> + }
>>>>>> +
>>>>>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>>>>>
>>>>> So does that mean that it tries MMC first, even when booted via SPI? So if
>>>>> there is a *non*-bootable microSD card in, it will read something from
>>>>> sector 80, and will execute that if this is a FIT or legacy image?
>>>> yes
>>> Uh sorry to bother you again but I cant seem to find a way to find where
>>> the bootrom got the spl. I could check other periphirals like pinmux. I
>>> could also just have it configured at build. Are both these options
>>> okay? I will try to find a way to find the boot device at runtime first.
>>
>> Don't bother for this version, it's fine as it is now, we can refine
>> this later. It's only a problem if there is a non-valid SPL, but a
>> valid U-Boot proper legacy image on the SD card.
>> I don't want to have a build time option, we try to keep a single image
>> for all boot sources.
>> So eventually I'd prefer the pinmux/clock check, since that's cheaper.
>> The alternative would be to read the SPL (again), check for a valid
>> header and verify the checksum. You can look at this for inspiration:
>> https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przywara@arm.com/
>
> I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
> it loaded SPL from, or make any other changes to the loaded eGON image. The boot
> ROM also completely cleans up its clock and pinctrl changes, regardless of the
> success/failure of a specific boot device.
>
> There's a function which loads some value to r2, but that gets called before the
> "load eGON from storage" functions, so r2 will be clobbered.
>
> So as far as I can tell, the only way to determine the boot device, other than
> reimplementing the BROM in SPL, is to look at the return address on the top of
> the BROM's stack. These are the possible values (in order of execution):
>
> 0xffff40f8: mmc0
> 0xffff4114: spi0 NAND
> 0xffff4130: spi0 NOR
> 0xffff4150: mmc1
If i save it in save_boot_params it does change when in a different boot
device. Ill look into it more.
the sp is also a good idea.
> Regards,
> Samuel
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-29 21:05 ` Jesse Taube
@ 2022-01-29 21:18 ` Giulio Benetti
2022-01-29 21:19 ` Jesse Taube
1 sibling, 0 replies; 43+ messages in thread
From: Giulio Benetti @ 2022-01-29 21:18 UTC (permalink / raw)
To: Jesse Taube, Samuel Holland, Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, arnaud.ferraris, thirtythreeforty,
Chris Morgan
Hi Jesse, Andre,
On 29/01/22 22:05, Jesse Taube wrote:
>
>
> On 1/29/22 15:59, Samuel Holland wrote:
>> On 1/29/22 5:51 AM, Andre Przywara wrote:
>>> On Fri, 28 Jan 2022 22:21:28 -0500
>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>> On 1/26/22 09:38, Jesse Taube wrote:
>>>>> On 1/26/22 09:13, Andre Przywara wrote:
>>>>>> On Tue, 4 Jan 2022 19:35:06 -0500
>>>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>>>
>>>>>>> u32 spl_boot_device(void)
>>>>>>> {
>>>>>>> return sunxi_get_boot_device();
>>>>>>> }
>>>>>>> +#else
>>>>>>> +/*
>>>>>>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>>>>>>> + * boot sequence in BROM: mmc0->spinor->fail.
>>>>>>> + */
>>>>>>> +void board_boot_order(u32 *spl_boot_list)
>>>>>>> +{
>>>>>>> + /*
>>>>>>> + * See the comments above in sunxi_get_boot_device() for information
>>>>>>> + * about FEL boot.
>>>>>>> + */
>>>>>>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>>>>>>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>>>>>>> + return;
>>>>>>> + }
>>>>>>> +
>>>>>>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>>>>>>
>>>>>> So does that mean that it tries MMC first, even when booted via SPI? So if
>>>>>> there is a *non*-bootable microSD card in, it will read something from
>>>>>> sector 80, and will execute that if this is a FIT or legacy image?
>>>>> yes
>>>> Uh sorry to bother you again but I cant seem to find a way to find where
>>>> the bootrom got the spl. I could check other periphirals like pinmux. I
>>>> could also just have it configured at build. Are both these options
>>>> okay? I will try to find a way to find the boot device at runtime first.
>>>
>>> Don't bother for this version, it's fine as it is now, we can refine
>>> this later. It's only a problem if there is a non-valid SPL, but a
>>> valid U-Boot proper legacy image on the SD card.
>>> I don't want to have a build time option, we try to keep a single image
>>> for all boot sources.
>>> So eventually I'd prefer the pinmux/clock check, since that's cheaper.
>>> The alternative would be to read the SPL (again), check for a valid
>>> header and verify the checksum. You can look at this for inspiration:
>>> https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przywara@arm.com/
>>
>> I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
>> it loaded SPL from, or make any other changes to the loaded eGON image. The boot
>> ROM also completely cleans up its clock and pinctrl changes, regardless of the
>> success/failure of a specific boot device.
>>
>> There's a function which loads some value to r2, but that gets called before the
>> "load eGON from storage" functions, so r2 will be clobbered.
Samuel, are you sure about this? Maybe Jesse can double check what
happens stepping here:
https://elixir.bootlin.com/u-boot/latest/source/arch/arm/cpu/armv7/start.S#L40
Because Jesse mentioned R2 contains the value, so I expect it to be here.
>> So as far as I can tell, the only way to determine the boot device, other than
>> reimplementing the BROM in SPL, is to look at the return address on the top of
>> the BROM's stack. These are the possible values (in order of execution):
>>
>> 0xffff40f8: mmc0
>> 0xffff4114: spi0 NAND
>> 0xffff4130: spi0 NOR
>> 0xffff4150: mmc1
>
> If i save it in save_boot_params it does change when in a different boot
> device. Ill look into it more.
Are the values in R2 the same as the other sunxi SoCs?
And if yes, you can save it in a global variable here:
https://elixir.bootlin.com/u-boot/latest/source/arch/arm/cpu/armv7/start.S#L40
since that is the very beginning of SPL using a #ifdef SUNIV/#endif
> the sp is also a good idea.
This is also another good option. But if the previous works I would go
for that IMHO.
Best regards
--
Giulio Benetti
Benetti Engineering sas
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-29 21:05 ` Jesse Taube
2022-01-29 21:18 ` Giulio Benetti
@ 2022-01-29 21:19 ` Jesse Taube
2022-01-29 21:21 ` Giulio Benetti
1 sibling, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-29 21:19 UTC (permalink / raw)
To: Samuel Holland, Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On 1/29/22 16:05, Jesse Taube wrote:
>
>
> On 1/29/22 15:59, Samuel Holland wrote:
>> On 1/29/22 5:51 AM, Andre Przywara wrote:
>>> On Fri, 28 Jan 2022 22:21:28 -0500
>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>> On 1/26/22 09:38, Jesse Taube wrote:
>>>>> On 1/26/22 09:13, Andre Przywara wrote:
>>>>>> On Tue, 4 Jan 2022 19:35:06 -0500
>>>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>>>
>>>>>>> u32 spl_boot_device(void)
>>>>>>> {
>>>>>>> return sunxi_get_boot_device();
>>>>>>> }
>>>>>>> +#else
>>>>>>> +/*
>>>>>>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>>>>>>> + * boot sequence in BROM: mmc0->spinor->fail.
>>>>>>> + */
>>>>>>> +void board_boot_order(u32 *spl_boot_list)
>>>>>>> +{
>>>>>>> + /*
>>>>>>> + * See the comments above in sunxi_get_boot_device() for information
>>>>>>> + * about FEL boot.
>>>>>>> + */
>>>>>>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>>>>>>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>>>>>>> + return;
>>>>>>> + }
>>>>>>> +
>>>>>>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>>>>>>
>>>>>> So does that mean that it tries MMC first, even when booted via SPI? So if
>>>>>> there is a *non*-bootable microSD card in, it will read something from
>>>>>> sector 80, and will execute that if this is a FIT or legacy image?
>>>>> yes
>>>> Uh sorry to bother you again but I cant seem to find a way to find where
>>>> the bootrom got the spl. I could check other periphirals like pinmux. I
>>>> could also just have it configured at build. Are both these options
>>>> okay? I will try to find a way to find the boot device at runtime first.
>>>
>>> Don't bother for this version, it's fine as it is now, we can refine
>>> this later. It's only a problem if there is a non-valid SPL, but a
>>> valid U-Boot proper legacy image on the SD card.
>>> I don't want to have a build time option, we try to keep a single image
>>> for all boot sources.
>>> So eventually I'd prefer the pinmux/clock check, since that's cheaper.
>>> The alternative would be to read the SPL (again), check for a valid
>>> header and verify the checksum. You can look at this for inspiration:
>>> https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przywara@arm.com/
>>
>> I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
>> it loaded SPL from, or make any other changes to the loaded eGON image. The boot
>> ROM also completely cleans up its clock and pinctrl changes, regardless of the
>> success/failure of a specific boot device.
>>
>> There's a function which loads some value to r2, but that gets called before the
>> "load eGON from storage" functions, so r2 will be clobbered.
>>
>> So as far as I can tell, the only way to determine the boot device, other than
>> reimplementing the BROM in SPL, is to look at the return address on the top of
>> the BROM's stack. These are the possible values (in order of execution):
>>
>> 0xffff40f8: mmc0
>> 0xffff4114: spi0 NAND
>> 0xffff4130: spi0 NOR
>> 0xffff4150: mmc1
>
> If i save it in save_boot_params it does change when in a different boot
> device. Ill look into it more.
> the sp is also a good idea.
Sry Im just dumb. it does change but it is because it doesn't clean the
registers.
Thanks sam, looking at the stack is the best option.
Sorry,
Jesse Taube
>> Regards,
>> Samuel
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-29 21:19 ` Jesse Taube
@ 2022-01-29 21:21 ` Giulio Benetti
2022-01-29 21:23 ` Jesse Taube
0 siblings, 1 reply; 43+ messages in thread
From: Giulio Benetti @ 2022-01-29 21:21 UTC (permalink / raw)
To: Jesse Taube, Samuel Holland, Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, arnaud.ferraris, thirtythreeforty,
Chris Morgan
On 29/01/22 22:19, Jesse Taube wrote:
>
>
> On 1/29/22 16:05, Jesse Taube wrote:
>>
>>
>> On 1/29/22 15:59, Samuel Holland wrote:
>>> On 1/29/22 5:51 AM, Andre Przywara wrote:
>>>> On Fri, 28 Jan 2022 22:21:28 -0500
>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>> On 1/26/22 09:38, Jesse Taube wrote:
>>>>>> On 1/26/22 09:13, Andre Przywara wrote:
>>>>>>> On Tue, 4 Jan 2022 19:35:06 -0500
>>>>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>>>>
>>>>>>>> u32 spl_boot_device(void)
>>>>>>>> {
>>>>>>>> return sunxi_get_boot_device();
>>>>>>>> }
>>>>>>>> +#else
>>>>>>>> +/*
>>>>>>>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>>>>>>>> + * boot sequence in BROM: mmc0->spinor->fail.
>>>>>>>> + */
>>>>>>>> +void board_boot_order(u32 *spl_boot_list)
>>>>>>>> +{
>>>>>>>> + /*
>>>>>>>> + * See the comments above in sunxi_get_boot_device() for information
>>>>>>>> + * about FEL boot.
>>>>>>>> + */
>>>>>>>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>>>>>>>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>>>>>>>> + return;
>>>>>>>> + }
>>>>>>>> +
>>>>>>>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>>>>>>>
>>>>>>> So does that mean that it tries MMC first, even when booted via SPI? So if
>>>>>>> there is a *non*-bootable microSD card in, it will read something from
>>>>>>> sector 80, and will execute that if this is a FIT or legacy image?
>>>>>> yes
>>>>> Uh sorry to bother you again but I cant seem to find a way to find where
>>>>> the bootrom got the spl. I could check other periphirals like pinmux. I
>>>>> could also just have it configured at build. Are both these options
>>>>> okay? I will try to find a way to find the boot device at runtime first.
>>>>
>>>> Don't bother for this version, it's fine as it is now, we can refine
>>>> this later. It's only a problem if there is a non-valid SPL, but a
>>>> valid U-Boot proper legacy image on the SD card.
>>>> I don't want to have a build time option, we try to keep a single image
>>>> for all boot sources.
>>>> So eventually I'd prefer the pinmux/clock check, since that's cheaper.
>>>> The alternative would be to read the SPL (again), check for a valid
>>>> header and verify the checksum. You can look at this for inspiration:
>>>> https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przywara@arm.com/
>>>
>>> I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
>>> it loaded SPL from, or make any other changes to the loaded eGON image. The boot
>>> ROM also completely cleans up its clock and pinctrl changes, regardless of the
>>> success/failure of a specific boot device.
>>>
>>> There's a function which loads some value to r2, but that gets called before the
>>> "load eGON from storage" functions, so r2 will be clobbered.
>>>
>>> So as far as I can tell, the only way to determine the boot device, other than
>>> reimplementing the BROM in SPL, is to look at the return address on the top of
>>> the BROM's stack. These are the possible values (in order of execution):
>>>
>>> 0xffff40f8: mmc0
>>> 0xffff4114: spi0 NAND
>>> 0xffff4130: spi0 NOR
>>> 0xffff4150: mmc1
>>
>> If i save it in save_boot_params it does change when in a different boot
>> device. Ill look into it more.
>> the sp is also a good idea.
> Sry Im just dumb. it does change but it is because it doesn't clean the
> registers.
> Thanks sam, looking at the stack is the best option.
I've been too late :-)
So happy assembly coding Jesse!
Best regards
--
Giulio Benetti
Benetti Engineering sas
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
2022-01-29 21:21 ` Giulio Benetti
@ 2022-01-29 21:23 ` Jesse Taube
0 siblings, 0 replies; 43+ messages in thread
From: Jesse Taube @ 2022-01-29 21:23 UTC (permalink / raw)
To: Giulio Benetti, Samuel Holland, Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson,
jernej.skrabec, hs, arnaud.ferraris, thirtythreeforty,
Chris Morgan
On 1/29/22 16:21, Giulio Benetti wrote:
> On 29/01/22 22:19, Jesse Taube wrote:
>>
>>
>> On 1/29/22 16:05, Jesse Taube wrote:
>>>
>>>
>>> On 1/29/22 15:59, Samuel Holland wrote:
>>>> On 1/29/22 5:51 AM, Andre Przywara wrote:
>>>>> On Fri, 28 Jan 2022 22:21:28 -0500
>>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>>> On 1/26/22 09:38, Jesse Taube wrote:
>>>>>>> On 1/26/22 09:13, Andre Przywara wrote:
>>>>>>>> On Tue, 4 Jan 2022 19:35:06 -0500
>>>>>>>> Jesse Taube <mr.bossman075@gmail.com> wrote:
>>>>>>>>
>>>>>>>>> u32 spl_boot_device(void)
>>>>>>>>> {
>>>>>>>>> return sunxi_get_boot_device();
>>>>>>>>> }
>>>>>>>>> +#else
>>>>>>>>> +/*
>>>>>>>>> + * suniv BROM do not pass the boot media type to SPL, so we try with the
>>>>>>>>> + * boot sequence in BROM: mmc0->spinor->fail.
>>>>>>>>> + */
>>>>>>>>> +void board_boot_order(u32 *spl_boot_list)
>>>>>>>>> +{
>>>>>>>>> + /*
>>>>>>>>> + * See the comments above in sunxi_get_boot_device() for information
>>>>>>>>> + * about FEL boot.
>>>>>>>>> + */
>>>>>>>>> + if (!is_boot0_magic(SPL_ADDR + 4)) {
>>>>>>>>> + spl_boot_list[0] = BOOT_DEVICE_BOARD;
>>>>>>>>> + return;
>>>>>>>>> + }
>>>>>>>>> +
>>>>>>>>> + spl_boot_list[0] = BOOT_DEVICE_MMC1;
>>>>>>>>
>>>>>>>> So does that mean that it tries MMC first, even when booted via SPI? So if
>>>>>>>> there is a *non*-bootable microSD card in, it will read something from
>>>>>>>> sector 80, and will execute that if this is a FIT or legacy image?
>>>>>>> yes
>>>>>> Uh sorry to bother you again but I cant seem to find a way to find where
>>>>>> the bootrom got the spl. I could check other periphirals like pinmux. I
>>>>>> could also just have it configured at build. Are both these options
>>>>>> okay? I will try to find a way to find the boot device at runtime first.
>>>>>
>>>>> Don't bother for this version, it's fine as it is now, we can refine
>>>>> this later. It's only a problem if there is a non-valid SPL, but a
>>>>> valid U-Boot proper legacy image on the SD card.
>>>>> I don't want to have a build time option, we try to keep a single image
>>>>> for all boot sources.
>>>>> So eventually I'd prefer the pinmux/clock check, since that's cheaper.
>>>>> The alternative would be to read the SPL (again), check for a valid
>>>>> header and verify the checksum. You can look at this for inspiration:
>>>>> https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przywara@arm.com/
>>>>
>>>> I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
>>>> it loaded SPL from, or make any other changes to the loaded eGON image. The boot
>>>> ROM also completely cleans up its clock and pinctrl changes, regardless of the
>>>> success/failure of a specific boot device.
>>>>
>>>> There's a function which loads some value to r2, but that gets called before the
>>>> "load eGON from storage" functions, so r2 will be clobbered.
>>>>
>>>> So as far as I can tell, the only way to determine the boot device, other than
>>>> reimplementing the BROM in SPL, is to look at the return address on the top of
>>>> the BROM's stack. These are the possible values (in order of execution):
>>>>
>>>> 0xffff40f8: mmc0
>>>> 0xffff4114: spi0 NAND
>>>> 0xffff4130: spi0 NOR
>>>> 0xffff4150: mmc1
>>>
>>> If i save it in save_boot_params it does change when in a different boot
>>> device. Ill look into it more.
>>> the sp is also a good idea.
>> Sry Im just dumb. it does change but it is because it doesn't clean the
>> registers.
>> Thanks sam, looking at the stack is the best option.
>
> I've been too late :-)
Im sorry only by a couple of seconds.
> So happy assembly coding Jesse!
Its very difficult :( I'm not used to how it works yet.
Thanks,
Jesse Taube
>
> Best regards
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 10/11] ARM: dts: suniv: Add device tree files for F1C100s
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
` (8 preceding siblings ...)
2022-01-05 0:35 ` [PATCH 09/11] sunxi: Add support for SUNIV architecture Jesse Taube
@ 2022-01-05 0:35 ` Jesse Taube
2022-01-21 1:59 ` Andre Przywara
2022-01-05 0:35 ` [PATCH 11/11] configs: sunxi: Add support for Lichee Pi Nano Jesse Taube
2022-01-05 11:36 ` [PATCH 00/11] Add support for SUNIV and F1C100s Icenowy Zheng
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:35 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
Add device tree files for suniv and
Lichee Pi Nano it is a board based on F1C100s.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 64 ++++++
arch/arm/dts/suniv-f1c100s.dtsi | 6 +
arch/arm/dts/suniv.dtsi | 224 +++++++++++++++++++
4 files changed, 296 insertions(+)
create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi
create mode 100644 arch/arm/dts/suniv.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 453e2fd1a9..07030deeca 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -497,6 +497,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
stm32h743i-eval.dtb \
stm32h750i-art-pi.dtb
+dtb-$(CONFIG_MACH_SUNIV) += \
+ suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
new file mode 100644
index 0000000000..919fc01b0e
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Lichee Pi Nano";
+ compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s",
+ "allwinner,suniv";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
new file mode 100644
index 0000000000..f084bc8dd1
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include "suniv.dtsi"
diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
new file mode 100644
index 0000000000..a4e933505d
--- /dev/null
+++ b/arch/arm/dts/suniv.dtsi
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <dt-bindings/clock/suniv-ccu.h>
+#include <dt-bindings/reset/suniv-ccu.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: clk-24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk-32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ fake100M: clk-100M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "fake-100M";
+ };
+ };
+
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram-controller@1c00000 {
+ compatible = "allwinner,sun4i-a10-sram-controller";
+ reg = <0x01c00000 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_d: sram@10000 {
+ compatible = "mmio-sram";
+ reg = <0x00010000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00010000 0x1000>;
+
+ otg_sram: sram-section@0 {
+ compatible = "allwinner,sun4i-a10-sram-d";
+ reg = <0x0000 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ spi0: spi@1c05000 {
+ compatible = "allwinner,suniv-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <10>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun4i-a10-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ interrupts = <32>;
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ccu: clock@1c20000 {
+ compatible = "allwinner,suniv-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ intc: interrupt-controller@1c20400 {
+ compatible = "allwinner,suniv-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pio: pinctrl@1c20800 {
+ compatible = "allwinner,suniv-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <38>, <39>, <40>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #gpio-cells = <3>;
+
+ spi0_pins_a: spi0-pins-pc {
+ pins = "PC0", "PC1", "PC2", "PC3";
+ function = "spi0";
+ };
+
+ uart0_pins_a: uart-pins-pe {
+ pins = "PE0", "PE1";
+ function = "uart0";
+ };
+
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2",
+ "PF3", "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+ };
+
+ timer@1c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <13>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@1c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ };
+
+ uart0: serial@1c25000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25000 0x400>;
+ interrupts = <1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@1c25400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25400 0x400>;
+ interrupts = <2>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@1c25800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ usb_otg: usb@1c13000 {
+ compatible = "allwinner,suniv-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,suniv-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 10/11] ARM: dts: suniv: Add device tree files for F1C100s
2022-01-05 0:35 ` [PATCH 10/11] ARM: dts: suniv: Add device tree files for F1C100s Jesse Taube
@ 2022-01-21 1:59 ` Andre Przywara
2022-01-21 2:12 ` Jesse Taube
0 siblings, 1 reply; 43+ messages in thread
From: Andre Przywara @ 2022-01-21 1:59 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On Tue, 4 Jan 2022 19:35:07 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi,
> From: Icenowy Zheng <icenowy@aosc.io>
>
> Add device tree files for suniv and
> Lichee Pi Nano it is a board based on F1C100s.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Those files differ significantly from the kernel. It looks like the
copies here enable MMC, SPI and USB, which are missing from the Linux
tree. At the same time both seem to be coming from a slightly different
base. So I'd suggest to fix this up (create a minimal diff between
Linux and this, changing this version if needed), then sending this to
the kernel. Meanwhile we could go with the mainline Linux versions. I
am willing to merge them once the updates reach some maintainer tree.
Cheers,
Andre
> ---
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 64 ++++++
> arch/arm/dts/suniv-f1c100s.dtsi | 6 +
> arch/arm/dts/suniv.dtsi | 224 +++++++++++++++++++
> 4 files changed, 296 insertions(+)
> create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi
> create mode 100644 arch/arm/dts/suniv.dtsi
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 453e2fd1a9..07030deeca 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -497,6 +497,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
> stm32h743i-eval.dtb \
> stm32h750i-art-pi.dtb
>
> +dtb-$(CONFIG_MACH_SUNIV) += \
> + suniv-f1c100s-licheepi-nano.dtb
> dtb-$(CONFIG_MACH_SUN4I) += \
> sun4i-a10-a1000.dtb \
> sun4i-a10-ba10-tvbox.dtb \
> diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> new file mode 100644
> index 0000000000..919fc01b0e
> --- /dev/null
> +++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> @@ -0,0 +1,64 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> +/*
> + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +/dts-v1/;
> +#include "suniv-f1c100s.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Lichee Pi Nano";
> + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s",
> + "allwinner,suniv";
> +
> + aliases {
> + serial0 = &uart0;
> + spi0 = &spi0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&otg_sram {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + bus-width = <4>;
> + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
> + status = "okay";
> +};
> +
> +&spi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins_a>;
> + status = "okay";
> +
> + flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "winbond,w25q128", "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
> new file mode 100644
> index 0000000000..f084bc8dd1
> --- /dev/null
> +++ b/arch/arm/dts/suniv-f1c100s.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> +/*
> + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +#include "suniv.dtsi"
> diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
> new file mode 100644
> index 0000000000..a4e933505d
> --- /dev/null
> +++ b/arch/arm/dts/suniv.dtsi
> @@ -0,0 +1,224 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> +/*
> + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +#include <dt-bindings/clock/suniv-ccu.h>
> +#include <dt-bindings/reset/suniv-ccu.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&intc>;
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: clk-24M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: clk-32k {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + fake100M: clk-100M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <100000000>;
> + clock-output-names = "fake-100M";
> + };
> + };
> +
> + cpus {
> + #address-cells = <0>;
> + #size-cells = <0>;
> +
> + cpu {
> + compatible = "arm,arm926ej-s";
> + device_type = "cpu";
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram-controller@1c00000 {
> + compatible = "allwinner,sun4i-a10-sram-controller";
> + reg = <0x01c00000 0x30>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram_d: sram@10000 {
> + compatible = "mmio-sram";
> + reg = <0x00010000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x00010000 0x1000>;
> +
> + otg_sram: sram-section@0 {
> + compatible = "allwinner,sun4i-a10-sram-d";
> + reg = <0x0000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + spi0: spi@1c05000 {
> + compatible = "allwinner,suniv-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x01c05000 0x1000>;
> + interrupts = <10>;
> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc0: mmc@1c0f000 {
> + compatible = "allwinner,sun4i-a10-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> + clock-names = "ahb", "mmc";
> + interrupts = <32>;
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + ccu: clock@1c20000 {
> + compatible = "allwinner,suniv-ccu";
> + reg = <0x01c20000 0x400>;
> + clocks = <&osc24M>, <&osc32k>;
> + clock-names = "hosc", "losc";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + intc: interrupt-controller@1c20400 {
> + compatible = "allwinner,suniv-ic";
> + reg = <0x01c20400 0x400>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + pio: pinctrl@1c20800 {
> + compatible = "allwinner,suniv-pinctrl";
> + reg = <0x01c20800 0x400>;
> + interrupts = <38>, <39>, <40>;
> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #gpio-cells = <3>;
> +
> + spi0_pins_a: spi0-pins-pc {
> + pins = "PC0", "PC1", "PC2", "PC3";
> + function = "spi0";
> + };
> +
> + uart0_pins_a: uart-pins-pe {
> + pins = "PE0", "PE1";
> + function = "uart0";
> + };
> +
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2",
> + "PF3", "PF4", "PF5";
> + function = "mmc0";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> + };
> +
> + timer@1c20c00 {
> + compatible = "allwinner,sun4i-a10-timer";
> + reg = <0x01c20c00 0x90>;
> + interrupts = <13>;
> + clocks = <&osc24M>;
> + };
> +
> + wdt: watchdog@1c20ca0 {
> + compatible = "allwinner,sun6i-a31-wdt";
> + reg = <0x01c20ca0 0x20>;
> + };
> +
> + uart0: serial@1c25000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c25000 0x400>;
> + interrupts = <1>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> + status = "disabled";
> + };
> +
> + uart1: serial@1c25400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c25400 0x400>;
> + interrupts = <2>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> + status = "disabled";
> + };
> +
> + uart2: serial@1c25800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c25800 0x400>;
> + interrupts = <3>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + status = "disabled";
> + };
> +
> + usb_otg: usb@1c13000 {
> + compatible = "allwinner,suniv-musb";
> + reg = <0x01c13000 0x0400>;
> + clocks = <&ccu CLK_BUS_OTG>;
> + resets = <&ccu RST_BUS_OTG>;
> + interrupts = <26>;
> + interrupt-names = "mc";
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + extcon = <&usbphy 0>;
> + allwinner,sram = <&otg_sram 1>;
> + status = "disabled";
> + };
> +
> + usbphy: phy@1c13400 {
> + compatible = "allwinner,suniv-usb-phy";
> + reg = <0x01c13400 0x10>;
> + reg-names = "phy_ctrl";
> + clocks = <&ccu CLK_USB_PHY0>;
> + clock-names = "usb0_phy";
> + resets = <&ccu RST_USB_PHY0>;
> + reset-names = "usb0_reset";
> + #phy-cells = <1>;
> + status = "disabled";
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 10/11] ARM: dts: suniv: Add device tree files for F1C100s
2022-01-21 1:59 ` Andre Przywara
@ 2022-01-21 2:12 ` Jesse Taube
0 siblings, 0 replies; 43+ messages in thread
From: Jesse Taube @ 2022-01-21 2:12 UTC (permalink / raw)
To: Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty, Chris Morgan
On 1/20/22 20:59, Andre Przywara wrote:
> On Tue, 4 Jan 2022 19:35:07 -0500
> Jesse Taube <mr.bossman075@gmail.com> wrote:
>
> Hi,
>
>> From: Icenowy Zheng <icenowy@aosc.io>
>>
>> Add device tree files for suniv and
>> Lichee Pi Nano it is a board based on F1C100s.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>
> Those files differ significantly from the kernel. It looks like the
> copies here enable MMC, SPI and USB, which are missing from the Linux
> tree.
Thx for pointing this out I will fix it. Although SPI and MMC are the
two boot devices so they will be needed. I'm confused as to why and how
they arent' in Linux as they have drivers, USB even has a driver.
Thanks for the Reviews!
Kindly,
Jesse Taube
At the same time both seem to be coming from a slightly different
> base. So I'd suggest to fix this up (create a minimal diff between
> Linux and this, changing this version if needed), then sending this to
> the kernel. Meanwhile we could go with the mainline Linux versions. I
> am willing to merge them once the updates reach some maintainer tree.
>
> Cheers,
> Andre
>
>> ---
>> arch/arm/dts/Makefile | 2 +
>> arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 64 ++++++
>> arch/arm/dts/suniv-f1c100s.dtsi | 6 +
>> arch/arm/dts/suniv.dtsi | 224 +++++++++++++++++++
>> 4 files changed, 296 insertions(+)
>> create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
>> create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi
>> create mode 100644 arch/arm/dts/suniv.dtsi
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index 453e2fd1a9..07030deeca 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -497,6 +497,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
>> stm32h743i-eval.dtb \
>> stm32h750i-art-pi.dtb
>>
>> +dtb-$(CONFIG_MACH_SUNIV) += \
>> + suniv-f1c100s-licheepi-nano.dtb
>> dtb-$(CONFIG_MACH_SUN4I) += \
>> sun4i-a10-a1000.dtb \
>> sun4i-a10-ba10-tvbox.dtb \
>> diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
>> new file mode 100644
>> index 0000000000..919fc01b0e
>> --- /dev/null
>> +++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
>> @@ -0,0 +1,64 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
>> +/*
>> + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
>> + */
>> +
>> +/dts-v1/;
>> +#include "suniv-f1c100s.dtsi"
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + model = "Lichee Pi Nano";
>> + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s",
>> + "allwinner,suniv";
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + spi0 = &spi0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +&otg_sram {
>> + status = "okay";
>> +};
>> +
>> +&mmc0 {
>> + bus-width = <4>;
>> + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
>> + status = "okay";
>> +};
>> +
>> +&spi0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&spi0_pins_a>;
>> + status = "okay";
>> +
>> + flash@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "winbond,w25q128", "jedec,spi-nor";
>> + reg = <0>;
>> + spi-max-frequency = <40000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart0_pins_a>;
>> + status = "okay";
>> +};
>> +
>> +&usb_otg {
>> + dr_mode = "otg";
>> + status = "okay";
>> +};
>> +
>> +&usbphy {
>> + usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
>> + status = "okay";
>> +};
>> diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
>> new file mode 100644
>> index 0000000000..f084bc8dd1
>> --- /dev/null
>> +++ b/arch/arm/dts/suniv-f1c100s.dtsi
>> @@ -0,0 +1,6 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
>> +/*
>> + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
>> + */
>> +
>> +#include "suniv.dtsi"
>> diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
>> new file mode 100644
>> index 0000000000..a4e933505d
>> --- /dev/null
>> +++ b/arch/arm/dts/suniv.dtsi
>> @@ -0,0 +1,224 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
>> +/*
>> + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
>> + */
>> +
>> +#include <dt-bindings/clock/suniv-ccu.h>
>> +#include <dt-bindings/reset/suniv-ccu.h>
>> +
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + interrupt-parent = <&intc>;
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: clk-24M {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + clock-output-names = "osc24M";
>> + };
>> +
>> + osc32k: clk-32k {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + fake100M: clk-100M {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <100000000>;
>> + clock-output-names = "fake-100M";
>> + };
>> + };
>> +
>> + cpus {
>> + #address-cells = <0>;
>> + #size-cells = <0>;
>> +
>> + cpu {
>> + compatible = "arm,arm926ej-s";
>> + device_type = "cpu";
>> + };
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + sram-controller@1c00000 {
>> + compatible = "allwinner,sun4i-a10-sram-controller";
>> + reg = <0x01c00000 0x30>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + sram_d: sram@10000 {
>> + compatible = "mmio-sram";
>> + reg = <0x00010000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x00010000 0x1000>;
>> +
>> + otg_sram: sram-section@0 {
>> + compatible = "allwinner,sun4i-a10-sram-d";
>> + reg = <0x0000 0x1000>;
>> + status = "disabled";
>> + };
>> + };
>> + };
>> +
>> + spi0: spi@1c05000 {
>> + compatible = "allwinner,suniv-spi",
>> + "allwinner,sun8i-h3-spi";
>> + reg = <0x01c05000 0x1000>;
>> + interrupts = <10>;
>> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI0>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc0: mmc@1c0f000 {
>> + compatible = "allwinner,sun4i-a10-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>> + clock-names = "ahb", "mmc";
>> + interrupts = <32>;
>> + resets = <&ccu RST_BUS_MMC0>;
>> + reset-names = "ahb";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mmc0_pins>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + ccu: clock@1c20000 {
>> + compatible = "allwinner,suniv-ccu";
>> + reg = <0x01c20000 0x400>;
>> + clocks = <&osc24M>, <&osc32k>;
>> + clock-names = "hosc", "losc";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + intc: interrupt-controller@1c20400 {
>> + compatible = "allwinner,suniv-ic";
>> + reg = <0x01c20400 0x400>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + pio: pinctrl@1c20800 {
>> + compatible = "allwinner,suniv-pinctrl";
>> + reg = <0x01c20800 0x400>;
>> + interrupts = <38>, <39>, <40>;
>> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
>> + clock-names = "apb", "hosc", "losc";
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + #gpio-cells = <3>;
>> +
>> + spi0_pins_a: spi0-pins-pc {
>> + pins = "PC0", "PC1", "PC2", "PC3";
>> + function = "spi0";
>> + };
>> +
>> + uart0_pins_a: uart-pins-pe {
>> + pins = "PE0", "PE1";
>> + function = "uart0";
>> + };
>> +
>> + mmc0_pins: mmc0-pins {
>> + pins = "PF0", "PF1", "PF2",
>> + "PF3", "PF4", "PF5";
>> + function = "mmc0";
>> + drive-strength = <30>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + timer@1c20c00 {
>> + compatible = "allwinner,sun4i-a10-timer";
>> + reg = <0x01c20c00 0x90>;
>> + interrupts = <13>;
>> + clocks = <&osc24M>;
>> + };
>> +
>> + wdt: watchdog@1c20ca0 {
>> + compatible = "allwinner,sun6i-a31-wdt";
>> + reg = <0x01c20ca0 0x20>;
>> + };
>> +
>> + uart0: serial@1c25000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c25000 0x400>;
>> + interrupts = <1>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&ccu CLK_BUS_UART0>;
>> + resets = <&ccu RST_BUS_UART0>;
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@1c25400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c25400 0x400>;
>> + interrupts = <2>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&ccu CLK_BUS_UART1>;
>> + resets = <&ccu RST_BUS_UART1>;
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@1c25800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c25800 0x400>;
>> + interrupts = <3>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&ccu CLK_BUS_UART2>;
>> + resets = <&ccu RST_BUS_UART2>;
>> + status = "disabled";
>> + };
>> +
>> + usb_otg: usb@1c13000 {
>> + compatible = "allwinner,suniv-musb";
>> + reg = <0x01c13000 0x0400>;
>> + clocks = <&ccu CLK_BUS_OTG>;
>> + resets = <&ccu RST_BUS_OTG>;
>> + interrupts = <26>;
>> + interrupt-names = "mc";
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + extcon = <&usbphy 0>;
>> + allwinner,sram = <&otg_sram 1>;
>> + status = "disabled";
>> + };
>> +
>> + usbphy: phy@1c13400 {
>> + compatible = "allwinner,suniv-usb-phy";
>> + reg = <0x01c13400 0x10>;
>> + reg-names = "phy_ctrl";
>> + clocks = <&ccu CLK_USB_PHY0>;
>> + clock-names = "usb0_phy";
>> + resets = <&ccu RST_USB_PHY0>;
>> + reset-names = "usb0_reset";
>> + #phy-cells = <1>;
>> + status = "disabled";
>> + };
>> + };
>> +};
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 11/11] configs: sunxi: Add support for Lichee Pi Nano
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
` (9 preceding siblings ...)
2022-01-05 0:35 ` [PATCH 10/11] ARM: dts: suniv: Add device tree files for F1C100s Jesse Taube
@ 2022-01-05 0:35 ` Jesse Taube
2022-01-26 14:13 ` Andre Przywara
2022-01-05 11:36 ` [PATCH 00/11] Add support for SUNIV and F1C100s Icenowy Zheng
11 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 0:35 UTC (permalink / raw)
To: u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, icenowy, marek.behun,
festevam, narmstrong, tharvey, christianshewitt, pbrobinson,
lokeshvutla, jernej.skrabec, hs, samuel, arnaud.ferraris,
giulio.benetti, Mr.Bossman075, thirtythreeforty
From: Icenowy Zheng <icenowy@aosc.io>
The Lichee Pi Nano is a board based on the F1C100s.
Add defconfigs for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
configs/licheepi_nano_defconfig | 13 ++++++++++++
configs/licheepi_nano_spiflash_defconfig | 25 ++++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 configs/licheepi_nano_defconfig
create mode 100644 configs/licheepi_nano_spiflash_defconfig
diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig
new file mode 100644
index 0000000000..3a24870aaf
--- /dev/null
+++ b/configs/licheepi_nano_defconfig
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUNIV=y
+CONFIG_SYS_TEXT_BASE=0x81700000
+CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_SYS_MALLOC_LEN=0x120000
+CONFIG_DRAM_CLK=156
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_DRAM_ZQ=0
+# CONFIG_VIDEO_SUNXI is not set
+CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
+CONFIG_SPL=y
+# CONFIG_SPL_DM_SERIAL is not set
diff --git a/configs/licheepi_nano_spiflash_defconfig b/configs/licheepi_nano_spiflash_defconfig
new file mode 100644
index 0000000000..07b6a27dbe
--- /dev/null
+++ b/configs/licheepi_nano_spiflash_defconfig
@@ -0,0 +1,25 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ENV_SIZE=0x8000
+CONFIG_ENV_OFFSET=0xf8000
+CONFIG_MACH_SUNIV=y
+CONFIG_DRAM_CLK=156
+CONFIG_DRAM_ZQ=0
+# CONFIG_VIDEO_SUNXI is not set
+CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
+CONFIG_SPL=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPL_SPI_SUNXI=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_DM_SPI=y
+CONFIG_SUN6I_SPI=y
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 11/11] configs: sunxi: Add support for Lichee Pi Nano
2022-01-05 0:35 ` [PATCH 11/11] configs: sunxi: Add support for Lichee Pi Nano Jesse Taube
@ 2022-01-26 14:13 ` Andre Przywara
2022-01-26 14:48 ` Jesse Taube
0 siblings, 1 reply; 43+ messages in thread
From: Andre Przywara @ 2022-01-26 14:13 UTC (permalink / raw)
To: Jesse Taube
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
On Tue, 4 Jan 2022 19:35:08 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi,
> From: Icenowy Zheng <icenowy@aosc.io>
>
> The Lichee Pi Nano is a board based on the F1C100s.
> Add defconfigs for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> configs/licheepi_nano_defconfig | 13 ++++++++++++
> configs/licheepi_nano_spiflash_defconfig | 25 ++++++++++++++++++++++++
> 2 files changed, 38 insertions(+)
> create mode 100644 configs/licheepi_nano_defconfig
> create mode 100644 configs/licheepi_nano_spiflash_defconfig
>
> diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig
> new file mode 100644
> index 0000000000..3a24870aaf
> --- /dev/null
> +++ b/configs/licheepi_nano_defconfig
> @@ -0,0 +1,13 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SUNXI=y
> +CONFIG_MACH_SUNIV=y
> +CONFIG_SYS_TEXT_BASE=0x81700000
This belongs into boot/Kconfig, where we set the values for the other SoCs.
Please reorder them on the way, Kconfig goes with the first match, so we
should have a "default 0x4a000000 if ARCH_SUNXI" line at the end, and the
special snowflakes first. No need for && ARCH_SUNXI, MACH_SUNxxx is always
a subset of that.
> +CONFIG_SYS_LOAD_ADDR=0x81000000
This should be set in /Kconfig, as for the other SoCs.
> +CONFIG_SYS_MALLOC_LEN=0x120000
Same here, in /Kconfig, and reordering to simplify the expressions.
> +CONFIG_DRAM_CLK=156
> +CONFIG_SYS_DCACHE_OFF=y
Mmh, why is this?
> +CONFIG_DRAM_ZQ=0
> +# CONFIG_VIDEO_SUNXI is not set
> +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
> +CONFIG_SPL=y
> +# CONFIG_SPL_DM_SERIAL is not set
That should not be needed?
> diff --git a/configs/licheepi_nano_spiflash_defconfig b/configs/licheepi_nano_spiflash_defconfig
> new file mode 100644
> index 0000000000..07b6a27dbe
> --- /dev/null
> +++ b/configs/licheepi_nano_spiflash_defconfig
I dislike the idea of providing separate defconfigs for those board
variants. We have other examples where a SPI flash chip is not always
populated, but that should go well with one defconfig. If there is no SPI
flash, the code will see that and bail out gracefully, no problems with
that.
So there should be one defconfig, including SPI flash support. I'd suggest
to drop that for now, as the current series does not cover this, AFAICT.
We can add this later, which should be simpler with my SPI fix series.
Cheers,
Andre
> @@ -0,0 +1,25 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SUNXI=y
> +CONFIG_ENV_SIZE=0x8000
> +CONFIG_ENV_OFFSET=0xf8000
> +CONFIG_MACH_SUNIV=y
> +CONFIG_DRAM_CLK=156
> +CONFIG_DRAM_ZQ=0
> +# CONFIG_VIDEO_SUNXI is not set
> +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
> +CONFIG_SPL=y
> +# CONFIG_CMD_FLASH is not set
> +# CONFIG_CMD_FPGA is not set
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_SPL_SPI_SUNXI=y
> +# CONFIG_SPL_DM_SERIAL is not set
> +CONFIG_DM_SPI=y
> +CONFIG_SUN6I_SPI=y
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 11/11] configs: sunxi: Add support for Lichee Pi Nano
2022-01-26 14:13 ` Andre Przywara
@ 2022-01-26 14:48 ` Jesse Taube
0 siblings, 0 replies; 43+ messages in thread
From: Jesse Taube @ 2022-01-26 14:48 UTC (permalink / raw)
To: Andre Przywara
Cc: u-boot, jagan, hdegoede, sjg, icenowy, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
On 1/26/22 09:13, Andre Przywara wrote:
> On Tue, 4 Jan 2022 19:35:08 -0500
> Jesse Taube <mr.bossman075@gmail.com> wrote:
>
> Hi,
>
>> From: Icenowy Zheng <icenowy@aosc.io>
>>
>> The Lichee Pi Nano is a board based on the F1C100s.
>> Add defconfigs for it.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>> ---
>> configs/licheepi_nano_defconfig | 13 ++++++++++++
>> configs/licheepi_nano_spiflash_defconfig | 25 ++++++++++++++++++++++++
>> 2 files changed, 38 insertions(+)
>> create mode 100644 configs/licheepi_nano_defconfig
>> create mode 100644 configs/licheepi_nano_spiflash_defconfig
>>
>> diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig
>> new file mode 100644
>> index 0000000000..3a24870aaf
>> --- /dev/null
>> +++ b/configs/licheepi_nano_defconfig
>> @@ -0,0 +1,13 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_SUNXI=y
>> +CONFIG_MACH_SUNIV=y
>> +CONFIG_SYS_TEXT_BASE=0x81700000
>
> This belongs into boot/Kconfig, where we set the values for the other SoCs.
> Please reorder them on the way, Kconfig goes with the first match, so we
> should have a "default 0x4a000000 if ARCH_SUNXI" line at the end, and the
> special snowflakes first. No need for && ARCH_SUNXI, MACH_SUNxxx is always
> a subet of that.
hmm this is new to me, i will change it.
>> +CONFIG_SYS_LOAD_ADDR=0x81000000
>
> This should be set in /Kconfig, as for the other SoCs.
>
>> +CONFIG_SYS_MALLOC_LEN=0x120000
>
> Same here, in /Kconfig, and reordering to simplify the expressions.
>
>> +CONFIG_DRAM_CLK=156
>> +CONFIG_SYS_DCACHE_OFF=y
>
> Mmh, why is this?
doesn't boot when `enable_caches` gets called in mach-sunxi/board.c.
>
>> +CONFIG_DRAM_ZQ=0
>> +# CONFIG_VIDEO_SUNXI is not set
>> +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
>> +CONFIG_SPL=y
>> +# CONFIG_SPL_DM_SERIAL is not set
>
> That should not be needed?
Yup DM_SPL isnt set, ill remove it.
>> diff --git a/configs/licheepi_nano_spiflash_defconfig b/configs/licheepi_nano_spiflash_defconfig
>> new file mode 100644
>> index 0000000000..07b6a27dbe
>> --- /dev/null
>> +++ b/configs/licheepi_nano_spiflash_defconfig
>
> I dislike the idea of providing separate defconfigs for those board
> variants. We have other examples where a SPI flash chip is not always
> populated, but that should go well with one defconfig. If there is no SPI
> flash, the code will see that and bail out gracefully, no problems with
> that.
Yes i already fixed.
> So there should be one defconfig, including SPI flash support. I'd suggest
> to drop that for now, as the current series does not cover this, AFAICT.
> We can add this later, which should be simpler with my SPI fix series.
>
> Cheers,
> Andre
>
>> @@ -0,0 +1,25 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_SUNXI=y
>> +CONFIG_ENV_SIZE=0x8000
>> +CONFIG_ENV_OFFSET=0xf8000
>> +CONFIG_MACH_SUNIV=y
>> +CONFIG_DRAM_CLK=156
>> +CONFIG_DRAM_ZQ=0
>> +# CONFIG_VIDEO_SUNXI is not set
>> +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
>> +CONFIG_SPL=y
>> +# CONFIG_CMD_FLASH is not set
>> +# CONFIG_CMD_FPGA is not set
>> +CONFIG_CMD_SF=y
>> +CONFIG_CMD_SPI=y
>> +CONFIG_ENV_IS_IN_SPI_FLASH=y
>> +CONFIG_DM_SPI_FLASH=y
>> +CONFIG_SPI_FLASH=y
>> +CONFIG_SPI_FLASH_BAR=y
>> +CONFIG_SPI_FLASH_GIGADEVICE=y
>> +CONFIG_SPI_FLASH_MACRONIX=y
>> +CONFIG_SPI_FLASH_WINBOND=y
>> +CONFIG_SPL_SPI_SUNXI=y
>> +# CONFIG_SPL_DM_SERIAL is not set
>> +CONFIG_DM_SPI=y
>> +CONFIG_SUN6I_SPI=y
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 00/11] Add support for SUNIV and F1C100s.
2022-01-05 0:34 [PATCH 00/11] Add support for SUNIV and F1C100s Jesse Taube
` (10 preceding siblings ...)
2022-01-05 0:35 ` [PATCH 11/11] configs: sunxi: Add support for Lichee Pi Nano Jesse Taube
@ 2022-01-05 11:36 ` Icenowy Zheng
2022-01-05 12:14 ` Andre Przywara
11 siblings, 1 reply; 43+ messages in thread
From: Icenowy Zheng @ 2022-01-05 11:36 UTC (permalink / raw)
To: Jesse Taube, u-boot
Cc: jagan, andre.przywara, hdegoede, sjg, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
在 2022-01-04星期二的 19:34 -0500，Jesse Taube写道：
> This patch set aims to add suport for the SUNIV and F1C100s.
> Suport has been in linux for a while now, but not in u-boot.
>
> This patchset contains:
> - CPU specific initialization code
> - SUNIV dram driver
> - SUNIV clock driver adaption
> - SUNIV gpio driver adaption
> - SUNIV uart driver adaption
> - F1C100s basic support
>
> I am hoping to get Icenowy's patches in as it seems she hasnt
> submitted
> in a while. The only edits I made to her code is rebasing it against
> ML
> and changing some formating. I also re-grouped her commits.
I got too lazy to send it (because I think F1C100s is just too weak)...
>
> I am wondering if the dram driver should be moved into device drivers
> rather than in mach-sunxi.
> I am also wondering if it is okay to submit some one elses code,
> and if so how should I do so.
As you are keeping my SoB and adding yours, it's totally okay.
Thanks for cleaning up these patches! ;-)
>
> Icenowy Zheng (11):
> arm: arm926ej-s: start.S: port save_boot_params support from armv7
> code
> arm: arm926ej-s: add sunxi code
> dt-bindings: clock: Add initial suniv headers
> dt-bindings: reset: Add initial suniv headers
> ARM: sunxi: Add support for F1C100s
> sunxi: Add F1C100s DRAM initial support
> sunxi: board: Add support for SUNIV
> configs: sunxi: Add common SUNIV header
> sunxi: Add support for SUNIV architecture
> ARM: dts: suniv: Add device tree files for F1C100s
> configs: sunxi: Add support for Lichee Pi Nano
>
> arch/arm/cpu/arm926ejs/Makefile | 1 +
> arch/arm/cpu/arm926ejs/start.S | 19 +
> arch/arm/cpu/arm926ejs/sunxi/Makefile | 15 +
> arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 +
> arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 37 ++
> arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S | 67 +++
> arch/arm/cpu/arm926ejs/sunxi/start.c | 1 +
> arch/arm/cpu/arm926ejs/sunxi/timer.c | 114 +++++
> arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 62 +++
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 64 +++
> arch/arm/dts/suniv-f1c100s.dtsi | 6 +
> arch/arm/dts/suniv.dtsi | 224 ++++++++++
> arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 25 ++
> arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 +
> arch/arm/include/asm/arch-sunxi/dram.h | 2 +
> arch/arm/include/asm/arch-sunxi/dram_suniv.h | 46 ++
> arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
> arch/arm/mach-sunxi/Kconfig | 16 +-
> arch/arm/mach-sunxi/Makefile | 2 +
> arch/arm/mach-sunxi/board.c | 31 +-
> arch/arm/mach-sunxi/clock.c | 3 +-
> arch/arm/mach-sunxi/clock_sun6i.c | 46 +-
> arch/arm/mach-sunxi/cpu_info.c | 2 +
> arch/arm/mach-sunxi/dram_helpers.c | 4 +
> arch/arm/mach-sunxi/dram_suniv.c | 420
> ++++++++++++++++++
> board/sunxi/board.c | 4 +-
> configs/licheepi_nano_defconfig | 13 +
> configs/licheepi_nano_spiflash_defconfig | 25 ++
> include/configs/suniv.h | 14 +
> include/configs/sunxi-common.h | 67 ++-
> include/dt-bindings/clock/suniv-ccu.h | 68 +++
> include/dt-bindings/reset/suniv-ccu.h | 36 ++
> 34 files changed, 1424 insertions(+), 29 deletions(-)
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/start.c
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/timer.c
> create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
> create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi
> create mode 100644 arch/arm/dts/suniv.dtsi
> create mode 100644 arch/arm/include/asm/arch-sunxi/dram_suniv.h
> create mode 100644 arch/arm/mach-sunxi/dram_suniv.c
> create mode 100644 configs/licheepi_nano_defconfig
> create mode 100644 configs/licheepi_nano_spiflash_defconfig
> create mode 100644 include/configs/suniv.h
> create mode 100644 include/dt-bindings/clock/suniv-ccu.h
> create mode 100644 include/dt-bindings/reset/suniv-ccu.h
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 00/11] Add support for SUNIV and F1C100s.
2022-01-05 11:36 ` [PATCH 00/11] Add support for SUNIV and F1C100s Icenowy Zheng
@ 2022-01-05 12:14 ` Andre Przywara
2022-01-05 12:54 ` Jesse Taube
0 siblings, 1 reply; 43+ messages in thread
From: Andre Przywara @ 2022-01-05 12:14 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Jesse Taube, u-boot, jagan, hdegoede, sjg, marek.behun, festevam,
narmstrong, tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
On Wed, 05 Jan 2022 19:36:29 +0800
Icenowy Zheng <icenowy@aosc.io> wrote:
Hi Jesse,
> 在 2022-01-04星期二的 19:34 -0500，Jesse Taube写道：
> > This patch set aims to add suport for the SUNIV and F1C100s.
> > Suport has been in linux for a while now, but not in u-boot.
> >
> > This patchset contains:
> > - CPU specific initialization code
> > - SUNIV dram driver
> > - SUNIV clock driver adaption
> > - SUNIV gpio driver adaption
> > - SUNIV uart driver adaption
> > - F1C100s basic support
> >
> > I am hoping to get Icenowy's patches in as it seems she hasnt
> > submitted
> > in a while. The only edits I made to her code is rebasing it against
> > ML
> > and changing some formating. I also re-grouped her commits.
>
> I got too lazy to send it (because I think F1C100s is just too weak)...
>
> >
> > I am wondering if the dram driver should be moved into device drivers
> > rather than in mach-sunxi.
> > I am also wondering if it is okay to submit some one elses code,
> > and if so how should I do so.
>
> As you are keeping my SoB and adding yours, it's totally okay.
Thanks Icenowy for confirming!
Jesse: yes, it's perfectly fine to send patches from someone else, as
long as you keep the authorship, their SoB, and add your's.
Typical reasons are lack of time or interest from the original author.
But it's customary to ask the author first, and care should be taken
when changing patches, as this might not be in the interest of the
original author (and they are the ones who will get blamed for bugs).
Also please mark the series either as a Resend or as a v2.
So with Icenowy's confirmation above I consider this fine.
But what was actually holding back this series was lack of review,
testing and/or interest. Similar to Icenowy my personal interest in
crufty old cores is somewhat limited, so this wasn't very high on my
priority list.
So given that there is apparently some interest now:
Can you confirm that you have reviewed the series, or at least tested
this? I would be interested to know if a second pair of eyes had a
look, and to what extent. I don't have any hardware, so would need to
rely on others to make sure this code is somewhat sane.
And it basically looks like a v2 of Icenowy's series, so can you give a
Changelog of the differences? I skimmed over her original series back
then, so I would be interested in what makes this version special.
Cheers,
Andre
> Thanks for cleaning up these patches! ;-)
>
> >
> > Icenowy Zheng (11):
> > arm: arm926ej-s: start.S: port save_boot_params support from armv7
> > code
> > arm: arm926ej-s: add sunxi code
> > dt-bindings: clock: Add initial suniv headers
> > dt-bindings: reset: Add initial suniv headers
> > ARM: sunxi: Add support for F1C100s
> > sunxi: Add F1C100s DRAM initial support
> > sunxi: board: Add support for SUNIV
> > configs: sunxi: Add common SUNIV header
> > sunxi: Add support for SUNIV architecture
> > ARM: dts: suniv: Add device tree files for F1C100s
> > configs: sunxi: Add support for Lichee Pi Nano
> >
> > arch/arm/cpu/arm926ejs/Makefile | 1 +
> > arch/arm/cpu/arm926ejs/start.S | 19 +
> > arch/arm/cpu/arm926ejs/sunxi/Makefile | 15 +
> > arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 +
> > arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 37 ++
> > arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S | 67 +++
> > arch/arm/cpu/arm926ejs/sunxi/start.c | 1 +
> > arch/arm/cpu/arm926ejs/sunxi/timer.c | 114 +++++
> > arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 62 +++
> > arch/arm/dts/Makefile | 2 +
> > arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 64 +++
> > arch/arm/dts/suniv-f1c100s.dtsi | 6 +
> > arch/arm/dts/suniv.dtsi | 224 ++++++++++
> > arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
> > arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 25 ++
> > arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 +
> > arch/arm/include/asm/arch-sunxi/dram.h | 2 +
> > arch/arm/include/asm/arch-sunxi/dram_suniv.h | 46 ++
> > arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
> > arch/arm/mach-sunxi/Kconfig | 16 +-
> > arch/arm/mach-sunxi/Makefile | 2 +
> > arch/arm/mach-sunxi/board.c | 31 +-
> > arch/arm/mach-sunxi/clock.c | 3 +-
> > arch/arm/mach-sunxi/clock_sun6i.c | 46 +-
> > arch/arm/mach-sunxi/cpu_info.c | 2 +
> > arch/arm/mach-sunxi/dram_helpers.c | 4 +
> > arch/arm/mach-sunxi/dram_suniv.c | 420
> > ++++++++++++++++++
> > board/sunxi/board.c | 4 +-
> > configs/licheepi_nano_defconfig | 13 +
> > configs/licheepi_nano_spiflash_defconfig | 25 ++
> > include/configs/suniv.h | 14 +
> > include/configs/sunxi-common.h | 67 ++-
> > include/dt-bindings/clock/suniv-ccu.h | 68 +++
> > include/dt-bindings/reset/suniv-ccu.h | 36 ++
> > 34 files changed, 1424 insertions(+), 29 deletions(-)
> > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile
> > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk
> > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
> > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S
> > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/start.c
> > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/timer.c
> > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
> > create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> > create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi
> > create mode 100644 arch/arm/dts/suniv.dtsi
> > create mode 100644 arch/arm/include/asm/arch-sunxi/dram_suniv.h
> > create mode 100644 arch/arm/mach-sunxi/dram_suniv.c
> > create mode 100644 configs/licheepi_nano_defconfig
> > create mode 100644 configs/licheepi_nano_spiflash_defconfig
> > create mode 100644 include/configs/suniv.h
> > create mode 100644 include/dt-bindings/clock/suniv-ccu.h
> > create mode 100644 include/dt-bindings/reset/suniv-ccu.h
> >
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 00/11] Add support for SUNIV and F1C100s.
2022-01-05 12:14 ` Andre Przywara
@ 2022-01-05 12:54 ` Jesse Taube
2022-01-05 16:00 ` Giulio Benetti
0 siblings, 1 reply; 43+ messages in thread
From: Jesse Taube @ 2022-01-05 12:54 UTC (permalink / raw)
To: Andre Przywara, Icenowy Zheng
Cc: u-boot, jagan, hdegoede, sjg, marek.behun, festevam, narmstrong,
tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, giulio.benetti,
thirtythreeforty
On 1/5/22 07:14, Andre Przywara wrote:
> On Wed, 05 Jan 2022 19:36:29 +0800
> Icenowy Zheng <icenowy@aosc.io> wrote:
>
> Hi Jesse,
>
>> 在 2022-01-04星期二的 19:34 -0500，Jesse Taube写道：
>>> This patch set aims to add suport for the SUNIV and F1C100s.
>>> Suport has been in linux for a while now, but not in u-boot.
>>>
>>> This patchset contains:
>>> - CPU specific initialization code
>>> - SUNIV dram driver
>>> - SUNIV clock driver adaption
>>> - SUNIV gpio driver adaption
>>> - SUNIV uart driver adaption
>>> - F1C100s basic support
>>>
>>> I am hoping to get Icenowy's patches in as it seems she hasnt
>>> submitted
>>> in a while. The only edits I made to her code is rebasing it against
>>> ML
>>> and changing some formating. I also re-grouped her commits.
>>
>> I got too lazy to send it (because I think F1C100s is just too weak)...
>>
>>>
>>> I am wondering if the dram driver should be moved into device drivers
>>> rather than in mach-sunxi.
>>> I am also wondering if it is okay to submit some one elses code,
>>> and if so how should I do so.
>>
>> As you are keeping my SoB and adding yours, it's totally okay.
>
> Thanks Icenowy for confirming!
>
> Jesse: yes, it's perfectly fine to send patches from someone else, as
> long as you keep the authorship, their SoB, and add your's.
> Typical reasons are lack of time or interest from the original author.
>
> But it's customary to ask the author first
I did but it must have gotten lost in the cosmos.
, and care should be taken
> when changing patches, as this might not be in the interest of the
> original author (and they are the ones who will get blamed for bugs).
> Also please mark the series either as a Resend or as a v2.
>
> So with Icenowy's confirmation above I consider this fine.
>
> But what was actually holding back this series was lack of review,
> testing and/or interest.
Well the price of the SOC has gained it some popularity, aswell as a
couple forum posts.
> Similar to Icenowy my personal interest in
> crufty old cores is somewhat limited, so this wasn't very high on my
> priority list.
It is very slow but its a good challenge.
>
> So given that there is apparently some interest now:
> Can you confirm that you have reviewed the series, or at least tested
> this?
I have tested this yes.
I would be interested to know if a second pair of eyes had a
> look, and to what extent.
I'm Sending giulio.benetti@ some boards I made he will also test. I'm
sure many other people will be willing to test aswell.
> I don't have any hardware, so would need to
> rely on others to make sure this code is somewhat sane.
I can send you one of my many boards :)
> And it basically looks like a v2 of Icenowy's series, so can you give a
> Changelog of the differences? I skimmed over her original series back
> then, so I would be interested in what makes this version special.
It passes checkpatch on the latest.
>
> Cheers,
> Andre
>
>> Thanks for cleaning up these patches! ;-)
NP!
I took https://github.com/Lichee-Pi/u-boot/tree/nano-v2018.01
re-based it against mainline and fixed formatting in a few files.
I also removed the spi-flash driver as it was causing issues and we can
boot from sdcard for now. there are some things I did to make the old
code compatible with new code but mostly preprocessor and configs.
For the dram driver I had to change a bit but none of the logic, i am
worried that i may have to move it to /drivers.
Do you want a more comprehensive list of changes?
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 00/11] Add support for SUNIV and F1C100s.
2022-01-05 12:54 ` Jesse Taube
@ 2022-01-05 16:00 ` Giulio Benetti
0 siblings, 0 replies; 43+ messages in thread
From: Giulio Benetti @ 2022-01-05 16:00 UTC (permalink / raw)
To: Jesse Taube, Andre Przywara, Icenowy Zheng
Cc: u-boot, jagan, hdegoede, sjg, marek.behun, festevam, narmstrong,
tharvey, christianshewitt, pbrobinson, lokeshvutla,
jernej.skrabec, hs, samuel, arnaud.ferraris, thirtythreeforty
Hi All,
On 05/01/22 13:54, Jesse Taube wrote:
>
>
> On 1/5/22 07:14, Andre Przywara wrote:
>> On Wed, 05 Jan 2022 19:36:29 +0800
>> Icenowy Zheng <icenowy@aosc.io> wrote:
>>
>> Hi Jesse,
>>
>>> 在 2022-01-04星期二的 19:34 -0500，Jesse Taube写道：
>>>> This patch set aims to add suport for the SUNIV and F1C100s.
>>>> Suport has been in linux for a while now, but not in u-boot.
>>>>
>>>> This patchset contains:
>>>> - CPU specific initialization code
>>>> - SUNIV dram driver
>>>> - SUNIV clock driver adaption
>>>> - SUNIV gpio driver adaption
>>>> - SUNIV uart driver adaption
>>>> - F1C100s basic support
>>>>
>>>> I am hoping to get Icenowy's patches in as it seems she hasnt
>>>> submitted
>>>> in a while. The only edits I made to her code is rebasing it against
>>>> ML
>>>> and changing some formating. I also re-grouped her commits.
>>>
>>> I got too lazy to send it (because I think F1C100s is just too weak)...
>>>
>>>>
>>>> I am wondering if the dram driver should be moved into device drivers
>>>> rather than in mach-sunxi.
>>>> I am also wondering if it is okay to submit some one elses code,
>>>> and if so how should I do so.
>>>
>>> As you are keeping my SoB and adding yours, it's totally okay.
>>
>> Thanks Icenowy for confirming!
>>
>> Jesse: yes, it's perfectly fine to send patches from someone else, as
>> long as you keep the authorship, their SoB, and add your's.
>> Typical reasons are lack of time or interest from the original author.
>>
>> But it's customary to ask the author first
> I did but it must have gotten lost in the cosmos.
> , and care should be taken
>> when changing patches, as this might not be in the interest of the
>> original author (and they are the ones who will get blamed for bugs).
>> Also please mark the series either as a Resend or as a v2.
>>
>> So with Icenowy's confirmation above I consider this fine.
>>
>> But what was actually holding back this series was lack of review,
>> testing and/or interest.
> Well the price of the SOC has gained it some popularity, aswell as a
> couple forum posts.
>> Similar to Icenowy my personal interest in
>> crufty old cores is somewhat limited, so this wasn't very high on my
>> priority list.
> It is very slow but its a good challenge.
Slow depending on application :-)
Two of my customers would like to use it in Q2/Q3 for very low-end HMIs.
And as I see, one of the last F1Cxxx is F1C800s released in 2017. Here
the good thing they have is ram onboard.
>>
>> So given that there is apparently some interest now:
>> Can you confirm that you have reviewed the series, or at least tested
>> this?
> I have tested this yes.
> I would be interested to know if a second pair of eyes had a
>> look, and to what extent.
> I'm Sending giulio.benetti@ some boards I made he will also test. I'm
> sure many other people will be willing to test aswell.
Yes, I'll test on Jesse's board and on Lichee-pi-nano too when I have
time, this way I'll be able to give a Tested-by: me.
Best regards
--
Giulio Benetti
Benetti Engineering sas
>> I don't have any hardware, so would need to
>> rely on others to make sure this code is somewhat sane.
> I can send you one of my many boards :)
>> And it basically looks like a v2 of Icenowy's series, so can you give a
>> Changelog of the differences? I skimmed over her original series back
>> then, so I would be interested in what makes this version special.
> It passes checkpatch on the latest.
>>
>> Cheers,
>> Andre
>>
>>> Thanks for cleaning up these patches! ;-)
> NP!
>
> I took https://github.com/Lichee-Pi/u-boot/tree/nano-v2018.01
> re-based it against mainline and fixed formatting in a few files.
> I also removed the spi-flash driver as it was causing issues and we can
> boot from sdcard for now. there are some things I did to make the old
> code compatible with new code but mostly preprocessor and configs.
>
> For the dram driver I had to change a bit but none of the logic, i am
> worried that i may have to move it to /drivers.
>
> Do you want a more comprehensive list of changes?
>
^ permalink raw reply [flat|nested] 43+ messages in thread