From: Jingyi Wang <wangjingyi11@huawei.com> To: Auger Eric <eric.auger@redhat.com>, Marc Zyngier <maz@kernel.org> Cc: <drjones@redhat.com>, <kvm@vger.kernel.org>, <kvmarm@lists.cs.columbia.edu>, <wanghaibin.wang@huawei.com>, <yuzenghui@huawei.com> Subject: Re: [kvm-unit-tests PATCH v2 3/8] arm64: microbench: gic: Add gicv4.1 support for ipi latency test. Date: Fri, 3 Jul 2020 11:39:10 +0800 [thread overview] Message-ID: <2a50fc3a-c3d1-0fc9-dccc-d878ce0a7bb5@huawei.com> (raw) In-Reply-To: <69a37427-7e93-3411-f61c-50525a0ca3e1@redhat.com> On 7/2/2020 9:42 PM, Auger Eric wrote: > Hi Marc, > > On 7/2/20 3:08 PM, Marc Zyngier wrote: >> Hi Eric, >> >> On 2020-07-02 13:57, Auger Eric wrote: >>> Hi Jingyi, >>> >>> On 7/2/20 5:01 AM, Jingyi Wang wrote: >>>> If gicv4.1(sgi hardware injection) supported, we test ipi injection >>>> via hw/sw way separately. >>>> >>>> Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com> >>>> --- >>>> arm/micro-bench.c | 45 +++++++++++++++++++++++++++++++++++++++----- >>>> lib/arm/asm/gic-v3.h | 3 +++ >>>> lib/arm/asm/gic.h | 1 + >>>> 3 files changed, 44 insertions(+), 5 deletions(-) >>>> >>>> diff --git a/arm/micro-bench.c b/arm/micro-bench.c >>>> index fc4d356..80d8db3 100644 >>>> --- a/arm/micro-bench.c >>>> +++ b/arm/micro-bench.c >>>> @@ -91,9 +91,40 @@ static void gic_prep_common(void) >>>> assert(irq_ready); >>>> } >>>> >>>> -static void ipi_prep(void) >>>> +static bool ipi_prep(void) >>> Any reason why the bool returned value is preferred over the standard >>> int? >>>> { >>>> + u32 val; >>>> + >>>> + val = readl(vgic_dist_base + GICD_CTLR); >>>> + if (readl(vgic_dist_base + GICD_TYPER2) & GICD_TYPER2_nASSGIcap) { >>>> + val &= ~GICD_CTLR_ENABLE_G1A; >>>> + val &= ~GICD_CTLR_nASSGIreq; >>>> + writel(val, vgic_dist_base + GICD_CTLR); >>>> + val |= GICD_CTLR_ENABLE_G1A; >>>> + writel(val, vgic_dist_base + GICD_CTLR); >>> Why do we need this G1A dance? >> >> Because it isn't legal to change the SGI behaviour when groups are enabled. >> Yes, it is described in this bit of documentation nobody has access to. > > OK thank you for the explanation. Jingyi, maybe add a comment to avoid > the question again ;-) > > Thanks > > Eric Okay, I will add a comment here in the next version. Thanks, Jingyi >> >> And this code needs to track RWP on disabling Group-1. >> >> M. > > > . >
WARNING: multiple messages have this Message-ID (diff)
From: Jingyi Wang <wangjingyi11@huawei.com> To: Auger Eric <eric.auger@redhat.com>, Marc Zyngier <maz@kernel.org> Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: Re: [kvm-unit-tests PATCH v2 3/8] arm64: microbench: gic: Add gicv4.1 support for ipi latency test. Date: Fri, 3 Jul 2020 11:39:10 +0800 [thread overview] Message-ID: <2a50fc3a-c3d1-0fc9-dccc-d878ce0a7bb5@huawei.com> (raw) In-Reply-To: <69a37427-7e93-3411-f61c-50525a0ca3e1@redhat.com> On 7/2/2020 9:42 PM, Auger Eric wrote: > Hi Marc, > > On 7/2/20 3:08 PM, Marc Zyngier wrote: >> Hi Eric, >> >> On 2020-07-02 13:57, Auger Eric wrote: >>> Hi Jingyi, >>> >>> On 7/2/20 5:01 AM, Jingyi Wang wrote: >>>> If gicv4.1(sgi hardware injection) supported, we test ipi injection >>>> via hw/sw way separately. >>>> >>>> Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com> >>>> --- >>>> arm/micro-bench.c | 45 +++++++++++++++++++++++++++++++++++++++----- >>>> lib/arm/asm/gic-v3.h | 3 +++ >>>> lib/arm/asm/gic.h | 1 + >>>> 3 files changed, 44 insertions(+), 5 deletions(-) >>>> >>>> diff --git a/arm/micro-bench.c b/arm/micro-bench.c >>>> index fc4d356..80d8db3 100644 >>>> --- a/arm/micro-bench.c >>>> +++ b/arm/micro-bench.c >>>> @@ -91,9 +91,40 @@ static void gic_prep_common(void) >>>> assert(irq_ready); >>>> } >>>> >>>> -static void ipi_prep(void) >>>> +static bool ipi_prep(void) >>> Any reason why the bool returned value is preferred over the standard >>> int? >>>> { >>>> + u32 val; >>>> + >>>> + val = readl(vgic_dist_base + GICD_CTLR); >>>> + if (readl(vgic_dist_base + GICD_TYPER2) & GICD_TYPER2_nASSGIcap) { >>>> + val &= ~GICD_CTLR_ENABLE_G1A; >>>> + val &= ~GICD_CTLR_nASSGIreq; >>>> + writel(val, vgic_dist_base + GICD_CTLR); >>>> + val |= GICD_CTLR_ENABLE_G1A; >>>> + writel(val, vgic_dist_base + GICD_CTLR); >>> Why do we need this G1A dance? >> >> Because it isn't legal to change the SGI behaviour when groups are enabled. >> Yes, it is described in this bit of documentation nobody has access to. > > OK thank you for the explanation. Jingyi, maybe add a comment to avoid > the question again ;-) > > Thanks > > Eric Okay, I will add a comment here in the next version. Thanks, Jingyi >> >> And this code needs to track RWP on disabling Group-1. >> >> M. > > > . > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-07-03 3:39 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-02 3:01 [kvm-unit-tests PATCH v2 0/8] arm/arm64: Add IPI/LPI/vtimer latency test Jingyi Wang 2020-07-02 3:01 ` Jingyi Wang 2020-07-02 3:01 ` [kvm-unit-tests PATCH v2 1/8] arm64: microbench: get correct ipi received num Jingyi Wang 2020-07-02 3:01 ` Jingyi Wang 2020-07-02 12:36 ` Auger Eric 2020-07-02 12:36 ` Auger Eric 2020-07-02 3:01 ` [kvm-unit-tests PATCH v2 2/8] arm64: microbench: Use the funcions for ipi test as the general functions for gic(ipi/lpi/timer) test Jingyi Wang 2020-07-02 3:01 ` Jingyi Wang 2020-07-02 5:25 ` Andrew Jones 2020-07-02 5:25 ` Andrew Jones 2020-07-02 8:21 ` Jingyi Wang 2020-07-02 8:21 ` Jingyi Wang 2020-07-02 12:36 ` Auger Eric 2020-07-02 12:36 ` Auger Eric 2020-07-02 3:01 ` [kvm-unit-tests PATCH v2 3/8] arm64: microbench: gic: Add gicv4.1 support for ipi latency test Jingyi Wang 2020-07-02 3:01 ` Jingyi Wang 2020-07-02 8:22 ` Marc Zyngier 2020-07-02 8:22 ` Marc Zyngier 2020-07-02 9:02 ` Jingyi Wang 2020-07-02 9:02 ` Jingyi Wang 2020-07-02 9:17 ` Marc Zyngier 2020-07-02 9:17 ` Marc Zyngier 2020-07-02 9:29 ` Jingyi Wang 2020-07-02 9:29 ` Jingyi Wang 2020-07-02 12:36 ` Auger Eric 2020-07-02 12:36 ` Auger Eric 2020-07-02 13:03 ` Marc Zyngier 2020-07-02 13:03 ` Marc Zyngier 2020-07-02 12:57 ` Auger Eric 2020-07-02 12:57 ` Auger Eric 2020-07-02 13:08 ` Marc Zyngier 2020-07-02 13:08 ` Marc Zyngier 2020-07-02 13:42 ` Auger Eric 2020-07-02 13:42 ` Auger Eric 2020-07-03 3:39 ` Jingyi Wang [this message] 2020-07-03 3:39 ` Jingyi Wang 2020-07-02 21:33 ` Andrew Jones 2020-07-02 21:33 ` Andrew Jones 2020-07-02 3:01 ` [kvm-unit-tests PATCH v2 4/8] arm64: its: Handle its command queue wrapping Jingyi Wang 2020-07-02 3:01 ` Jingyi Wang 2020-07-02 13:01 ` Auger Eric 2020-07-02 13:01 ` Auger Eric 2020-07-02 3:01 ` [kvm-unit-tests PATCH v2 5/8] arm64: microbench: its: Add LPI latency test Jingyi Wang 2020-07-02 3:01 ` Jingyi Wang 2020-07-02 13:13 ` Auger Eric 2020-07-02 13:13 ` Auger Eric 2020-07-02 3:01 ` [kvm-unit-tests PATCH v2 6/8] arm64: microbench: Allow each test to specify its running times Jingyi Wang 2020-07-02 3:01 ` Jingyi Wang 2020-07-02 5:29 ` Andrew Jones 2020-07-02 5:29 ` Andrew Jones 2020-07-02 8:46 ` Jingyi Wang 2020-07-02 8:46 ` Jingyi Wang 2020-07-02 13:17 ` Auger Eric 2020-07-02 13:17 ` Auger Eric 2020-07-02 3:01 ` [kvm-unit-tests PATCH v2 7/8] arm64: microbench: Add time limit for each individual test Jingyi Wang 2020-07-02 3:01 ` Jingyi Wang 2020-07-02 5:48 ` Andrew Jones 2020-07-02 5:48 ` Andrew Jones 2020-07-02 8:47 ` Jingyi Wang 2020-07-02 8:47 ` Jingyi Wang 2020-07-02 13:23 ` Auger Eric 2020-07-02 13:23 ` Auger Eric 2020-07-03 3:42 ` Jingyi Wang 2020-07-03 3:42 ` Jingyi Wang 2020-07-02 3:01 ` [kvm-unit-tests PATCH v2 8/8] arm64: microbench: Add vtimer latency test Jingyi Wang 2020-07-02 3:01 ` Jingyi Wang 2020-07-02 5:44 ` Andrew Jones 2020-07-02 5:44 ` Andrew Jones 2020-07-02 8:56 ` Jingyi Wang 2020-07-02 8:56 ` Jingyi Wang 2020-07-02 13:36 ` Auger Eric 2020-07-02 13:36 ` Auger Eric 2020-07-03 7:41 ` Jingyi Wang 2020-07-03 7:41 ` Jingyi Wang 2020-07-03 7:45 ` Auger Eric 2020-07-03 7:45 ` Auger Eric 2020-07-06 12:23 ` Jingyi Wang 2020-07-06 12:23 ` Jingyi Wang
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