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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	Paolo Bonzini <pbonzini@redhat.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
	"Richard W.M. Jones" <rjones@redhat.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>,
	Alistair Francis <alistair23@gmail.com>,
	Bin Meng <bmeng.cn@gmail.com>, Guenter Roeck <linux@roeck-us.net>
Subject: Re: [PULL 00/19] riscv-to-apply queue
Date: Fri, 19 Feb 2021 14:31:20 +0100	[thread overview]
Message-ID: <2bd4745b-03f2-220c-619f-2298d99038cc@amsat.org> (raw)
In-Reply-To: <CAFEAcA8BwTO7OT91B=d1tZrk9+PMiSLTmKtiv_Yd2BNdb1syRQ@mail.gmail.com>

Hi Peter,

[+John/Richards/Paolo/Gueunter]

On 2/18/21 3:22 PM, Peter Maydell wrote:
> On Thu, 18 Feb 2021 at 14:07, Bin Meng <bmeng.cn@gmail.com> wrote:
>> On Thu, Feb 18, 2021 at 9:26 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>>> Fails to compile, 32 bit hosts:
>>>
>>> ../../hw/riscv/virt.c: In function 'virt_machine_init':
>>> ../../hw/riscv/virt.c:621:43: error: comparison is always false due to
>>> limited range of data type [-Werror=type-limits]
>>>          if ((uint64_t)(machine->ram_size) > 10 * GiB) {
>>>                                            ^
>>> ../../hw/riscv/virt.c:623:33: error: large integer implicitly
>>> truncated to unsigned type [-Werror=overflow]
>>>              machine->ram_size = 10 * GiB;
>>>                                  ^~
>>
>> This kind of error is tricky. I wonder whether we should deprecate
>> 32-bit host support though.
> 
> 32-bit host is still not uncommon outside the x86 world...
> 
> The thing that makes this particular check awkward is that
> machine->ram_size is a ram_addr_t, whose size is 64 bits if
> either (a) the host is 64 bits or (b) CONFIG_XEN_BACKEND is
> enabled, so it's effectively only 32-bits on 32-bit-not-x86.
> 
> It might be a good idea if we decided that we would just make
> ram_addr_t 64-bits everywhere, to avoid this kind of "we
> have an unusual config only on some more-obscure hosts" issue.
> (We did that for hwaddr back in commit 4be403c8158e1 in 2012,
> when it was still called target_phys_addr_t.) This change
> would probably be a performance hit for 32-bit-non-x86 hosts;
> it would be interesting to see whether it was measurably
> significant.

You once explained me we have 'hwaddr' (physical address)
of 64-bit because we can 64-bit buses on 32-bit targets.
hwaddr is available in all emulation modes.

ram_addr_t is restricted to system emulation. I understand
it as the limit addressable by a CPU.

Back to your comment, we only have 32-bit ram_addr_t on
system-emulation on 32-bit (non-x86) hosts.

Question I asked yesterday on IRC, do you know if there
is still interest in having system-emulation on 32-bit
hosts?

It is important to keep user-mode emulation on 32-bit hosts,
but I doubt there are many uses of system-emulation on them
(even less non non-x86 archs).

Regards,

Phil.


  parent reply	other threads:[~2021-02-19 13:33 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-18  1:59 [PULL 00/19] riscv-to-apply queue Alistair Francis
2021-02-18  1:59 ` [PULL 01/19] target/riscv: Declare csr_ops[] with a known size Alistair Francis
2021-02-18  1:59 ` [PULL 02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails Alistair Francis
2021-02-18  1:59 ` [PULL 03/19] roms/opensbi: Upgrade from v0.8 to v0.9 Alistair Francis
2021-02-18  1:59 ` [PULL 04/19] target-riscv: support QMP dump-guest-memory Alistair Francis
2021-02-18  1:59 ` [PULL 05/19] hw/block: m25p80: Add ISSI SPI flash support Alistair Francis
2021-02-18  1:59 ` [PULL 06/19] hw/block: m25p80: Add various ISSI flash information Alistair Francis
2021-02-18  1:59 ` [PULL 07/19] hw/ssi: Add SiFive SPI controller support Alistair Francis
2021-02-18  1:59 ` [PULL 08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash Alistair Francis
2021-02-18  1:59 ` [PULL 09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card Alistair Francis
2021-02-18  1:59 ` [PULL 10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value Alistair Francis
2021-02-18  1:59 ` [PULL 11/19] docs/system: Sort targets in alphabetical order Alistair Francis
2021-02-18  1:59 ` [PULL 12/19] docs/system: Add RISC-V documentation Alistair Francis
2021-02-18  1:59 ` [PULL 13/19] docs/system: riscv: Add documentation for sifive_u machine Alistair Francis
2021-02-18  1:59 ` [PULL 14/19] goldfish_rtc: re-arm the alarm after migration Alistair Francis
2021-02-18  1:59 ` [PULL 15/19] MAINTAINERS: Add a SiFive machine section Alistair Francis
2021-02-18  1:59 ` [PULL 16/19] hw/riscv: Drop 'struct MemmapEntry' Alistair Francis
2021-02-18  1:59 ` [PULL 17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Alistair Francis
2021-02-18  1:59 ` [PULL 18/19] hw/riscv: virt: Limit RAM size in a 32-bit system Alistair Francis
2021-02-18  1:59 ` [PULL 19/19] hw/riscv: virt: Map high mmio for PCIe Alistair Francis
2021-02-18 13:25 ` [PULL 00/19] riscv-to-apply queue Peter Maydell
2021-02-18 14:07   ` Bin Meng
2021-02-18 14:22     ` Peter Maydell
2021-02-19 12:36       ` Bin Meng
2021-02-19 13:31       ` Philippe Mathieu-Daudé [this message]
2021-02-19 13:40         ` Peter Maydell
2021-02-19 16:12         ` Richard W.M. Jones
2022-07-03  0:09 Alistair Francis
2022-07-03  0:12 ` Alistair Francis

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