From: Richard Henderson <richard.henderson@linaro.org>
To: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
Xiong Yining <xiongyining1480@phytium.com.cn>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: rad@semihalf.com, peter.maydell@linaro.org, quic_llindhol@quicinc.com
Subject: Re: [PATCH v4 1/1] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
Date: Mon, 29 Apr 2024 05:21:55 -0700 [thread overview]
Message-ID: <2deb6299-eca1-4611-8977-73ee2d792b5a@linaro.org> (raw)
In-Reply-To: <559cc23e-f581-4f0d-bf59-94a516d1ef56@linaro.org>
On 4/28/24 23:35, Marcin Juszkiewicz wrote:
> W dniu 26.04.2024 o 18:06, Richard Henderson pisze:
>>
>> Isn't this basically what MPIDR_EL1 is supposed to indicate?
>> We do not yet implement all of that in QEMU, but should.
>
> QEMU has socket/cluster/core/thread model which could map to
> aff3/aff2/aff1/aff0 (or aff0/1/2/3) of MPIDR_EL1 register, right? But it does not.
Yes, I know, but there's patches on list that started to deal with MPIDR.SMT,
https://lore.kernel.org/qemu-devel/20240419183135.12276-1-dorjoychy111@gmail.com/
and I suggested that we go whole hog and support all of the -smp options.
r~
next prev parent reply other threads:[~2024-04-29 12:23 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-26 7:35 [PATCH v4 0/1] ARM Sbsa-ref: Enable CPU cluster topology Xiong Yining
2024-04-26 7:35 ` [PATCH v4 1/1] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine Xiong Yining
2024-04-26 10:59 ` Marcin Juszkiewicz
2024-04-26 16:06 ` Richard Henderson
2024-04-28 2:12 ` xiongyining1480
2024-04-29 6:35 ` Marcin Juszkiewicz
2024-04-29 12:21 ` Richard Henderson [this message]
2024-05-23 18:47 ` Marcin Juszkiewicz
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