[PATCH v3] stmmac: enable rx queues

[PATCH v3] stmmac: enable rx queues

[Joao Pinto]

When the hardware is synthesized with multiple queues, all queues are
disabled for default. This patch adds the rx queues configuration.
This patch was successfully tested in a Synopsys QoS Reference design.

Signed-off-by: Joao Pinto <jpinto@synopsys.com>
---
changes v2 -> v3 (Seraphin Bonnaffe):
- GMAC_RX_QUEUE_CLEAR macro simplified
changes v1 -> v2 (Niklas Cassel and Seraphin Bonnaffe):
- Instead of using number of DMA channels, lets use number of queues
- Create 2 flavors of RX queue enable Macros: AV and DCB (AV by default)
- Make sure that the RX queue related bits are cleared before setting
- Check if rx_queue_enable is available before executing

 drivers/net/ethernet/stmicro/stmmac/common.h      |  5 +++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h      |  8 ++++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 12 ++++++++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c  |  5 +++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 22 ++++++++++++++++++++++
 5 files changed, 52 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index b13a144..6c96291 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -323,6 +323,9 @@ struct dma_features {
 	/* TX and RX number of channels */
 	unsigned int number_rx_channel;
 	unsigned int number_tx_channel;
+	/* TX and RX number of queues */
+	unsigned int number_rx_queues;
+	unsigned int number_tx_queues;
 	/* Alternate (enhanced) DESC mode */
 	unsigned int enh_desc;
 };
@@ -454,6 +457,8 @@ struct stmmac_ops {
 	void (*core_init)(struct mac_device_info *hw, int mtu);
 	/* Enable and verify that the IPC module is supported */
 	int (*rx_ipc)(struct mac_device_info *hw);
+	/* Enable RX Queues */
+	void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);
 	/* Dump MAC registers */
 	void (*dump_regs)(struct mac_device_info *hw);
 	/* Handle extra events on specific interrupts hw dependent */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index 3e8d4fe..b524598 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -22,6 +22,7 @@
 #define GMAC_HASH_TAB_32_63		0x00000014
 #define GMAC_RX_FLOW_CTRL		0x00000090
 #define GMAC_QX_TX_FLOW_CTRL(x)		(0x70 + x * 4)
+#define GMAC_RXQ_CTRL0			0x000000a0
 #define GMAC_INT_STATUS			0x000000b0
 #define GMAC_INT_EN			0x000000b4
 #define GMAC_PCS_BASE			0x000000e0
@@ -44,6 +45,11 @@
 
 #define GMAC_MAX_PERFECT_ADDRESSES	128
 
+/* MAC RX Queue Enable */
+#define GMAC_RX_QUEUE_CLEAR(queue)	~(GENMASK(1, 0) << ((queue) * 2))
+#define GMAC_RX_AV_QUEUE_ENABLE(queue)	BIT((queue) * 2)
+#define GMAC_RX_DCB_QUEUE_ENABLE(queue)	BIT(((queue) * 2) + 1)
+
 /* MAC Flow Control RX */
 #define GMAC_RX_FLOW_CTRL_RFE		BIT(0)
 
@@ -133,6 +139,8 @@ enum power_event {
 /* MAC HW features2 bitmap */
 #define GMAC_HW_FEAT_TXCHCNT		GENMASK(21, 18)
 #define GMAC_HW_FEAT_RXCHCNT		GENMASK(15, 12)
+#define GMAC_HW_FEAT_TXQCNT		GENMASK(9, 6)
+#define GMAC_HW_FEAT_RXQCNT		GENMASK(3, 0)
 
 /* MAC HW ADDR regs */
 #define GMAC_HI_DCS			GENMASK(18, 16)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index eaed7cb..ecfbf57 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -59,6 +59,17 @@ static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
 	writel(value, ioaddr + GMAC_INT_EN);
 }
 
+static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
+
+	value &= GMAC_RX_QUEUE_CLEAR(queue);
+	value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
+
+	writel(value, ioaddr + GMAC_RXQ_CTRL0);
+}
+
 static void dwmac4_dump_regs(struct mac_device_info *hw)
 {
 	void __iomem *ioaddr = hw->pcsr;
@@ -392,6 +403,7 @@ static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 static const struct stmmac_ops dwmac4_ops = {
 	.core_init = dwmac4_core_init,
 	.rx_ipc = dwmac4_rx_ipc_enable,
+	.rx_queue_enable = dwmac4_rx_queue_enable,
 	.dump_regs = dwmac4_dump_regs,
 	.host_irq_status = dwmac4_irq_status,
 	.flow_ctrl = dwmac4_flow_ctrl,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 8196ab5..377d1b4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -303,6 +303,11 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr,
 		((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
 	dma_cap->number_tx_channel =
 		((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
+	/* TX and RX number of queues */
+	dma_cap->number_rx_queues =
+		((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
+	dma_cap->number_tx_queues =
+		((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
 
 	/* IEEE 1588-2002 */
 	dma_cap->time_stamp = 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 3e40578..bc9cff9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1271,6 +1271,24 @@ static void free_dma_desc_resources(struct stmmac_priv *priv)
 }
 
 /**
+ *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
+ *  @priv: driver private structure
+ *  Description: It is used for enabling the rx queues in the MAC
+ */
+static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
+{
+	int rx_count = priv->dma_cap.number_rx_queues;
+	int queue = 0;
+
+	/* If GMAC does not have multiqueues, then this is not necessary*/
+	if (rx_count == 1)
+		return;
+
+	for (queue = 0; queue < rx_count; queue++)
+		priv->hw->mac->rx_queue_enable(priv->hw, queue);
+}
+
+/**
  *  stmmac_dma_operation_mode - HW DMA operation mode
  *  @priv: driver private structure
  *  Description: it is used for configuring the DMA operation mode register in
@@ -1691,6 +1709,10 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
 	/* Initialize the MAC Core */
 	priv->hw->mac->core_init(priv->hw, dev->mtu);
 
+	/* Initialize MAC RX Queues */
+	if (priv->hw->mac->rx_queue_enable)
+		stmmac_mac_enable_rx_queues(priv);
+
 	ret = priv->hw->mac->rx_ipc(priv->hw);
 	if (!ret) {
 		netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
-- 
2.9.3

Re: [PATCH v3] stmmac: enable rx queues

[Joao Pinto]

Hello,

Às 11:50 AM de 12/28/2016, Kishan Sandeep escreveu:
> On Wed, Dec 28, 2016 at 4:45 PM, Joao Pinto <Joao.Pinto@synopsys.com> wrote:
> 
>> When the hardware is synthesized with multiple queues, all queues are
>> disabled for default. This patch adds the rx queues configuration.
>> This patch was successfully tested in a Synopsys QoS Reference design.
>>
>> Signed-off-by: Joao Pinto <jpinto@synopsys.com>
>> ---
>> changes v2 -> v3 (Seraphin Bonnaffe):
>> - GMAC_RX_QUEUE_CLEAR macro simplified
>> changes v1 -> v2 (Niklas Cassel and Seraphin Bonnaffe):
>> - Instead of using number of DMA channels, lets use number of queues
>> - Create 2 flavors of RX queue enable Macros: AV and DCB (AV by default)
>> - Make sure that the RX queue related bits are cleared before setting
>> - Check if rx_queue_enable is available before executing
>>
>>  drivers/net/ethernet/stmicro/stmmac/common.h      |  5 +++++
>>  drivers/net/ethernet/stmicro/stmmac/dwmac4.h      |  8 ++++++++
>>  drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 12 ++++++++++++
>>  drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c  |  5 +++++
>>  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 22
>> ++++++++++++++++++++++
>>  5 files changed, 52 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h
>> b/drivers/net/ethernet/stmicro/stmmac/common.h
>> index b13a144..6c96291 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/common.h
>> +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
>> @@ -323,6 +323,9 @@ struct dma_features {
>>         /* TX and RX number of channels */
>>         unsigned int number_rx_channel;
>>         unsigned int number_tx_channel;
>> +       /* TX and RX number of queues */
>> +       unsigned int number_rx_queues;
>> +       unsigned int number_tx_queues;
>>
> 
> Looks like this variable is unused. Current driver is only supporting
> single Tx channel/queue. ??  Is current driver not supporting
> multichannel/multiqueue ?

stmmac has a good base for multichannel / multiple queue support, but is only
using 1 for now. My next task is to add complete multiple queues / channel to
stmmac amd that is why number of tx queues is being available.

Thanks!

> 
> Thanks!
> 

Re: [PATCH v3] stmmac: enable rx queues

[Kishan Sandeep]

On Wed, Dec 28, 2016 at 5:23 PM, Joao Pinto <Joao.Pinto@synopsys.com> wrote:
> Hello,
>
> Às 11:50 AM de 12/28/2016, Kishan Sandeep escreveu:
>> On Wed, Dec 28, 2016 at 4:45 PM, Joao Pinto <Joao.Pinto@synopsys.com> wrote:
>>
>>> When the hardware is synthesized with multiple queues, all queues are
>>> disabled for default. This patch adds the rx queues configuration.
>>> This patch was successfully tested in a Synopsys QoS Reference design.
>>>
>>> Signed-off-by: Joao Pinto <jpinto@synopsys.com>
>>> ---
>>> changes v2 -> v3 (Seraphin Bonnaffe):
>>> - GMAC_RX_QUEUE_CLEAR macro simplified
>>> changes v1 -> v2 (Niklas Cassel and Seraphin Bonnaffe):
>>> - Instead of using number of DMA channels, lets use number of queues
>>> - Create 2 flavors of RX queue enable Macros: AV and DCB (AV by default)
>>> - Make sure that the RX queue related bits are cleared before setting
>>> - Check if rx_queue_enable is available before executing
>>>
>>>  drivers/net/ethernet/stmicro/stmmac/common.h      |  5 +++++
>>>  drivers/net/ethernet/stmicro/stmmac/dwmac4.h      |  8 ++++++++
>>>  drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 12 ++++++++++++
>>>  drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c  |  5 +++++
>>>  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 22
>>> ++++++++++++++++++++++
>>>  5 files changed, 52 insertions(+)
>>>
>>> diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h
>>> b/drivers/net/ethernet/stmicro/stmmac/common.h
>>> index b13a144..6c96291 100644
>>> --- a/drivers/net/ethernet/stmicro/stmmac/common.h
>>> +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
>>> @@ -323,6 +323,9 @@ struct dma_features {
>>>         /* TX and RX number of channels */
>>>         unsigned int number_rx_channel;
>>>         unsigned int number_tx_channel;
>>> +       /* TX and RX number of queues */
>>> +       unsigned int number_rx_queues;
>>> +       unsigned int number_tx_queues;
>>>
>>
>> Looks like this variable is unused. Current driver is only supporting
>> single Tx channel/queue. ??  Is current driver not supporting
>> multichannel/multiqueue ?
>
> stmmac has a good base for multichannel / multiple queue support, but is only
> using 1 for now. My next task is to add complete multiple queues / channel to
> stmmac amd that is why number of tx queues is being available.
>
> Thanks!

I believe *number_tx_queues* variable can be added at the time support
we are providing.

One query is that what is the algorithm that we are following
currently in the driver if we enable multi Rx queues/DMA channels ?

Thanks!

Re: [PATCH v3] stmmac: enable rx queues

[Joao Pinto]

Às 12:02 PM de 12/28/2016, Kishan Sandeep escreveu:
> On Wed, Dec 28, 2016 at 5:23 PM, Joao Pinto <Joao.Pinto@synopsys.com> wrote:
>> Hello,
>>
>> Às 11:50 AM de 12/28/2016, Kishan Sandeep escreveu:
>>> On Wed, Dec 28, 2016 at 4:45 PM, Joao Pinto <Joao.Pinto@synopsys.com> wrote:
>>>
>>>> When the hardware is synthesized with multiple queues, all queues are
>>>> disabled for default. This patch adds the rx queues configuration.
>>>> This patch was successfully tested in a Synopsys QoS Reference design.
>>>>
>>>> Signed-off-by: Joao Pinto <jpinto@synopsys.com>
>>>> ---
>>>> changes v2 -> v3 (Seraphin Bonnaffe):
>>>> - GMAC_RX_QUEUE_CLEAR macro simplified
>>>> changes v1 -> v2 (Niklas Cassel and Seraphin Bonnaffe):
>>>> - Instead of using number of DMA channels, lets use number of queues
>>>> - Create 2 flavors of RX queue enable Macros: AV and DCB (AV by default)
>>>> - Make sure that the RX queue related bits are cleared before setting
>>>> - Check if rx_queue_enable is available before executing
>>>>
>>>>  drivers/net/ethernet/stmicro/stmmac/common.h      |  5 +++++
>>>>  drivers/net/ethernet/stmicro/stmmac/dwmac4.h      |  8 ++++++++
>>>>  drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 12 ++++++++++++
>>>>  drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c  |  5 +++++
>>>>  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 22
>>>> ++++++++++++++++++++++
>>>>  5 files changed, 52 insertions(+)
>>>>
>>>> diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h
>>>> b/drivers/net/ethernet/stmicro/stmmac/common.h
>>>> index b13a144..6c96291 100644
>>>> --- a/drivers/net/ethernet/stmicro/stmmac/common.h
>>>> +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
>>>> @@ -323,6 +323,9 @@ struct dma_features {
>>>>         /* TX and RX number of channels */
>>>>         unsigned int number_rx_channel;
>>>>         unsigned int number_tx_channel;
>>>> +       /* TX and RX number of queues */
>>>> +       unsigned int number_rx_queues;
>>>> +       unsigned int number_tx_queues;
>>>>
>>>
>>> Looks like this variable is unused. Current driver is only supporting
>>> single Tx channel/queue. ??  Is current driver not supporting
>>> multichannel/multiqueue ?
>>
>> stmmac has a good base for multichannel / multiple queue support, but is only
>> using 1 for now. My next task is to add complete multiple queues / channel to
>> stmmac amd that is why number of tx queues is being available.
>>
>> Thanks!
> 
> I believe *number_tx_queues* variable can be added at the time support
> we are providing.
> 
> One query is that what is the algorithm that we are following
> currently in the driver if we enable multi Rx queues/DMA channels ?

In a synthesized core with single channel, multi dma/queues is not an issue
since it has a single queue and that's it. For a synthesized core with multiple
there are some algorithms that can be configured in the driver. I will include
them later. I can change this patch and enale rx queue 0 only, no problem.

> 
> Thanks!
> 

Re: [PATCH v3] stmmac: enable rx queues

[Joao Pinto]

Às 12:23 PM de 12/28/2016, Kishan Sandeep escreveu:
> On Dec 28, 2016 5:50 PM, "Joao Pinto" <Joao.Pinto@synopsys.com> wrote:
>>
>> Às 12:19 PM de 12/28/2016, Joao Pinto escreveu:
>>> Às 12:15 PM de 12/28/2016, Kishan Sandeep escreveu:
>>>> On Dec 28, 2016 5:36 PM, "Joao Pinto" <Joao.Pinto@synopsys.com> wrote:
>>>>>
>>>>> Às 12:02 PM de 12/28/2016, Kishan Sandeep escreveu:
>>>>>> On Wed, Dec 28, 2016 at 5:23 PM, Joao Pinto <Joao.Pinto@synopsys.com>
>>>> wrote:
>>>>>>> Hello,
>>>>>>>
>>>>>>> Às 11:50 AM de 12/28/2016, Kishan Sandeep escreveu:
>>>>>>>> On Wed, Dec 28, 2016 at 4:45 PM, Joao Pinto <
> Joao.Pinto@synopsys.com>
>>>> wrote:
>>>>>>>>
>>>>>>>>> When the hardware is synthesized with multiple queues, all queues
> are
>>>>>>>>> disabled for default. This patch adds the rx queues configuration.
>>>>>>>>> This patch was successfully tested in a Synopsys QoS Reference
>>>> design.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Joao Pinto <jpinto@synopsys.com>
>>>>>>>>> ---
>>>>>>>>> changes v2 -> v3 (Seraphin Bonnaffe):
>>>>>>>>> - GMAC_RX_QUEUE_CLEAR macro simplified
>>>>>>>>> changes v1 -> v2 (Niklas Cassel and Seraphin Bonnaffe):
>>>>>>>>> - Instead of using number of DMA channels, lets use number of
> queues
>>>>>>>>> - Create 2 flavors of RX queue enable Macros: AV and DCB (AV by
>>>> default)
>>>>>>>>> - Make sure that the RX queue related bits are cleared before
> setting
>>>>>>>>> - Check if rx_queue_enable is available before executing
>>>>>>>>>
>>>>>>>>>  drivers/net/ethernet/stmicro/stmmac/common.h      |  5 +++++
>>>>>>>>>  drivers/net/ethernet/stmicro/stmmac/dwmac4.h      |  8 ++++++++
>>>>>>>>>  drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 12
> ++++++++++++
>>>>>>>>>  drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c  |  5 +++++
>>>>>>>>>  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 22
>>>>>>>>> ++++++++++++++++++++++
>>>>>>>>>  5 files changed, 52 insertions(+)
>>>>>>>>>
>>>>>>>>> diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h
>>>>>>>>> b/drivers/net/ethernet/stmicro/stmmac/common.h
>>>>>>>>> index b13a144..6c96291 100644
>>>>>>>>> --- a/drivers/net/ethernet/stmicro/stmmac/common.h
>>>>>>>>> +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
>>>>>>>>> @@ -323,6 +323,9 @@ struct dma_features {
>>>>>>>>>         /* TX and RX number of channels */
>>>>>>>>>         unsigned int number_rx_channel;
>>>>>>>>>         unsigned int number_tx_channel;
>>>>>>>>> +       /* TX and RX number of queues */
>>>>>>>>> +       unsigned int number_rx_queues;
>>>>>>>>> +       unsigned int number_tx_queues;
>>>>>>>>>
>>>>>>>>
>>>>>>>> Looks like this variable is unused. Current driver is only
> supporting
>>>>>>>> single Tx channel/queue. ??  Is current driver not supporting
>>>>>>>> multichannel/multiqueue ?
>>>>>>>
>>>>>>> stmmac has a good base for multichannel / multiple queue support,
> but
>>>> is only
>>>>>>> using 1 for now. My next task is to add complete multiple queues /
>>>> channel to
>>>>>>> stmmac amd that is why number of tx queues is being available.
>>>>>>>
>>>>>>> Thanks!
>>>>>>
>>>>>> I believe *number_tx_queues* variable can be added at the time
> support
>>>>>> we are providing.
>>>>>>
>>>>>> One query is that what is the algorithm that we are following
>>>>>> currently in the driver if we enable multi Rx queues/DMA channels ?
>>>>>
>>>>> In a synthesized core with single channel, multi dma/queues is not an
>>>> issue
>>>>> since it has a single queue and that's it. For a synthesized core with
>>>> multiple
>>>>> there are some algorithms that can be configured in the driver. I will
>>>> include
>>>>> them later. I can change this patch and enale rx queue 0 only, no
> problem.
>>>>
>>>> Generally there will be one to one mapping from the DMA channel to
>>>> corresponding MTL queue. If we enable multiple MTL RX queues, is there
> any
>>>> requirement to use those many number of DMA channels in RX path or
> single
>>>> DMA RX channel is sufficient ???
>>>
>>> I am using an ethernet QoS reference design synthesized  with 4
> channels / 4
>>> queues. Since stmmac only uses one 1 queue / 1 dma channel. Of course
> the
>>> performance is not the same as using the 4 available ones. I would say
> the
>>> correct approach would be tp get the available rx/tx dma channel number
> and
>>> rx/tx queue number configured in the hardware and get the driver adapt
> and use
>>> as many as there are.
>>
>> Of course there should be always dma  channels = queues.
>>
>>>
>>>>
>>>
> In that case here we need to enable multi DMA channels along with multiple
> RX channels also we may need to program the algorithm that needs to run on
> queues

I understand your concern. In order to do this step by step, I am going to
change the patch and enable RX queue 0 only, and then when I finish multiple
support I will add multi rx and tx. I will send a v4 in the afternoon. This way
it will be cleaner and less confusing.

Thanks.

Re: [PATCH v3] stmmac: enable rx queues

[Joao Pinto]

Às 6:26 PM de 12/21/2016, David Miller escreveu:
> From: Joao Pinto <Joao.Pinto@synopsys.com>
> Date: Tue, 20 Dec 2016 17:09:28 +0000
> 
>> When the hardware is synthesized with multiple queues, all queues are
>> disabled for default. This patch adds the rx queues configuration.
>> This patch was successfully tested in a Synopsys QoS Reference design.
>>
>> Signed-off-by: Joao Pinto <jpinto@synopsys.com>
>> ---
>> changes v2 -> v3 (Seraphin Bonnaffe):
>> - GMAC_RX_QUEUE_CLEAR macro simplified
>> changes v1 -> v2 (Niklas Cassel and Seraphin Bonnaffe):
>> - Instead of using number of DMA channels, lets use number of queues
>> - Create 2 flavors of RX queue enable Macros: AV and DCB (AV by default)
>> - Make sure that the RX queue related bits are cleared before setting
>> - Check if rx_queue_enable is available before executing
> 
> This change seems more appropriate for net-next, please resubmit when
> that tree opens up again.
> 
> Thanks.
> 

Ok, great! Could you please send me an estimate of when the net-next is going to
open again?

Thanks

Re: [PATCH v3] stmmac: enable rx queues

[David Miller]

From: Joao Pinto <Joao.Pinto@synopsys.com>
Date: Tue, 20 Dec 2016 17:09:28 +0000

> When the hardware is synthesized with multiple queues, all queues are
> disabled for default. This patch adds the rx queues configuration.
> This patch was successfully tested in a Synopsys QoS Reference design.
> 
> Signed-off-by: Joao Pinto <jpinto@synopsys.com>
> ---
> changes v2 -> v3 (Seraphin Bonnaffe):
> - GMAC_RX_QUEUE_CLEAR macro simplified
> changes v1 -> v2 (Niklas Cassel and Seraphin Bonnaffe):
> - Instead of using number of DMA channels, lets use number of queues
> - Create 2 flavors of RX queue enable Macros: AV and DCB (AV by default)
> - Make sure that the RX queue related bits are cleared before setting
> - Check if rx_queue_enable is available before executing

This change seems more appropriate for net-next, please resubmit when
that tree opens up again.

Thanks.

[PATCH v3] stmmac: enable rx queues

[Joao Pinto]

When the hardware is synthesized with multiple queues, all queues are
disabled for default. This patch adds the rx queues configuration.
This patch was successfully tested in a Synopsys QoS Reference design.

Signed-off-by: Joao Pinto <jpinto@synopsys.com>
---
changes v2 -> v3 (Seraphin Bonnaffe):
- GMAC_RX_QUEUE_CLEAR macro simplified
changes v1 -> v2 (Niklas Cassel and Seraphin Bonnaffe):
- Instead of using number of DMA channels, lets use number of queues
- Create 2 flavors of RX queue enable Macros: AV and DCB (AV by default)
- Make sure that the RX queue related bits are cleared before setting
- Check if rx_queue_enable is available before executing

 drivers/net/ethernet/stmicro/stmmac/common.h      |  5 +++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h      |  8 ++++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 12 ++++++++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c  |  5 +++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 22 ++++++++++++++++++++++
 5 files changed, 52 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index b13a144..6c96291 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -323,6 +323,9 @@ struct dma_features {
 	/* TX and RX number of channels */
 	unsigned int number_rx_channel;
 	unsigned int number_tx_channel;
+	/* TX and RX number of queues */
+	unsigned int number_rx_queues;
+	unsigned int number_tx_queues;
 	/* Alternate (enhanced) DESC mode */
 	unsigned int enh_desc;
 };
@@ -454,6 +457,8 @@ struct stmmac_ops {
 	void (*core_init)(struct mac_device_info *hw, int mtu);
 	/* Enable and verify that the IPC module is supported */
 	int (*rx_ipc)(struct mac_device_info *hw);
+	/* Enable RX Queues */
+	void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);
 	/* Dump MAC registers */
 	void (*dump_regs)(struct mac_device_info *hw);
 	/* Handle extra events on specific interrupts hw dependent */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index 3e8d4fe..b524598 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -22,6 +22,7 @@
 #define GMAC_HASH_TAB_32_63		0x00000014
 #define GMAC_RX_FLOW_CTRL		0x00000090
 #define GMAC_QX_TX_FLOW_CTRL(x)		(0x70 + x * 4)
+#define GMAC_RXQ_CTRL0			0x000000a0
 #define GMAC_INT_STATUS			0x000000b0
 #define GMAC_INT_EN			0x000000b4
 #define GMAC_PCS_BASE			0x000000e0
@@ -44,6 +45,11 @@
 
 #define GMAC_MAX_PERFECT_ADDRESSES	128
 
+/* MAC RX Queue Enable */
+#define GMAC_RX_QUEUE_CLEAR(queue)	~(GENMASK(1, 0) << ((queue) * 2))
+#define GMAC_RX_AV_QUEUE_ENABLE(queue)	BIT((queue) * 2)
+#define GMAC_RX_DCB_QUEUE_ENABLE(queue)	BIT(((queue) * 2) + 1)
+
 /* MAC Flow Control RX */
 #define GMAC_RX_FLOW_CTRL_RFE		BIT(0)
 
@@ -133,6 +139,8 @@ enum power_event {
 /* MAC HW features2 bitmap */
 #define GMAC_HW_FEAT_TXCHCNT		GENMASK(21, 18)
 #define GMAC_HW_FEAT_RXCHCNT		GENMASK(15, 12)
+#define GMAC_HW_FEAT_TXQCNT		GENMASK(9, 6)
+#define GMAC_HW_FEAT_RXQCNT		GENMASK(3, 0)
 
 /* MAC HW ADDR regs */
 #define GMAC_HI_DCS			GENMASK(18, 16)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index eaed7cb..ecfbf57 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -59,6 +59,17 @@ static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
 	writel(value, ioaddr + GMAC_INT_EN);
 }
 
+static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
+
+	value &= GMAC_RX_QUEUE_CLEAR(queue);
+	value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
+
+	writel(value, ioaddr + GMAC_RXQ_CTRL0);
+}
+
 static void dwmac4_dump_regs(struct mac_device_info *hw)
 {
 	void __iomem *ioaddr = hw->pcsr;
@@ -392,6 +403,7 @@ static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 static const struct stmmac_ops dwmac4_ops = {
 	.core_init = dwmac4_core_init,
 	.rx_ipc = dwmac4_rx_ipc_enable,
+	.rx_queue_enable = dwmac4_rx_queue_enable,
 	.dump_regs = dwmac4_dump_regs,
 	.host_irq_status = dwmac4_irq_status,
 	.flow_ctrl = dwmac4_flow_ctrl,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index 8196ab5..377d1b4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -303,6 +303,11 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr,
 		((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
 	dma_cap->number_tx_channel =
 		((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
+	/* TX and RX number of queues */
+	dma_cap->number_rx_queues =
+		((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
+	dma_cap->number_tx_queues =
+		((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
 
 	/* IEEE 1588-2002 */
 	dma_cap->time_stamp = 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 3e40578..bc9cff9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1271,6 +1271,24 @@ static void free_dma_desc_resources(struct stmmac_priv *priv)
 }
 
 /**
+ *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
+ *  @priv: driver private structure
+ *  Description: It is used for enabling the rx queues in the MAC
+ */
+static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
+{
+	int rx_count = priv->dma_cap.number_rx_queues;
+	int queue = 0;
+
+	/* If GMAC does not have multiqueues, then this is not necessary*/
+	if (rx_count == 1)
+		return;
+
+	for (queue = 0; queue < rx_count; queue++)
+		priv->hw->mac->rx_queue_enable(priv->hw, queue);
+}
+
+/**
  *  stmmac_dma_operation_mode - HW DMA operation mode
  *  @priv: driver private structure
  *  Description: it is used for configuring the DMA operation mode register in
@@ -1691,6 +1709,10 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
 	/* Initialize the MAC Core */
 	priv->hw->mac->core_init(priv->hw, dev->mtu);
 
+	/* Initialize MAC RX Queues */
+	if (priv->hw->mac->rx_queue_enable)
+		stmmac_mac_enable_rx_queues(priv);
+
 	ret = priv->hw->mac->rx_ipc(priv->hw);
 	if (!ret) {
 		netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
-- 
2.9.3