From: "Philippe Mathieu-Daudé" <f4bug@amsat.org> To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Fabien Portas <fabien.portas@grenoble-inp.org> Subject: Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions Date: Mon, 30 Aug 2021 23:35:35 +0200 [thread overview] Message-ID: <343cc196-3d69-6785-9228-3edbf9645041@amsat.org> (raw) In-Reply-To: <20210830171638.126325-3-frederic.petrot@univ-grenoble-alpes.fr> On 8/30/21 7:16 PM, Frédéric Pétrot wrote: > Addition of the load(s) and store instructions of the 128-bit extension. > These instructions have addresses on 128-bit but explicitly assume that the > upper 64-bit of the address registers is null, and therefore can use the > existing address translation mechanism. > 128-bit memory access identification and 64-bit signedness is handled a bit > off-the-record: > MemOp reserves 2 bits for size and a contiguous 3rd bit for the sign, so we > cannot simply take value 4 to indicate a size of 16 bytes. > Additionally, MO_TEQ | MO_SIGN seems to be a sentinel value, leading to a > QEMU assertion violation. > Modifying the existing state in QEMU has a great impact that we are not > capable of fully evaluating, so we choose to pass this information into > another parameter and let memop as it is for now. > > Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> > Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> > --- > include/tcg/tcg-op.h | 1 + > tcg/tcg-op.c | 6 + Please split in 2 patches, first TCG generic, > target/riscv/insn16.decode | 33 ++++- > target/riscv/insn32.decode | 5 + > target/riscv/insn_trans/trans_rvi.c.inc | 188 +++++++++++++++++++++--- Second particular RISCV implementation. > 5 files changed, 207 insertions(+), 26 deletions(-)
WARNING: multiple messages have this Message-ID (diff)
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org> To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Fabien Portas <fabien.portas@grenoble-inp.org>, Alistair Francis <alistair.francis@wdc.com> Subject: Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions Date: Mon, 30 Aug 2021 23:35:35 +0200 [thread overview] Message-ID: <343cc196-3d69-6785-9228-3edbf9645041@amsat.org> (raw) In-Reply-To: <20210830171638.126325-3-frederic.petrot@univ-grenoble-alpes.fr> On 8/30/21 7:16 PM, Frédéric Pétrot wrote: > Addition of the load(s) and store instructions of the 128-bit extension. > These instructions have addresses on 128-bit but explicitly assume that the > upper 64-bit of the address registers is null, and therefore can use the > existing address translation mechanism. > 128-bit memory access identification and 64-bit signedness is handled a bit > off-the-record: > MemOp reserves 2 bits for size and a contiguous 3rd bit for the sign, so we > cannot simply take value 4 to indicate a size of 16 bytes. > Additionally, MO_TEQ | MO_SIGN seems to be a sentinel value, leading to a > QEMU assertion violation. > Modifying the existing state in QEMU has a great impact that we are not > capable of fully evaluating, so we choose to pass this information into > another parameter and let memop as it is for now. > > Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> > Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> > --- > include/tcg/tcg-op.h | 1 + > tcg/tcg-op.c | 6 + Please split in 2 patches, first TCG generic, > target/riscv/insn16.decode | 33 ++++- > target/riscv/insn32.decode | 5 + > target/riscv/insn_trans/trans_rvi.c.inc | 188 +++++++++++++++++++++--- Second particular RISCV implementation. > 5 files changed, 207 insertions(+), 26 deletions(-)
next prev parent reply other threads:[~2021-08-30 21:36 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-30 17:16 [PATCH 1/8] target/riscv: Settings for 128-bit extension support Frédéric Pétrot 2021-08-30 17:16 ` Frédéric Pétrot 2021-08-30 17:16 ` [PATCH 2/8] target/riscv: 128-bit registers creation and access Frédéric Pétrot 2021-08-30 17:16 ` Frédéric Pétrot 2021-08-30 21:34 ` Philippe Mathieu-Daudé 2021-08-30 21:34 ` Philippe Mathieu-Daudé 2021-08-30 17:16 ` [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions Frédéric Pétrot 2021-08-30 17:16 ` Frédéric Pétrot 2021-08-30 21:35 ` Philippe Mathieu-Daudé [this message] 2021-08-30 21:35 ` Philippe Mathieu-Daudé 2021-08-31 2:24 ` Richard Henderson 2021-08-31 2:24 ` Richard Henderson 2021-08-31 16:00 ` Frédéric Pétrot 2021-08-31 16:00 ` Frédéric Pétrot 2021-08-31 2:30 ` Richard Henderson 2021-08-31 2:30 ` Richard Henderson 2021-08-30 17:16 ` [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions Frédéric Pétrot 2021-08-30 17:16 ` Frédéric Pétrot 2021-08-30 21:38 ` Philippe Mathieu-Daudé 2021-08-30 21:38 ` Philippe Mathieu-Daudé 2021-08-30 21:40 ` Philippe Mathieu-Daudé 2021-08-30 21:40 ` Philippe Mathieu-Daudé 2021-08-31 15:57 ` Frédéric Pétrot 2021-08-31 15:57 ` Frédéric Pétrot 2021-08-31 3:32 ` Richard Henderson 2021-08-31 3:32 ` Richard Henderson 2021-08-31 3:30 ` Richard Henderson 2021-08-31 3:30 ` Richard Henderson 2021-08-30 17:16 ` [PATCH 5/8] target/riscv: 128-bit multiply and divide Frédéric Pétrot 2021-08-30 17:16 ` Frédéric Pétrot 2021-08-30 17:16 ` [PATCH 6/8] target/riscv: Support of compiler's 128-bit integer types Frédéric Pétrot 2021-08-30 17:16 ` Frédéric Pétrot 2021-08-31 3:38 ` Richard Henderson 2021-08-31 3:38 ` Richard Henderson 2021-08-30 17:16 ` [PATCH 7/8] target/riscv: 128-bit support for some csrs Frédéric Pétrot 2021-08-30 17:16 ` Frédéric Pétrot 2021-08-31 3:43 ` Richard Henderson 2021-08-31 3:43 ` Richard Henderson 2021-08-30 17:16 ` [PATCH 8/8] target/riscv: Support for 128-bit satp Frédéric Pétrot 2021-08-30 17:16 ` Frédéric Pétrot 2021-08-31 3:13 ` [PATCH 1/8] target/riscv: Settings for 128-bit extension support Alistair Francis 2021-08-31 3:13 ` Alistair Francis 2021-08-31 16:20 ` Frédéric Pétrot 2021-08-31 16:20 ` Frédéric Pétrot
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