From: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> To: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>, Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> Cc: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, stuart.yoder-3arQi8VN3Tc@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Subject: Re: [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum Date: Mon, 24 Oct 2016 09:36:20 +0100 [thread overview] Message-ID: <3a29c03a-2da1-7bfe-28ff-21dada50ee8d@arm.com> (raw) In-Reply-To: <962ea92f-870b-e1d0-5bb7-1a6d66c35122-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> On 23/10/16 04:21, Ding Tianhong wrote: > This erratum describes a bug in logic outside the core, so MIDR can't be > used to identify its presence, and reading an SoC-specific revision > register from common arch timer code would be awkward. So, describe it > in the device tree. > > Signed-off-by: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> > --- > Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt > index ef5fbe9..26bc837 100644 > --- a/Documentation/devicetree/bindings/arm/arch_timer.txt > +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt > @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. > This also affects writes to the tval register, due to the implicit > counter read. > > +- hisilicon,erratum-161x01 : A boolean property. Indicates the presence of > + QorIQ erratum 161201, which says that reading the counter is Other than the copy/paste of the FSL erratum, please document the actual erratum number. Is that 161x01 or 161201? > + unreliable unless the small range of value is returned by back-to-back reads. That's a detail that doesn't belong in the DT, but that would be much better next to the code doing the actual handling. > + This also affects writes to the tval register, due to the implicit > + counter read. > + > ** Optional properties: > > - arm,cpu-registers-not-fw-configured : Firmware does not initialize > Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum Date: Mon, 24 Oct 2016 09:36:20 +0100 [thread overview] Message-ID: <3a29c03a-2da1-7bfe-28ff-21dada50ee8d@arm.com> (raw) In-Reply-To: <962ea92f-870b-e1d0-5bb7-1a6d66c35122@huawei.com> On 23/10/16 04:21, Ding Tianhong wrote: > This erratum describes a bug in logic outside the core, so MIDR can't be > used to identify its presence, and reading an SoC-specific revision > register from common arch timer code would be awkward. So, describe it > in the device tree. > > Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> > --- > Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt > index ef5fbe9..26bc837 100644 > --- a/Documentation/devicetree/bindings/arm/arch_timer.txt > +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt > @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. > This also affects writes to the tval register, due to the implicit > counter read. > > +- hisilicon,erratum-161x01 : A boolean property. Indicates the presence of > + QorIQ erratum 161201, which says that reading the counter is Other than the copy/paste of the FSL erratum, please document the actual erratum number. Is that 161x01 or 161201? > + unreliable unless the small range of value is returned by back-to-back reads. That's a detail that doesn't belong in the DT, but that would be much better next to the code doing the actual handling. > + This also affects writes to the tval register, due to the implicit > + counter read. > + > ** Optional properties: > > - arm,cpu-registers-not-fw-configured : Firmware does not initialize > Thanks, M. -- Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2016-10-24 8:36 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-10-23 3:21 [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum Ding Tianhong 2016-10-23 3:21 ` Ding Tianhong [not found] ` <962ea92f-870b-e1d0-5bb7-1a6d66c35122-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2016-10-23 12:04 ` Shawn Guo 2016-10-23 12:04 ` Shawn Guo 2016-10-24 5:46 ` Ding Tianhong 2016-10-24 5:46 ` Ding Tianhong 2016-10-24 8:36 ` Marc Zyngier [this message] 2016-10-24 8:36 ` Marc Zyngier [not found] ` <3a29c03a-2da1-7bfe-28ff-21dada50ee8d-5wv7dgnIgG8@public.gmane.org> 2016-10-24 8:43 ` Ding Tianhong 2016-10-24 8:43 ` Ding Tianhong 2016-10-24 11:16 ` Mark Rutland 2016-10-24 11:16 ` Mark Rutland 2016-10-24 12:40 ` Ding Tianhong 2016-10-24 12:40 ` Ding Tianhong [not found] ` <7e839df8-f8f7-3b16-8321-4ff45b6c5884-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2016-10-24 13:16 ` Mark Rutland 2016-10-24 13:16 ` Mark Rutland 2016-10-24 13:23 ` Ding Tianhong 2016-10-24 13:23 ` Ding Tianhong [not found] ` <1dcfb21a-7417-282e-f187-425d2c148672-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> 2016-10-24 13:39 ` Mark Rutland 2016-10-24 13:39 ` Mark Rutland 2016-10-26 2:59 ` Ding Tianhong 2016-10-26 2:59 ` Ding Tianhong
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