* [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-12 4:08 ` Takashi Sakamoto
` (2 more replies)
2018-12-11 21:30 ` [PATCH 02/21] ASoC: SOF: Intel: Add HSW HW DSP support Pierre-Louis Bossart
` (19 subsequent siblings)
20 siblings, 3 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pan Xiuli,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
Rander Wang, sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add support for the audio DSP hardware found on Intel Baytrail,
Cherrytrail and Braswell based devices.
Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/byt.c | 805 +++++++++++++++++++++++++++++++++++++
sound/soc/sof/intel/shim.h | 159 ++++++++
2 files changed, 964 insertions(+)
create mode 100644 sound/soc/sof/intel/byt.c
create mode 100644 sound/soc/sof/intel/shim.h
diff --git a/sound/soc/sof/intel/byt.c b/sound/soc/sof/intel/byt.c
new file mode 100644
index 000000000000..1695d67c3360
--- /dev/null
+++ b/sound/soc/sof/intel/byt.c
@@ -0,0 +1,805 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+//
+
+/*
+ * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
+ */
+
+#include <linux/module.h>
+#include <sound/sof.h>
+#include <sound/sof/xtensa.h>
+#include "../ops.h"
+#include "shim.h"
+
+/* DSP memories */
+#define IRAM_OFFSET 0x0C0000
+#define IRAM_SIZE (80 * 1024)
+#define DRAM_OFFSET 0x100000
+#define DRAM_SIZE (160 * 1024)
+#define SHIM_OFFSET 0x140000
+#define SHIM_SIZE 0x100
+#define MBOX_OFFSET 0x144000
+#define MBOX_SIZE 0x1000
+#define EXCEPT_OFFSET 0x800
+
+/* DSP peripherals */
+#define DMAC0_OFFSET 0x098000
+#define DMAC1_OFFSET 0x09c000
+#define DMAC2_OFFSET 0x094000
+#define DMAC_SIZE 0x420
+#define SSP0_OFFSET 0x0a0000
+#define SSP1_OFFSET 0x0a1000
+#define SSP2_OFFSET 0x0a2000
+#define SSP3_OFFSET 0x0a4000
+#define SSP4_OFFSET 0x0a5000
+#define SSP5_OFFSET 0x0a6000
+#define SSP_SIZE 0x100
+
+#define BYT_STACK_DUMP_SIZE 32
+
+#define BYT_PCI_BAR_SIZE 0x200000
+
+#define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32)
+
+/*
+ * Debug
+ */
+
+#define MBOX_DUMP_SIZE 0x30
+
+/* BARs */
+#define BYT_DSP_BAR 0
+#define BYT_PCI_BAR 1
+#define BYT_IMR_BAR 2
+
+static const struct snd_sof_debugfs_map byt_debugfs[] = {
+ {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE},
+ {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE},
+ {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE},
+ {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE},
+ {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE},
+ {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE},
+ {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE},
+ {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE},
+};
+
+static const struct snd_sof_debugfs_map cht_debugfs[] = {
+ {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE},
+ {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE},
+ {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE},
+ {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE},
+ {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE},
+ {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE},
+ {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE},
+ {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE},
+ {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE},
+ {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE},
+ {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE},
+ {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE},
+};
+
+static int byt_cmd_done(struct snd_sof_dev *sdev, int dir);
+
+/*
+ * IPC Firmware ready.
+ */
+static void byt_get_windows(struct snd_sof_dev *sdev)
+{
+ struct sof_ipc_window_elem *elem;
+ u32 outbox_offset = 0;
+ u32 stream_offset = 0;
+ u32 inbox_offset = 0;
+ u32 outbox_size = 0;
+ u32 stream_size = 0;
+ u32 inbox_size = 0;
+ int i;
+
+ if (!sdev->info_window) {
+ dev_err(sdev->dev, "error: have no window info\n");
+ return;
+ }
+
+ for (i = 0; i < sdev->info_window->num_windows; i++) {
+ elem = &sdev->info_window->window[i];
+
+ switch (elem->type) {
+ case SOF_IPC_REGION_UPBOX:
+ inbox_offset = elem->offset + MBOX_OFFSET;
+ inbox_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BYT_DSP_BAR] +
+ inbox_offset,
+ elem->size, "inbox");
+ break;
+ case SOF_IPC_REGION_DOWNBOX:
+ outbox_offset = elem->offset + MBOX_OFFSET;
+ outbox_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BYT_DSP_BAR] +
+ outbox_offset,
+ elem->size, "outbox");
+ break;
+ case SOF_IPC_REGION_TRACE:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BYT_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "etrace");
+ break;
+ case SOF_IPC_REGION_DEBUG:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BYT_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "debug");
+ break;
+ case SOF_IPC_REGION_STREAM:
+ stream_offset = elem->offset + MBOX_OFFSET;
+ stream_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BYT_DSP_BAR] +
+ stream_offset,
+ elem->size, "stream");
+ break;
+ case SOF_IPC_REGION_REGS:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BYT_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "regs");
+ break;
+ case SOF_IPC_REGION_EXCEPTION:
+ sdev->dsp_oops_offset = elem->offset + MBOX_OFFSET;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BYT_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "exception");
+ break;
+ default:
+ dev_err(sdev->dev, "error: get illegal window info\n");
+ return;
+ }
+ }
+
+ if (outbox_size == 0 || inbox_size == 0) {
+ dev_err(sdev->dev, "error: get illegal mailbox window\n");
+ return;
+ }
+
+ snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size,
+ outbox_offset, outbox_size);
+ sdev->stream_box.offset = stream_offset;
+ sdev->stream_box.size = stream_size;
+
+ dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n",
+ inbox_offset, inbox_size);
+ dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n",
+ outbox_offset, outbox_size);
+ dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n",
+ stream_offset, stream_size);
+}
+
+static int byt_fw_ready(struct snd_sof_dev *sdev, u32 msg_id)
+{
+ struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready;
+ u32 offset;
+ int ret;
+
+ /* mailbox must be on 4k boundary */
+ offset = MBOX_OFFSET;
+
+ dev_dbg(sdev->dev, "ipc: DSP is ready 0x%8.8x offset 0x%x\n",
+ msg_id, offset);
+
+ /* no need to re-check version/ABI for subsequent boots */
+ if (!sdev->first_boot)
+ return 0;
+
+ /* copy data from the DSP FW ready offset */
+ sof_block_read(sdev, offset, fw_ready, sizeof(*fw_ready));
+
+ snd_sof_dsp_mailbox_init(sdev, fw_ready->dspbox_offset,
+ fw_ready->dspbox_size,
+ fw_ready->hostbox_offset,
+ fw_ready->hostbox_size);
+
+ /* make sure ABI version is compatible */
+ ret = snd_sof_ipc_valid(sdev);
+ if (ret < 0)
+ return ret;
+
+ /* now check for extended data */
+ snd_sof_fw_parse_ext_data(sdev, MBOX_OFFSET +
+ sizeof(struct sof_ipc_fw_ready));
+
+ byt_get_windows(sdev);
+
+ return 0;
+}
+
+/*
+ * Debug
+ */
+
+static void byt_get_registers(struct snd_sof_dev *sdev,
+ struct sof_ipc_dsp_oops_xtensa *xoops,
+ struct sof_ipc_panic_info *panic_info,
+ u32 *stack, size_t stack_words)
+{
+ /* first read regsisters */
+ sof_mailbox_read(sdev, sdev->dsp_oops_offset, xoops, sizeof(*xoops));
+
+ /* then get panic info */
+ sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops),
+ panic_info, sizeof(*panic_info));
+
+ /* then get the stack */
+ sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops) +
+ sizeof(*panic_info), stack,
+ stack_words * sizeof(u32));
+}
+
+static void byt_dump(struct snd_sof_dev *sdev, u32 flags)
+{
+ struct sof_ipc_dsp_oops_xtensa xoops;
+ struct sof_ipc_panic_info panic_info;
+ u32 stack[BYT_STACK_DUMP_SIZE];
+ u32 status, panic;
+
+ /* now try generic SOF status messages */
+ status = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IPCD);
+ panic = snd_sof_dsp_read(sdev, BYT_DSP_BAR, SHIM_IPCX);
+ byt_get_registers(sdev, &xoops, &panic_info, stack,
+ BYT_STACK_DUMP_SIZE);
+ snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
+ BYT_STACK_DUMP_SIZE);
+}
+
+/*
+ * IPC Doorbell IRQ handler and thread.
+ */
+
+static irqreturn_t byt_irq_handler(int irq, void *context)
+{
+ struct snd_sof_dev *sdev = (struct snd_sof_dev *)context;
+ u64 isr;
+ int ret = IRQ_NONE;
+
+ /* Interrupt arrived, check src */
+ isr = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_ISRX);
+ if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY))
+ ret = IRQ_WAKE_THREAD;
+
+ return ret;
+}
+
+static irqreturn_t byt_irq_thread(int irq, void *context)
+{
+ struct snd_sof_dev *sdev = (struct snd_sof_dev *)context;
+ u64 ipcx, ipcd;
+ u64 imrx;
+
+ imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX);
+ ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
+
+ /* reply message from DSP */
+ if (ipcx & SHIM_BYT_IPCX_DONE &&
+ !(imrx & SHIM_IMRX_DONE)) {
+ /* Mask Done interrupt before first */
+ snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
+ SHIM_IMRX,
+ SHIM_IMRX_DONE,
+ SHIM_IMRX_DONE);
+ /*
+ * handle immediate reply from DSP core. If the msg is
+ * found, set done bit in cmd_done which is called at the
+ * end of message processing function, else set it here
+ * because the done bit can't be set in cmd_done function
+ * which is triggered by msg
+ */
+ if (snd_sof_ipc_reply(sdev, ipcx))
+ byt_cmd_done(sdev, SOF_IPC_DSP_REPLY);
+ }
+
+ /* new message from DSP */
+ ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
+ if (ipcd & SHIM_BYT_IPCD_BUSY &&
+ !(imrx & SHIM_IMRX_BUSY)) {
+ /* Mask Busy interrupt before return */
+ snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
+ SHIM_IMRX,
+ SHIM_IMRX_BUSY,
+ SHIM_IMRX_BUSY);
+
+ /* Handle messages from DSP Core */
+ if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
+ snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) +
+ MBOX_OFFSET);
+ } else {
+ snd_sof_ipc_msgs_rx(sdev);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int byt_is_ready(struct snd_sof_dev *sdev)
+{
+ u64 ipcx;
+
+ ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
+ if ((ipcx & SHIM_BYT_IPCX_BUSY) || (ipcx & SHIM_BYT_IPCX_DONE))
+ return 0;
+
+ return 1;
+}
+
+static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
+{
+ u64 cmd = msg->header;
+
+ /* send the message */
+ sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
+ msg->msg_size);
+ snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX,
+ cmd | SHIM_BYT_IPCX_BUSY);
+
+ return 0;
+}
+
+static int byt_get_reply(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
+{
+ struct sof_ipc_reply reply;
+ int ret = 0;
+ u32 size;
+
+ /* get reply */
+ sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
+ if (reply.error < 0) {
+ size = sizeof(reply);
+ ret = reply.error;
+ } else {
+ /* reply correct size ? */
+ if (reply.hdr.size != msg->reply_size) {
+ dev_err(sdev->dev, "error: reply expected 0x%zx got 0x%x bytes\n",
+ msg->reply_size, reply.hdr.size);
+ size = msg->reply_size;
+ ret = -EINVAL;
+ } else {
+ size = reply.hdr.size;
+ }
+ }
+
+ /* read the message */
+ if (msg->msg_data && size > 0)
+ sof_mailbox_read(sdev, sdev->host_box.offset, msg->reply_data,
+ size);
+
+ return ret;
+}
+
+static int byt_cmd_done(struct snd_sof_dev *sdev, int dir)
+{
+ if (dir == SOF_IPC_HOST_REPLY) {
+ /* clear BUSY bit and set DONE bit - accept new messages */
+ snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD,
+ SHIM_BYT_IPCD_BUSY |
+ SHIM_BYT_IPCD_DONE,
+ SHIM_BYT_IPCD_DONE);
+
+ /* unmask busy interrupt */
+ snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
+ SHIM_IMRX_BUSY, 0);
+ } else {
+ /* clear DONE bit - tell DSP we have completed */
+ snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX,
+ SHIM_BYT_IPCX_DONE, 0);
+
+ /* unmask Done interrupt */
+ snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
+ SHIM_IMRX_DONE, 0);
+ }
+
+ return 0;
+}
+
+/*
+ * DSP control.
+ */
+
+static int byt_run(struct snd_sof_dev *sdev)
+{
+ int tries = 10;
+
+ /* release stall and wait to unstall */
+ snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
+ SHIM_BYT_CSR_STALL, 0x0);
+ while (tries--) {
+ if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) &
+ SHIM_BYT_CSR_PWAITMODE))
+ break;
+ msleep(100);
+ }
+ if (tries < 0) {
+ dev_err(sdev->dev, "error: unable to run DSP firmware\n");
+ byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int byt_reset(struct snd_sof_dev *sdev)
+{
+ /* put DSP into reset, set reset vector and stall */
+ snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
+ SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
+ SHIM_BYT_CSR_STALL,
+ SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
+ SHIM_BYT_CSR_STALL);
+
+ usleep_range(10, 15);
+
+ /* take DSP out of reset and keep stalled for FW loading */
+ snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
+ SHIM_BYT_CSR_RST, 0);
+
+ return 0;
+}
+
+/*
+ * Probe and remove.
+ */
+
+static int byt_acpi_probe(struct snd_sof_dev *sdev)
+{
+ struct snd_sof_pdata *pdata = sdev->pdata;
+ const struct sof_dev_desc *desc = pdata->desc;
+ struct platform_device *pdev =
+ container_of(sdev->parent, struct platform_device, dev);
+ struct resource *mmio;
+ u32 base, size;
+ int ret = 0;
+
+ /* set DSP arch ops */
+ sdev->arch_ops = &sof_xtensa_arch_ops;
+
+ /* DSP DMA can only access low 31 bits of host memory */
+ ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
+ return ret;
+ }
+
+ /* LPE base */
+ mmio = platform_get_resource(pdev, IORESOURCE_MEM,
+ desc->resindex_lpe_base);
+ if (mmio) {
+ base = mmio->start;
+ size = resource_size(mmio);
+ } else {
+ dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
+ desc->resindex_lpe_base);
+ return -EINVAL;
+ }
+
+ dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
+ sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
+ if (!sdev->bar[BYT_DSP_BAR]) {
+ dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
+ base, size);
+ return -ENODEV;
+ }
+ dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
+
+ /* TODO: add offsets */
+ sdev->mmio_bar = BYT_DSP_BAR;
+ sdev->mailbox_bar = BYT_DSP_BAR;
+
+ /* IMR base - optional */
+ if (desc->resindex_imr_base == -1)
+ goto irq;
+
+ mmio = platform_get_resource(pdev, IORESOURCE_MEM,
+ desc->resindex_imr_base);
+ if (mmio) {
+ base = mmio->start;
+ size = resource_size(mmio);
+ } else {
+ dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
+ desc->resindex_imr_base);
+ return -ENODEV;
+ }
+
+ /* some BIOSes don't map IMR */
+ if (base == 0x55aa55aa || base == 0x0) {
+ dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
+ goto irq;
+ }
+
+ dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
+ sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
+ if (!sdev->bar[BYT_IMR_BAR]) {
+ dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
+ base, size);
+ return -ENODEV;
+ }
+ dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
+
+irq:
+ /* register our IRQ */
+ sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
+ if (sdev->ipc_irq < 0) {
+ dev_err(sdev->dev, "error: failed to get IRQ at index %d\n",
+ desc->irqindex_host_ipc);
+ return sdev->ipc_irq;
+ }
+
+ dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
+ ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
+ byt_irq_handler, byt_irq_thread,
+ IRQF_SHARED, "AudioDSP", sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to register IRQ %d\n",
+ sdev->ipc_irq);
+ return ret;
+ }
+
+ /* enable Interrupt from both sides */
+ snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0);
+ snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0);
+
+ /* set BARS */
+ sdev->cl_bar = BYT_DSP_BAR;
+
+ /* set default mailbox offset for FW ready message */
+ sdev->dsp_box.offset = MBOX_OFFSET;
+
+ return ret;
+}
+
+static int byt_pci_probe(struct snd_sof_dev *sdev)
+{
+ struct snd_sof_pdata *pdata = sdev->pdata;
+ const struct sof_dev_desc *desc = pdata->desc;
+ struct pci_dev *pci = sdev->pci;
+ u32 base, size;
+ int ret = 0;
+
+ /* DSP DMA can only access low 31 bits of host memory */
+ ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
+ return ret;
+ }
+
+ /* LPE base */
+ base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
+ size = BYT_PCI_BAR_SIZE;
+
+ dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
+ sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
+ if (!sdev->bar[BYT_DSP_BAR]) {
+ dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
+ base, size);
+ return -ENODEV;
+ }
+ dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
+
+ /* IMR base - optional */
+ if (desc->resindex_imr_base == -1)
+ goto irq;
+
+ base = pci_resource_start(pci, desc->resindex_imr_base);
+ size = pci_resource_len(pci, desc->resindex_imr_base);
+
+ /* some BIOSes don't map IMR */
+ if (base == 0x55aa55aa || base == 0x0) {
+ dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
+ goto irq;
+ }
+
+ dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
+ sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
+ if (!sdev->bar[BYT_IMR_BAR]) {
+ dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
+ base, size);
+ return -ENODEV;
+ }
+ dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
+
+irq:
+ /* register our IRQ */
+ sdev->ipc_irq = pci->irq;
+ dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
+ ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
+ byt_irq_handler, byt_irq_thread,
+ 0, "AudioDSP", sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to register IRQ %d\n",
+ sdev->ipc_irq);
+ return ret;
+ }
+
+ /* enable Interrupt from both sides */
+ snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0);
+ snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0);
+
+ /* set BARS */
+ sdev->cl_bar = BYT_DSP_BAR;
+
+ /* set default mailbox offset for FW ready message */
+ sdev->dsp_box.offset = MBOX_OFFSET;
+
+ return ret;
+}
+
+static int byt_probe(struct snd_sof_dev *sdev)
+{
+ if (sdev->pci)
+ return byt_pci_probe(sdev);
+
+ return byt_acpi_probe(sdev);
+}
+
+#define BYT_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+/* Baytrail DAIs */
+static struct snd_soc_dai_driver byt_dai[] = {
+{
+ .name = "ssp0-port",
+ .playback = SOF_DAI_STREAM("ssp0 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp0 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+},
+{
+ .name = "ssp1-port",
+ .playback = SOF_DAI_STREAM("ssp1 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp1 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+},
+{
+ .name = "ssp2-port",
+ .playback = SOF_DAI_STREAM("ssp2 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp2 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+},
+{
+ .name = "ssp3-port",
+ .playback = SOF_DAI_STREAM("ssp3 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp3 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+},
+{
+ .name = "ssp4-port",
+ .playback = SOF_DAI_STREAM("ssp4 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp4 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+},
+{
+ .name = "ssp5-port",
+ .playback = SOF_DAI_STREAM("ssp5 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp5 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BYT_FORMATS),
+},
+};
+
+/* baytrail ops */
+struct snd_sof_dsp_ops sof_byt_ops = {
+ /* device init */
+ .probe = byt_probe,
+
+ /* DSP core boot / reset */
+ .run = byt_run,
+ .reset = byt_reset,
+
+ /* Register IO */
+ .write = sof_io_write,
+ .read = sof_io_read,
+ .write64 = sof_io_write64,
+ .read64 = sof_io_read64,
+
+ /* Block IO */
+ .block_read = sof_block_read,
+ .block_write = sof_block_write,
+
+ /* doorbell */
+ .irq_handler = byt_irq_handler,
+ .irq_thread = byt_irq_thread,
+
+ /* mailbox */
+ .mailbox_read = sof_mailbox_read,
+ .mailbox_write = sof_mailbox_write,
+
+ /* ipc */
+ .send_msg = byt_send_msg,
+ .get_reply = byt_get_reply,
+ .fw_ready = byt_fw_ready,
+ .is_ready = byt_is_ready,
+ .cmd_done = byt_cmd_done,
+
+ /* debug */
+ .debug_map = byt_debugfs,
+ .debug_map_count = ARRAY_SIZE(byt_debugfs),
+ .dbg_dump = byt_dump,
+
+ /* module loading */
+ .load_module = snd_sof_parse_module_memcpy,
+
+ /*Firmware loading */
+ .load_firmware = snd_sof_load_firmware_memcpy,
+
+ /* DAI drivers */
+ .drv = byt_dai,
+ .num_drv = 3, /* we have only 3 SSPs on byt*/
+};
+EXPORT_SYMBOL(sof_byt_ops);
+
+/* cherrytrail and braswell ops */
+struct snd_sof_dsp_ops sof_cht_ops = {
+ /* device init */
+ .probe = byt_probe,
+
+ /* DSP core boot / reset */
+ .run = byt_run,
+ .reset = byt_reset,
+
+ /* Register IO */
+ .write = sof_io_write,
+ .read = sof_io_read,
+ .write64 = sof_io_write64,
+ .read64 = sof_io_read64,
+
+ /* Block IO */
+ .block_read = sof_block_read,
+ .block_write = sof_block_write,
+
+ /* doorbell */
+ .irq_handler = byt_irq_handler,
+ .irq_thread = byt_irq_thread,
+
+ /* mailbox */
+ .mailbox_read = sof_mailbox_read,
+ .mailbox_write = sof_mailbox_write,
+
+ /* ipc */
+ .send_msg = byt_send_msg,
+ .get_reply = byt_get_reply,
+ .fw_ready = byt_fw_ready,
+ .is_ready = byt_is_ready,
+ .cmd_done = byt_cmd_done,
+
+ /* debug */
+ .debug_map = cht_debugfs,
+ .debug_map_count = ARRAY_SIZE(cht_debugfs),
+ .dbg_dump = byt_dump,
+
+ /* module loading */
+ .load_module = snd_sof_parse_module_memcpy,
+
+ /*Firmware loading */
+ .load_firmware = snd_sof_load_firmware_memcpy,
+
+ /* DAI drivers */
+ .drv = byt_dai,
+ /* all 6 SSPs may be available for cherrytrail */
+ .num_drv = ARRAY_SIZE(byt_dai),
+};
+EXPORT_SYMBOL(sof_cht_ops);
+
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
new file mode 100644
index 000000000000..2fdcb2d262f4
--- /dev/null
+++ b/sound/soc/sof/intel/shim.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ */
+
+#ifndef __SOF_INTEL_SHIM_H
+#define __SOF_INTEL_SHIM_H
+
+/*
+ * SHIM registers for BYT, BSW, CHT, HSW, BDW
+ */
+
+#define SHIM_CSR (SHIM_OFFSET + 0x00)
+#define SHIM_PISR (SHIM_OFFSET + 0x08)
+#define SHIM_PIMR (SHIM_OFFSET + 0x10)
+#define SHIM_ISRX (SHIM_OFFSET + 0x18)
+#define SHIM_ISRD (SHIM_OFFSET + 0x20)
+#define SHIM_IMRX (SHIM_OFFSET + 0x28)
+#define SHIM_IMRD (SHIM_OFFSET + 0x30)
+#define SHIM_IPCX (SHIM_OFFSET + 0x38)
+#define SHIM_IPCD (SHIM_OFFSET + 0x40)
+#define SHIM_ISRSC (SHIM_OFFSET + 0x48)
+#define SHIM_ISRLPESC (SHIM_OFFSET + 0x50)
+#define SHIM_IMRSC (SHIM_OFFSET + 0x58)
+#define SHIM_IMRLPESC (SHIM_OFFSET + 0x60)
+#define SHIM_IPCSC (SHIM_OFFSET + 0x68)
+#define SHIM_IPCLPESC (SHIM_OFFSET + 0x70)
+#define SHIM_CLKCTL (SHIM_OFFSET + 0x78)
+#define SHIM_CSR2 (SHIM_OFFSET + 0x80)
+#define SHIM_LTRC (SHIM_OFFSET + 0xE0)
+#define SHIM_HMDC (SHIM_OFFSET + 0xE8)
+
+#define SHIM_PWMCTRL 0x1000
+
+/*
+ * SST SHIM register bits for BYT, BSW, CHT HSW, BDW
+ * Register bit naming and functionaility can differ between devices.
+ */
+
+/* CSR / CS */
+#define SHIM_CSR_RST BIT(1)
+#define SHIM_CSR_SBCS0 BIT(2)
+#define SHIM_CSR_SBCS1 BIT(3)
+#define SHIM_CSR_DCS(x) ((x) << 4)
+#define SHIM_CSR_DCS_MASK (0x7 << 4)
+#define SHIM_CSR_STALL BIT(10)
+#define SHIM_CSR_S0IOCS BIT(21)
+#define SHIM_CSR_S1IOCS BIT(23)
+#define SHIM_CSR_LPCS BIT(31)
+#define SHIM_CSR_24MHZ_LPCS \
+ (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
+#define SHIM_CSR_24MHZ_NO_LPCS (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
+#define SHIM_BYT_CSR_RST BIT(0)
+#define SHIM_BYT_CSR_VECTOR_SEL BIT(1)
+#define SHIM_BYT_CSR_STALL BIT(2)
+#define SHIM_BYT_CSR_PWAITMODE BIT(3)
+
+/* ISRX / ISC */
+#define SHIM_ISRX_BUSY BIT(1)
+#define SHIM_ISRX_DONE BIT(0)
+#define SHIM_BYT_ISRX_REQUEST BIT(1)
+
+/* ISRD / ISD */
+#define SHIM_ISRD_BUSY BIT(1)
+#define SHIM_ISRD_DONE BIT(0)
+
+/* IMRX / IMC */
+#define SHIM_IMRX_BUSY BIT(1)
+#define SHIM_IMRX_DONE BIT(0)
+#define SHIM_BYT_IMRX_REQUEST BIT(1)
+
+/* IMRD / IMD */
+#define SHIM_IMRD_DONE BIT(0)
+#define SHIM_IMRD_BUSY BIT(1)
+#define SHIM_IMRD_SSP0 BIT(16)
+#define SHIM_IMRD_DMAC0 BIT(21)
+#define SHIM_IMRD_DMAC1 BIT(22)
+#define SHIM_IMRD_DMAC (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
+
+/* IPCX / IPCC */
+#define SHIM_IPCX_DONE BIT(30)
+#define SHIM_IPCX_BUSY BIT(31)
+#define SHIM_BYT_IPCX_DONE BIT_ULL(62)
+#define SHIM_BYT_IPCX_BUSY BIT_ULL(63)
+
+/* IPCD */
+#define SHIM_IPCD_DONE BIT(30)
+#define SHIM_IPCD_BUSY BIT(31)
+#define SHIM_BYT_IPCD_DONE BIT_ULL(62)
+#define SHIM_BYT_IPCD_BUSY BIT_ULL(63)
+
+/* CLKCTL */
+#define SHIM_CLKCTL_SMOS(x) ((x) << 24)
+#define SHIM_CLKCTL_MASK (3 << 24)
+#define SHIM_CLKCTL_DCPLCG BIT(18)
+#define SHIM_CLKCTL_SCOE1 BIT(17)
+#define SHIM_CLKCTL_SCOE0 BIT(16)
+
+/* CSR2 / CS2 */
+#define SHIM_CSR2_SDFD_SSP0 BIT(1)
+#define SHIM_CSR2_SDFD_SSP1 BIT(2)
+
+/* LTRC */
+#define SHIM_LTRC_VAL(x) ((x) << 0)
+
+/* HMDC */
+#define SHIM_HMDC_HDDA0(x) ((x) << 0)
+#define SHIM_HMDC_HDDA1(x) ((x) << 7)
+#define SHIM_HMDC_HDDA_E0_CH0 1
+#define SHIM_HMDC_HDDA_E0_CH1 2
+#define SHIM_HMDC_HDDA_E0_CH2 4
+#define SHIM_HMDC_HDDA_E0_CH3 8
+#define SHIM_HMDC_HDDA_E1_CH0 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0)
+#define SHIM_HMDC_HDDA_E1_CH1 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1)
+#define SHIM_HMDC_HDDA_E1_CH2 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2)
+#define SHIM_HMDC_HDDA_E1_CH3 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3)
+#define SHIM_HMDC_HDDA_E0_ALLCH \
+ (SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \
+ SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3)
+#define SHIM_HMDC_HDDA_E1_ALLCH \
+ (SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \
+ SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3)
+
+/* Audio DSP PCI registers */
+#define PCI_VDRTCTL0 0xa0
+#define PCI_VDRTCTL1 0xa4
+#define PCI_VDRTCTL2 0xa8
+#define PCI_VDRTCTL3 0xaC
+
+/* VDRTCTL0 */
+#define PCI_VDRTCL0_D3PGD BIT(0)
+#define PCI_VDRTCL0_D3SRAMPGD BIT(1)
+#define PCI_VDRTCL0_DSRAMPGE_SHIFT 12
+#define PCI_VDRTCL0_DSRAMPGE_MASK GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
+ PCI_VDRTCL0_DSRAMPGE_SHIFT)
+#define PCI_VDRTCL0_ISRAMPGE_SHIFT 2
+#define PCI_VDRTCL0_ISRAMPGE_MASK GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
+ PCI_VDRTCL0_ISRAMPGE_SHIFT)
+
+/* VDRTCTL2 */
+#define PCI_VDRTCL2_DCLCGE BIT(1)
+#define PCI_VDRTCL2_DTCGE BIT(10)
+#define PCI_VDRTCL2_APLLSE_MASK BIT(31)
+
+/* PMCS */
+#define PCI_PMCS 0x84
+#define PCI_PMCS_PS_MASK 0x3
+
+extern struct snd_sof_dsp_ops sof_byt_ops;
+extern struct snd_sof_dsp_ops sof_cht_ops;
+extern struct snd_sof_dsp_ops sof_hsw_ops;
+extern struct snd_sof_dsp_ops sof_bdw_ops;
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2018-12-11 21:30 ` [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support Pierre-Louis Bossart
@ 2018-12-12 4:08 ` Takashi Sakamoto
2018-12-12 14:45 ` Pierre-Louis Bossart
[not found] ` <b8db627a-bd32-34d7-b45b-aeb2206b2b17@linux.intel.com>
2019-01-18 8:14 ` Daniel Baluta
2019-01-22 7:35 ` Daniel Baluta
2 siblings, 2 replies; 37+ messages in thread
From: Takashi Sakamoto @ 2018-12-12 4:08 UTC (permalink / raw)
To: Pierre-Louis Bossart, alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pan Xiuli,
liam.r.girdwood, vkoul, broonie, sound-open-firmware,
Rander Wang, Alan Cox
Hi,
I have small nitpicking.
On 2018/12/12 6:30, Pierre-Louis Bossart wrote:
> From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
>
> Add support for the audio DSP hardware found on Intel Baytrail,
> Cherrytrail and Braswell based devices.
>
> Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
> Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
> Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
> ---
> sound/soc/sof/intel/byt.c | 805 +++++++++++++++++++++++++++++++++++++
> sound/soc/sof/intel/shim.h | 159 ++++++++
> 2 files changed, 964 insertions(+)
> create mode 100644 sound/soc/sof/intel/byt.c
> create mode 100644 sound/soc/sof/intel/shim.h
> ..
> diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
> new file mode 100644
> index 000000000000..2fdcb2d262f4
> --- /dev/null
> +++ b/sound/soc/sof/intel/shim.h
> @@ -0,0 +1,159 @@
> ...
> +extern struct snd_sof_dsp_ops sof_byt_ops;
> +extern struct snd_sof_dsp_ops sof_cht_ops;
These two symbols are found in this patch.
> +extern struct snd_sof_dsp_ops sof_hsw_ops;
This symbol is added in second patch and this first patch has
no reference to it.
> +extern struct snd_sof_dsp_ops sof_bdw_ops;
This symbol is added in third patch and this first patch has
no reference to it.
> +
> +#endif
I think it better to add these extern declarations when adding
corresponding symbols (Of course no issues as is).
Furthermore, if you have no plan to change contents of these symbols in
kernel run time, it's better to have 'const' qualifier to locate the
symbol to readonly section. However, user of these symbols is machine
driver and you have a plan to implement it later. They can get 'const'
when you work for arrangement of existent/new codes.
In this meaning, it might be good to add a new member to 'struct
snd_soc_acpi_mach' for new drivers to refer to the const ops, then
'pdata' member is used from the existent drivers.
Regards
Takashi Sakamoto
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2018-12-12 4:08 ` Takashi Sakamoto
@ 2018-12-12 14:45 ` Pierre-Louis Bossart
2018-12-12 19:24 ` [Sound-open-firmware] " Pierre-Louis Bossart
[not found] ` <b8db627a-bd32-34d7-b45b-aeb2206b2b17@linux.intel.com>
1 sibling, 1 reply; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-12 14:45 UTC (permalink / raw)
To: Takashi Sakamoto, alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pan Xiuli,
liam.r.girdwood, vkoul, broonie, Alan Cox, Rander Wang,
sound-open-firmware
Thanks for the review.
>> +++ b/sound/soc/sof/intel/shim.h
>> @@ -0,0 +1,159 @@
>> ...
>> +extern struct snd_sof_dsp_ops sof_byt_ops;
>> +extern struct snd_sof_dsp_ops sof_cht_ops;
>
> These two symbols are found in this patch.
>
>> +extern struct snd_sof_dsp_ops sof_hsw_ops;
>
> This symbol is added in second patch and this first patch has
> no reference to it.
>
>> +extern struct snd_sof_dsp_ops sof_bdw_ops;
>
> This symbol is added in third patch and this first patch has
> no reference to it.
>
>> +
>> +#endif
>
> I think it better to add these extern declarations when adding
> corresponding symbols (Of course no issues as is).
Yes, that's no big deal. It won't break as is though since the build is
added in the last patch.
>
> Furthermore, if you have no plan to change contents of these symbols in
> kernel run time, it's better to have 'const' qualifier to locate the
> symbol to readonly section. However, user of these symbols is machine
> driver and you have a plan to implement it later. They can get 'const'
> when you work for arrangement of existent/new codes.
Good point, I don't think the ops are changed, ever. I'll double-check
and change if indeed this is the case, thanks for the suggestion.
>
> In this meaning, it might be good to add a new member to 'struct
> snd_soc_acpi_mach' for new drivers to refer to the const ops, then
> 'pdata' member is used from the existent drivers.
Sorry, I don't get your point. the ops structure is included in the
sof_ops_table, not the snd_soc_acpi_mach.
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [Sound-open-firmware] [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2018-12-12 14:45 ` Pierre-Louis Bossart
@ 2018-12-12 19:24 ` Pierre-Louis Bossart
0 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-12 19:24 UTC (permalink / raw)
To: Takashi Sakamoto, alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pan Xiuli,
liam.r.girdwood, vkoul, broonie, sound-open-firmware,
Rander Wang, Alan Cox
>>
>> Furthermore, if you have no plan to change contents of these symbols in
>> kernel run time, it's better to have 'const' qualifier to locate the
>> symbol to readonly section. However, user of these symbols is machine
>> driver and you have a plan to implement it later. They can get 'const'
>> when you work for arrangement of existent/new codes.
> Good point, I don't think the ops are changed, ever. I'll double-check
> and change if indeed this is the case, thanks for the suggestion.
>>
>> In this meaning, it might be good to add a new member to 'struct
>> snd_soc_acpi_mach' for new drivers to refer to the const ops, then
>> 'pdata' member is used from the existent drivers.
> Sorry, I don't get your point. the ops structure is included in the
> sof_ops_table, not the snd_soc_acpi_mach.
I get your point now, after moving all the ops to a const qualifier, I
still have the 3 errors below. We should indeed have an ops field in the
generic acpi structure, excellent suggestion. This change also helped
identify that we have redundant/hidden declarations in hda.c, so we can
improve the code further.
I'll do that at a later point though since it will impact 2 other
drivers, for now I'll mark these as TODO with an explicit cast.
Thanks again for your feedback
-Pierre
sound/soc/sof/sof-acpi-dev.c: In function ‘sof_acpi_probe’:
sound/soc/sof/sof-acpi-dev.c:200:14: warning: assignment discards
‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
mach->pdata = ops;
^
CC [M] sound/soc/sof/sof-pci-dev.o
sound/soc/sof/sof-pci-dev.c: In function ‘sof_pci_probe’:
sound/soc/sof/sof-pci-dev.c:247:14: warning: assignment discards ‘const’
qualifier from pointer target type [-Wdiscarded-qualifiers]
mach->pdata = ops;
^
CC [M] sound/soc/sof/sof-spi-dev.o
sound/soc/sof/sof-spi-dev.c: In function ‘sof_spi_probe’:
sound/soc/sof/sof-spi-dev.c:119:14: warning: assignment discards ‘const’
qualifier from pointer target type [-Wdiscarded-qualifiers]
mach->pdata = sof_get_ops(desc, spi_mach_ops, ARRAY_SIZE(spi_mach_ops));
_______________________________________________
Alsa-devel mailing list
Alsa-devel@alsa-project.org
http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
^ permalink raw reply [flat|nested] 37+ messages in thread
[parent not found: <b8db627a-bd32-34d7-b45b-aeb2206b2b17@linux.intel.com>]
* Re: [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
[not found] ` <b8db627a-bd32-34d7-b45b-aeb2206b2b17@linux.intel.com>
@ 2018-12-17 13:40 ` Yang, Libin
0 siblings, 0 replies; 37+ messages in thread
From: Yang, Libin @ 2018-12-17 13:40 UTC (permalink / raw)
To: o-takashi, pierre-louis.bossart, alsa-devel
Cc: daniel.baluta, Shevchenko, Andriy, tiwai, xiuli.pan,
liam.r.girdwood, vkoul, broonie, alan, rander.wang,
sound-open-firmware
Hi Sakamoto,
>
>-------- Forwarded Message --------
>Subject: Re: [alsa-devel] [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and
>BSW DSP HW support.
>Date: Wed, 12 Dec 2018 13:08:48 +0900
>From: Takashi Sakamoto <o-takashi@sakamocchi.jp>
>To: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>,
>alsa-devel@alsa-project.org
>CC: Daniel Baluta <daniel.baluta@gmail.com>, andriy.shevchenko@intel.com,
>tiwai@suse.de, Pan Xiuli <xiuli.pan@linux.intel.com>,
>liam.r.girdwood@linux.intel.com, vkoul@kernel.org, broonie@kernel.org,
>sound-open-firmware@alsa-project.org, Rander Wang
><rander.wang@linux.intel.com>, Alan Cox <alan@linux.intel.com>
>
>Hi,
>
>I have small nitpicking.
>
>On 2018/12/12 6:30, Pierre-Louis Bossart wrote:
>> From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
>>
>> Add support for the audio DSP hardware found on Intel Baytrail,
>> Cherrytrail and Braswell based devices.
>>
>> Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
>> Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
>> Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
>> Signed-off-by: Pierre-Louis Bossart
>> <pierre-louis.bossart@linux.intel.com>
>> ---
>> sound/soc/sof/intel/byt.c | 805
>+++++++++++++++++++++++++++++++++++++
>> sound/soc/sof/intel/shim.h | 159 ++++++++
>> 2 files changed, 964 insertions(+)
>> create mode 100644 sound/soc/sof/intel/byt.c
>> create mode 100644 sound/soc/sof/intel/shim.h ..
>> diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
>> new file mode 100644 index 000000000000..2fdcb2d262f4
>> --- /dev/null
>> +++ b/sound/soc/sof/intel/shim.h
>> @@ -0,0 +1,159 @@
>> ...
>> +extern struct snd_sof_dsp_ops sof_byt_ops; extern struct
>> +snd_sof_dsp_ops sof_cht_ops;
>
>These two symbols are found in this patch.
>
>> +extern struct snd_sof_dsp_ops sof_hsw_ops;
>
>This symbol is added in second patch and this first patch has no reference to it.
>
>> +extern struct snd_sof_dsp_ops sof_bdw_ops;
>
>This symbol is added in third patch and this first patch has no reference to it.
>
>> +
>> +#endif
>
>I think it better to add these extern declarations when adding corresponding
>symbols (Of course no issues as is).
>
>Furthermore, if you have no plan to change contents of these symbols in
>kernel run time, it's better to have 'const' qualifier to locate the symbol to
>readonly section. However, user of these symbols is machine driver and you
>have a plan to implement it later. They can get 'const'
>when you work for arrangement of existent/new codes.
>
>In this meaning, it might be good to add a new member to 'struct
>snd_soc_acpi_mach' for new drivers to refer to the const ops, then 'pdata'
>member is used from the existent drivers.
I made a patch based on your suggestion. Could you please help review
to see if my understanding is right?
https://github.com/thesofproject/linux/pull/457
Regards,
Libin
>
>
>Regards
>
>Takashi Sakamoto
>_______________________________________________
>Alsa-devel mailing list
>Alsa-devel@alsa-project.org
>http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2018-12-11 21:30 ` [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support Pierre-Louis Bossart
2018-12-12 4:08 ` Takashi Sakamoto
@ 2019-01-18 8:14 ` Daniel Baluta
2019-01-18 15:02 ` [Sound-open-firmware] " Pierre-Louis Bossart
2019-01-22 7:35 ` Daniel Baluta
2 siblings, 1 reply; 37+ messages in thread
From: Daniel Baluta @ 2019-01-18 8:14 UTC (permalink / raw)
To: Pierre-Louis Bossart
Cc: Linux-ALSA, andriy.shevchenko, Takashi Iwai, Pan Xiuli,
Liam Girdwood, vkoul, Mark Brown, Alan Cox, Rander Wang,
sound-open-firmware
Hi Pierre,
<snip>
> +/* cherrytrail and braswell ops */
> +struct snd_sof_dsp_ops sof_cht_ops = {
> + /* device init */
> + .probe = byt_probe,
> +
> + /* DSP core boot / reset */
> + .run = byt_run,
> + .reset = byt_reset,
> +
> + /* Register IO */
> + .write = sof_io_write,
> + .read = sof_io_read,
> + .write64 = sof_io_write64,
> + .read64 = sof_io_read64,
> +
> + /* Block IO */
> + .block_read = sof_block_read,
> + .block_write = sof_block_write,
> +
> + /* doorbell */
> + .irq_handler = byt_irq_handler,
> + .irq_thread = byt_irq_thread,
> +
What is the reason for having irq_handler/irq_thread functions inside the
snd_sof_dsp_ops structure?
These functions are never used outside via sdev->ops pointer.
thanks,
Daniel.
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [Sound-open-firmware] [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2019-01-18 8:14 ` Daniel Baluta
@ 2019-01-18 15:02 ` Pierre-Louis Bossart
2019-01-18 15:29 ` Daniel Baluta
0 siblings, 1 reply; 37+ messages in thread
From: Pierre-Louis Bossart @ 2019-01-18 15:02 UTC (permalink / raw)
To: Daniel Baluta
Cc: Linux-ALSA, andriy.shevchenko, Takashi Iwai, Pan Xiuli,
Liam Girdwood, vkoul, Mark Brown, sound-open-firmware,
Rander Wang, Alan Cox
>> +struct snd_sof_dsp_ops sof_cht_ops = {
>> + /* device init */
>> + .probe = byt_probe,
>> +
>> + /* DSP core boot / reset */
>> + .run = byt_run,
>> + .reset = byt_reset,
>> +
>> + /* Register IO */
>> + .write = sof_io_write,
>> + .read = sof_io_read,
>> + .write64 = sof_io_write64,
>> + .read64 = sof_io_read64,
>> +
>> + /* Block IO */
>> + .block_read = sof_block_read,
>> + .block_write = sof_block_write,
>> +
>> + /* doorbell */
>> + .irq_handler = byt_irq_handler,
>> + .irq_thread = byt_irq_thread,
>> +
> What is the reason for having irq_handler/irq_thread functions inside the
> snd_sof_dsp_ops structure?
>
> These functions are never used outside via sdev->ops pointer.
Good point indeed, thanks for raising it. We were in the middle of
tagging which ops are required/optional (feedback from Mark) but we
started from the core and should have looked at the structure definition.
Most drivers are "self-contained" and can reference the irq_thread and
irq_handler directly.
The exception where the abstraction is used is internal to the HDaudio
stuff:
intel/hda.c: ret = request_threaded_irq(sdev->ipc_irq,
hda_dsp_ipc_irq_handler,
intel/hda.c: sof_ops(sdev)->irq_thread, IRQF_SHARED,
That's useful since there a minor variations between hardware
generations and you want to hide the hardware-specific parts.
But as you point out, it's a "private" use of ops callbacks, the core
doesn't touch this.
I have no explanation other than legacy/historical reasons or a shortcut
to make one's life easier during development. Liam and Keyon might know?
We could try and move this to a more "private" structure, the
"chip_info" part might be more suitable for this?
_______________________________________________
Alsa-devel mailing list
Alsa-devel@alsa-project.org
http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [Sound-open-firmware] [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2019-01-18 15:02 ` [Sound-open-firmware] " Pierre-Louis Bossart
@ 2019-01-18 15:29 ` Daniel Baluta
2019-01-18 16:14 ` Pierre-Louis Bossart
0 siblings, 1 reply; 37+ messages in thread
From: Daniel Baluta @ 2019-01-18 15:29 UTC (permalink / raw)
To: Pierre-Louis Bossart
Cc: Linux-ALSA, andriy.shevchenko, Takashi Iwai, Pan Xiuli,
Liam Girdwood, vkoul, Mark Brown, sound-open-firmware,
Rander Wang, Alan Cox
On Fri, Jan 18, 2019 at 5:03 PM Pierre-Louis Bossart
<pierre-louis.bossart@linux.intel.com> wrote:
>
>
> >> +struct snd_sof_dsp_ops sof_cht_ops = {
> >> + /* device init */
> >> + .probe = byt_probe,
> >> +
> >> + /* DSP core boot / reset */
> >> + .run = byt_run,
> >> + .reset = byt_reset,
> >> +
> >> + /* Register IO */
> >> + .write = sof_io_write,
> >> + .read = sof_io_read,
> >> + .write64 = sof_io_write64,
> >> + .read64 = sof_io_read64,
> >> +
> >> + /* Block IO */
> >> + .block_read = sof_block_read,
> >> + .block_write = sof_block_write,
> >> +
> >> + /* doorbell */
> >> + .irq_handler = byt_irq_handler,
> >> + .irq_thread = byt_irq_thread,
> >> +
> > What is the reason for having irq_handler/irq_thread functions inside the
> > snd_sof_dsp_ops structure?
> >
> > These functions are never used outside via sdev->ops pointer.
>
> Good point indeed, thanks for raising it. We were in the middle of
> tagging which ops are required/optional (feedback from Mark) but we
> started from the core and should have looked at the structure definition.
>
> Most drivers are "self-contained" and can reference the irq_thread and
> irq_handler directly.
>
> The exception where the abstraction is used is internal to the HDaudio
> stuff:
>
> intel/hda.c: ret = request_threaded_irq(sdev->ipc_irq,
> hda_dsp_ipc_irq_handler,
> intel/hda.c: sof_ops(sdev)->irq_thread, IRQF_SHARED,
>
> That's useful since there a minor variations between hardware
> generations and you want to hide the hardware-specific parts.
>
> But as you point out, it's a "private" use of ops callbacks, the core
> doesn't touch this.
>
> I have no explanation other than legacy/historical reasons or a shortcut
> to make one's life easier during development. Liam and Keyon might know?
>
> We could try and move this to a more "private" structure, the
> "chip_info" part might be more suitable for this?
I have no preference over this, I was just confused and wanting to
know if one will use
these members in the future.
We can either move them to a more private structure or at least have a
comment saying that
these will not be used by the core.
I have few things to bring into discussion now, perhaps you can comment on it.
Firstly, we might want to look at the mailbox controller
(drivers/mailbox/mailbox.c).
It looks like the communication from AP (application processor) and
the DSP uses shim + mailbox
in Intel implementation, which could be abstracted by a mailbox client.
The confusing part here is the naming. In the Linux kernel the shim
layer you use is abstracted
by the mailbox controller, while mailbox from Intel implementation is
really a shared memory area.
We have this already implemented for our mailbox (Messaging Unit) in
drivers/mailbox/imx-mailbox.c and
trying to integrate with SOF.
So, for IPC we have the following "naming" differences:
* imx mailbox MU - equivalent with SHIM layer from Intel SOF.
* imx shared memory - equivalent with mailbox layer from Intel SOF.
Secondly, the "doorbell" naming of the interrupts. It surely looks
like a doorbell because we notify the
DSP that we pushed some data in a shared memory area. Anyhow, besides
pushing data to the shared
memory area we also send some data with the notification too.
For example, in byt_send_msg we do:
sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, msg->msg_size);
snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, cmd | SHIM_BYT_IPCX_BUSY);
Not sure how cmd is used on the DSP side. Anyhow, this is not really
important for the next version
of the patches. Just wanted to hear your opinion.
thanks,
Daniel.
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [Sound-open-firmware] [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2019-01-18 15:29 ` Daniel Baluta
@ 2019-01-18 16:14 ` Pierre-Louis Bossart
0 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2019-01-18 16:14 UTC (permalink / raw)
To: Daniel Baluta
Cc: Linux-ALSA, andriy.shevchenko, Takashi Iwai, Pan Xiuli,
Liam Girdwood, vkoul, Mark Brown, sound-open-firmware,
Rander Wang, Alan Cox
> I have few things to bring into discussion now, perhaps you can comment on it.
>
> Firstly, we might want to look at the mailbox controller
> (drivers/mailbox/mailbox.c).
> It looks like the communication from AP (application processor) and
> the DSP uses shim + mailbox
> in Intel implementation, which could be abstracted by a mailbox client.
>
> The confusing part here is the naming. In the Linux kernel the shim
> layer you use is abstracted
> by the mailbox controller, while mailbox from Intel implementation is
> really a shared memory area.
>
> We have this already implemented for our mailbox (Messaging Unit) in
> drivers/mailbox/imx-mailbox.c and
> trying to integrate with SOF.
>
> So, for IPC we have the following "naming" differences:
> * imx mailbox MU - equivalent with SHIM layer from Intel SOF.
> * imx shared memory - equivalent with mailbox layer from Intel SOF.
the "shim" on the intel side is a mix of control capabilities. There are
indeed IPC registers in there, but also clock, DMA and power control
capabilities. I am not sure we can really remove direct access to the
shim, it's really the host-visible set of DSP registers.
We'll look at the pointer to the i.mx mailbox, thanks for the information.
>
> Secondly, the "doorbell" naming of the interrupts. It surely looks
> like a doorbell because we notify the
> DSP that we pushed some data in a shared memory area. Anyhow, besides
> pushing data to the shared
> memory area we also send some data with the notification too.
>
> For example, in byt_send_msg we do:
>
> sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, msg->msg_size);
> snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, cmd | SHIM_BYT_IPCX_BUSY);
>
> Not sure how cmd is used on the DSP side. Anyhow, this is not really
> important for the next version
> of the patches. Just wanted to hear your opinion.
Humm, that one looks like an exception as well, it makes no sense. This
is over a year old. Liam, any memories of this?
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2018-12-11 21:30 ` [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support Pierre-Louis Bossart
2018-12-12 4:08 ` Takashi Sakamoto
2019-01-18 8:14 ` Daniel Baluta
@ 2019-01-22 7:35 ` Daniel Baluta
2019-01-22 16:22 ` Pierre-Louis Bossart
2 siblings, 1 reply; 37+ messages in thread
From: Daniel Baluta @ 2019-01-22 7:35 UTC (permalink / raw)
To: Pierre-Louis Bossart
Cc: Linux-ALSA, andriy.shevchenko, Takashi Iwai, Pan Xiuli,
Liam Girdwood, Vinod Koul, Mark Brown, Alan Cox, Rander Wang,
sound-open-firmware
> +static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
> +{
> + u64 cmd = msg->header;
> +
> + /* send the message */
> + sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
> + msg->msg_size);
I was wondering if the mailbox shared memory wouldn't be better
implemented as a queue.
Do you support playing multiple streams in parallel?
We have this use case where we need to to memory to memory
decoding/encoding with lots
of streams in parallel.
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2019-01-22 7:35 ` Daniel Baluta
@ 2019-01-22 16:22 ` Pierre-Louis Bossart
2019-01-22 16:49 ` Daniel Baluta
0 siblings, 1 reply; 37+ messages in thread
From: Pierre-Louis Bossart @ 2019-01-22 16:22 UTC (permalink / raw)
To: Daniel Baluta
Cc: Linux-ALSA, andriy.shevchenko, Takashi Iwai, Pan Xiuli,
Liam Girdwood, Vinod Koul, Mark Brown, Alan Cox, Rander Wang,
sound-open-firmware
On 1/22/19 1:35 AM, Daniel Baluta wrote:
>> +static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
>> +{
>> + u64 cmd = msg->header;
>> +
>> + /* send the message */
>> + sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
>> + msg->msg_size);
> I was wondering if the mailbox shared memory wouldn't be better
> implemented as a queue.
> Do you support playing multiple streams in parallel?
>
> We have this use case where we need to to memory to memory
> decoding/encoding with lots
> of streams in parallel.
Sorry Daniel, I didn't get your point.
we do support multiple streams in parallel and there's been quite a few
issues fixed in the IPC mechanisms due to concurrency. The IPC mechanism
is serialized however since there are only few resources available,
typically only a couple of doorbell registers and a small memory window.
For multiple streams the PCM data is exchanged over DMA typically - the
streams don't go over the IPC channel but the information related to a
stream is passed using a tag or ID.
Can you clarify what you had in mind?
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
2019-01-22 16:22 ` Pierre-Louis Bossart
@ 2019-01-22 16:49 ` Daniel Baluta
0 siblings, 0 replies; 37+ messages in thread
From: Daniel Baluta @ 2019-01-22 16:49 UTC (permalink / raw)
To: Pierre-Louis Bossart
Cc: Linux-ALSA, andriy.shevchenko, Takashi Iwai, S.j. Wang,
Pan Xiuli, Liam Girdwood, Vinod Koul, Mark Brown, Alan Cox,
Rander Wang, sound-open-firmware
On Tue, Jan 22, 2019 at 6:22 PM Pierre-Louis Bossart
<pierre-louis.bossart@linux.intel.com> wrote:
>
>
> On 1/22/19 1:35 AM, Daniel Baluta wrote:
> >> +static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
> >> +{
> >> + u64 cmd = msg->header;
> >> +
> >> + /* send the message */
> >> + sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
> >> + msg->msg_size);
> > I was wondering if the mailbox shared memory wouldn't be better
> > implemented as a queue.
> > Do you support playing multiple streams in parallel?
> >
> > We have this use case where we need to to memory to memory
> > decoding/encoding with lots
> > of streams in parallel.
>
> Sorry Daniel, I didn't get your point.
>
> we do support multiple streams in parallel and there's been quite a few
> issues fixed in the IPC mechanisms due to concurrency. The IPC mechanism
> is serialized however since there are only few resources available,
> typically only a couple of doorbell registers and a small memory window.
> For multiple streams the PCM data is exchanged over DMA typically - the
> streams don't go over the IPC channel but the information related to a
> stream is passed using a tag or ID.
>
> Can you clarify what you had in mind?
Sometimes is hard feven for me to clarify that :)
The question was raised mostly because our audio framework
uses queues here instead just of a mailbox.
We might actually need to have an implementation ready to test
if this serialization has an impact on performance.
I will get back to you when this question will make more sense
in my mind.
thanks,
daniel.
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 02/21] ASoC: SOF: Intel: Add HSW HW DSP support
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 03/21] ASoC: SOF: Intel: Add support for BDW " Pierre-Louis Bossart
` (18 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pan Xiuli,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
Rander Wang, sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add DSP hardware support for Intel Haswell based devices.
Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hsw.c | 701 ++++++++++++++++++++++++++++++++++++++
1 file changed, 701 insertions(+)
create mode 100644 sound/soc/sof/intel/hsw.c
diff --git a/sound/soc/sof/intel/hsw.c b/sound/soc/sof/intel/hsw.c
new file mode 100644
index 000000000000..27e5675f7c96
--- /dev/null
+++ b/sound/soc/sof/intel/hsw.c
@@ -0,0 +1,701 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+//
+
+/*
+ * Hardware interface for audio DSP on Haswell
+ */
+
+#include <linux/module.h>
+#include <sound/sof.h>
+#include <sound/sof/xtensa.h>
+#include "../ops.h"
+#include "shim.h"
+
+/* BARs */
+#define HSW_DSP_BAR 0
+#define HSW_PCI_BAR 1
+
+/*
+ * Debug
+ */
+
+/* DSP memories for HSW */
+#define IRAM_OFFSET 0x80000
+#define HSW_IRAM_SIZE (10 * 32 * 1024)
+#define DRAM_OFFSET 0x00000
+#define HSW_DRAM_SIZE (16 * 32 * 1024)
+#define SHIM_OFFSET 0xE7000
+#define SHIM_SIZE 0x100
+#define MBOX_OFFSET 0x7E000
+#define MBOX_SIZE 0x1000
+#define MBOX_DUMP_SIZE 0x30
+#define EXCEPT_OFFSET 0x800
+
+/* DSP peripherals */
+#define DMAC0_OFFSET 0xFE000
+#define DMAC1_OFFSET 0xFF000
+#define DMAC_SIZE 0x420
+#define SSP0_OFFSET 0xFC000
+#define SSP1_OFFSET 0xFD000
+#define SSP_SIZE 0x100
+
+#define HSW_STACK_DUMP_SIZE 32
+
+#define HSW_PANIC_OFFSET(x) ((x) & 0xFFFF)
+
+static const struct snd_sof_debugfs_map hsw_debugfs[] = {
+ {"dmac0", HSW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE},
+ {"dmac1", HSW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE},
+ {"ssp0", HSW_DSP_BAR, SSP0_OFFSET, SSP_SIZE},
+ {"ssp1", HSW_DSP_BAR, SSP1_OFFSET, SSP_SIZE},
+ {"iram", HSW_DSP_BAR, IRAM_OFFSET, HSW_IRAM_SIZE},
+ {"dram", HSW_DSP_BAR, DRAM_OFFSET, HSW_DRAM_SIZE},
+ {"shim", HSW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE},
+};
+
+static int hsw_cmd_done(struct snd_sof_dev *sdev, int dir);
+
+/*
+ * DSP Control.
+ */
+
+static int hsw_run(struct snd_sof_dev *sdev)
+{
+ /* set opportunistic mode on engine 0,1 for all channels */
+ snd_sof_dsp_update_bits(sdev, HSW_DSP_BAR, SHIM_HMDC,
+ SHIM_HMDC_HDDA_E0_ALLCH |
+ SHIM_HMDC_HDDA_E1_ALLCH, 0);
+
+ /* set DSP to RUN */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_CSR,
+ SHIM_CSR_STALL, 0x0);
+
+ return 0; //TODO: Fix return value
+}
+
+static int hsw_reset(struct snd_sof_dev *sdev)
+{
+ /* put DSP into reset and stall */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_CSR,
+ SHIM_CSR_RST | SHIM_CSR_STALL,
+ SHIM_CSR_RST | SHIM_CSR_STALL);
+
+ /* keep in reset for 10ms */
+ mdelay(10);
+
+ /* take DSP out of reset and keep stalled for FW loading */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_CSR,
+ SHIM_CSR_RST | SHIM_CSR_STALL,
+ SHIM_CSR_STALL);
+
+ return 0; //TODO: Fix return value
+}
+
+static int hsw_set_dsp_D0(struct snd_sof_dev *sdev)
+{
+ int tries = 10;
+ u32 reg;
+
+ /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_PCI_BAR, PCI_VDRTCTL2,
+ PCI_VDRTCL2_DCLCGE | PCI_VDRTCL2_DTCGE,
+ 0);
+
+ /* Disable D3PG (VDRTCTL0.D3PGD = 1) */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_PCI_BAR, PCI_VDRTCTL0,
+ PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD);
+
+ /* Set D0 state */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_PCI_BAR, PCI_PMCS,
+ PCI_PMCS_PS_MASK, 0);
+
+ /* check that ADSP shim is enabled */
+ while (tries--) {
+ reg = readl(sdev->bar[HSW_PCI_BAR] + PCI_PMCS)
+ & PCI_PMCS_PS_MASK;
+ if (reg == 0)
+ goto finish;
+
+ msleep(20);
+ }
+
+ return -ENODEV;
+
+finish:
+ /*
+ * select SSP1 19.2MHz base clock, SSP clock 0,
+ * turn off Low Power Clock
+ */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_CSR,
+ SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 |
+ SHIM_CSR_LPCS, 0x0);
+
+ /* stall DSP core, set clk to 192/96Mhz */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR,
+ SHIM_CSR, SHIM_CSR_STALL |
+ SHIM_CSR_DCS_MASK,
+ SHIM_CSR_STALL | SHIM_CSR_DCS(4));
+
+ /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_CLKCTL,
+ SHIM_CLKCTL_MASK | SHIM_CLKCTL_DCPLCG |
+ SHIM_CLKCTL_SCOE0,
+ SHIM_CLKCTL_MASK | SHIM_CLKCTL_DCPLCG |
+ SHIM_CLKCTL_SCOE0);
+
+ /* Stall and reset core, set CSR */
+ hsw_reset(sdev);
+
+ /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_PCI_BAR, PCI_VDRTCTL2,
+ PCI_VDRTCL2_DCLCGE |
+ PCI_VDRTCL2_DTCGE,
+ PCI_VDRTCL2_DCLCGE |
+ PCI_VDRTCL2_DTCGE);
+
+ usleep_range(50, 55);
+
+ /* switch on audio PLL */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_PCI_BAR, PCI_VDRTCTL2,
+ PCI_VDRTCL2_APLLSE_MASK, 0);
+
+ /*
+ * set default power gating control, enable power gating control for
+ * all blocks. that is, can't be accessed, please enable each block
+ * before accessing.
+ */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_PCI_BAR, PCI_VDRTCTL0,
+ PCI_VDRTCL0_DSRAMPGE_MASK |
+ PCI_VDRTCL0_ISRAMPGE_MASK, 0);
+
+ /* disable DMA finish function for SSP0 & SSP1 */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_CSR2,
+ SHIM_CSR2_SDFD_SSP1,
+ SHIM_CSR2_SDFD_SSP1);
+
+ /* set on-demond mode on engine 0,1 for all channels */
+ snd_sof_dsp_update_bits(sdev, HSW_DSP_BAR, SHIM_HMDC,
+ SHIM_HMDC_HDDA_E0_ALLCH |
+ SHIM_HMDC_HDDA_E1_ALLCH,
+ SHIM_HMDC_HDDA_E0_ALLCH |
+ SHIM_HMDC_HDDA_E1_ALLCH);
+
+ /* Enable Interrupt from both sides */
+ snd_sof_dsp_update_bits(sdev, HSW_DSP_BAR, SHIM_IMRX,
+ (SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0);
+ snd_sof_dsp_update_bits(sdev, HSW_DSP_BAR, SHIM_IMRD,
+ (SHIM_IMRD_DONE | SHIM_IMRD_BUSY |
+ SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0);
+
+ /* clear IPC registers */
+ snd_sof_dsp_write(sdev, HSW_DSP_BAR, SHIM_IPCX, 0x0);
+ snd_sof_dsp_write(sdev, HSW_DSP_BAR, SHIM_IPCD, 0x0);
+ snd_sof_dsp_write(sdev, HSW_DSP_BAR, 0x80, 0x6);
+ snd_sof_dsp_write(sdev, HSW_DSP_BAR, 0xe0, 0x300a);
+
+ return 0;
+}
+
+static void hsw_get_registers(struct snd_sof_dev *sdev,
+ struct sof_ipc_dsp_oops_xtensa *xoops,
+ struct sof_ipc_panic_info *panic_info,
+ u32 *stack, size_t stack_words)
+{
+ /* first read regsisters */
+ sof_mailbox_read(sdev, sdev->dsp_oops_offset, xoops, sizeof(*xoops));
+
+ /* then get panic info */
+ sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops),
+ panic_info, sizeof(*panic_info));
+
+ /* then get the stack */
+ sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops) +
+ sizeof(*panic_info), stack,
+ stack_words * sizeof(u32));
+}
+
+static void hsw_dump(struct snd_sof_dev *sdev, u32 flags)
+{
+ struct sof_ipc_dsp_oops_xtensa xoops;
+ struct sof_ipc_panic_info panic_info;
+ u32 stack[HSW_STACK_DUMP_SIZE];
+ u32 status, panic;
+
+ /* now try generic SOF status messages */
+ status = snd_sof_dsp_read(sdev, HSW_DSP_BAR, SHIM_IPCD);
+ panic = snd_sof_dsp_read(sdev, HSW_DSP_BAR, SHIM_IPCX);
+ hsw_get_registers(sdev, &xoops, &panic_info, stack,
+ HSW_STACK_DUMP_SIZE);
+ snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
+ HSW_STACK_DUMP_SIZE);
+}
+
+/*
+ * IPC Doorbell IRQ handler and thread.
+ */
+
+static irqreturn_t hsw_irq_handler(int irq, void *context)
+{
+ struct snd_sof_dev *sdev = (struct snd_sof_dev *)context;
+ u32 isr;
+ int ret = IRQ_NONE;
+
+ spin_lock(&sdev->hw_lock);
+
+ /* Interrupt arrived, check src */
+ isr = snd_sof_dsp_read(sdev, HSW_DSP_BAR, SHIM_ISRX);
+ if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY))
+ ret = IRQ_WAKE_THREAD;
+
+ spin_unlock(&sdev->hw_lock);
+ return ret;
+}
+
+static irqreturn_t hsw_irq_thread(int irq, void *context)
+{
+ struct snd_sof_dev *sdev = (struct snd_sof_dev *)context;
+ u32 ipcx, ipcd, imrx;
+
+ imrx = snd_sof_dsp_read64(sdev, HSW_DSP_BAR, SHIM_IMRX);
+ ipcx = snd_sof_dsp_read(sdev, HSW_DSP_BAR, SHIM_IPCX);
+
+ /* reply message from DSP */
+ if (ipcx & SHIM_IPCX_DONE &&
+ !(imrx & SHIM_IMRX_DONE)) {
+ /* Mask Done interrupt before return */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR,
+ SHIM_IMRX, SHIM_IMRX_DONE,
+ SHIM_IMRX_DONE);
+
+ /*
+ * handle immediate reply from DSP core. If the msg is
+ * found, set done bit in cmd_done which is called at the
+ * end of message processing function, else set it here
+ * because the done bit can't be set in cmd_done function
+ * which is triggered by msg
+ */
+ if (snd_sof_ipc_reply(sdev, ipcx))
+ hsw_cmd_done(sdev, SOF_IPC_DSP_REPLY);
+ }
+
+ ipcd = snd_sof_dsp_read(sdev, HSW_DSP_BAR, SHIM_IPCD);
+
+ /* new message from DSP */
+ if (ipcd & SHIM_IPCD_BUSY &&
+ !(imrx & SHIM_IMRX_BUSY)) {
+ /* Mask Busy interrupt before return */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR,
+ SHIM_IMRX, SHIM_IMRX_BUSY,
+ SHIM_IMRX_BUSY);
+
+ /* Handle messages from DSP Core */
+ if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
+ snd_sof_dsp_panic(sdev, HSW_PANIC_OFFSET(ipcx) +
+ MBOX_OFFSET);
+ } else {
+ snd_sof_ipc_msgs_rx(sdev);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * IPC Firmware ready.
+ */
+static void hsw_get_windows(struct snd_sof_dev *sdev)
+{
+ struct sof_ipc_window_elem *elem;
+ u32 outbox_offset = 0;
+ u32 stream_offset = 0;
+ u32 inbox_offset = 0;
+ u32 outbox_size = 0;
+ u32 stream_size = 0;
+ u32 inbox_size = 0;
+ int i;
+
+ if (!sdev->info_window) {
+ dev_err(sdev->dev, "error: have no window info\n");
+ return;
+ }
+
+ for (i = 0; i < sdev->info_window->num_windows; i++) {
+ elem = &sdev->info_window->window[i];
+
+ switch (elem->type) {
+ case SOF_IPC_REGION_UPBOX:
+ inbox_offset = elem->offset + MBOX_OFFSET;
+ inbox_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HSW_DSP_BAR] +
+ inbox_offset,
+ elem->size, "inbox");
+ break;
+ case SOF_IPC_REGION_DOWNBOX:
+ outbox_offset = elem->offset + MBOX_OFFSET;
+ outbox_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HSW_DSP_BAR] +
+ outbox_offset,
+ elem->size, "outbox");
+ break;
+ case SOF_IPC_REGION_TRACE:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HSW_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "etrace");
+ break;
+ case SOF_IPC_REGION_DEBUG:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HSW_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "debug");
+ break;
+ case SOF_IPC_REGION_STREAM:
+ stream_offset = elem->offset + MBOX_OFFSET;
+ stream_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HSW_DSP_BAR] +
+ stream_offset,
+ elem->size, "stream");
+ break;
+ case SOF_IPC_REGION_REGS:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HSW_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "regs");
+ break;
+ case SOF_IPC_REGION_EXCEPTION:
+ sdev->dsp_oops_offset = elem->offset + MBOX_OFFSET;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HSW_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "exception");
+ break;
+ default:
+ dev_err(sdev->dev, "error: get illegal window info\n");
+ return;
+ }
+ }
+
+ if (outbox_size == 0 || inbox_size == 0) {
+ dev_err(sdev->dev, "error: get illegal mailbox window\n");
+ return;
+ }
+
+ snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size,
+ outbox_offset, outbox_size);
+ sdev->stream_box.offset = stream_offset;
+ sdev->stream_box.size = stream_size;
+
+ dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n",
+ inbox_offset, inbox_size);
+ dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n",
+ outbox_offset, outbox_size);
+ dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n",
+ stream_offset, stream_size);
+}
+
+static int hsw_fw_ready(struct snd_sof_dev *sdev, u32 msg_id)
+{
+ struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready;
+ u32 offset;
+ int ret;
+
+ /* mailbox must be on 4k boundary */
+ offset = MBOX_OFFSET;
+
+ dev_dbg(sdev->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
+ msg_id, offset);
+
+ /* no need to re-check version/ABI for subsequent boots */
+ if (!sdev->first_boot)
+ return 0;
+
+ /* copy data from the DSP FW ready offset */
+ sof_block_read(sdev, offset, fw_ready, sizeof(*fw_ready));
+
+ snd_sof_dsp_mailbox_init(sdev, fw_ready->dspbox_offset,
+ fw_ready->dspbox_size,
+ fw_ready->hostbox_offset,
+ fw_ready->hostbox_size);
+
+ /* make sure ABI version is compatible */
+ ret = snd_sof_ipc_valid(sdev);
+ if (ret < 0)
+ return ret;
+
+ /* now check for extended data */
+ snd_sof_fw_parse_ext_data(sdev, MBOX_OFFSET +
+ sizeof(struct sof_ipc_fw_ready));
+
+ hsw_get_windows(sdev);
+
+ return 0;
+}
+
+/*
+ * IPC Mailbox IO
+ */
+
+static int hsw_is_ready(struct snd_sof_dev *sdev)
+{
+ u32 val;
+
+ val = snd_sof_dsp_read(sdev, HSW_DSP_BAR, SHIM_IPCX);
+ if ((val & SHIM_IPCX_BUSY) || (val & SHIM_IPCX_DONE))
+ return 0;
+
+ return 1;
+}
+
+static int hsw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
+{
+ /* send the message */
+ sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
+ msg->msg_size);
+ snd_sof_dsp_write(sdev, HSW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);
+
+ return 0;
+}
+
+static int hsw_get_reply(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
+{
+ struct sof_ipc_reply reply;
+ int ret = 0;
+ u32 size;
+
+ /* get reply */
+ sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
+ if (reply.error < 0) {
+ size = sizeof(reply);
+ ret = reply.error;
+ } else {
+ /* reply correct size ? */
+ if (reply.hdr.size != msg->reply_size) {
+ dev_err(sdev->dev, "error: reply expected 0x%zx got 0x%x bytes\n",
+ msg->reply_size, reply.hdr.size);
+ size = msg->reply_size;
+ ret = -EINVAL;
+ } else {
+ size = reply.hdr.size;
+ }
+ }
+
+ /* read the message */
+ if (msg->msg_data && size > 0)
+ sof_mailbox_read(sdev, sdev->host_box.offset, msg->reply_data,
+ size);
+ return ret;
+}
+
+static int hsw_cmd_done(struct snd_sof_dev *sdev, int dir)
+{
+ if (dir == SOF_IPC_HOST_REPLY) {
+ /* clear BUSY bit and set DONE bit - accept new messages */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_IPCD,
+ SHIM_IPCD_BUSY | SHIM_IPCD_DONE,
+ SHIM_IPCD_DONE);
+
+ /* unmask busy interrupt */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_IMRX,
+ SHIM_IMRX_BUSY, 0);
+ } else {
+ /* clear DONE bit - tell DSP we have completed */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_IPCX,
+ SHIM_IPCX_DONE, 0);
+
+ /* unmask Done interrupt */
+ snd_sof_dsp_update_bits_unlocked(sdev, HSW_DSP_BAR, SHIM_IMRX,
+ SHIM_IMRX_DONE, 0);
+ }
+
+ return 0;
+}
+
+/*
+ * Probe and remove.
+ */
+static int hsw_probe(struct snd_sof_dev *sdev)
+{
+ struct snd_sof_pdata *pdata = sdev->pdata;
+ const struct sof_dev_desc *desc = pdata->desc;
+ struct platform_device *pdev =
+ container_of(sdev->parent, struct platform_device, dev);
+ struct resource *mmio;
+ u32 base, size;
+ int ret = 0;
+
+ /* set DSP arch ops */
+ sdev->arch_ops = &sof_xtensa_arch_ops;
+
+ /* LPE base */
+ mmio = platform_get_resource(pdev, IORESOURCE_MEM,
+ desc->resindex_lpe_base);
+ if (mmio) {
+ base = mmio->start;
+ size = resource_size(mmio);
+ } else {
+ dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
+ desc->resindex_lpe_base);
+ return -EINVAL;
+ }
+
+ dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
+ sdev->bar[HSW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
+ if (!sdev->bar[HSW_DSP_BAR]) {
+ dev_err(sdev->dev,
+ "error: failed to ioremap LPE base 0x%x size 0x%x\n",
+ base, size);
+ return -ENODEV;
+ }
+ dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[HSW_DSP_BAR]);
+
+ /* TODO: add offsets */
+ sdev->mmio_bar = HSW_DSP_BAR;
+ sdev->mailbox_bar = HSW_DSP_BAR;
+
+ /* PCI base */
+ mmio = platform_get_resource(pdev, IORESOURCE_MEM,
+ desc->resindex_pcicfg_base);
+ if (mmio) {
+ base = mmio->start;
+ size = resource_size(mmio);
+ } else {
+ dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n",
+ desc->resindex_pcicfg_base);
+ return -ENODEV;
+ }
+
+ dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);
+ sdev->bar[HSW_PCI_BAR] = devm_ioremap(sdev->dev, base, size);
+ if (!sdev->bar[HSW_PCI_BAR]) {
+ dev_err(sdev->dev,
+ "error: failed to ioremap PCI base 0x%x size 0x%x\n",
+ base, size);
+ return -ENODEV;
+ }
+ dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[HSW_PCI_BAR]);
+
+ /* register our IRQ */
+ sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
+ if (sdev->ipc_irq < 0) {
+ dev_err(sdev->dev, "error: failed to get IRQ at index %d\n",
+ desc->irqindex_host_ipc);
+ return sdev->ipc_irq;
+ }
+
+ dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
+ ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
+ hsw_irq_handler, hsw_irq_thread,
+ 0, "AudioDSP", sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to register IRQ %d\n",
+ sdev->ipc_irq);
+ return ret;
+ }
+
+ /* enable the DSP SHIM */
+ ret = hsw_set_dsp_D0(sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to set DSP D0\n");
+ return ret;
+ }
+
+ /* DSP DMA can only access low 31 bits of host memory */
+ ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
+ return ret;
+ }
+
+ /* set BARS */
+ sdev->cl_bar = HSW_DSP_BAR;
+
+ /* set default mailbox */
+ snd_sof_dsp_mailbox_init(sdev, MBOX_OFFSET, MBOX_SIZE, 0, 0);
+
+ return ret;
+}
+
+#define HSW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+/* Haswell DAIs */
+static struct snd_soc_dai_driver hsw_dai[] = {
+{
+ .name = "ssp0-port",
+ .playback = SOF_DAI_STREAM("ssp0 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, HSW_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp0 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, HSW_FORMATS),
+},
+{
+ .name = "ssp1-port",
+ .playback = SOF_DAI_STREAM("ssp1 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, HSW_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp1 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, HSW_FORMATS),
+},
+};
+
+/* haswell ops */
+struct snd_sof_dsp_ops sof_hsw_ops = {
+ /*Device init */
+ .probe = hsw_probe,
+
+ /* DSP Core Control */
+ .run = hsw_run,
+ .reset = hsw_reset,
+
+ /* Register IO */
+ .write = sof_io_write,
+ .read = sof_io_read,
+ .write64 = sof_io_write64,
+ .read64 = sof_io_read64,
+
+ /* Block IO */
+ .block_read = sof_block_read,
+ .block_write = sof_block_write,
+
+ /* mailbox */
+ .mailbox_read = sof_mailbox_read,
+ .mailbox_write = sof_mailbox_write,
+
+ /* ipc */
+ .send_msg = hsw_send_msg,
+ .get_reply = hsw_get_reply,
+ .fw_ready = hsw_fw_ready,
+ .is_ready = hsw_is_ready,
+ .cmd_done = hsw_cmd_done,
+
+ /* debug */
+ .debug_map = hsw_debugfs,
+ .debug_map_count = ARRAY_SIZE(hsw_debugfs),
+ .dbg_dump = hsw_dump,
+
+ /* Module loading */
+ .load_module = snd_sof_parse_module_memcpy,
+
+ /*Firmware loading */
+ .load_firmware = snd_sof_load_firmware_memcpy,
+
+ /* DAI drivers */
+ .drv = hsw_dai,
+ .num_drv = ARRAY_SIZE(hsw_dai)
+
+};
+EXPORT_SYMBOL(sof_hsw_ops);
+
+MODULE_LICENSE("Dual BSD/GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 03/21] ASoC: SOF: Intel: Add support for BDW HW DSP support
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 02/21] ASoC: SOF: Intel: Add HSW HW DSP support Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 04/21] ASoC: SOF: Intel: Add APL/CNL " Pierre-Louis Bossart
` (17 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pan Xiuli,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
Rander Wang, sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add SOF support for Intel Broadwell based devices.
Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/bdw.c | 700 ++++++++++++++++++++++++++++++++++++++
1 file changed, 700 insertions(+)
create mode 100644 sound/soc/sof/intel/bdw.c
diff --git a/sound/soc/sof/intel/bdw.c b/sound/soc/sof/intel/bdw.c
new file mode 100644
index 000000000000..a81f278e8c38
--- /dev/null
+++ b/sound/soc/sof/intel/bdw.c
@@ -0,0 +1,700 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+//
+
+/*
+ * Hardware interface for audio DSP on Broadwell
+ */
+
+#include <linux/module.h>
+#include <sound/sof.h>
+#include <sound/sof/xtensa.h>
+#include "../ops.h"
+#include "shim.h"
+
+/* BARs */
+#define BDW_DSP_BAR 0
+#define BDW_PCI_BAR 1
+
+/*
+ * Debug
+ */
+
+/* DSP memories for BDW */
+#define IRAM_OFFSET 0xA0000
+#define BDW_IRAM_SIZE (10 * 32 * 1024)
+#define DRAM_OFFSET 0x00000
+#define BDW_DRAM_SIZE (20 * 32 * 1024)
+#define SHIM_OFFSET 0xFB000
+#define SHIM_SIZE 0x100
+#define MBOX_OFFSET 0x9E000
+#define MBOX_SIZE 0x1000
+#define MBOX_DUMP_SIZE 0x30
+#define EXCEPT_OFFSET 0x800
+
+/* DSP peripherals */
+#define DMAC0_OFFSET 0xFE000
+#define DMAC1_OFFSET 0xFF000
+#define DMAC_SIZE 0x420
+#define SSP0_OFFSET 0xFC000
+#define SSP1_OFFSET 0xFD000
+#define SSP_SIZE 0x100
+
+#define BDW_STACK_DUMP_SIZE 32
+
+#define BDW_PANIC_OFFSET(x) ((x) & 0xFFFF)
+
+static const struct snd_sof_debugfs_map bdw_debugfs[] = {
+ {"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE},
+ {"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE},
+ {"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE},
+ {"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE},
+ {"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE},
+ {"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE},
+ {"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE},
+};
+
+static int bdw_cmd_done(struct snd_sof_dev *sdev, int dir);
+
+/*
+ * DSP Control.
+ */
+
+static int bdw_run(struct snd_sof_dev *sdev)
+{
+ /* set opportunistic mode on engine 0,1 for all channels */
+ snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
+ SHIM_HMDC_HDDA_E0_ALLCH |
+ SHIM_HMDC_HDDA_E1_ALLCH, 0);
+
+ /* set DSP to RUN */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
+ SHIM_CSR_STALL, 0x0);
+
+ return 0;
+}
+
+static int bdw_reset(struct snd_sof_dev *sdev)
+{
+ /* put DSP into reset and stall */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
+ SHIM_CSR_RST | SHIM_CSR_STALL,
+ SHIM_CSR_RST | SHIM_CSR_STALL);
+
+ /* keep in reset for 10ms */
+ mdelay(10);
+
+ /* take DSP out of reset and keep stalled for FW loading */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
+ SHIM_CSR_RST | SHIM_CSR_STALL,
+ SHIM_CSR_STALL);
+
+ return 0;
+}
+
+static int bdw_set_dsp_D0(struct snd_sof_dev *sdev)
+{
+ int tries = 10;
+ u32 reg;
+
+ /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
+ PCI_VDRTCL2_DCLCGE |
+ PCI_VDRTCL2_DTCGE, 0);
+
+ /* Disable D3PG (VDRTCTL0.D3PGD = 1) */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
+ PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD);
+
+ /* Set D0 state */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS,
+ PCI_PMCS_PS_MASK, 0);
+
+ /* check that ADSP shim is enabled */
+ while (tries--) {
+ reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS)
+ & PCI_PMCS_PS_MASK;
+ if (reg == 0)
+ goto finish;
+
+ msleep(20);
+ }
+
+ return -ENODEV;
+
+finish:
+ /*
+ * select SSP1 19.2MHz base clock, SSP clock 0,
+ * turn off Low Power Clock
+ */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
+ SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 |
+ SHIM_CSR_LPCS, 0x0);
+
+ /* stall DSP core, set clk to 192/96Mhz */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
+ SHIM_CSR, SHIM_CSR_STALL |
+ SHIM_CSR_DCS_MASK,
+ SHIM_CSR_STALL |
+ SHIM_CSR_DCS(4));
+
+ /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,
+ SHIM_CLKCTL_MASK |
+ SHIM_CLKCTL_DCPLCG |
+ SHIM_CLKCTL_SCOE0,
+ SHIM_CLKCTL_MASK |
+ SHIM_CLKCTL_DCPLCG |
+ SHIM_CLKCTL_SCOE0);
+
+ /* Stall and reset core, set CSR */
+ bdw_reset(sdev);
+
+ /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
+ PCI_VDRTCL2_DCLCGE |
+ PCI_VDRTCL2_DTCGE,
+ PCI_VDRTCL2_DCLCGE |
+ PCI_VDRTCL2_DTCGE);
+
+ usleep_range(50, 55);
+
+ /* switch on audio PLL */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
+ PCI_VDRTCL2_APLLSE_MASK, 0);
+
+ /*
+ * set default power gating control, enable power gating control for
+ * all blocks. that is, can't be accessed, please enable each block
+ * before accessing.
+ */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
+ 0xfffffffC, 0x0);
+
+ /* disable DMA finish function for SSP0 & SSP1 */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2,
+ SHIM_CSR2_SDFD_SSP1,
+ SHIM_CSR2_SDFD_SSP1);
+
+ /* set on-demond mode on engine 0,1 for all channels */
+ snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
+ SHIM_HMDC_HDDA_E0_ALLCH |
+ SHIM_HMDC_HDDA_E1_ALLCH,
+ SHIM_HMDC_HDDA_E0_ALLCH |
+ SHIM_HMDC_HDDA_E1_ALLCH);
+
+ /* Enable Interrupt from both sides */
+ snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX,
+ (SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0);
+ snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD,
+ (SHIM_IMRD_DONE | SHIM_IMRD_BUSY |
+ SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0);
+
+ /* clear IPC registers */
+ snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);
+ snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);
+ snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);
+ snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);
+
+ return 0;
+}
+
+static void bdw_get_registers(struct snd_sof_dev *sdev,
+ struct sof_ipc_dsp_oops_xtensa *xoops,
+ struct sof_ipc_panic_info *panic_info,
+ u32 *stack, size_t stack_words)
+{
+ /* first read regsisters */
+ sof_mailbox_read(sdev, sdev->dsp_oops_offset, xoops, sizeof(*xoops));
+
+ /* then get panic info */
+ sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops),
+ panic_info, sizeof(*panic_info));
+
+ /* then get the stack */
+ sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops) +
+ sizeof(*panic_info), stack,
+ stack_words * sizeof(u32));
+}
+
+static void bdw_dump(struct snd_sof_dev *sdev, u32 flags)
+{
+ struct sof_ipc_dsp_oops_xtensa xoops;
+ struct sof_ipc_panic_info panic_info;
+ u32 stack[BDW_STACK_DUMP_SIZE];
+ u32 status, panic;
+
+ /* now try generic SOF status messages */
+ status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
+ panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
+ bdw_get_registers(sdev, &xoops, &panic_info, stack,
+ BDW_STACK_DUMP_SIZE);
+ snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
+ BDW_STACK_DUMP_SIZE);
+}
+
+/*
+ * IPC Doorbell IRQ handler and thread.
+ */
+
+static irqreturn_t bdw_irq_handler(int irq, void *context)
+{
+ struct snd_sof_dev *sdev = (struct snd_sof_dev *)context;
+ u32 isr;
+ int ret = IRQ_NONE;
+
+ /* Interrupt arrived, check src */
+ isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX);
+ if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY))
+ ret = IRQ_WAKE_THREAD;
+
+ return ret;
+}
+
+static irqreturn_t bdw_irq_thread(int irq, void *context)
+{
+ struct snd_sof_dev *sdev = (struct snd_sof_dev *)context;
+ u32 ipcx, ipcd, imrx;
+
+ imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX);
+ ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
+
+ /* reply message from DSP */
+ if (ipcx & SHIM_IPCX_DONE &&
+ !(imrx & SHIM_IMRX_DONE)) {
+ /* Mask Done interrupt before return */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
+ SHIM_IMRX, SHIM_IMRX_DONE,
+ SHIM_IMRX_DONE);
+
+ /*
+ * handle immediate reply from DSP core. If the msg is
+ * found, set done bit in cmd_done which is called at the
+ * end of message processing function, else set it here
+ * because the done bit can't be set in cmd_done function
+ * which is triggered by msg
+ */
+ if (snd_sof_ipc_reply(sdev, ipcx))
+ bdw_cmd_done(sdev, SOF_IPC_DSP_REPLY);
+ }
+
+ ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
+
+ /* new message from DSP */
+ if (ipcd & SHIM_IPCD_BUSY &&
+ !(imrx & SHIM_IMRX_BUSY)) {
+ /* Mask Busy interrupt before return */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
+ SHIM_IMRX, SHIM_IMRX_BUSY,
+ SHIM_IMRX_BUSY);
+
+ /* Handle messages from DSP Core */
+ if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
+ snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) +
+ MBOX_OFFSET);
+ } else {
+ snd_sof_ipc_msgs_rx(sdev);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * IPC Firmware ready.
+ */
+static void bdw_get_windows(struct snd_sof_dev *sdev)
+{
+ struct sof_ipc_window_elem *elem;
+ u32 outbox_offset = 0;
+ u32 stream_offset = 0;
+ u32 inbox_offset = 0;
+ u32 outbox_size = 0;
+ u32 stream_size = 0;
+ u32 inbox_size = 0;
+ int i;
+
+ if (!sdev->info_window) {
+ dev_err(sdev->dev, "error: have no window info\n");
+ return;
+ }
+
+ for (i = 0; i < sdev->info_window->num_windows; i++) {
+ elem = &sdev->info_window->window[i];
+
+ switch (elem->type) {
+ case SOF_IPC_REGION_UPBOX:
+ inbox_offset = elem->offset + MBOX_OFFSET;
+ inbox_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BDW_DSP_BAR] +
+ inbox_offset,
+ elem->size, "inbox");
+ break;
+ case SOF_IPC_REGION_DOWNBOX:
+ outbox_offset = elem->offset + MBOX_OFFSET;
+ outbox_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BDW_DSP_BAR] +
+ outbox_offset,
+ elem->size, "outbox");
+ break;
+ case SOF_IPC_REGION_TRACE:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BDW_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "etrace");
+ break;
+ case SOF_IPC_REGION_DEBUG:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BDW_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "debug");
+ break;
+ case SOF_IPC_REGION_STREAM:
+ stream_offset = elem->offset + MBOX_OFFSET;
+ stream_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BDW_DSP_BAR] +
+ stream_offset,
+ elem->size, "stream");
+ break;
+ case SOF_IPC_REGION_REGS:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BDW_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "regs");
+ break;
+ case SOF_IPC_REGION_EXCEPTION:
+ sdev->dsp_oops_offset = elem->offset + MBOX_OFFSET;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[BDW_DSP_BAR] +
+ elem->offset +
+ MBOX_OFFSET,
+ elem->size, "exception");
+ break;
+ default:
+ dev_err(sdev->dev, "error: get illegal window info\n");
+ return;
+ }
+ }
+
+ if (outbox_size == 0 || inbox_size == 0) {
+ dev_err(sdev->dev, "error: get illegal mailbox window\n");
+ return;
+ }
+
+ snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size,
+ outbox_offset, outbox_size);
+ sdev->stream_box.offset = stream_offset;
+ sdev->stream_box.size = stream_size;
+
+ dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n",
+ inbox_offset, inbox_size);
+ dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n",
+ outbox_offset, outbox_size);
+ dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n",
+ stream_offset, stream_size);
+}
+
+static int bdw_fw_ready(struct snd_sof_dev *sdev, u32 msg_id)
+{
+ struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready;
+ u32 offset;
+ int ret;
+
+ /* mailbox must be on 4k boundary */
+ offset = MBOX_OFFSET;
+
+ dev_dbg(sdev->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
+ msg_id, offset);
+
+ /* no need to re-check version/ABI for subsequent boots */
+ if (!sdev->first_boot)
+ return 0;
+
+ /* copy data from the DSP FW ready offset */
+ sof_block_read(sdev, offset, fw_ready, sizeof(*fw_ready));
+
+ snd_sof_dsp_mailbox_init(sdev, fw_ready->dspbox_offset,
+ fw_ready->dspbox_size,
+ fw_ready->hostbox_offset,
+ fw_ready->hostbox_size);
+
+ /* make sure ABI version is compatible */
+ ret = snd_sof_ipc_valid(sdev);
+ if (ret < 0)
+ return ret;
+
+ /* now check for extended data */
+ snd_sof_fw_parse_ext_data(sdev, MBOX_OFFSET +
+ sizeof(struct sof_ipc_fw_ready));
+
+ bdw_get_windows(sdev);
+
+ return 0;
+}
+
+/*
+ * IPC Mailbox IO
+ */
+
+static int bdw_is_ready(struct snd_sof_dev *sdev)
+{
+ u32 val;
+
+ val = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
+ if ((val & SHIM_IPCX_BUSY) || (val & SHIM_IPCX_DONE))
+ return 0;
+
+ return 1;
+}
+
+static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
+{
+ /* send the message */
+ sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
+ msg->msg_size);
+ snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);
+
+ return 0;
+}
+
+static int bdw_get_reply(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
+{
+ struct sof_ipc_reply reply;
+ int ret = 0;
+ u32 size;
+
+ /* get reply */
+ sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
+ if (reply.error < 0) {
+ size = sizeof(reply);
+ ret = reply.error;
+ } else {
+ /* reply correct size ? */
+ if (reply.hdr.size != msg->reply_size) {
+ dev_err(sdev->dev, "error: reply expected 0x%zx got 0x%x bytes\n",
+ msg->reply_size, reply.hdr.size);
+ size = msg->reply_size;
+ ret = -EINVAL;
+ } else {
+ size = reply.hdr.size;
+ }
+ }
+
+ /* read the message */
+ if (msg->msg_data && size > 0)
+ sof_mailbox_read(sdev, sdev->host_box.offset, msg->reply_data,
+ size);
+
+ return ret;
+}
+
+static int bdw_cmd_done(struct snd_sof_dev *sdev, int dir)
+{
+ if (dir == SOF_IPC_HOST_REPLY) {
+ /* clear BUSY bit and set DONE bit - accept new messages */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,
+ SHIM_IPCD_BUSY | SHIM_IPCD_DONE,
+ SHIM_IPCD_DONE);
+
+ /* unmask busy interrupt */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
+ SHIM_IMRX_BUSY, 0);
+ } else {
+ /* clear DONE bit - tell DSP we have completed */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,
+ SHIM_IPCX_DONE, 0);
+
+ /* unmask Done interrupt */
+ snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
+ SHIM_IMRX_DONE, 0);
+ }
+
+ return 0;
+}
+
+/*
+ * Probe and remove.
+ */
+static int bdw_probe(struct snd_sof_dev *sdev)
+{
+ struct snd_sof_pdata *pdata = sdev->pdata;
+ const struct sof_dev_desc *desc = pdata->desc;
+ struct platform_device *pdev =
+ container_of(sdev->parent, struct platform_device, dev);
+ struct resource *mmio;
+ u32 base, size;
+ int ret = 0;
+
+ /* set DSP arch ops */
+ sdev->arch_ops = &sof_xtensa_arch_ops;
+
+ /* LPE base */
+ mmio = platform_get_resource(pdev, IORESOURCE_MEM,
+ desc->resindex_lpe_base);
+ if (mmio) {
+ base = mmio->start;
+ size = resource_size(mmio);
+ } else {
+ dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
+ desc->resindex_lpe_base);
+ return -EINVAL;
+ }
+
+ dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
+ sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
+ if (!sdev->bar[BDW_DSP_BAR]) {
+ dev_err(sdev->dev,
+ "error: failed to ioremap LPE base 0x%x size 0x%x\n",
+ base, size);
+ return -ENODEV;
+ }
+ dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]);
+
+ /* TODO: add offsets */
+ sdev->mmio_bar = BDW_DSP_BAR;
+ sdev->mailbox_bar = BDW_DSP_BAR;
+
+ /* PCI base */
+ mmio = platform_get_resource(pdev, IORESOURCE_MEM,
+ desc->resindex_pcicfg_base);
+ if (mmio) {
+ base = mmio->start;
+ size = resource_size(mmio);
+ } else {
+ dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n",
+ desc->resindex_pcicfg_base);
+ return -ENODEV;
+ }
+
+ dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);
+ sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size);
+ if (!sdev->bar[BDW_PCI_BAR]) {
+ dev_err(sdev->dev,
+ "error: failed to ioremap PCI base 0x%x size 0x%x\n",
+ base, size);
+ return -ENODEV;
+ }
+ dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]);
+
+ /* register our IRQ */
+ sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
+ if (sdev->ipc_irq < 0) {
+ dev_err(sdev->dev, "error: failed to get IRQ at index %d\n",
+ desc->irqindex_host_ipc);
+ return sdev->ipc_irq;
+ }
+
+ dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
+ ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
+ bdw_irq_handler, bdw_irq_thread,
+ IRQF_SHARED, "AudioDSP", sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to register IRQ %d\n",
+ sdev->ipc_irq);
+ return ret;
+ }
+
+ /* enable the DSP SHIM */
+ ret = bdw_set_dsp_D0(sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to set DSP D0\n");
+ return ret;
+ }
+
+ /* DSP DMA can only access low 31 bits of host memory */
+ ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
+ return ret;
+ }
+
+ /* set BARS */
+ sdev->cl_bar = BDW_DSP_BAR;
+
+ /* set default mailbox */
+ snd_sof_dsp_mailbox_init(sdev, MBOX_OFFSET, MBOX_SIZE, 0, 0);
+
+ return ret;
+}
+
+#define BDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+/* Broadwell DAIs */
+static struct snd_soc_dai_driver bdw_dai[] = {
+{
+ .name = "ssp0-port",
+ .playback = SOF_DAI_STREAM("ssp0 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BDW_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp0 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BDW_FORMATS),
+},
+{
+ .name = "ssp1-port",
+ .playback = SOF_DAI_STREAM("ssp1 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BDW_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp1 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, BDW_FORMATS),
+},
+};
+
+/* broadwell ops */
+struct snd_sof_dsp_ops sof_bdw_ops = {
+ /*Device init */
+ .probe = bdw_probe,
+
+ /* DSP Core Control */
+ .run = bdw_run,
+ .reset = bdw_reset,
+
+ /* Register IO */
+ .write = sof_io_write,
+ .read = sof_io_read,
+ .write64 = sof_io_write64,
+ .read64 = sof_io_read64,
+
+ /* Block IO */
+ .block_read = sof_block_read,
+ .block_write = sof_block_write,
+
+ /* mailbox */
+ .mailbox_read = sof_mailbox_read,
+ .mailbox_write = sof_mailbox_write,
+
+ /* ipc */
+ .send_msg = bdw_send_msg,
+ .get_reply = bdw_get_reply,
+ .fw_ready = bdw_fw_ready,
+ .is_ready = bdw_is_ready,
+ .cmd_done = bdw_cmd_done,
+
+ /* debug */
+ .debug_map = bdw_debugfs,
+ .debug_map_count = ARRAY_SIZE(bdw_debugfs),
+ .dbg_dump = bdw_dump,
+
+ /* Module loading */
+ .load_module = snd_sof_parse_module_memcpy,
+
+ /*Firmware loading */
+ .load_firmware = snd_sof_load_firmware_memcpy,
+
+ /* DAI drivers */
+ .drv = bdw_dai,
+ .num_drv = ARRAY_SIZE(bdw_dai)
+};
+EXPORT_SYMBOL(sof_bdw_ops);
+
+MODULE_LICENSE("Dual BSD/GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 04/21] ASoC: SOF: Intel: Add APL/CNL HW DSP support
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (2 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 03/21] ASoC: SOF: Intel: Add support for BDW " Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 05/21] ASoC: SOF: Intel: Add HDA controller for Intel DSP Pierre-Louis Bossart
` (16 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add SOF hardware DSP support for Intel Apollolake and Cannonlake based
devices.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda.c | 704 ++++++++++++++++++++++++++++++++++++++
sound/soc/sof/intel/hda.h | 536 +++++++++++++++++++++++++++++
2 files changed, 1240 insertions(+)
create mode 100644 sound/soc/sof/intel/hda.c
create mode 100644 sound/soc/sof/intel/hda.h
diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
new file mode 100644
index 000000000000..b726e2708210
--- /dev/null
+++ b/sound/soc/sof/intel/hda.c
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for generic Intel audio DSP HDA IP
+ */
+
+#include <linux/module.h>
+#include <sound/hdaudio_ext.h>
+#include <sound/sof.h>
+#include <sound/sof/xtensa.h>
+#include "../ops.h"
+#include "hda.h"
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
+#include "../../codecs/hdac_hda.h"
+#endif
+
+/* platform specific devices */
+#include "shim.h"
+
+/*
+ * Debug
+ */
+
+struct hda_dsp_msg_code {
+ u32 code;
+ const char *msg;
+};
+
+static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
+ {HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
+ {HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
+ {HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
+ {HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
+ {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
+ {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
+ {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
+ {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
+ {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
+ {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
+ {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
+ {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
+ {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatble"},
+ {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
+ {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
+ {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
+ {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
+ {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
+ {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
+};
+
+static void hda_dsp_get_status_skl(struct snd_sof_dev *sdev)
+{
+ u32 status;
+ int i;
+
+ status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_ADSP_FW_STATUS_SKL);
+
+ for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
+ if (status == hda_dsp_rom_msg[i].code) {
+ dev_err(sdev->dev, "%s - code %8.8x\n",
+ hda_dsp_rom_msg[i].msg, status);
+ return;
+ }
+ }
+
+ /* not for us, must be generic sof message */
+ dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
+}
+
+static void hda_dsp_get_status(struct snd_sof_dev *sdev)
+{
+ u32 status;
+ int i;
+
+ status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_SRAM_REG_ROM_STATUS);
+
+ for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
+ if (status == hda_dsp_rom_msg[i].code) {
+ dev_err(sdev->dev, "%s - code %8.8x\n",
+ hda_dsp_rom_msg[i].msg, status);
+ return;
+ }
+ }
+
+ /* not for us, must be generic sof message */
+ dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
+}
+
+static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
+ struct sof_ipc_dsp_oops_xtensa *xoops,
+ struct sof_ipc_panic_info *panic_info,
+ u32 *stack, size_t stack_words)
+{
+ /* first read registers */
+ sof_block_read(sdev, sdev->dsp_oops_offset, xoops, sizeof(*xoops));
+
+ /* then get panic info */
+ sof_block_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops),
+ panic_info, sizeof(*panic_info));
+
+ /* then get the stack */
+ sof_block_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops) +
+ sizeof(*panic_info), stack,
+ stack_words * sizeof(u32));
+}
+
+void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags)
+{
+ struct sof_ipc_dsp_oops_xtensa xoops;
+ struct sof_ipc_panic_info panic_info;
+ u32 stack[HDA_DSP_STACK_DUMP_SIZE];
+ u32 status, panic;
+
+ /* try APL specific status message types first */
+ hda_dsp_get_status_skl(sdev);
+
+ /* now try generic SOF status messages */
+ status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_ADSP_ERROR_CODE_SKL);
+
+ /*TODO: Check: there is no define in spec, but it is used in the code*/
+ panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_ADSP_ERROR_CODE_SKL + 0x4);
+
+ if (sdev->boot_complete) {
+ hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
+ HDA_DSP_STACK_DUMP_SIZE);
+ snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
+ stack, HDA_DSP_STACK_DUMP_SIZE);
+ } else {
+ dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
+ status, panic);
+ hda_dsp_get_status_skl(sdev);
+ }
+}
+
+void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
+{
+ struct sof_ipc_dsp_oops_xtensa xoops;
+ struct sof_ipc_panic_info panic_info;
+ u32 stack[HDA_DSP_STACK_DUMP_SIZE];
+ u32 status, panic;
+
+ /* try APL specific status message types first */
+ hda_dsp_get_status(sdev);
+
+ /* now try generic SOF status messages */
+ status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_SRAM_REG_FW_STATUS);
+ panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
+
+ if (sdev->boot_complete) {
+ hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
+ HDA_DSP_STACK_DUMP_SIZE);
+ snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
+ stack, HDA_DSP_STACK_DUMP_SIZE);
+ } else {
+ dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
+ status, panic);
+ hda_dsp_get_status(sdev);
+ }
+}
+
+/*
+ * Supported devices.
+ */
+
+static const struct sof_intel_dsp_desc chip_info[] = {
+{
+ /* Skylake */
+ .id = 0x9d70,
+ .cores_num = 2,
+ .cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
+ .ipc_req = HDA_DSP_REG_HIPCI,
+ .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
+ .ipc_ack = HDA_DSP_REG_HIPCIE,
+ .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
+ .ipc_ctl = HDA_DSP_REG_HIPCCTL,
+ .ops = &sof_skl_ops,
+},
+{
+ /* Kabylake */
+ .id = 0x9d71,
+ .cores_num = 2,
+ .cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
+ .ipc_req = HDA_DSP_REG_HIPCI,
+ .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
+ .ipc_ack = HDA_DSP_REG_HIPCIE,
+ .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
+ .ipc_ctl = HDA_DSP_REG_HIPCCTL,
+ .ops = &sof_skl_ops,
+},
+{
+ /* Apollolake - BXT-P */
+ .id = 0x5a98,
+ .cores_num = 2,
+ .cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
+ .ipc_req = HDA_DSP_REG_HIPCI,
+ .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
+ .ipc_ack = HDA_DSP_REG_HIPCIE,
+ .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
+ .ipc_ctl = HDA_DSP_REG_HIPCCTL,
+ .ops = &sof_apl_ops,
+},
+{
+ /* BXT-M */
+ .id = 0x1a98,
+ .cores_num = 2,
+ .cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
+ .ipc_req = HDA_DSP_REG_HIPCI,
+ .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
+ .ipc_ack = HDA_DSP_REG_HIPCIE,
+ .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
+ .ipc_ctl = HDA_DSP_REG_HIPCCTL,
+ .ops = &sof_apl_ops,
+},
+{
+ /* GeminiLake */
+ .id = 0x3198,
+ .cores_num = 2,
+ .cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
+ .ipc_req = HDA_DSP_REG_HIPCI,
+ .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
+ .ipc_ack = HDA_DSP_REG_HIPCIE,
+ .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
+ .ipc_ctl = HDA_DSP_REG_HIPCCTL,
+ .ops = &sof_apl_ops,
+},
+{
+ /* Cannonlake */
+ .id = 0x9dc8,
+ .cores_num = 4,
+ .cores_mask = HDA_DSP_CORE_MASK(0) |
+ HDA_DSP_CORE_MASK(1) |
+ HDA_DSP_CORE_MASK(2) |
+ HDA_DSP_CORE_MASK(3),
+ .ipc_req = CNL_DSP_REG_HIPCIDR,
+ .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
+ .ipc_ack = CNL_DSP_REG_HIPCIDA,
+ .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
+ .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+ .ops = &sof_cnl_ops,
+},
+{
+ /* Icelake */
+ .id = 0x34c8,
+ .cores_num = 4,
+ .cores_mask = HDA_DSP_CORE_MASK(0) |
+ HDA_DSP_CORE_MASK(1) |
+ HDA_DSP_CORE_MASK(2) |
+ HDA_DSP_CORE_MASK(3),
+ .ipc_req = CNL_DSP_REG_HIPCIDR,
+ .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
+ .ipc_ack = CNL_DSP_REG_HIPCIDA,
+ .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
+ .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+ .ops = &sof_cnl_ops,
+},
+};
+
+static const struct sof_intel_dsp_desc *get_chip_info(int pci_id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chip_info); i++) {
+ if (chip_info[i].id == pci_id)
+ return &chip_info[i];
+ }
+
+ return NULL;
+}
+
+static int hda_init(struct snd_sof_dev *sdev)
+{
+ struct hda_bus *hbus;
+ struct hdac_bus *bus;
+ struct hdac_ext_bus_ops *ext_ops = NULL;
+ struct pci_dev *pci = sdev->pci;
+ int ret;
+
+ hbus = sof_to_hbus(sdev);
+ bus = sof_to_bus(sdev);
+
+ /* HDA bus init */
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
+ ext_ops = snd_soc_hdac_hda_get_ops();
+#endif
+ sof_hda_bus_init(bus, &pci->dev, ext_ops);
+ bus->use_posbuf = 1;
+ bus->bdl_pos_adj = 0;
+
+ mutex_init(&hbus->prepare_mutex);
+ hbus->pci = pci;
+ hbus->mixer_assigned = -1;
+ hbus->modelname = "sofbus";
+
+ /* initialise hdac bus */
+ bus->addr = pci_resource_start(pci, 0);
+ bus->remap_addr = pci_ioremap_bar(pci, 0);
+ if (!bus->remap_addr) {
+ dev_err(bus->dev, "error: ioremap error\n");
+ return -ENXIO;
+ }
+
+ /* HDA base */
+ sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
+
+ /* get controller capabilities */
+ ret = hda_dsp_ctrl_get_caps(sdev);
+ if (ret < 0)
+ dev_err(&pci->dev, "error: get caps error\n");
+
+ return ret;
+}
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+
+static int hda_init_caps(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct pci_dev *pci = sdev->pci;
+ struct hdac_ext_link *hlink = NULL;
+ struct snd_soc_acpi_mach_params *mach_params;
+ int ret = 0;
+ int err;
+
+ device_disable_async_suspend(bus->dev);
+
+ /* check if dsp is there */
+ if (bus->ppcap)
+ dev_dbg(&pci->dev, "PP capability, will probe DSP later.\n");
+
+ if (bus->mlcap)
+ snd_hdac_ext_bus_get_ml_capabilities(bus);
+
+ /* init i915 and HDMI codecs */
+ ret = hda_codec_i915_init(sdev);
+ if (ret < 0) {
+ dev_err(&pci->dev, "error: no HDMI audio devices found\n");
+ return ret;
+ }
+
+ ret = hda_dsp_ctrl_init_chip(sdev, true);
+ if (ret < 0) {
+ dev_err(bus->dev, "error: init chip failed with ret: %d\n", ret);
+ err = hda_codec_i915_put(sdev);
+ if (err < 0)
+ return err;
+ return ret;
+ }
+
+ /* codec detection */
+ if (!bus->codec_mask)
+ dev_info(bus->dev, "no hda codecs found!\n");
+ else
+ dev_info(bus->dev, "hda codecs found, mask %lx!\n", bus->codec_mask);
+
+ /* used by hda machine driver to create dai links */
+ mach_params = (struct snd_soc_acpi_mach_params *)
+ &sdev->pdata->machine->mach_params;
+ mach_params->codec_mask = bus->codec_mask;
+
+ /* create codec instances */
+ hda_codec_probe_bus(sdev);
+
+ ret = hda_codec_i915_put(sdev);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * we are done probing so decrement link counts
+ */
+ list_for_each_entry(hlink, &bus->hlink_list, list)
+ snd_hdac_ext_bus_link_put(bus, hlink);
+
+ return 0;
+}
+
+#else
+
+static int hda_init_caps(struct snd_sof_dev *sdev)
+{
+ /*
+ * set CGCTL.MISCBDCGE to 0 during reset and set back to 1
+ * when reset finished.
+ * TODO: maybe no need for init_caps?
+ */
+ hda_dsp_ctrl_misc_clock_gating(sdev, 0);
+
+ /* clear WAKESTS */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
+ SOF_HDA_WAKESTS_INT_MASK,
+ SOF_HDA_WAKESTS_INT_MASK);
+
+ return 0;
+}
+
+#endif
+
+/*
+ * We don't need to do a full HDA codec probe as external HDA codec mode is
+ * considered legacy and will not be supported under SOF. HDMI/DP HDA will
+ * be supported in the DSP.
+ */
+int hda_dsp_probe(struct snd_sof_dev *sdev)
+{
+ struct pci_dev *pci = sdev->pci;
+ struct sof_intel_hda_dev *hdev;
+ struct hdac_bus *bus;
+ struct hdac_stream *stream;
+ const struct sof_intel_dsp_desc *chip;
+ int sd_offset, ret = 0;
+
+ /*
+ * detect DSP by checking class/subclass/prog-id information
+ * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
+ * class=04 subclass 01 prog-if 00: DSP is present
+ * (and may be required e.g. for DMIC or SSP support)
+ * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
+ */
+ if (pci->class == 0x040300) {
+ dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n");
+ return -ENODEV;
+ } else if (pci->class != 0x040100 && pci->class != 0x040380) {
+ dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class);
+ return -ENODEV;
+ }
+ dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class);
+
+ /* set DSP arch ops */
+ sdev->arch_ops = &sof_xtensa_arch_ops;
+
+ chip = get_chip_info(pci->device);
+ if (!chip) {
+ dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
+ pci->device);
+ ret = -EIO;
+ goto err;
+ }
+
+ hdev = devm_kzalloc(&pci->dev, sizeof(*hdev), GFP_KERNEL);
+ if (!hdev)
+ return -ENOMEM;
+ sdev->hda = hdev;
+ hdev->desc = chip;
+
+ hdev->dmic_dev = platform_device_register_data(&pci->dev, "dmic-codec",
+ -1, NULL, 0);
+ if (IS_ERR(hdev->dmic_dev)) {
+ dev_err(&pci->dev, "error: failed to create DMIC device\n");
+ return PTR_ERR(hdev->dmic_dev);
+ }
+
+ /*
+ * use position update IPC if either it is forced
+ * or we don't have other choice
+ */
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
+ hdev->no_ipc_position = 0;
+#else
+ hdev->no_ipc_position = sdev->ops->pcm_pointer ? 1 : 0;
+#endif
+
+ /* set up HDA base */
+ bus = sof_to_bus(sdev);
+ ret = hda_init(sdev);
+ if (ret < 0)
+ goto hdac_bus_unmap;
+
+ /* DSP base */
+ sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
+ if (!sdev->bar[HDA_DSP_BAR]) {
+ dev_err(&pci->dev, "error: ioremap error\n");
+ ret = -ENXIO;
+ goto hdac_bus_unmap;
+ }
+
+ sdev->mmio_bar = HDA_DSP_BAR;
+ sdev->mailbox_bar = HDA_DSP_BAR;
+
+ /* allow 64bit DMA address if supported by H/W */
+ if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
+ dev_dbg(&pci->dev, "DMA mask is 64 bit\n");
+ dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
+ } else {
+ dev_dbg(&pci->dev, "DMA mask is 32 bit\n");
+ dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
+ dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
+ }
+
+ /* init streams */
+ ret = hda_dsp_stream_init(sdev);
+ if (ret < 0) {
+ dev_err(&pci->dev, "error: failed to init streams\n");
+ /*
+ * not all errors are due to memory issues, but trying
+ * to free everything does not harm
+ */
+ goto free_streams;
+ }
+
+ /*
+ * register our IRQ
+ * let's try to enable msi firstly
+ * if it fails, use legacy interrupt mode
+ * TODO: support interrupt mode selection with kernel parameter
+ * support msi multiple vectors
+ */
+ ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI);
+ if (ret < 0) {
+ dev_info(sdev->dev, "use legacy interrupt mode\n");
+ /*
+ * in IO-APIC mode, hda->irq and ipc_irq are using the same
+ * irq number of pci->irq
+ */
+ sdev->hda->irq = pci->irq;
+ sdev->ipc_irq = pci->irq;
+ sdev->msi_enabled = 0;
+ } else {
+ dev_info(sdev->dev, "use msi interrupt mode\n");
+ sdev->hda->irq = pci_irq_vector(pci, 0);
+ /* ipc irq number is the same of hda irq */
+ sdev->ipc_irq = sdev->hda->irq;
+ sdev->msi_enabled = 1;
+ }
+
+ dev_dbg(sdev->dev, "using HDA IRQ %d\n", sdev->hda->irq);
+ ret = request_threaded_irq(sdev->hda->irq, hda_dsp_stream_interrupt,
+ hda_dsp_stream_threaded_handler,
+ IRQF_SHARED, "AudioHDA", bus);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to register HDA IRQ %d\n",
+ sdev->hda->irq);
+ goto free_irq_vector;
+ }
+
+ dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
+ ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_ipc_irq_handler,
+ chip->ops->irq_thread, IRQF_SHARED,
+ "AudioDSP", sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
+ sdev->ipc_irq);
+ goto free_hda_irq;
+ }
+
+ pci_set_master(pci);
+ synchronize_irq(pci->irq);
+
+ /*
+ * clear TCSEL to clear playback on some HD Audio
+ * codecs. PCI TCSEL is defined in the Intel manuals.
+ */
+ snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
+
+ /* init HDA capabilities */
+ ret = hda_init_caps(sdev);
+ if (ret < 0)
+ goto free_ipc_irq;
+
+ /* reset HDA controller */
+ ret = hda_dsp_ctrl_link_reset(sdev, true);
+ if (ret < 0) {
+ dev_err(&pci->dev, "error: failed to reset HDA controller\n");
+ goto free_ipc_irq;
+ }
+
+ /* exit HDA controller reset */
+ ret = hda_dsp_ctrl_link_reset(sdev, false);
+ if (ret < 0) {
+ dev_err(&pci->dev, "error: failed to exit HDA controller reset\n");
+ goto free_ipc_irq;
+ }
+
+ /* clear stream status */
+ list_for_each_entry(stream, &bus->stream_list, list) {
+ sd_offset = SOF_STREAM_SD_OFFSET(stream);
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+ sd_offset +
+ SOF_HDA_ADSP_REG_CL_SD_STS,
+ SOF_HDA_CL_DMA_SD_INT_MASK,
+ SOF_HDA_CL_DMA_SD_INT_MASK);
+ }
+
+ /* clear WAKESTS */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
+ SOF_HDA_WAKESTS_INT_MASK,
+ SOF_HDA_WAKESTS_INT_MASK);
+
+ /* clear interrupt status register */
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
+ SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
+
+ /* enable CIE and GIE interrupts */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
+ SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
+ SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
+
+ /* re-enable CGCTL.MISCBDCGE after reset */
+ hda_dsp_ctrl_misc_clock_gating(sdev, true);
+
+ device_disable_async_suspend(&pci->dev);
+
+ /* enable DSP features */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
+ SOF_HDA_PPCTL_GPROCEN, SOF_HDA_PPCTL_GPROCEN);
+
+ /* enable DSP IRQ */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
+ SOF_HDA_PPCTL_PIE, SOF_HDA_PPCTL_PIE);
+
+ /* initialize waitq for code loading */
+ init_waitqueue_head(&sdev->waitq);
+
+ /* set default mailbox offset for FW ready message */
+ sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;
+
+ return 0;
+
+free_ipc_irq:
+ free_irq(sdev->ipc_irq, sdev);
+free_hda_irq:
+ free_irq(sdev->hda->irq, bus);
+free_irq_vector:
+ if (sdev->msi_enabled)
+ pci_free_irq_vectors(pci);
+free_streams:
+ hda_dsp_stream_free(sdev);
+/* dsp_unmap: not currently used */
+ iounmap(sdev->bar[HDA_DSP_BAR]);
+hdac_bus_unmap:
+ iounmap(bus->remap_addr);
+err:
+ return ret;
+}
+
+int hda_dsp_remove(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct pci_dev *pci = sdev->pci;
+ const struct sof_intel_dsp_desc *chip = NULL;
+
+ if (sdev->hda)
+ chip = sdev->hda->desc;
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ /* codec removal, invoke bus_device_remove */
+ snd_hdac_ext_bus_device_remove(bus);
+#endif
+
+ if (sdev->hda && (!IS_ERR(sdev->hda->dmic_dev)))
+ platform_device_unregister(sdev->hda->dmic_dev);
+
+ /* disable DSP IRQ */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
+ SOF_HDA_PPCTL_PIE, 0);
+
+ /* disable CIE and GIE interrupts */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
+ SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);
+
+ /* disable cores */
+ if (chip)
+ hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
+
+ /* disable DSP */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
+ SOF_HDA_PPCTL_GPROCEN, 0);
+
+ free_irq(sdev->ipc_irq, sdev);
+ free_irq(sdev->hda->irq, bus);
+ if (sdev->msi_enabled)
+ pci_free_irq_vectors(pci);
+
+ hda_dsp_stream_free(sdev);
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ snd_hdac_link_free_all(bus);
+#endif
+
+ iounmap(sdev->bar[HDA_DSP_BAR]);
+ iounmap(bus->remap_addr);
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ snd_hdac_ext_bus_exit(bus);
+#endif
+ hda_codec_i915_exit(sdev);
+
+ return 0;
+}
+
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
new file mode 100644
index 000000000000..1d1b8a843ecc
--- /dev/null
+++ b/sound/soc/sof/intel/hda.h
@@ -0,0 +1,536 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
+/*
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ */
+
+#ifndef __SOF_INTEL_HDA_H
+#define __SOF_INTEL_HDA_H
+
+#include <sound/hda_codec.h>
+
+/* PCI registers */
+#define PCI_TCSEL 0x44
+#define PCI_PGCTL PCI_TCSEL
+#define PCI_CGCTL 0x48
+
+/* PCI_PGCTL bits */
+#define PCI_PGCTL_ADSPPGD BIT(2)
+#define PCI_PGCTL_LSRMD_MASK BIT(4)
+
+/* PCI_CGCTL bits */
+#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
+#define PCI_CGCTL_ADSPDCGE BIT(1)
+
+/* Legacy HDA registers and bits used - widths are variable */
+#define SOF_HDA_GCAP 0x0
+#define SOF_HDA_GCTL 0x8
+/* accept unsol. response enable */
+#define SOF_HDA_GCTL_UNSOL BIT(8)
+#define SOF_HDA_LLCH 0x14
+#define SOF_HDA_INTCTL 0x20
+#define SOF_HDA_INTSTS 0x24
+#define SOF_HDA_WAKESTS 0x0E
+#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
+#define SOF_HDA_RIRBSTS 0x5d
+#define SOF_HDA_VS_EM2_L1SEN BIT(13)
+
+/* SOF_HDA_GCTL register bist */
+#define SOF_HDA_GCTL_RESET BIT(0)
+
+/* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */
+#define SOF_HDA_INT_GLOBAL_EN BIT(31)
+#define SOF_HDA_INT_CTRL_EN BIT(30)
+#define SOF_HDA_INT_ALL_STREAM 0xff
+
+#define SOF_HDA_MAX_CAPS 10
+#define SOF_HDA_CAP_ID_OFF 16
+#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
+ SOF_HDA_CAP_ID_OFF)
+#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
+
+#define SOF_HDA_GTS_CAP_ID 0x1
+#define SOF_HDA_ML_CAP_ID 0x2
+
+#define SOF_HDA_PP_CAP_ID 0x3
+#define SOF_HDA_REG_PP_PPCH 0x10
+#define SOF_HDA_REG_PP_PPCTL 0x04
+#define SOF_HDA_PPCTL_PIE BIT(31)
+#define SOF_HDA_PPCTL_GPROCEN BIT(30)
+
+/* DPIB entry size: 8 Bytes = 2 DWords */
+#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
+
+#define SOF_HDA_SPIB_CAP_ID 0x4
+#define SOF_HDA_DRSM_CAP_ID 0x5
+
+#define SOF_HDA_SPIB_BASE 0x08
+#define SOF_HDA_SPIB_INTERVAL 0x08
+#define SOF_HDA_SPIB_SPIB 0x00
+#define SOF_HDA_SPIB_MAXFIFO 0x04
+
+#define SOF_HDA_PPHC_BASE 0x10
+#define SOF_HDA_PPHC_INTERVAL 0x10
+
+#define SOF_HDA_PPLC_BASE 0x10
+#define SOF_HDA_PPLC_MULTI 0x10
+#define SOF_HDA_PPLC_INTERVAL 0x10
+
+#define SOF_HDA_DRSM_BASE 0x08
+#define SOF_HDA_DRSM_INTERVAL 0x08
+
+/* Descriptor error interrupt */
+#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
+
+/* FIFO error interrupt */
+#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
+
+/* Buffer completion interrupt */
+#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
+
+#define SOF_HDA_CL_DMA_SD_INT_MASK \
+ (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
+ SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
+ SOF_HDA_CL_DMA_SD_INT_COMPLETE)
+#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
+
+/* Intel HD Audio Code Loader DMA Registers */
+#define SOF_HDA_ADSP_LOADER_BASE 0x80
+#define SOF_HDA_ADSP_DPLBASE 0x70
+#define SOF_HDA_ADSP_DPUBASE 0x74
+#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
+
+/* Stream Registers */
+#define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
+#define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
+#define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
+#define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
+#define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
+#define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
+#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
+#define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
+#define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
+#define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
+#define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
+#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
+
+/* CL: Software Position Based FIFO Capability Registers */
+#define SOF_DSP_REG_CL_SPBFIFO \
+ (SOF_HDA_ADSP_LOADER_BASE + 0x20)
+#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
+#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
+#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
+#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
+
+/* Stream Number */
+#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
+#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
+ GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
+ SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
+
+#define HDA_DSP_HDA_BAR 0
+#define HDA_DSP_PP_BAR 1
+#define HDA_DSP_SPIB_BAR 2
+#define HDA_DSP_DRSM_BAR 3
+#define HDA_DSP_BAR 4
+
+#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
+
+#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
+
+#define HDA_DSP_PANIC_OFFSET(x) \
+ (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
+
+/* SRAM window 0 FW "registers" */
+#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
+#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
+/* FW and ROM share offset 4 */
+#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
+#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
+#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
+
+#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
+
+#define HDA_DSP_STREAM_RESET_TIMEOUT 300
+#define HDA_DSP_CL_TRIGGER_TIMEOUT 300
+
+#define HDA_DSP_SPIB_ENABLE 1
+#define HDA_DSP_SPIB_DISABLE 0
+
+#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
+
+#define HDA_DSP_STACK_DUMP_SIZE 32
+
+/* ROM status/error values */
+#define HDA_DSP_ROM_STS_MASK 0xf
+#define HDA_DSP_ROM_INIT 0x1
+#define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
+#define HDA_DSP_ROM_FW_FW_LOADED 0x4
+#define HDA_DSP_ROM_FW_ENTERED 0x5
+#define HDA_DSP_ROM_RFW_START 0xf
+#define HDA_DSP_ROM_CSE_ERROR 40
+#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
+#define HDA_DSP_ROM_IMR_TO_SMALL 42
+#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
+#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
+#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
+#define HDA_DSP_ROM_L2_CACHE_ERROR 46
+#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
+#define HDA_DSP_ROM_API_PTR_INVALID 50
+#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
+#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
+#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
+#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
+#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
+#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
+#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
+#define HDA_DSP_IPC_PURGE_FW 0x01004000
+
+/* various timeout values */
+#define HDA_DSP_PU_TIMEOUT 50
+#define HDA_DSP_PD_TIMEOUT 50
+#define HDA_DSP_RESET_TIMEOUT 50
+#define HDA_DSP_BASEFW_TIMEOUT 3000
+#define HDA_DSP_INIT_TIMEOUT 500
+#define HDA_DSP_CTRL_RESET_TIMEOUT 100
+#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
+
+#define HDA_DSP_ADSPIC_IPC 1
+#define HDA_DSP_ADSPIS_IPC 1
+
+/* Intel HD Audio General DSP Registers */
+#define HDA_DSP_GEN_BASE 0x0
+#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
+#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
+#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
+#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
+#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
+
+/* Intel HD Audio Inter-Processor Communication Registers */
+#define HDA_DSP_IPC_BASE 0x40
+#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
+#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
+#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
+#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
+#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
+
+/* HIPCI */
+#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
+#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
+
+/* HIPCIE */
+#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
+#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
+
+/* HIPCCTL */
+#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
+#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
+
+/* HIPCT */
+#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
+#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
+
+/* HIPCTE */
+#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
+
+#define HDA_DSP_ADSPIC_CL_DMA 0x2
+#define HDA_DSP_ADSPIS_CL_DMA 0x2
+
+/* Delay before scheduling D0i3 entry */
+#define BXT_D0I3_DELAY 5000
+
+#define FW_CL_STREAM_NUMBER 0x1
+
+/* ADSPCS - Audio DSP Control & Status */
+
+/*
+ * Core Reset - asserted high
+ * CRST Mask for a given core mask pattern, cm
+ */
+#define HDA_DSP_ADSPCS_CRST_SHIFT 0
+#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
+
+/*
+ * Core run/stall - when set to '1' core is stalled
+ * CSTALL Mask for a given core mask pattern, cm
+ */
+#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
+#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
+
+/*
+ * Set Power Active - when set to '1' turn cores on
+ * SPA Mask for a given core mask pattern, cm
+ */
+#define HDA_DSP_ADSPCS_SPA_SHIFT 16
+#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
+
+/*
+ * Current Power Active - power status of cores, set by hardware
+ * CPA Mask for a given core mask pattern, cm
+ */
+#define HDA_DSP_ADSPCS_CPA_SHIFT 24
+#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
+
+/* Mask for a given core index, c = 0.. number of supported cores - 1 */
+#define HDA_DSP_CORE_MASK(c) BIT(c)
+
+/*
+ * Mask for a given number of cores
+ * nc = number of supported cores
+ */
+#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
+
+/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
+#define CNL_DSP_IPC_BASE 0xc0
+#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
+#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
+#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
+#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
+#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
+#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
+
+/* HIPCI */
+#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
+#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
+
+/* HIPCIE */
+#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
+#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
+
+/* HIPCCTL */
+#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
+#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
+
+/* HIPCT */
+#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
+#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
+
+/* HIPCTDA */
+#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
+#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
+
+/* HIPCTDD */
+#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
+
+/* BDL */
+#define HDA_DSP_BDL_SIZE 4096
+#define HDA_DSP_MAX_BDL_ENTRIES \
+ (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
+
+/* Number of DAIs */
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+#define SOF_SKL_NUM_DAIS 14
+#else
+#define SOF_SKL_NUM_DAIS 8
+#endif
+
+/* Intel HD Audio SRAM Window 0*/
+#define HDA_ADSP_SRAM0_BASE_SKL 0x8000
+
+/* Firmware status window */
+#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
+#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
+
+struct sof_intel_dsp_bdl {
+ __le32 addr_l;
+ __le32 addr_h;
+ __le32 size;
+ __le32 ioc;
+} __attribute((packed));
+
+/* DSP hardware descriptor */
+struct sof_intel_dsp_desc {
+ int id;
+ int cores_num;
+ int cores_mask;
+ int ipc_req;
+ int ipc_req_mask;
+ int ipc_ack;
+ int ipc_ack_mask;
+ int ipc_ctl;
+ struct snd_sof_dsp_ops *ops;
+};
+
+#define SOF_HDA_PLAYBACK_STREAMS 16
+#define SOF_HDA_CAPTURE_STREAMS 16
+#define SOF_HDA_PLAYBACK 0
+#define SOF_HDA_CAPTURE 1
+
+/* represents DSP HDA controller frontend - i.e. host facing control */
+struct sof_intel_hda_dev {
+
+ struct hda_bus hbus;
+
+ /* hw config */
+ const struct sof_intel_dsp_desc *desc;
+
+ /*trace */
+ struct hdac_ext_stream *dtrace_stream;
+
+ /* if position update IPC needed */
+ u32 no_ipc_position;
+
+ int irq;
+
+ /* DMIC device */
+ struct platform_device *dmic_dev;
+};
+
+#define bus_to_sof_hda(bus) \
+ container_of(bus, struct sof_intel_hda_dev, hbus.core)
+
+#define SOF_STREAM_SD_OFFSET(s) \
+ (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
+ + SOF_HDA_ADSP_LOADER_BASE)
+
+/*
+ * DSP Core services.
+ */
+int hda_dsp_probe(struct snd_sof_dev *sdev);
+int hda_dsp_remove(struct snd_sof_dev *sdev);
+int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
+ unsigned int core_mask);
+int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
+ unsigned int core_mask);
+int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
+int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
+int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
+int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
+int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
+bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
+ unsigned int core_mask);
+int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
+ unsigned int core_mask);
+int hda_dsp_suspend(struct snd_sof_dev *sdev, int state);
+int hda_dsp_resume(struct snd_sof_dev *sdev);
+int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev, int state);
+int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
+void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
+void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
+
+/*
+ * DSP PCM Operations.
+ */
+int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream);
+int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream);
+int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct sof_ipc_stream_params *ipc_params);
+int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream, int cmd);
+snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream);
+
+/*
+ * DSP Stream Operations.
+ */
+
+int hda_dsp_stream_init(struct snd_sof_dev *sdev);
+void hda_dsp_stream_free(struct snd_sof_dev *sdev);
+int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
+ struct hdac_ext_stream *stream,
+ struct snd_dma_buffer *dmab,
+ struct snd_pcm_hw_params *params);
+int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
+ struct hdac_ext_stream *stream, int cmd);
+irqreturn_t hda_dsp_stream_interrupt(int irq, void *context);
+irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
+int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
+ struct snd_dma_buffer *dmab,
+ struct hdac_stream *stream);
+
+struct hdac_ext_stream *
+ hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
+int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
+int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
+ struct hdac_ext_stream *stream,
+ int enable, u32 size);
+
+/*
+ * DSP IPC Operations.
+ */
+int hda_dsp_ipc_is_ready(struct snd_sof_dev *sdev);
+int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
+ struct snd_sof_ipc_msg *msg);
+int hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev,
+ struct snd_sof_ipc_msg *msg);
+int hda_dsp_ipc_fw_ready(struct snd_sof_dev *sdev, u32 msg_id);
+irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context);
+irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
+int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
+
+/*
+ * DSP Code loader.
+ */
+int hda_dsp_cl_load_fw(struct snd_sof_dev *sdev);
+int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
+int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
+
+/* pre and post fw run ops */
+int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
+int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
+
+/*
+ * HDA Controller Operations.
+ */
+int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
+int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
+void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
+int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
+int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
+
+/*
+ * HDA bus operations.
+ */
+void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev,
+ const struct hdac_ext_bus_ops *ext_ops);
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+/*
+ * HDA Codec operations.
+ */
+int hda_codec_probe_bus(struct snd_sof_dev *sdev);
+
+#endif /* CONFIG_SND_SOC_SOF_HDA */
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)
+
+int hda_codec_i915_get(struct snd_sof_dev *sdev);
+int hda_codec_i915_put(struct snd_sof_dev *sdev);
+int hda_codec_i915_init(struct snd_sof_dev *sdev);
+int hda_codec_i915_exit(struct snd_sof_dev *sdev);
+
+#else
+
+static inline int hda_codec_i915_get(struct snd_sof_dev *sdev) { return 0; }
+static inline int hda_codec_i915_put(struct snd_sof_dev *sdev) { return 0; }
+static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
+static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
+
+#endif /* CONFIG_SND_SOC_SOF_HDA && CONFIG_SND_SOC_HDAC_HDMI */
+
+/*
+ * Trace Control.
+ */
+int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
+int hda_dsp_trace_release(struct snd_sof_dev *sdev);
+int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
+
+/* common dai driver */
+extern struct snd_soc_dai_driver skl_dai[];
+
+/*
+ * Platform Specific HW abstraction Ops.
+ */
+extern struct snd_sof_dsp_ops sof_apl_ops;
+extern struct snd_sof_dsp_ops sof_cnl_ops;
+extern struct snd_sof_dsp_ops sof_skl_ops;
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 05/21] ASoC: SOF: Intel: Add HDA controller for Intel DSP
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (3 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 04/21] ASoC: SOF: Intel: Add APL/CNL " Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 06/21] ASoC: SOF: Intel: Add Intel specific HDA DSP HW operations Pierre-Louis Bossart
` (15 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Support HDA controller operations for DSP and provide space for future
DSP HDA FW integration.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-ctrl.c | 166 +++++++++++++++++++++++++++++++++
1 file changed, 166 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-ctrl.c
diff --git a/sound/soc/sof/intel/hda-ctrl.c b/sound/soc/sof/intel/hda-ctrl.c
new file mode 100644
index 000000000000..e8f27012ec11
--- /dev/null
+++ b/sound/soc/sof/intel/hda-ctrl.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for generic Intel audio DSP HDA IP
+ */
+
+#include <sound/hdaudio_ext.h>
+#include <sound/hda_register.h>
+#include "../ops.h"
+#include "hda.h"
+
+/*
+ * HDA Operations.
+ */
+
+int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)
+{
+ unsigned long timeout;
+ u32 gctl = 0;
+ u32 val;
+
+ /* 0 to enter reset and 1 to exit reset */
+ val = reset ? 0 : SOF_HDA_GCTL_RESET;
+
+ /* enter/exit HDA controller reset */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
+ SOF_HDA_GCTL_RESET, val);
+
+ /* wait to enter/exit reset */
+ timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT);
+ while (time_before(jiffies, timeout)) {
+ gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
+ if ((gctl & SOF_HDA_GCTL_RESET) == val)
+ return 0;
+ usleep_range(500, 1000);
+ }
+
+ /* enter/exit reset failed */
+ dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",
+ reset ? "reset" : "ready", gctl);
+ return -EIO;
+}
+
+int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ u32 cap, offset, feature;
+ int count = 0;
+
+ offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
+
+ do {
+ cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
+
+ dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
+ offset & SOF_HDA_CAP_NEXT_MASK);
+
+ feature = (cap & SOF_HDA_CAP_ID_MASK) >> SOF_HDA_CAP_ID_OFF;
+
+ switch (feature) {
+ case SOF_HDA_PP_CAP_ID:
+ dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
+ offset);
+ bus->ppcap = bus->remap_addr + offset;
+ sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
+ break;
+ case SOF_HDA_SPIB_CAP_ID:
+ dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
+ offset);
+ bus->spbcap = bus->remap_addr + offset;
+ sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
+ break;
+ case SOF_HDA_DRSM_CAP_ID:
+ dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
+ offset);
+ bus->drsmcap = bus->remap_addr + offset;
+ sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
+ break;
+ case SOF_HDA_GTS_CAP_ID:
+ dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
+ offset);
+ bus->gtscap = bus->remap_addr + offset;
+ break;
+ case SOF_HDA_ML_CAP_ID:
+ dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
+ offset);
+ bus->mlcap = bus->remap_addr + offset;
+ break;
+ default:
+ dev_vdbg(sdev->dev, "found capability %d at 0x%x\n",
+ feature, offset);
+ break;
+ }
+
+ offset = cap & SOF_HDA_CAP_NEXT_MASK;
+ } while (count++ <= SOF_HDA_MAX_CAPS && offset);
+
+ return 0;
+}
+
+void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
+{
+ u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0;
+
+ snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
+}
+
+/*
+ * enable/disable audio dsp clock gating and power gating bits.
+ * This allows the HW to opportunistically power and clock gate
+ * the audio dsp when it is idle
+ */
+int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
+{
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ struct hdac_bus *bus = sof_to_bus(sdev);
+#endif
+ u32 val;
+
+ /* enable/disable audio dsp clock gating */
+ val = enable ? PCI_CGCTL_ADSPDCGE : 0;
+ snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ /* enable/disable L1 support */
+ val = enable ? SOF_HDA_VS_EM2_L1SEN : 0;
+ snd_hdac_chip_updatel(bus, VS_EM2, SOF_HDA_VS_EM2_L1SEN, val);
+#endif
+
+ /* enable/disable audio dsp power gating */
+ val = enable ? 0 : PCI_PGCTL_ADSPPGD;
+ snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+/*
+ * While performing reset, controller may not come back properly and causing
+ * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
+ * (init chip) and then again set CGCTL.MISCBDCGE to 1
+ */
+int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ int ret;
+
+ hda_dsp_ctrl_misc_clock_gating(sdev, false);
+ ret = snd_hdac_bus_init_chip(bus, full_reset);
+ hda_dsp_ctrl_misc_clock_gating(sdev, true);
+
+ return ret;
+}
+#endif
+
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 06/21] ASoC: SOF: Intel: Add Intel specific HDA DSP HW operations
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (4 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 05/21] ASoC: SOF: Intel: Add HDA controller for Intel DSP Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-12 12:04 ` Takashi Iwai
2018-12-11 21:30 ` [PATCH 07/21] ASoC: SOF: Intel: Add Intel specific HDA IPC mechanisms Pierre-Louis Bossart
` (14 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add support for various PM and core reset/run state transitions.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-dsp.c | 417 ++++++++++++++++++++++++++++++++++
1 file changed, 417 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-dsp.c
diff --git a/sound/soc/sof/intel/hda-dsp.c b/sound/soc/sof/intel/hda-dsp.c
new file mode 100644
index 000000000000..bdcbc9c8d43f
--- /dev/null
+++ b/sound/soc/sof/intel/hda-dsp.c
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for generic Intel audio DSP HDA IP
+ */
+
+#include <sound/hdaudio_ext.h>
+#include <sound/hda_register.h>
+#include "../ops.h"
+#include "hda.h"
+
+/*
+ * DSP Core control.
+ */
+
+int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
+{
+ u32 adspcs;
+ int ret;
+
+ /* set reset bits for cores */
+ snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS,
+ HDA_DSP_ADSPCS_CRST_MASK(core_mask),
+ HDA_DSP_ADSPCS_CRST_MASK(core_mask));
+
+ /* poll with timeout to check if operation successful */
+ ret = snd_sof_dsp_register_poll(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS,
+ HDA_DSP_ADSPCS_CRST_MASK(core_mask),
+ HDA_DSP_ADSPCS_CRST_MASK(core_mask),
+ HDA_DSP_RESET_TIMEOUT);
+
+ /* has core entered reset ? */
+ adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS);
+ if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
+ HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
+ dev_err(sdev->dev,
+ "error: reset enter failed: core_mask %x adspcs 0x%x\n",
+ core_mask, adspcs);
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
+{
+ u32 adspcs;
+ int ret;
+
+ /* clear reset bits for cores */
+ snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS,
+ HDA_DSP_ADSPCS_CRST_MASK(core_mask),
+ 0);
+
+ /* poll with timeout to check if operation successful */
+ ret = snd_sof_dsp_register_poll(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS,
+ HDA_DSP_ADSPCS_CRST_MASK(core_mask), 0,
+ HDA_DSP_RESET_TIMEOUT);
+
+ /* has core left reset ? */
+ adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS);
+ if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
+ dev_err(sdev->dev,
+ "error: reset leave failed: core_mask %x adspcs 0x%x\n",
+ core_mask, adspcs);
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
+{
+ /* stall core */
+ snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS,
+ HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
+ HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
+
+ /* set reset state */
+ return hda_dsp_core_reset_enter(sdev, core_mask);
+}
+
+int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
+{
+ int ret;
+
+ /* leave reset state */
+ ret = hda_dsp_core_reset_leave(sdev, core_mask);
+ if (ret < 0)
+ return ret;
+
+ /* run core */
+ dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
+ snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS,
+ HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
+ 0);
+
+ /* is core now running ? */
+ if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
+ hda_dsp_core_stall_reset(sdev, core_mask);
+ dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
+ core_mask);
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+/*
+ * Power Management.
+ */
+
+int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
+{
+ u32 adspcs;
+ int ret;
+
+ /* update bits */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
+ HDA_DSP_ADSPCS_SPA_MASK(core_mask),
+ HDA_DSP_ADSPCS_SPA_MASK(core_mask));
+
+ /* poll with timeout to check if operation successful */
+ ret = snd_sof_dsp_register_poll(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS,
+ HDA_DSP_ADSPCS_CPA_MASK(core_mask),
+ HDA_DSP_ADSPCS_CPA_MASK(core_mask),
+ HDA_DSP_PU_TIMEOUT);
+ if (ret < 0)
+ dev_err(sdev->dev, "error: timeout on core powerup\n");
+
+ /* did core power up ? */
+ adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS);
+ if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
+ HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
+ dev_err(sdev->dev,
+ "error: power up core failed core_mask %xadspcs 0x%x\n",
+ core_mask, adspcs);
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
+{
+ /* update bits */
+ snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS,
+ HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
+
+ /* poll with timeout to check if operation successful */
+ return snd_sof_dsp_register_poll(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPCS, HDA_DSP_ADSPCS_CPA_MASK(core_mask), 0,
+ HDA_DSP_PD_TIMEOUT);
+}
+
+bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
+ unsigned int core_mask)
+{
+ int val;
+ bool is_enable;
+
+ val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
+
+ is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) &&
+ (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) &&
+ !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
+ !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)));
+
+ dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
+ is_enable, core_mask);
+
+ return is_enable;
+}
+
+int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
+{
+ int ret;
+
+ /* return if core is already enabled */
+ if (hda_dsp_core_is_enabled(sdev, core_mask))
+ return 0;
+
+ /* power up */
+ ret = hda_dsp_core_power_up(sdev, core_mask);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
+ core_mask);
+ return ret;
+ }
+
+ return hda_dsp_core_run(sdev, core_mask);
+}
+
+int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
+ unsigned int core_mask)
+{
+ int ret;
+
+ /* place core in reset prior to power down */
+ ret = hda_dsp_core_stall_reset(sdev, core_mask);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
+ core_mask);
+ return ret;
+ }
+
+ /* power down core */
+ ret = hda_dsp_core_power_down(sdev, core_mask);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
+ core_mask, ret);
+ return ret;
+ }
+
+ /* make sure we are in OFF state */
+ if (hda_dsp_core_is_enabled(sdev, core_mask)) {
+ dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
+ core_mask, ret);
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static int hda_suspend(struct snd_sof_dev *sdev, int state)
+{
+ const struct sof_intel_dsp_desc *chip = sdev->hda->desc;
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ struct hdac_bus *bus = sof_to_bus(sdev);
+#endif
+ int ret = 0;
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ /* power down all hda link */
+ snd_hdac_ext_bus_link_power_down_all(bus);
+#endif
+
+ /* power down DSP */
+ ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
+ if (ret < 0) {
+ dev_err(sdev->dev,
+ "error: failed to power down core during suspend\n");
+ return ret;
+ }
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ /* disable ppcap interrupt */
+ snd_hdac_ext_bus_ppcap_int_enable(bus, false);
+ snd_hdac_ext_bus_ppcap_enable(bus, false);
+
+ /* disable hda bus irq and i/o */
+ snd_hdac_bus_stop_chip(bus);
+#endif
+
+ /* disable LP retention mode */
+ snd_sof_pci_update_bits(sdev, PCI_PGCTL,
+ PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
+
+ /* reset controller */
+ ret = hda_dsp_ctrl_link_reset(sdev, true);
+ if (ret < 0) {
+ dev_err(sdev->dev,
+ "error: failed to reset controller during suspend\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int hda_resume(struct snd_sof_dev *sdev)
+{
+ const struct sof_intel_dsp_desc *chip = sdev->hda->desc;
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct hdac_ext_link *hlink = NULL;
+#endif
+ int ret;
+
+ /*
+ * clear TCSEL to clear playback on some HD Audio
+ * codecs. PCI TCSEL is defined in the Intel manuals.
+ */
+ snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ /* reset and start hda controller */
+ ret = hda_dsp_ctrl_init_chip(sdev, true);
+ if (ret < 0) {
+ dev_err(sdev->dev,
+ "error: failed to start controller after resume\n");
+ return ret;
+ }
+
+ hda_dsp_ctrl_misc_clock_gating(sdev, false);
+
+ /* Reset stream-to-link mapping */
+ list_for_each_entry(hlink, &bus->hlink_list, list)
+ bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
+
+ hda_dsp_ctrl_misc_clock_gating(sdev, true);
+
+ /* enable ppcap interrupt */
+ snd_hdac_ext_bus_ppcap_enable(bus, true);
+ snd_hdac_ext_bus_ppcap_int_enable(bus, true);
+#else
+
+ /* reset controller */
+ ret = hda_dsp_ctrl_link_reset(sdev, true);
+ if (ret < 0) {
+ dev_err(sdev->dev,
+ "error: failed to reset controller during resume\n");
+ return ret;
+ }
+
+ /* take controller out of reset */
+ ret = hda_dsp_ctrl_link_reset(sdev, false);
+ if (ret < 0) {
+ dev_err(sdev->dev,
+ "error: failed to ready controller during resume\n");
+ return ret;
+ }
+#endif
+
+ /* power up the DSP */
+ ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
+ if (ret < 0) {
+ dev_err(sdev->dev,
+ "error: failed to power up core after resume\n");
+ return ret;
+ }
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ /* turn off the links that were off before suspend */
+ list_for_each_entry(hlink, &bus->hlink_list, list) {
+ if (!hlink->ref_count)
+ snd_hdac_ext_bus_link_power_down(hlink);
+ }
+
+ /* check dma status and clean up CORB/RIRB buffers */
+ if (!bus->cmd_dma_state)
+ snd_hdac_bus_stop_cmd_io(bus);
+#endif
+
+ return 0;
+}
+
+int hda_dsp_resume(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ int ret;
+
+ /* turn display power on */
+ ret = hda_codec_i915_get(sdev);
+ if (ret < 0) {
+ dev_err(bus->dev, "error: cannot turn on display power on i915 after resume\n");
+ return ret;
+ }
+
+ /* init hda controller and power dsp up */
+ return hda_resume(sdev);
+}
+
+int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
+{
+ /* init hda controller and power dsp up */
+ return hda_resume(sdev);
+}
+
+int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev, int state)
+{
+ /* stop hda controller and power dsp off */
+ return hda_suspend(sdev, state);
+}
+
+int hda_dsp_suspend(struct snd_sof_dev *sdev, int state)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ int ret;
+
+ /* stop hda controller and power dsp off */
+ ret = hda_suspend(sdev, state);
+ if (ret < 0) {
+ dev_err(bus->dev, "error: suspending dsp\n");
+ return ret;
+ }
+
+ /* turn display power off */
+ ret = hda_codec_i915_put(sdev);
+ if (ret < 0) {
+ dev_err(bus->dev, "error: cannot turn OFF display power on i915 during suspend\n");
+ return ret;
+ }
+
+ return 0;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 06/21] ASoC: SOF: Intel: Add Intel specific HDA DSP HW operations
2018-12-11 21:30 ` [PATCH 06/21] ASoC: SOF: Intel: Add Intel specific HDA DSP HW operations Pierre-Louis Bossart
@ 2018-12-12 12:04 ` Takashi Iwai
2018-12-12 14:48 ` Pierre-Louis Bossart
0 siblings, 1 reply; 37+ messages in thread
From: Takashi Iwai @ 2018-12-12 12:04 UTC (permalink / raw)
To: Pierre-Louis Bossart
Cc: alsa-devel, andriy.shevchenko, Keyon Jie, Daniel Baluta,
liam.r.girdwood, vkoul, broonie, sound-open-firmware, Alan Cox
On Tue, 11 Dec 2018 22:30:14 +0100,
Pierre-Louis Bossart wrote:
>
> +int hda_dsp_resume(struct snd_sof_dev *sdev)
> +{
> + struct hdac_bus *bus = sof_to_bus(sdev);
> + int ret;
> +
> + /* turn display power on */
> + ret = hda_codec_i915_get(sdev);
OK, we need to change this one for following my latest HD-audio PM
refactoring...
> + if (ret < 0) {
> + dev_err(bus->dev, "error: cannot turn on display power on i915 after resume\n");
> + return ret;
> + }
> +
> + /* init hda controller and power dsp up */
> + return hda_resume(sdev);
> +}
> +
> +int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
> +{
> + /* init hda controller and power dsp up */
> + return hda_resume(sdev);
> +}
But why can't runtime PM turn on/off the display power?
thanks,
Takashi
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 06/21] ASoC: SOF: Intel: Add Intel specific HDA DSP HW operations
2018-12-12 12:04 ` Takashi Iwai
@ 2018-12-12 14:48 ` Pierre-Louis Bossart
0 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-12 14:48 UTC (permalink / raw)
To: Takashi Iwai
Cc: Daniel Baluta, andriy.shevchenko, Keyon Jie, alsa-devel,
liam.r.girdwood, vkoul, broonie, Alan Cox, sound-open-firmware
Thanks for the reviews Takashi.
On 12/12/18 6:04 AM, Takashi Iwai wrote:
> On Tue, 11 Dec 2018 22:30:14 +0100,
> Pierre-Louis Bossart wrote:
>> +int hda_dsp_resume(struct snd_sof_dev *sdev)
>> +{
>> + struct hdac_bus *bus = sof_to_bus(sdev);
>> + int ret;
>> +
>> + /* turn display power on */
>> + ret = hda_codec_i915_get(sdev);
> OK, we need to change this one for following my latest HD-audio PM
> refactoring...
Yes, it's already tracked as an item to fix. We might change the name
even since there is no reference count any longer, so something like
hda_codec_i915_power would make more sense.
>
>> + if (ret < 0) {
>> + dev_err(bus->dev, "error: cannot turn on display power on i915 after resume\n");
>> + return ret;
>> + }
>> +
>> + /* init hda controller and power dsp up */
>> + return hda_resume(sdev);
>> +}
>> +
>> +int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
>> +{
>> + /* init hda controller and power dsp up */
>> + return hda_resume(sdev);
>> +}
> But why can't runtime PM turn on/off the display power?
I think it does? We'll double-check this.
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 07/21] ASoC: SOF: Intel: Add Intel specific HDA IPC mechanisms.
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (5 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 06/21] ASoC: SOF: Intel: Add Intel specific HDA DSP HW operations Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 08/21] ASoC: SOF: Intel: Add Intel specific HDA firmware loader Pierre-Louis Bossart
` (13 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add HDA specific IPC mechanism for Intel DSP HW.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-ipc.c | 387 ++++++++++++++++++++++++++++++++++
1 file changed, 387 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-ipc.c
diff --git a/sound/soc/sof/intel/hda-ipc.c b/sound/soc/sof/intel/hda-ipc.c
new file mode 100644
index 000000000000..5673905046cf
--- /dev/null
+++ b/sound/soc/sof/intel/hda-ipc.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for generic Intel audio DSP HDA IP
+ */
+
+#include "../ops.h"
+#include "hda.h"
+
+int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir)
+{
+ if (dir == SOF_IPC_HOST_REPLY) {
+ /*
+ * tell DSP cmd is done - clear busy
+ * interrupt and send reply msg to dsp
+ */
+ snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_HIPCT,
+ HDA_DSP_REG_HIPCT_BUSY,
+ HDA_DSP_REG_HIPCT_BUSY);
+
+ /* unmask BUSY interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_HIPCCTL,
+ HDA_DSP_REG_HIPCCTL_BUSY,
+ HDA_DSP_REG_HIPCCTL_BUSY);
+ } else {
+ /*
+ * set DONE bit - tell DSP we have received the reply msg
+ * from DSP, and processed it, don't send more reply to host
+ */
+ snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_HIPCIE,
+ HDA_DSP_REG_HIPCIE_DONE,
+ HDA_DSP_REG_HIPCIE_DONE);
+
+ /* unmask Done interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_HIPCCTL,
+ HDA_DSP_REG_HIPCCTL_DONE,
+ HDA_DSP_REG_HIPCCTL_DONE);
+ }
+
+ return 0;
+}
+
+int hda_dsp_ipc_is_ready(struct snd_sof_dev *sdev)
+{
+ u64 busy, done;
+
+ /* is DSP ready for next IPC command */
+ busy = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
+ done = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
+ if ((busy & HDA_DSP_REG_HIPCI_BUSY) ||
+ (done & HDA_DSP_REG_HIPCIE_DONE))
+ return 0;
+
+ return 1;
+}
+
+int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
+{
+ u32 cmd = msg->header;
+
+ /* send IPC message to DSP */
+ sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
+ msg->msg_size);
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
+ cmd | HDA_DSP_REG_HIPCI_BUSY);
+
+ return 0;
+}
+
+int hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev,
+ struct snd_sof_ipc_msg *msg)
+{
+ struct sof_ipc_reply reply;
+ int ret = 0;
+ u32 size;
+
+ /* get IPC reply from DSP in the mailbox */
+ sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
+ if (reply.error < 0) {
+ size = sizeof(reply);
+ ret = reply.error;
+ } else {
+ /* reply correct size ? */
+ if (reply.hdr.size != msg->reply_size) {
+ dev_err(sdev->dev, "error: reply expected 0x%zx got 0x%x bytes\n",
+ msg->reply_size, reply.hdr.size);
+ size = msg->reply_size;
+ ret = -EINVAL;
+ } else {
+ size = reply.hdr.size;
+ }
+ }
+
+ /* read the message */
+ if (msg->msg_data && size > 0)
+ sof_mailbox_read(sdev, sdev->host_box.offset,
+ msg->reply_data, size);
+
+ return ret;
+}
+
+/* IPC handler thread */
+irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context)
+{
+ struct snd_sof_dev *sdev = (struct snd_sof_dev *)context;
+ u32 hipci, hipcie, hipct, hipcte, hipcctl, msg = 0, msg_ext = 0;
+ irqreturn_t ret = IRQ_NONE;
+ int reply = -EINVAL;
+
+ /* here we handle IPC interrupts only */
+ if (!(sdev->irq_status & HDA_DSP_ADSPIS_IPC))
+ return ret;
+
+ /* read IPC status */
+ hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_HIPCIE);
+ hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
+ hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
+
+ /* is this a reply message from the DSP */
+ if (hipcie & HDA_DSP_REG_HIPCIE_DONE &&
+ hipcctl & HDA_DSP_REG_HIPCCTL_DONE) {
+
+ hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_HIPCI);
+ msg = hipci & HDA_DSP_REG_HIPCI_MSG_MASK;
+ msg_ext = hipcie & HDA_DSP_REG_HIPCIE_MSG_MASK;
+
+ dev_vdbg(sdev->dev,
+ "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
+ msg, msg_ext);
+
+ /* mask Done interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_HIPCCTL,
+ HDA_DSP_REG_HIPCCTL_DONE, 0);
+
+ /* handle immediate reply from DSP core - ignore ROM messages */
+ if (msg != 0x1004000)
+ reply = snd_sof_ipc_reply(sdev, msg);
+
+ /*
+ * handle immediate reply from DSP core. If the msg is
+ * found, set done bit in cmd_done which is called at the
+ * end of message processing function, else set it here
+ * because the done bit can't be set in cmd_done function
+ * which is triggered by msg
+ */
+ if (reply)
+ hda_dsp_ipc_cmd_done(sdev, SOF_IPC_DSP_REPLY);
+
+ ret = IRQ_HANDLED;
+ }
+
+ /* is this a new message from DSP */
+ if (hipct & HDA_DSP_REG_HIPCT_BUSY &&
+ hipcctl & HDA_DSP_REG_HIPCCTL_BUSY) {
+
+ hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_HIPCTE);
+ msg = hipct & HDA_DSP_REG_HIPCT_MSG_MASK;
+ msg_ext = hipcte & HDA_DSP_REG_HIPCTE_MSG_MASK;
+
+ dev_vdbg(sdev->dev,
+ "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
+ msg, msg_ext);
+
+ /* mask BUSY interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_HIPCCTL,
+ HDA_DSP_REG_HIPCCTL_BUSY, 0);
+
+ /* handle messages from DSP */
+ if ((hipct & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
+ /* this is a PANIC message !! */
+ snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
+ } else {
+ /* normal message - process normally*/
+ snd_sof_ipc_msgs_rx(sdev);
+ }
+
+ ret = IRQ_HANDLED;
+ }
+
+ if (ret == IRQ_HANDLED) {
+ /* reenable IPC interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
+ HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
+ }
+
+ /* wake up sleeper if we are loading code */
+ if (sdev->code_loading) {
+ sdev->code_loading = 0;
+ wake_up(&sdev->waitq);
+ }
+
+ return ret;
+}
+
+/* is this IRQ for ADSP ? - we only care about IPC here */
+irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context)
+{
+ struct snd_sof_dev *sdev = (struct snd_sof_dev *)context;
+ int ret = IRQ_NONE;
+
+ spin_lock(&sdev->hw_lock);
+
+ /* store status */
+ sdev->irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPIS);
+
+ /* invalid message ? */
+ if (sdev->irq_status == 0xffffffff)
+ goto out;
+
+ /* IPC message ? */
+ if (sdev->irq_status & HDA_DSP_ADSPIS_IPC) {
+ /* disable IPC interrupt */
+ snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
+ HDA_DSP_REG_ADSPIC,
+ HDA_DSP_ADSPIC_IPC, 0);
+ ret = IRQ_WAKE_THREAD;
+ }
+
+out:
+ spin_unlock(&sdev->hw_lock);
+ return ret;
+}
+
+/*
+ * IPC Firmware ready.
+ */
+
+static void ipc_get_windows(struct snd_sof_dev *sdev)
+{
+ struct sof_ipc_window_elem *elem;
+ u32 outbox_offset = 0;
+ u32 stream_offset = 0;
+ u32 inbox_offset = 0;
+ u32 outbox_size = 0;
+ u32 stream_size = 0;
+ u32 inbox_size = 0;
+ int i;
+
+ if (!sdev->info_window) {
+ dev_err(sdev->dev, "error: have no window info\n");
+ return;
+ }
+
+ for (i = 0; i < sdev->info_window->num_windows; i++) {
+ elem = &sdev->info_window->window[i];
+
+ switch (elem->type) {
+ case SOF_IPC_REGION_UPBOX:
+ inbox_offset =
+ elem->offset + SRAM_WINDOW_OFFSET(elem->id);
+ inbox_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HDA_DSP_BAR] +
+ inbox_offset,
+ elem->size, "inbox");
+ break;
+ case SOF_IPC_REGION_DOWNBOX:
+ outbox_offset =
+ elem->offset + SRAM_WINDOW_OFFSET(elem->id);
+ outbox_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HDA_DSP_BAR] +
+ outbox_offset,
+ elem->size, "outbox");
+ break;
+ case SOF_IPC_REGION_TRACE:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HDA_DSP_BAR] +
+ elem->offset +
+ SRAM_WINDOW_OFFSET
+ (elem->id),
+ elem->size, "etrace");
+ break;
+ case SOF_IPC_REGION_DEBUG:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HDA_DSP_BAR] +
+ elem->offset +
+ SRAM_WINDOW_OFFSET
+ (elem->id),
+ elem->size, "debug");
+ break;
+ case SOF_IPC_REGION_STREAM:
+ stream_offset =
+ elem->offset + SRAM_WINDOW_OFFSET(elem->id);
+ stream_size = elem->size;
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HDA_DSP_BAR] +
+ elem->offset +
+ SRAM_WINDOW_OFFSET
+ (elem->id),
+ elem->size, "stream");
+ break;
+ case SOF_IPC_REGION_REGS:
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HDA_DSP_BAR] +
+ elem->offset +
+ SRAM_WINDOW_OFFSET
+ (elem->id),
+ elem->size, "regs");
+ break;
+ case SOF_IPC_REGION_EXCEPTION:
+ sdev->dsp_oops_offset = elem->offset +
+ SRAM_WINDOW_OFFSET(elem->id);
+ snd_sof_debugfs_io_create_item(sdev,
+ sdev->bar[HDA_DSP_BAR] +
+ elem->offset +
+ SRAM_WINDOW_OFFSET
+ (elem->id),
+ elem->size, "exception");
+ break;
+ default:
+ dev_err(sdev->dev, "error: get illegal window info\n");
+ return;
+ }
+ }
+
+ if (outbox_size == 0 || inbox_size == 0) {
+ dev_err(sdev->dev, "error: get illegal mailbox window\n");
+ return;
+ }
+
+ snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size,
+ outbox_offset, outbox_size);
+ sdev->stream_box.offset = stream_offset;
+ sdev->stream_box.size = stream_size;
+
+ dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n",
+ inbox_offset, inbox_size);
+ dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n",
+ outbox_offset, outbox_size);
+ dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n",
+ stream_offset, stream_size);
+}
+
+int hda_dsp_ipc_fw_ready(struct snd_sof_dev *sdev, u32 msg_id)
+{
+ struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready;
+ u32 offset;
+ int ret;
+
+ /* mailbox must be on 4k boundary */
+ offset = HDA_DSP_MBOX_UPLINK_OFFSET;
+
+ dev_dbg(sdev->dev, "ipc: DSP is ready 0x%8.8x offset 0x%x\n",
+ msg_id, offset);
+
+ /* no need to re-check version/ABI for subsequent boots */
+ if (!sdev->first_boot)
+ return 0;
+
+ /* copy data from the DSP FW ready offset */
+ sof_block_read(sdev, offset, fw_ready, sizeof(*fw_ready));
+
+ /* make sure ABI version is compatible */
+ ret = snd_sof_ipc_valid(sdev);
+ if (ret < 0)
+ return ret;
+
+ /* now check for extended data */
+ snd_sof_fw_parse_ext_data(sdev, HDA_DSP_MBOX_UPLINK_OFFSET +
+ sizeof(struct sof_ipc_fw_ready));
+
+ ipc_get_windows(sdev);
+
+ return 0;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 08/21] ASoC: SOF: Intel: Add Intel specific HDA firmware loader
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (6 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 07/21] ASoC: SOF: Intel: Add Intel specific HDA IPC mechanisms Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 09/21] ASoC: SOF: Intel: Add Intel specific HDA PCM operations Pierre-Louis Bossart
` (12 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add support for loading DSP firmware on Intel HDA based platforms.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-loader.c | 369 +++++++++++++++++++++++++++++++
1 file changed, 369 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-loader.c
diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c
new file mode 100644
index 000000000000..9cadaaf24614
--- /dev/null
+++ b/sound/soc/sof/intel/hda-loader.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for HDA DSP code loader
+ */
+
+#include <linux/firmware.h>
+#include <sound/hdaudio_ext.h>
+#include <sound/sof.h>
+#include "../ops.h"
+#include "hda.h"
+
+#define HDA_FW_BOOT_ATTEMPTS 3
+
+static int cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
+ unsigned int size, struct snd_dma_buffer *dmab,
+ int direction)
+{
+ struct hdac_ext_stream *dsp_stream = NULL;
+ struct hdac_stream *hstream;
+ struct pci_dev *pci = sdev->pci;
+ int ret;
+
+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+ dsp_stream = hda_dsp_stream_get(sdev, direction);
+ } else {
+ dev_err(sdev->dev, "error: code loading DMA is playback only\n");
+ return -EINVAL;
+ }
+
+ if (!dsp_stream) {
+ dev_err(sdev->dev, "error: no stream available\n");
+ return -ENODEV;
+ }
+ hstream = &dsp_stream->hstream;
+
+ /* allocate DMA buffer */
+ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret);
+ goto error;
+ }
+
+ hstream->period_bytes = 0;/* initialize period_bytes */
+ hstream->format_val = format;
+ hstream->bufsize = size;
+
+ ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
+ goto error;
+ }
+
+ hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size);
+
+ return hstream->stream_tag;
+
+error:
+ hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
+ snd_dma_free_pages(dmab);
+ return ret;
+}
+
+/*
+ * first boot sequence has some extra steps. core 0 waits for power
+ * status on core 1, so power up core 1 also momentarily, keep it in
+ * reset/stall and then turn it off
+ */
+static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata,
+ u32 fwsize)
+{
+ int tag, ret, i;
+ u32 hipcie;
+ const struct sof_intel_dsp_desc *chip = sdev->hda->desc;
+
+ /* prepare DMA for code loader stream */
+ tag = cl_stream_prepare(sdev, 0x40, fwsize, &sdev->dmab,
+ SNDRV_PCM_STREAM_PLAYBACK);
+
+ if (tag <= 0) {
+ dev_err(sdev->dev, "error: dma prepare for fw loading err: %x\n",
+ tag);
+ return tag;
+ }
+
+ memcpy(sdev->dmab.area, fwdata, fwsize);
+
+ /* step 1: power up corex */
+ ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
+ goto err;
+ }
+
+ /* step 2: purge FW request */
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
+ chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
+ ((tag - 1) << 9)));
+
+ /* step 3: unset core 0 reset state & unstall/run core 0 */
+ ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0));
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dsp core start failed %d\n", ret);
+ ret = -EIO;
+ goto err;
+ }
+
+ /* step 4: wait for IPC DONE bit from ROM */
+ for (i = HDA_DSP_INIT_TIMEOUT; i > 0; i--) {
+ hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ chip->ipc_ack);
+
+ if (hipcie & chip->ipc_ack_mask) {
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ chip->ipc_ack,
+ chip->ipc_ack_mask,
+ chip->ipc_ack_mask);
+ goto step5;
+ }
+ mdelay(1);
+ }
+
+ dev_err(sdev->dev, "error: waiting for HIPCIE done, reg: 0x%x\n",
+ hipcie);
+ goto err;
+
+step5:
+ /* step 5: power down corex */
+ ret = hda_dsp_core_power_down(sdev,
+ chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dsp core x power down failed\n");
+ goto err;
+ }
+
+ /* step 6: enable interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
+ HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
+
+ /* enable IPC DONE interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
+ HDA_DSP_REG_HIPCCTL_DONE,
+ HDA_DSP_REG_HIPCCTL_DONE);
+
+ /* enable IPC BUSY interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
+ HDA_DSP_REG_HIPCCTL_BUSY,
+ HDA_DSP_REG_HIPCCTL_BUSY);
+
+ /* step 7: wait for ROM init */
+ ret = snd_sof_dsp_register_poll(sdev, HDA_DSP_BAR,
+ HDA_DSP_SRAM_REG_ROM_STATUS,
+ HDA_DSP_ROM_STS_MASK, HDA_DSP_ROM_INIT,
+ HDA_DSP_INIT_TIMEOUT);
+ if (ret >= 0)
+ goto out;
+
+ ret = -EIO;
+
+err:
+ hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
+ hda_dsp_core_reset_power_down(sdev, HDA_DSP_CORE_MASK(0) |
+ HDA_DSP_CORE_MASK(1));
+ return ret;
+
+out:
+ return tag;
+}
+
+static int cl_trigger(struct snd_sof_dev *sdev,
+ struct hdac_ext_stream *stream, int cmd)
+{
+ struct hdac_stream *hstream = &stream->hstream;
+ int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
+
+ /* code loader is special case that reuses stream ops */
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ wait_event_timeout(sdev->waitq, !sdev->code_loading,
+ HDA_DSP_CL_TRIGGER_TIMEOUT);
+
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
+ 1 << hstream->index,
+ 1 << hstream->index);
+
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+ sd_offset,
+ SOF_HDA_SD_CTL_DMA_START |
+ SOF_HDA_CL_DMA_SD_INT_MASK,
+ SOF_HDA_SD_CTL_DMA_START |
+ SOF_HDA_CL_DMA_SD_INT_MASK);
+
+ hstream->running = true;
+ return 0;
+ default:
+ return hda_dsp_stream_trigger(sdev, stream, cmd);
+ }
+}
+
+static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
+ struct hdac_ext_stream *stream)
+{
+ struct hdac_stream *hstream = &stream->hstream;
+ int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
+ int ret;
+
+ ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
+
+ /* TODO: spin lock ?*/
+ hstream->opened = 0;
+ hstream->running = 0;
+ hstream->substream = NULL;
+
+ /* reset BDL address */
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
+
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
+ snd_dma_free_pages(dmab);
+ dmab->area = NULL;
+ hstream->bufsize = 0;
+ hstream->format_val = 0;
+
+ return ret;
+}
+
+static int cl_copy_fw(struct snd_sof_dev *sdev, int tag)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct hdac_ext_stream *stream = NULL;
+ struct hdac_stream *s;
+ int ret, status;
+
+ /* get stream with tag */
+ list_for_each_entry(s, &bus->stream_list, list) {
+ if (s->direction == SNDRV_PCM_STREAM_PLAYBACK &&
+ s->stream_tag == tag) {
+ stream = stream_to_hdac_ext_stream(s);
+ break;
+ }
+ }
+
+ if (!stream) {
+ dev_err(sdev->dev,
+ "error: could not get stream with stream tag%d\n",
+ tag);
+ return -ENODEV;
+ }
+
+ ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: DMA trigger start failed\n");
+ return ret;
+ }
+
+ status = snd_sof_dsp_register_poll(sdev, HDA_DSP_BAR,
+ HDA_DSP_SRAM_REG_ROM_STATUS,
+ HDA_DSP_ROM_STS_MASK,
+ HDA_DSP_ROM_FW_ENTERED,
+ HDA_DSP_BASEFW_TIMEOUT);
+
+ ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: DMA trigger stop failed\n");
+ return ret;
+ }
+
+ ret = cl_cleanup(sdev, &sdev->dmab, stream);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
+ return ret;
+ }
+
+ return status;
+}
+
+int hda_dsp_cl_load_fw(struct snd_sof_dev *sdev)
+{
+ struct snd_sof_pdata *plat_data = dev_get_platdata(sdev->dev);
+ const char *fw_filename;
+
+ /* set code loading condition to true */
+ sdev->code_loading = 1;
+ fw_filename = plat_data->machine->sof_fw_filename;
+
+ return request_firmware(&plat_data->fw, fw_filename, sdev->dev);
+}
+
+int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
+{
+ struct snd_sof_pdata *plat_data = dev_get_platdata(sdev->dev);
+ struct firmware stripped_firmware;
+ int ret, tag, i;
+
+ stripped_firmware.data = plat_data->fw->data;
+ stripped_firmware.size = plat_data->fw->size;
+
+ /* init for booting wait */
+ init_waitqueue_head(&sdev->boot_wait);
+ sdev->boot_complete = false;
+
+ /* try attempting fw boot a few times before giving up */
+ for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
+ tag = cl_dsp_init(sdev, stripped_firmware.data,
+ stripped_firmware.size);
+
+ if (tag <= 0) {
+ dev_err(sdev->dev, "error: Error code=0x%x: FW status=0x%x\n",
+ snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_SRAM_REG_ROM_ERROR),
+ snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_DSP_SRAM_REG_ROM_STATUS));
+ dev_err(sdev->dev, "error: iteration %d of Core En/ROM load fail:%d\n",
+ i, tag);
+ ret = tag;
+ continue;
+ }
+
+ /* at this point DSP ROM has been initialized and
+ * should be ready for code loading and firmware boot
+ */
+ ret = cl_copy_fw(sdev, tag);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: iteration %d of load fw failed err: %d\n",
+ i, ret);
+ continue;
+ }
+
+
+ dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
+ return ret;
+ }
+
+ hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
+
+ /* disable DSP */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
+ SOF_HDA_PPCTL_GPROCEN, 0);
+ dev_err(sdev->dev, "error: load fw failed after %d attempts with err: %d\n",
+ HDA_FW_BOOT_ATTEMPTS, ret);
+ return ret;
+}
+
+/* pre fw run operations */
+int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
+{
+ /* disable clock gating and power gating */
+ return hda_dsp_ctrl_clock_power_gating(sdev, false);
+}
+
+/* post fw run operations */
+int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
+{
+ /* re-enable clock gating and power gating */
+ return hda_dsp_ctrl_clock_power_gating(sdev, true);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 09/21] ASoC: SOF: Intel: Add Intel specific HDA PCM operations
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (7 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 08/21] ASoC: SOF: Intel: Add Intel specific HDA firmware loader Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 10/21] ASoC: SOF: Intel: Add hda-bus support and initialization Pierre-Louis Bossart
` (11 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add PCM operations for Intel HDA based DSPs.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-pcm.c | 232 ++++++++++++++++++++++++++++++++++
1 file changed, 232 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-pcm.c
diff --git a/sound/soc/sof/intel/hda-pcm.c b/sound/soc/sof/intel/hda-pcm.c
new file mode 100644
index 000000000000..862283ff02a2
--- /dev/null
+++ b/sound/soc/sof/intel/hda-pcm.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for generic Intel audio DSP HDA IP
+ */
+
+#include <sound/hdaudio_ext.h>
+#include <sound/hda_register.h>
+#include <sound/pcm_params.h>
+#include "../ops.h"
+#include "hda.h"
+
+#define SDnFMT_BASE(x) ((x) << 14)
+#define SDnFMT_MULT(x) (((x) - 1) << 11)
+#define SDnFMT_DIV(x) (((x) - 1) << 8)
+#define SDnFMT_BITS(x) ((x) << 4)
+#define SDnFMT_CHAN(x) ((x) << 0)
+
+static inline u32 get_mult_div(struct snd_sof_dev *sdev, int rate)
+{
+ switch (rate) {
+ case 8000:
+ return SDnFMT_DIV(6);
+ case 9600:
+ return SDnFMT_DIV(5);
+ case 11025:
+ return SDnFMT_BASE(1) | SDnFMT_DIV(4);
+ case 16000:
+ return SDnFMT_DIV(3);
+ case 22050:
+ return SDnFMT_BASE(1) | SDnFMT_DIV(2);
+ case 32000:
+ return SDnFMT_DIV(3) | SDnFMT_MULT(2);
+ case 44100:
+ return SDnFMT_BASE(1);
+ case 48000:
+ return 0;
+ case 88200:
+ return SDnFMT_BASE(1) | SDnFMT_MULT(2);
+ case 96000:
+ return SDnFMT_MULT(2);
+ case 176400:
+ return SDnFMT_BASE(1) | SDnFMT_MULT(4);
+ case 192000:
+ return SDnFMT_MULT(4);
+ default:
+ dev_warn(sdev->dev, "can't find div rate %d using 48kHz\n",
+ rate);
+ return 0; /* use 48KHz if not found */
+ }
+};
+
+static inline u32 get_bits(struct snd_sof_dev *sdev, int sample_bits)
+{
+ switch (sample_bits) {
+ case 8:
+ return SDnFMT_BITS(0);
+ case 16:
+ return SDnFMT_BITS(1);
+ case 20:
+ return SDnFMT_BITS(2);
+ case 24:
+ return SDnFMT_BITS(3);
+ case 32:
+ return SDnFMT_BITS(4);
+ default:
+ dev_warn(sdev->dev, "can't find %d bits using 16bit\n",
+ sample_bits);
+ return SDnFMT_BITS(1); /* use 16bits format if not found */
+ }
+};
+
+int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct sof_ipc_stream_params *ipc_params)
+{
+ struct hdac_stream *hstream = substream->runtime->private_data;
+ struct hdac_ext_stream *stream = stream_to_hdac_ext_stream(hstream);
+ struct snd_dma_buffer *dmab;
+ int ret;
+ u32 size, rate, bits;
+
+ size = params_buffer_bytes(params);
+ rate = get_mult_div(sdev, params_rate(params));
+ bits = get_bits(sdev, params_width(params));
+
+ hstream->substream = substream;
+
+ dmab = substream->runtime->dma_buffer_p;
+
+ hstream->format_val = rate | bits | (params_channels(params) - 1);
+ hstream->bufsize = size;
+ hstream->period_bytes = params_period_size(params);
+ hstream->no_period_wakeup =
+ (params->info & SNDRV_PCM_INFO_NO_PERIOD_WAKEUP) &&
+ (params->flags & SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP);
+
+ ret = hda_dsp_stream_hw_params(sdev, stream, dmab, params);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
+ return ret;
+ }
+
+ /* disable SPIB, to enable buffer wrap for stream */
+ hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
+
+ /* set host_period_bytes to 0 if no IPC position */
+ if (sdev->hda && sdev->hda->no_ipc_position)
+ ipc_params->host_period_bytes = 0;
+
+ ipc_params->stream_tag = hstream->stream_tag;
+
+ return 0;
+}
+
+int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream, int cmd)
+{
+ struct hdac_stream *hstream = substream->runtime->private_data;
+ struct hdac_ext_stream *stream = stream_to_hdac_ext_stream(hstream);
+
+ return hda_dsp_stream_trigger(sdev, stream, cmd);
+}
+
+snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream)
+{
+ struct hdac_stream *hstream = substream->runtime->private_data;
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_sof_pcm *spcm = rtd->private;
+ snd_pcm_uframes_t pos = 0;
+
+ if (!sdev->hda->no_ipc_position) {
+ /* read position from IPC position */
+ pos = spcm->stream[substream->stream].posn.host_posn;
+ goto found;
+ }
+
+ /*
+ * DPIB/posbuf position mode:
+ * For Playback, Use DPIB register from HDA space which
+ * reflects the actual data transferred.
+ * For Capture, Use the position buffer for pointer, as DPIB
+ * is not accurate enough, its update may be completed
+ * earlier than the data written to DDR.
+ */
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+ AZX_REG_VS_SDXDPIB_XBASE +
+ (AZX_REG_VS_SDXDPIB_XINTERVAL *
+ hstream->index));
+ } else {
+ /*
+ * For capture stream, we need more workaround to fix the
+ * position incorrect issue:
+ *
+ * 1. Wait at least 20us before reading position buffer after
+ * the interrupt generated(IOC), to make sure position update
+ * happens on frame boundary i.e. 20.833uSec for 48KHz.
+ * 2. Perform a dummy Read to DPIB register to flush DMA
+ * position value.
+ * 3. Read the DMA Position from posbuf. Now the readback
+ * value should be >= period boundary.
+ */
+ usleep_range(20, 21);
+ snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+ AZX_REG_VS_SDXDPIB_XBASE +
+ (AZX_REG_VS_SDXDPIB_XINTERVAL *
+ hstream->index));
+ pos = snd_hdac_stream_get_pos_posbuf(hstream);
+ }
+
+ if (pos >= hstream->bufsize)
+ pos = 0;
+
+found:
+ pos = bytes_to_frames(substream->runtime, pos);
+
+ dev_vdbg(sdev->dev, "PCM: stream %d dir %d position %lu\n",
+ hstream->index, substream->stream, pos);
+ return pos;
+}
+
+int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream)
+{
+ struct hdac_ext_stream *dsp_stream;
+ int direction = substream->stream;
+
+ dsp_stream = hda_dsp_stream_get(sdev, direction);
+
+ if (!dsp_stream) {
+ dev_err(sdev->dev, "error: no stream available\n");
+ return -ENODEV;
+ }
+
+ /* binding pcm substream to hda stream */
+ substream->runtime->private_data = &dsp_stream->hstream;
+ return 0;
+}
+
+int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
+ struct snd_pcm_substream *substream)
+{
+ struct hdac_stream *hstream = substream->runtime->private_data;
+ int direction = substream->stream;
+ int ret;
+
+ ret = hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
+
+ if (ret) {
+ dev_dbg(sdev->dev, "stream %s not opened!\n", substream->name);
+ return -ENODEV;
+ }
+
+ /* unbinding pcm substream to hda stream */
+ substream->runtime->private_data = NULL;
+ return 0;
+}
+
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 10/21] ASoC: SOF: Intel: Add hda-bus support and initialization
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (8 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 09/21] ASoC: SOF: Intel: Add Intel specific HDA PCM operations Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 11/21] ASoC: SOF: Intel: Add Intel specific HDA stream operations Pierre-Louis Bossart
` (10 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Keyon Jie <yang.jie@linux.intel.com>
Use hdac_io_ops and configure all required spin_locks/mutex to use
hdac_hda_ext library. Keep the code conditional so that the HDA link
and audio codec support can be removed.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-bus.c | 107 ++++++++++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-bus.c
diff --git a/sound/soc/sof/intel/hda-bus.c b/sound/soc/sof/intel/hda-bus.c
new file mode 100644
index 000000000000..cadf559f5a82
--- /dev/null
+++ b/sound/soc/sof/intel/hda-bus.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Keyon Jie <yang.jie@linux.intel.com>
+
+#include <sound/hdaudio.h>
+#include "../sof-priv.h"
+#include "hda.h"
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+
+static const struct hdac_bus_ops bus_ops = {
+ .command = snd_hdac_bus_send_cmd,
+ .get_response = snd_hdac_bus_get_response,
+};
+
+#endif
+
+static void sof_hda_writel(u32 value, u32 __iomem *addr)
+{
+ writel(value, addr);
+}
+
+static u32 sof_hda_readl(u32 __iomem *addr)
+{
+ return readl(addr);
+}
+
+static void sof_hda_writew(u16 value, u16 __iomem *addr)
+{
+ writew(value, addr);
+}
+
+static u16 sof_hda_readw(u16 __iomem *addr)
+{
+ return readw(addr);
+}
+
+static void sof_hda_writeb(u8 value, u8 __iomem *addr)
+{
+ writeb(value, addr);
+}
+
+static u8 sof_hda_readb(u8 __iomem *addr)
+{
+ return readb(addr);
+}
+
+static int sof_hda_dma_alloc_pages(struct hdac_bus *bus, int type,
+ size_t size, struct snd_dma_buffer *buf)
+{
+ return snd_dma_alloc_pages(type, bus->dev, size, buf);
+}
+
+static void sof_hda_dma_free_pages(struct hdac_bus *bus,
+ struct snd_dma_buffer *buf)
+{
+ snd_dma_free_pages(buf);
+}
+
+static const struct hdac_io_ops io_ops = {
+ .reg_writel = sof_hda_writel,
+ .reg_readl = sof_hda_readl,
+ .reg_writew = sof_hda_writew,
+ .reg_readw = sof_hda_readw,
+ .reg_writeb = sof_hda_writeb,
+ .reg_readb = sof_hda_readb,
+ .dma_alloc_pages = sof_hda_dma_alloc_pages,
+ .dma_free_pages = sof_hda_dma_free_pages,
+};
+
+/*
+ * This can be used for both with/without hda link support.
+ */
+void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev,
+ const struct hdac_ext_bus_ops *ext_ops)
+{
+ static int idx;
+
+ memset(bus, 0, sizeof(*bus));
+ bus->dev = dev;
+
+ bus->io_ops = &io_ops;
+ INIT_LIST_HEAD(&bus->stream_list);
+
+ bus->irq = -1;
+ bus->ext_ops = ext_ops;
+ bus->idx = idx++;
+
+ spin_lock_init(&bus->reg_lock);
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ INIT_LIST_HEAD(&bus->codec_list);
+ INIT_LIST_HEAD(&bus->hlink_list);
+
+ mutex_init(&bus->cmd_mutex);
+ mutex_init(&bus->lock);
+ bus->ops = &bus_ops;
+ INIT_WORK(&bus->unsol_work, snd_hdac_bus_process_unsol_events);
+ bus->cmd_dma_state = true;
+#endif
+
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 11/21] ASoC: SOF: Intel: Add Intel specific HDA stream operations
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (9 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 10/21] ASoC: SOF: Intel: Add hda-bus support and initialization Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 12/21] ASoC: SOF: Intel: Add Intel specific HDA trace operations Pierre-Louis Bossart
` (9 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add support or HDA DSP stream operations for Intel HDA DSPs.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-stream.c | 661 +++++++++++++++++++++++++++++++
1 file changed, 661 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-stream.c
diff --git a/sound/soc/sof/intel/hda-stream.c b/sound/soc/sof/intel/hda-stream.c
new file mode 100644
index 000000000000..815a74994bbc
--- /dev/null
+++ b/sound/soc/sof/intel/hda-stream.c
@@ -0,0 +1,661 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for generic Intel audio DSP HDA IP
+ */
+
+#include <linux/pm_runtime.h>
+#include <sound/hdaudio_ext.h>
+#include <sound/hda_register.h>
+#include <sound/sof.h>
+#include "../ops.h"
+#include "hda.h"
+
+/*
+ * set up one of BDL entries for a stream
+ */
+static int hda_setup_bdle(struct snd_sof_dev *sdev,
+ struct snd_dma_buffer *dmab,
+ struct hdac_stream *stream,
+ struct sof_intel_dsp_bdl **bdlp,
+ int offset, int size, int ioc)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct sof_intel_dsp_bdl *bdl = *bdlp;
+
+ while (size > 0) {
+ dma_addr_t addr;
+ int chunk;
+
+ if (stream->frags >= HDA_DSP_MAX_BDL_ENTRIES) {
+ dev_err(sdev->dev, "error: stream frags exceeded\n");
+ return -EINVAL;
+ }
+
+ addr = snd_sgbuf_get_addr(dmab, offset);
+ /* program BDL addr */
+ bdl->addr_l = cpu_to_le32(lower_32_bits(addr));
+ bdl->addr_h = cpu_to_le32(upper_32_bits(addr));
+ /* program BDL size */
+ chunk = snd_sgbuf_get_chunk_size(dmab, offset, size);
+ /* one BDLE should not cross 4K boundary */
+ if (bus->align_bdle_4k) {
+ u32 remain = 0x1000 - (offset & 0xfff);
+
+ if (chunk > remain)
+ chunk = remain;
+ }
+ bdl->size = cpu_to_le32(chunk);
+ /* only program IOC when the whole segment is processed */
+ size -= chunk;
+ bdl->ioc = (size || !ioc) ? 0 : cpu_to_le32(0x01);
+ bdl++;
+ stream->frags++;
+ offset += chunk;
+
+ dev_vdbg(sdev->dev, "bdl, frags:%d, chunk size:0x%x;\n",
+ stream->frags, chunk);
+ }
+
+ *bdlp = bdl;
+ return offset;
+}
+
+/*
+ * set up Buffer Descriptor List (BDL) for host memory transfer
+ * BDL describes the location of the individual buffers and is little endian.
+ */
+int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
+ struct snd_dma_buffer *dmab,
+ struct hdac_stream *stream)
+{
+ struct sof_intel_dsp_bdl *bdl;
+ int i, offset, period_bytes, periods;
+ int remain, ioc;
+
+ period_bytes = stream->period_bytes;
+ dev_dbg(sdev->dev, "period_bytes:0x%x\n", period_bytes);
+ if (!period_bytes)
+ period_bytes = stream->bufsize;
+
+ periods = stream->bufsize / period_bytes;
+
+ dev_dbg(sdev->dev, "periods:%d\n", periods);
+
+ remain = stream->bufsize % period_bytes;
+ if (remain)
+ periods++;
+
+ /* program the initial BDL entries */
+ bdl = (struct sof_intel_dsp_bdl *)stream->bdl.area;
+ offset = 0;
+ stream->frags = 0;
+
+ /*
+ * set IOC if don't use position IPC
+ * and period_wakeup needed.
+ */
+ ioc = sdev->hda->no_ipc_position ?
+ !stream->no_period_wakeup : 0;
+
+ for (i = 0; i < periods; i++) {
+ if (i == (periods - 1) && remain)
+ /* set the last small entry */
+ offset = hda_setup_bdle(sdev, dmab,
+ stream, &bdl, offset,
+ remain, 0);
+ else
+ offset = hda_setup_bdle(sdev, dmab,
+ stream, &bdl, offset,
+ period_bytes, ioc);
+ }
+
+ return offset;
+}
+
+int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
+ struct hdac_ext_stream *stream,
+ int enable, u32 size)
+{
+ struct hdac_stream *hstream = &stream->hstream;
+ u32 mask = 0;
+
+ if (!sdev->bar[HDA_DSP_SPIB_BAR]) {
+ dev_err(sdev->dev, "error: address of spib capability is NULL\n");
+ return -EINVAL;
+ }
+
+ mask |= (1 << hstream->index);
+
+ /* enable/disable SPIB for the stream */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR,
+ SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask,
+ enable << hstream->index);
+
+ /* set the SPIB value */
+ sof_io_write(sdev, stream->spib_addr, size);
+
+ return 0;
+}
+
+/* get next unused stream */
+struct hdac_ext_stream *
+hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct hdac_ext_stream *stream = NULL;
+ struct hdac_stream *s;
+
+ spin_lock_irq(&bus->reg_lock);
+
+ /* get an unused stream */
+ list_for_each_entry(s, &bus->stream_list, list) {
+ if (s->direction == direction && !s->opened) {
+ s->opened = true;
+ stream = stream_to_hdac_ext_stream(s);
+ break;
+ }
+ }
+
+ spin_unlock_irq(&bus->reg_lock);
+
+ /* stream found ? */
+ if (!stream)
+ dev_err(sdev->dev, "error: no free %s streams\n",
+ direction == SNDRV_PCM_STREAM_PLAYBACK ?
+ "playback" : "capture");
+
+ return stream;
+}
+
+/* free a stream */
+int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int tag)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct hdac_stream *s;
+
+ spin_lock_irq(&bus->reg_lock);
+
+ /* find used stream */
+ list_for_each_entry(s, &bus->stream_list, list) {
+ if (s->direction == direction &&
+ s->opened && s->stream_tag == tag) {
+ s->opened = false;
+ spin_unlock_irq(&bus->reg_lock);
+ return 0;
+ }
+ }
+
+ spin_unlock_irq(&bus->reg_lock);
+
+ dev_dbg(sdev->dev, "tag %d not opened!\n", tag);
+ return -ENODEV;
+}
+
+int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
+ struct hdac_ext_stream *stream, int cmd)
+{
+ struct hdac_stream *hstream = &stream->hstream;
+ int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
+
+ /* cmd must be for audio stream */
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ case SNDRV_PCM_TRIGGER_START:
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
+ 1 << hstream->index,
+ 1 << hstream->index);
+
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+ sd_offset,
+ SOF_HDA_SD_CTL_DMA_START |
+ SOF_HDA_CL_DMA_SD_INT_MASK,
+ SOF_HDA_SD_CTL_DMA_START |
+ SOF_HDA_CL_DMA_SD_INT_MASK);
+
+ hstream->running = true;
+ break;
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ case SNDRV_PCM_TRIGGER_STOP:
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+ sd_offset,
+ SOF_HDA_SD_CTL_DMA_START |
+ SOF_HDA_CL_DMA_SD_INT_MASK, 0x0);
+
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset +
+ SOF_HDA_ADSP_REG_CL_SD_STS,
+ SOF_HDA_CL_DMA_SD_INT_MASK);
+
+ hstream->running = false;
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
+ 1 << hstream->index, 0x0);
+ break;
+ default:
+ dev_err(sdev->dev, "error: unknown command: %d\n", cmd);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * prepare for common hdac registers settings, for both code loader
+ * and normal stream.
+ */
+int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
+ struct hdac_ext_stream *stream,
+ struct snd_dma_buffer *dmab,
+ struct snd_pcm_hw_params *params)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct hdac_stream *hstream = &stream->hstream;
+ int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
+ int ret, timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
+ u32 val, mask;
+
+ if (!stream) {
+ dev_err(sdev->dev, "error: no stream available\n");
+ return -ENODEV;
+ }
+
+ /* decouple host and link DMA */
+ mask = 0x1 << hstream->index;
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
+ mask, mask);
+
+ if (!dmab) {
+ dev_err(sdev->dev, "error: no dma buffer allocated!\n");
+ return -ENODEV;
+ }
+
+ /* clear stream status */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
+ SOF_HDA_CL_DMA_SD_INT_MASK |
+ SOF_HDA_SD_CTL_DMA_START, 0);
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
+ SOF_HDA_CL_DMA_SD_INT_MASK,
+ SOF_HDA_CL_DMA_SD_INT_MASK);
+
+ /* stream reset */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 0x1,
+ 0x1);
+ udelay(3);
+ do {
+ val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+ sd_offset);
+ if (val & 0x1)
+ break;
+ } while (--timeout);
+ if (timeout == 0) {
+ dev_err(sdev->dev, "error: stream reset failed\n");
+ return -ETIMEDOUT;
+ }
+
+ timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 0x1,
+ 0x0);
+
+ /* wait for hardware to report that stream is out of reset */
+ udelay(3);
+ do {
+ val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+ sd_offset);
+ if ((val & 0x1) == 0)
+ break;
+ } while (--timeout);
+ if (timeout == 0) {
+ dev_err(sdev->dev, "error: timeout waiting for stream reset\n");
+ return -ETIMEDOUT;
+ }
+
+ if (hstream->posbuf)
+ *hstream->posbuf = 0;
+
+ /* reset BDL address */
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+ 0x0);
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+ 0x0);
+
+ /* clear stream status */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
+ SOF_HDA_CL_DMA_SD_INT_MASK |
+ SOF_HDA_SD_CTL_DMA_START, 0);
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
+ SOF_HDA_CL_DMA_SD_INT_MASK,
+ SOF_HDA_CL_DMA_SD_INT_MASK);
+
+ hstream->frags = 0;
+
+ ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: set up of BDL failed\n");
+ return ret;
+ }
+
+ /* set up stream descriptor for DMA */
+ /* program stream tag */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
+ SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK,
+ hstream->stream_tag <<
+ SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT);
+
+ /* program cyclic buffer length */
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
+ hstream->bufsize);
+
+ /* program stream format */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+ sd_offset +
+ SOF_HDA_ADSP_REG_CL_SD_FORMAT,
+ 0xffff, hstream->format_val);
+
+ /* program last valid index */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
+ 0xffff, (hstream->frags - 1));
+
+ /* program BDL address */
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+ (u32)hstream->bdl.addr);
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+ upper_32_bits(hstream->bdl.addr));
+
+ /* enable position buffer */
+ if (!(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE)
+ & SOF_HDA_ADSP_DPLBASE_ENABLE)) {
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
+ upper_32_bits(bus->posbuf.addr));
+ snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
+ (u32)bus->posbuf.addr |
+ SOF_HDA_ADSP_DPLBASE_ENABLE);
+ }
+
+ /* set interrupt enable bits */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
+ SOF_HDA_CL_DMA_SD_INT_MASK,
+ SOF_HDA_CL_DMA_SD_INT_MASK);
+
+ /* read FIFO size */
+ if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) {
+ hstream->fifo_size =
+ snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+ sd_offset +
+ SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE);
+ hstream->fifo_size &= 0xffff;
+ hstream->fifo_size += 1;
+ } else {
+ hstream->fifo_size = 0;
+ }
+
+ return ret;
+}
+
+irqreturn_t hda_dsp_stream_interrupt(int irq, void *context)
+{
+ struct hdac_bus *bus = (struct hdac_bus *)context;
+ u32 status;
+
+ if (!pm_runtime_active(bus->dev))
+ return IRQ_NONE;
+
+ spin_lock(&bus->reg_lock);
+
+ status = snd_hdac_chip_readl(bus, INTSTS);
+ if (status == 0 || status == 0xffffffff) {
+ spin_unlock(&bus->reg_lock);
+ return IRQ_NONE;
+ }
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ /* clear rirb int */
+ status = snd_hdac_chip_readb(bus, RIRBSTS);
+ if (status & RIRB_INT_MASK) {
+ if (status & RIRB_INT_RESPONSE)
+ snd_hdac_bus_update_rirb(bus);
+ snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
+ }
+#endif
+
+ spin_unlock(&bus->reg_lock);
+
+ return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
+}
+
+irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context)
+{
+ struct hdac_bus *bus = (struct hdac_bus *)context;
+ struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
+ struct hdac_stream *s;
+ u32 status = snd_hdac_chip_readl(bus, INTSTS);
+ u32 sd_status;
+
+ /* check streams */
+ list_for_each_entry(s, &bus->stream_list, list) {
+ if (status & (1 << s->index) && s->opened) {
+ sd_status = snd_hdac_stream_readb(s, SD_STS);
+
+ dev_vdbg(bus->dev, "stream %d status 0x%x\n",
+ s->index, sd_status);
+
+ snd_hdac_stream_writeb(s, SD_STS, SD_INT_MASK);
+
+ if (!s->substream ||
+ !s->running ||
+ (sd_status & SOF_HDA_CL_DMA_SD_INT_COMPLETE) == 0)
+ continue;
+
+ /* Inform ALSA only in case not do that with IPC */
+ if (sof_hda->no_ipc_position)
+ snd_pcm_period_elapsed(s->substream);
+
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+int hda_dsp_stream_init(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct hdac_ext_stream *stream;
+ struct hdac_stream *hstream;
+ struct pci_dev *pci = sdev->pci;
+ int sd_offset;
+ int i, num_playback, num_capture, num_total, ret;
+ u32 gcap;
+
+ gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP);
+ dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap);
+
+ /* get stream count from GCAP */
+ num_capture = (gcap >> 8) & 0x0f;
+ num_playback = (gcap >> 12) & 0x0f;
+ num_total = num_playback + num_capture;
+
+ dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n",
+ num_playback, num_capture);
+
+ if (num_playback >= SOF_HDA_PLAYBACK_STREAMS) {
+ dev_err(sdev->dev, "error: too many playback streams %d\n",
+ num_playback);
+ return -EINVAL;
+ }
+
+ if (num_capture >= SOF_HDA_CAPTURE_STREAMS) {
+ dev_err(sdev->dev, "error: too many capture streams %d\n",
+ num_playback);
+ return -EINVAL;
+ }
+
+ /* mem alloc for the position buffer */
+ /* TODO: check position buffer update */
+ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
+ SOF_HDA_DPIB_ENTRY_SIZE * num_total,
+ &bus->posbuf);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: posbuffer dma alloc failed\n");
+ return -ENOMEM;
+ }
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ /* mem alloc for the CORB/RIRB ringbuffers */
+ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
+ PAGE_SIZE, &bus->rb);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: RB alloc failed\n");
+ return -ENOMEM;
+ }
+#endif
+
+ /* create capture streams */
+ for (i = 0; i < num_capture; i++) {
+
+ stream = devm_kzalloc(sdev->dev, sizeof(*stream), GFP_KERNEL);
+ if (!stream)
+ return -ENOMEM;
+
+ stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
+ SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
+
+ stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
+ SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
+ SOF_HDA_PPLC_INTERVAL * i;
+
+ /* do we support SPIB */
+ if (sdev->bar[HDA_DSP_SPIB_BAR]) {
+ stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
+ SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
+ SOF_HDA_SPIB_SPIB;
+
+ stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
+ SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
+ SOF_HDA_SPIB_MAXFIFO;
+ }
+
+ hstream = &stream->hstream;
+ hstream->bus = bus;
+ hstream->sd_int_sta_mask = 1 << i;
+ hstream->index = i;
+ sd_offset = SOF_STREAM_SD_OFFSET(hstream);
+ hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
+ hstream->stream_tag = i + 1;
+ hstream->opened = false;
+ hstream->running = false;
+ hstream->direction = SNDRV_PCM_STREAM_CAPTURE;
+
+ /* memory alloc for stream BDL */
+ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
+ HDA_DSP_BDL_SIZE, &hstream->bdl);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
+ return -ENOMEM;
+ }
+ hstream->posbuf = (__le32 *)(bus->posbuf.area +
+ (hstream->index) * 8);
+
+ list_add_tail(&hstream->list, &bus->stream_list);
+ }
+
+ /* create playback streams */
+ for (i = num_capture; i < num_total; i++) {
+
+ stream = devm_kzalloc(sdev->dev, sizeof(*stream), GFP_KERNEL);
+ if (!stream)
+ return -ENOMEM;
+
+ /* we always have DSP support */
+ stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
+ SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
+
+ stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
+ SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
+ SOF_HDA_PPLC_INTERVAL * i;
+
+ /* do we support SPIB */
+ if (sdev->bar[HDA_DSP_SPIB_BAR]) {
+ stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
+ SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
+ SOF_HDA_SPIB_SPIB;
+
+ stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
+ SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
+ SOF_HDA_SPIB_MAXFIFO;
+ }
+
+ hstream = &stream->hstream;
+ hstream->bus = bus;
+ hstream->sd_int_sta_mask = 1 << i;
+ hstream->index = i;
+ sd_offset = SOF_STREAM_SD_OFFSET(hstream);
+ hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
+ hstream->stream_tag = i - num_capture + 1;
+ hstream->opened = false;
+ hstream->running = false;
+ hstream->direction = SNDRV_PCM_STREAM_PLAYBACK;
+
+ /* mem alloc for stream BDL */
+ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
+ HDA_DSP_BDL_SIZE, &hstream->bdl);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
+ return -ENOMEM;
+ }
+
+ hstream->posbuf = (__le32 *)(bus->posbuf.area +
+ (hstream->index) * 8);
+
+ list_add_tail(&hstream->list, &bus->stream_list);
+ }
+
+ return 0;
+}
+
+void hda_dsp_stream_free(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ struct hdac_stream *s, *_s;
+ struct hdac_ext_stream *stream;
+
+ /* free position buffer */
+ if (bus->posbuf.area)
+ snd_dma_free_pages(&bus->posbuf);
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ /* free position buffer */
+ if (bus->rb.area)
+ snd_dma_free_pages(&bus->rb);
+#endif
+
+ list_for_each_entry_safe(s, _s, &bus->stream_list, list) {
+ /* TODO: decouple */
+
+ /* free bdl buffer */
+ if (s->bdl.area)
+ snd_dma_free_pages(&s->bdl);
+ list_del(&s->list);
+ stream = stream_to_hdac_ext_stream(s);
+ devm_kfree(sdev->dev, stream);
+ }
+}
+
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 12/21] ASoC: SOF: Intel: Add Intel specific HDA trace operations
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (10 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 11/21] ASoC: SOF: Intel: Add Intel specific HDA stream operations Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 13/21] ASoC: SOF: Intel: Add support for HDAudio codecs Pierre-Louis Bossart
` (8 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add trace operations for Intel based HDA DSPs
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-trace.c | 79 +++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-trace.c
diff --git a/sound/soc/sof/intel/hda-trace.c b/sound/soc/sof/intel/hda-trace.c
new file mode 100644
index 000000000000..5e9f73f09544
--- /dev/null
+++ b/sound/soc/sof/intel/hda-trace.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for generic Intel audio DSP HDA IP
+ */
+
+#include <sound/hdaudio_ext.h>
+#include "../ops.h"
+#include "hda.h"
+
+static int hda_dsp_trace_prepare(struct snd_sof_dev *sdev)
+{
+ struct hdac_ext_stream *stream = sdev->hda->dtrace_stream;
+ struct hdac_stream *hstream = &stream->hstream;
+ struct snd_dma_buffer *dmab = &sdev->dmatb;
+ int ret;
+
+ hstream->period_bytes = 0;/* initialize period_bytes */
+ hstream->bufsize = sdev->dmatb.bytes;
+
+ ret = hda_dsp_stream_hw_params(sdev, stream, dmab, NULL);
+ if (ret < 0)
+ dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
+
+ return ret;
+}
+
+int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *tag)
+{
+ sdev->hda->dtrace_stream = hda_dsp_stream_get(sdev,
+ SNDRV_PCM_STREAM_CAPTURE);
+
+ if (!sdev->hda->dtrace_stream) {
+ dev_err(sdev->dev,
+ "error: no available capture stream for DMA trace\n");
+ return -ENODEV;
+ }
+
+ *tag = sdev->hda->dtrace_stream->hstream.stream_tag;
+
+ /*
+ * initialize capture stream, set BDL address and return corresponding
+ * stream tag which will be sent to the firmware by IPC message.
+ */
+ return hda_dsp_trace_prepare(sdev);
+}
+
+int hda_dsp_trace_release(struct snd_sof_dev *sdev)
+{
+ struct hdac_stream *hstream;
+
+ if (sdev->hda->dtrace_stream) {
+ hstream = &sdev->hda->dtrace_stream->hstream;
+ hda_dsp_stream_put(sdev,
+ SNDRV_PCM_STREAM_CAPTURE,
+ hstream->stream_tag);
+ sdev->hda->dtrace_stream = NULL;
+ return 0;
+ }
+
+ dev_dbg(sdev->dev, "DMA trace stream is not opened!\n");
+ return -ENODEV;
+}
+
+int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd)
+{
+ return hda_dsp_stream_trigger(sdev, sdev->hda->dtrace_stream, cmd);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 13/21] ASoC: SOF: Intel: Add support for HDAudio codecs
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (11 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 12/21] ASoC: SOF: Intel: Add Intel specific HDA trace operations Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 14/21] ASoC: SOF: Intel: SKL, CNL, APL platform DAIs Pierre-Louis Bossart
` (7 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
Add probe, init and cleanup routines for HDaudio.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-codec.c | 185 ++++++++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-codec.c
diff --git a/sound/soc/sof/intel/hda-codec.c b/sound/soc/sof/intel/hda-codec.c
new file mode 100644
index 000000000000..8d0fe7b7554e
--- /dev/null
+++ b/sound/soc/sof/intel/hda-codec.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Keyon Jie <yang.jie@linux.intel.com>
+//
+
+#include <sound/hdaudio_ext.h>
+#include <sound/hda_codec.h>
+#include <sound/hda_i915.h>
+#include <sound/sof.h>
+#include "../ops.h"
+#include "hda.h"
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
+#include "../../codecs/hdac_hda.h"
+#endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */
+
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
+#define IDISP_VID_INTEL 0x80860000
+
+/* load the legacy HDA codec driver */
+#ifdef MODULE
+static void hda_codec_load_module(struct hda_codec *codec)
+{
+ char alias[MODULE_NAME_LEN];
+ const char *module = alias;
+
+ snd_hdac_codec_modalias(&codec->core, alias, sizeof(alias));
+ dev_dbg(&codec->core.dev, "loading codec module: %s\n", module);
+ request_module(module);
+}
+#else
+static void hda_codec_load_module(struct hda_codec *codec) {}
+#endif
+
+#endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */
+
+/* probe individual codec */
+static int hda_codec_probe(struct snd_sof_dev *sdev, int address)
+{
+ struct hda_bus *hbus = sof_to_hbus(sdev);
+ struct hdac_device *hdev;
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
+ struct hdac_hda_priv *hda_priv;
+#endif
+ u32 hda_cmd = (address << 28) | (AC_NODE_ROOT << 20) |
+ (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
+ u32 resp = -1;
+ int ret;
+
+ mutex_lock(&hbus->core.cmd_mutex);
+ snd_hdac_bus_send_cmd(&hbus->core, hda_cmd);
+ snd_hdac_bus_get_response(&hbus->core, address, &resp);
+ mutex_unlock(&hbus->core.cmd_mutex);
+ if (resp == -1)
+ return -EIO;
+ dev_dbg(sdev->dev, "HDA codec #%d probed OK: response: %x\n",
+ address, resp);
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
+ /* snd_hdac_ext_bus_device_exit will use kfree to free hdev */
+ hda_priv = kzalloc(sizeof(*hda_priv), GFP_KERNEL);
+ if (!hda_priv)
+ return -ENOMEM;
+
+ hda_priv->codec.bus = hbus;
+ hdev = &hda_priv->codec.core;
+
+ ret = snd_hdac_ext_bus_device_init(&hbus->core, address, hdev);
+ if (ret < 0)
+ return ret;
+
+ /* use legacy bus only for HDA codecs, idisp uses ext bus */
+ if ((resp & 0xFFFF0000) != IDISP_VID_INTEL) {
+ hdev->type = HDA_DEV_LEGACY;
+ hda_codec_load_module(&hda_priv->codec);
+ }
+
+ return 0;
+#else
+ /* snd_hdac_ext_bus_device_exit will use kfree to free hdev */
+ hdev = kzalloc(sizeof(*hdev), GFP_KERNEL);
+ if (!hdev)
+ return -ENOMEM;
+
+ ret = snd_hdac_ext_bus_device_init(&hbus->core, address, hdev);
+
+ return ret;
+#endif
+}
+
+/* Codec initialization */
+int hda_codec_probe_bus(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ int i, ret = 0;
+
+ /* probe codecs in avail slots */
+ for (i = 0; i < HDA_MAX_CODECS; i++) {
+
+ if (!(bus->codec_mask & (1 << i)))
+ continue;
+
+ ret = hda_codec_probe(sdev, i);
+ if (ret < 0) {
+ dev_err(bus->dev, "error: codec #%d probe error, ret: %d\n",
+ i, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(hda_codec_probe_bus);
+
+#if IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)
+
+int hda_codec_i915_get(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ int ret;
+
+ dev_dbg(bus->dev, "Turning i915 HDAC power on\n");
+ ret = snd_hdac_display_power(bus, true);
+ if (ret < 0)
+ dev_err(bus->dev, "error: i915 HDAC power on failed %d\n", ret);
+
+ return ret;
+}
+EXPORT_SYMBOL(hda_codec_i915_get);
+
+int hda_codec_i915_put(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ int ret;
+
+ dev_dbg(bus->dev, "Turning i915 HDAC power off\n");
+ ret = snd_hdac_display_power(bus, false);
+ if (ret < 0)
+ dev_err(bus->dev, "error: i915 HDAC power off failed %d\n", ret);
+
+ return ret;
+}
+EXPORT_SYMBOL(hda_codec_i915_put);
+
+int hda_codec_i915_init(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ int ret;
+
+ /* i915 exposes a HDA codec for HDMI audio */
+ ret = snd_hdac_i915_init(bus);
+ if (ret < 0)
+ return ret;
+
+ ret = hda_codec_i915_get(sdev);
+
+ return ret;
+}
+EXPORT_SYMBOL(hda_codec_i915_init);
+
+int hda_codec_i915_exit(struct snd_sof_dev *sdev)
+{
+ struct hdac_bus *bus = sof_to_bus(sdev);
+ int ret;
+
+ /*
+ * we don't need to decrease the refcount with
+ * hda_codec_i915_put() on exit since the device cannot be
+ * active
+ */
+
+ ret = snd_hdac_i915_exit(bus);
+
+ return ret;
+}
+EXPORT_SYMBOL(hda_codec_i915_exit);
+
+#endif /* CONFIG_SND_SOC_HDAC_HDMI */
+
+MODULE_LICENSE("Dual BSD/GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 14/21] ASoC: SOF: Intel: SKL, CNL, APL platform DAIs
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (12 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 13/21] ASoC: SOF: Intel: Add support for HDAudio codecs Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 15/21] ASoC: SOF: Intel: Add platform differentiation for SKL, APL and CNL Pierre-Louis Bossart
` (6 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Keyon Jie <yang.jie@linux.intel.com>
Add declarations for DAIs and utilities for link DMA management
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-dai.c | 368 ++++++++++++++++++++++++++++++++++
1 file changed, 368 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-dai.c
diff --git a/sound/soc/sof/intel/hda-dai.c b/sound/soc/sof/intel/hda-dai.c
new file mode 100644
index 000000000000..801d45e0218e
--- /dev/null
+++ b/sound/soc/sof/intel/hda-dai.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Keyon Jie <yang.jie@linux.intel.com>
+//
+
+#include <sound/pcm_params.h>
+#include <sound/hdaudio_ext.h>
+#include "../sof-priv.h"
+#include "hda.h"
+
+#define SKL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+
+struct hda_pipe_params {
+ u8 host_dma_id;
+ u8 link_dma_id;
+ u32 ch;
+ u32 s_freq;
+ u32 s_fmt;
+ u8 linktype;
+ snd_pcm_format_t format;
+ int link_index;
+ int stream;
+ unsigned int host_bps;
+ unsigned int link_bps;
+};
+
+/* Unlike GP dma, there is a set of stream registers in hda controller to
+ * control the link dma channels. Each register controls one link dma
+ * channel and the relation is fixed. To make sure FW uses the correct
+ * link dma channel, host allocates stream register and sends the
+ * corresponding link dma channel to FW to allocate link dma channel
+ *
+ * FIXME: this API is abused in the sense that tx_num and rx_num are
+ * passed as arguments, not returned. We need to find a better way to
+ * retrieve the stream tag allocated for the link DMA
+ *
+ */
+static int hda_link_dma_get_channels(struct snd_soc_dai *dai,
+ unsigned int *tx_num,
+ unsigned int *tx_slot,
+ unsigned int *rx_num,
+ unsigned int *rx_slot)
+{
+ struct hdac_bus *bus;
+ struct hdac_ext_stream *stream;
+ struct snd_pcm_substream substream;
+ struct snd_sof_dev *sdev =
+ snd_soc_component_get_drvdata(dai->component);
+
+ bus = sof_to_bus(sdev);
+
+ memset(&substream, 0, sizeof(substream));
+ if (*tx_num == 1) {
+ substream.stream = SNDRV_PCM_STREAM_PLAYBACK;
+ stream = snd_hdac_ext_stream_assign(bus, &substream,
+ HDAC_EXT_STREAM_TYPE_LINK);
+ if (!stream) {
+ dev_err(bus->dev, "error: failed to find a free hda ext stream for playback");
+ return -EBUSY;
+ }
+
+ snd_soc_dai_set_dma_data(dai, &substream, (void *)stream);
+ *tx_slot = hdac_stream(stream)->stream_tag - 1;
+
+ dev_dbg(bus->dev, "link dma channel %d for playback", *tx_slot);
+ }
+
+ if (*rx_num == 1) {
+ substream.stream = SNDRV_PCM_STREAM_CAPTURE;
+ stream = snd_hdac_ext_stream_assign(bus, &substream,
+ HDAC_EXT_STREAM_TYPE_LINK);
+ if (!stream) {
+ dev_err(bus->dev, "error: failed to find a free hda ext stream for capture");
+ return -EBUSY;
+ }
+
+ snd_soc_dai_set_dma_data(dai, &substream, (void *)stream);
+ *rx_slot = hdac_stream(stream)->stream_tag - 1;
+
+ dev_dbg(bus->dev, "link dma channel %d for capture", *rx_slot);
+ }
+
+ return 0;
+}
+
+static int hda_link_dma_params(struct hdac_ext_stream *stream,
+ struct hda_pipe_params *params)
+{
+ struct hdac_stream *hstream = &stream->hstream;
+ struct hdac_bus *bus = hstream->bus;
+ unsigned int format_val;
+ struct hdac_ext_link *link;
+
+ snd_hdac_ext_stream_decouple(bus, stream, true);
+ snd_hdac_ext_link_stream_reset(stream);
+
+ format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
+ params->format,
+ params->link_bps, 0);
+
+ dev_dbg(bus->dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
+ format_val, params->s_freq, params->ch, params->format);
+
+ snd_hdac_ext_link_stream_setup(stream, format_val);
+
+ list_for_each_entry(link, &bus->hlink_list, list) {
+ if (link->index == params->link_index)
+ snd_hdac_ext_link_set_stream_id(link,
+ hstream->stream_tag);
+ }
+
+ stream->link_prepared = 1;
+
+ return 0;
+}
+
+static int hda_link_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct hdac_stream *hstream = substream->runtime->private_data;
+ struct hdac_bus *bus = hstream->bus;
+ struct hdac_ext_stream *link_dev;
+ struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ struct hda_pipe_params p_params = {0};
+ struct hdac_ext_link *link;
+ int stream_tag;
+
+ link_dev = snd_soc_dai_get_dma_data(dai, substream);
+
+ link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name);
+ if (!link)
+ return -EINVAL;
+
+ stream_tag = hdac_stream(link_dev)->stream_tag;
+
+ /* set the stream tag in the codec dai dma params */
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0);
+ else
+ snd_soc_dai_set_tdm_slot(codec_dai, 0, stream_tag, 0, 0);
+
+ p_params.s_fmt = snd_pcm_format_width(params_format(params));
+ p_params.ch = params_channels(params);
+ p_params.s_freq = params_rate(params);
+ p_params.stream = substream->stream;
+ p_params.link_dma_id = stream_tag - 1;
+ p_params.link_index = link->index;
+ p_params.format = params_format(params);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ p_params.link_bps = codec_dai->driver->playback.sig_bits;
+ else
+ p_params.link_bps = codec_dai->driver->capture.sig_bits;
+
+ return hda_link_dma_params(link_dev, &p_params);
+}
+
+static int hda_link_pcm_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ struct hdac_ext_stream *link_dev =
+ snd_soc_dai_get_dma_data(dai, substream);
+ struct hdac_stream *hstream = substream->runtime->private_data;
+ struct hdac_bus *bus = hstream->bus;
+ struct hdac_ext_stream *stream = stream_to_hdac_ext_stream(hstream);
+
+ dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ snd_hdac_ext_link_stream_start(link_dev);
+ break;
+
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_STOP:
+ snd_hdac_ext_link_stream_clear(link_dev);
+ if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
+ snd_hdac_ext_stream_decouple(bus, stream, false);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/*
+ * FIXME: This API is also abused since it's used for two purposes.
+ * when the substream argument is NULL this function is used for cleanups
+ * that aren't necessarily required, and called explicitly by handling
+ * ASoC core structures, which is not recommended.
+ * This part will be reworked in follow-up patches.
+ */
+static int hda_link_hw_free(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ const char *name;
+ unsigned int stream_tag;
+ struct hdac_bus *bus;
+ struct hdac_ext_link *link;
+ struct snd_sof_dev *sdev;
+ struct hdac_stream *hstream;
+ struct hdac_ext_stream *stream;
+ struct snd_soc_pcm_runtime *rtd;
+ struct hdac_ext_stream *link_dev;
+ struct snd_pcm_substream pcm_substream;
+
+ memset(&pcm_substream, 0, sizeof(pcm_substream));
+ if (substream) {
+ hstream = substream->runtime->private_data;
+ bus = hstream->bus;
+ rtd = snd_pcm_substream_chip(substream);
+ link_dev = snd_soc_dai_get_dma_data(dai, substream);
+ name = rtd->codec_dai->component->name;
+ link = snd_hdac_ext_bus_get_link(bus, name);
+ if (!link)
+ return -EINVAL;
+
+ stream_tag = hdac_stream(link_dev)->stream_tag;
+ snd_hdac_ext_link_clear_stream_id(link, stream_tag);
+
+ link_dev->link_prepared = 0;
+ } else {
+ /* release all hda streams when dai link is unloaded */
+ sdev = snd_soc_component_get_drvdata(dai->component);
+ pcm_substream.stream = SNDRV_PCM_STREAM_PLAYBACK;
+ stream = snd_soc_dai_get_dma_data(dai, &pcm_substream);
+ if (stream) {
+ snd_soc_dai_set_dma_data(dai, &pcm_substream, NULL);
+ snd_hdac_ext_stream_release(stream,
+ HDAC_EXT_STREAM_TYPE_LINK);
+ }
+
+ pcm_substream.stream = SNDRV_PCM_STREAM_CAPTURE;
+ stream = snd_soc_dai_get_dma_data(dai, &pcm_substream);
+ if (stream) {
+ snd_soc_dai_set_dma_data(dai, &pcm_substream, NULL);
+ snd_hdac_ext_stream_release(stream,
+ HDAC_EXT_STREAM_TYPE_LINK);
+ }
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops hda_link_dai_ops = {
+ .hw_params = hda_link_hw_params,
+ .hw_free = hda_link_hw_free,
+ .trigger = hda_link_pcm_trigger,
+ .get_channel_map = hda_link_dma_get_channels,
+};
+#endif
+
+/*
+ * common dai driver for skl+ platforms.
+ * some products who use this DAI array only physically have a subset of
+ * the DAIs, but no harm is done here by adding the whole set.
+ */
+struct snd_soc_dai_driver skl_dai[] = {
+{
+ .name = "SSP0 Pin",
+ .playback = SOF_DAI_STREAM("ssp0 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp0 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "SSP1 Pin",
+ .playback = SOF_DAI_STREAM("ssp1 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp1 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "SSP2 Pin",
+ .playback = SOF_DAI_STREAM("ssp2 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp2 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "SSP3 Pin",
+ .playback = SOF_DAI_STREAM("ssp3 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp3 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "SSP4 Pin",
+ .playback = SOF_DAI_STREAM("ssp4 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp4 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "SSP5 Pin",
+ .playback = SOF_DAI_STREAM("ssp5 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+ .capture = SOF_DAI_STREAM("ssp5 Rx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "DMIC01 Pin",
+ .capture = SOF_DAI_STREAM("DMIC01 Rx", 1, 4,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "DMIC16k Pin",
+ .capture = SOF_DAI_STREAM("DMIC16k Rx", 1, 4,
+ SNDRV_PCM_RATE_16000, SKL_FORMATS),
+},
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+{
+ .name = "iDisp1 Pin",
+ .ops = &hda_link_dai_ops,
+ .playback = SOF_DAI_STREAM("iDisp1 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "iDisp2 Pin",
+ .ops = &hda_link_dai_ops,
+ .playback = SOF_DAI_STREAM("iDisp2 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "iDisp3 Pin",
+ .ops = &hda_link_dai_ops,
+ .playback = SOF_DAI_STREAM("iDisp3 Tx", 1, 8,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "Analog CPU DAI",
+ .ops = &hda_link_dai_ops,
+ .playback = SOF_DAI_STREAM("Analog CPU Playback", 1, 16,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+ .capture = SOF_DAI_STREAM("Analog CPU Capture", 1, 16,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "Digital CPU DAI",
+ .ops = &hda_link_dai_ops,
+ .playback = SOF_DAI_STREAM("Digital CPU Playback", 1, 16,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+ .capture = SOF_DAI_STREAM("Digital CPU Capture", 1, 16,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+{
+ .name = "Alt Analog CPU DAI",
+ .ops = &hda_link_dai_ops,
+ .playback = SOF_DAI_STREAM("Alt Analog CPU Playback", 1, 16,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+ .capture = SOF_DAI_STREAM("Alt Analog CPU Capture", 1, 16,
+ SNDRV_PCM_RATE_8000_192000, SKL_FORMATS),
+},
+#endif
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 15/21] ASoC: SOF: Intel: Add platform differentiation for SKL, APL and CNL
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (13 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 14/21] ASoC: SOF: Intel: SKL, CNL, APL platform DAIs Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 16/21] ASoC: SOF: Intel: Add SKL-specific code loader Pierre-Louis Bossart
` (5 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add platform differentiation operations for different Intel HDA DSP
platforms.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/apl.c | 99 ++++++++++++++++
sound/soc/sof/intel/cnl.c | 242 ++++++++++++++++++++++++++++++++++++++
sound/soc/sof/intel/skl.c | 92 +++++++++++++++
3 files changed, 433 insertions(+)
create mode 100644 sound/soc/sof/intel/apl.c
create mode 100644 sound/soc/sof/intel/cnl.c
create mode 100644 sound/soc/sof/intel/skl.c
diff --git a/sound/soc/sof/intel/apl.c b/sound/soc/sof/intel/apl.c
new file mode 100644
index 000000000000..61832da260d8
--- /dev/null
+++ b/sound/soc/sof/intel/apl.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for audio DSP on Apollolake and GeminiLake
+ */
+
+#include "../sof-priv.h"
+#include "hda.h"
+
+static const struct snd_sof_debugfs_map apl_dsp_debugfs[] = {
+ {"hda", HDA_DSP_HDA_BAR, 0, 0x4000},
+ {"pp", HDA_DSP_PP_BAR, 0, 0x1000},
+ {"dsp", HDA_DSP_BAR, 0, 0x10000},
+};
+
+/* apollolake ops */
+struct snd_sof_dsp_ops sof_apl_ops = {
+ /* probe and remove */
+ .probe = hda_dsp_probe,
+ .remove = hda_dsp_remove,
+
+ /* Register IO */
+ .write = sof_io_write,
+ .read = sof_io_read,
+ .write64 = sof_io_write64,
+ .read64 = sof_io_read64,
+
+ /* Block IO */
+ .block_read = sof_block_read,
+ .block_write = sof_block_write,
+
+ /* doorbell */
+ .irq_handler = hda_dsp_ipc_irq_handler,
+ .irq_thread = hda_dsp_ipc_irq_thread,
+
+ /* mailbox */
+ .mailbox_read = sof_mailbox_read,
+ .mailbox_write = sof_mailbox_write,
+
+ /* ipc */
+ .send_msg = hda_dsp_ipc_send_msg,
+ .get_reply = hda_dsp_ipc_get_reply,
+ .fw_ready = hda_dsp_ipc_fw_ready,
+ .is_ready = hda_dsp_ipc_is_ready,
+ .cmd_done = hda_dsp_ipc_cmd_done,
+
+ /* debug */
+ .debug_map = apl_dsp_debugfs,
+ .debug_map_count = ARRAY_SIZE(apl_dsp_debugfs),
+ .dbg_dump = hda_dsp_dump,
+
+ /* stream callbacks */
+ .pcm_open = hda_dsp_pcm_open,
+ .pcm_close = hda_dsp_pcm_close,
+ .pcm_hw_params = hda_dsp_pcm_hw_params,
+ .pcm_trigger = hda_dsp_pcm_trigger,
+ .pcm_pointer = hda_dsp_pcm_pointer,
+
+ /* firmware loading */
+ .load_firmware = hda_dsp_cl_load_fw,
+
+ /* firmware run */
+ .run = hda_dsp_cl_boot_firmware,
+
+ /* pre/post fw run */
+ .pre_fw_run = hda_dsp_pre_fw_run,
+ .post_fw_run = hda_dsp_post_fw_run,
+
+ /* dsp core power up/down */
+ .core_power_up = hda_dsp_enable_core,
+ .core_power_down = hda_dsp_core_reset_power_down,
+
+ /* trace callback */
+ .trace_init = hda_dsp_trace_init,
+ .trace_release = hda_dsp_trace_release,
+ .trace_trigger = hda_dsp_trace_trigger,
+
+ /* DAI drivers */
+ .drv = skl_dai,
+ .num_drv = SOF_SKL_NUM_DAIS,
+
+ /* PM */
+ .suspend = hda_dsp_suspend,
+ .resume = hda_dsp_resume,
+ .runtime_suspend = hda_dsp_runtime_suspend,
+ .runtime_resume = hda_dsp_runtime_resume,
+};
+EXPORT_SYMBOL(sof_apl_ops);
diff --git a/sound/soc/sof/intel/cnl.c b/sound/soc/sof/intel/cnl.c
new file mode 100644
index 000000000000..8e10441d6c84
--- /dev/null
+++ b/sound/soc/sof/intel/cnl.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for audio DSP on Cannonlake.
+ */
+
+#include "../ops.h"
+#include "hda.h"
+
+static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
+ {"hda", HDA_DSP_HDA_BAR, 0, 0x4000},
+ {"pp", HDA_DSP_PP_BAR, 0, 0x1000},
+ {"dsp", HDA_DSP_BAR, 0, 0x10000},
+};
+
+static int cnl_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
+
+static irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
+{
+ struct snd_sof_dev *sdev = (struct snd_sof_dev *)context;
+ u32 hipci, hipcctl, hipcida, hipctdr, hipctdd, msg = 0, msg_ext = 0;
+ irqreturn_t ret = IRQ_NONE;
+
+ /* here we handle IPC interrupts only */
+ if (!(sdev->irq_status & HDA_DSP_ADSPIS_IPC))
+ return ret;
+
+ hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
+ hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
+
+ /* reply message from DSP */
+ if (hipcida & CNL_DSP_REG_HIPCIDA_DONE &&
+ hipcctl & CNL_DSP_REG_HIPCCTL_DONE) {
+ hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ CNL_DSP_REG_HIPCIDR);
+ msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
+ msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
+
+ dev_vdbg(sdev->dev,
+ "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
+ msg, msg_ext);
+
+ /* mask Done interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ CNL_DSP_REG_HIPCCTL,
+ CNL_DSP_REG_HIPCCTL_DONE, 0);
+
+ /*
+ * handle immediate reply from DSP core. If the msg is
+ * found, set done bit in cmd_done which is called at the
+ * end of message processing function, else set it here
+ * because the done bit can't be set in cmd_done function
+ * which is triggered by msg
+ */
+ if (snd_sof_ipc_reply(sdev, msg))
+ cnl_ipc_cmd_done(sdev, SOF_IPC_DSP_REPLY);
+
+ ret = IRQ_HANDLED;
+ }
+
+ hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
+
+ /* new message from DSP */
+ if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
+ hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ CNL_DSP_REG_HIPCTDD);
+ msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
+ msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
+
+ dev_vdbg(sdev->dev,
+ "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
+ msg, msg_ext);
+
+ /* handle messages from DSP */
+ if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
+ SOF_IPC_PANIC_MAGIC) {
+ snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
+ } else {
+ snd_sof_ipc_msgs_rx(sdev);
+ }
+
+ /*
+ * clear busy interrupt to tell dsp controller this
+ * interrupt has been accepted, not trigger it again
+ */
+ snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
+ CNL_DSP_REG_HIPCTDR,
+ CNL_DSP_REG_HIPCTDR_BUSY,
+ CNL_DSP_REG_HIPCTDR_BUSY);
+
+ ret = IRQ_HANDLED;
+ }
+
+ if (ret == IRQ_HANDLED) {
+ /* reenable IPC interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
+ HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
+ }
+
+ if (sdev->code_loading) {
+ sdev->code_loading = 0;
+ wake_up(&sdev->waitq);
+ }
+
+ return ret;
+}
+
+static int cnl_ipc_cmd_done(struct snd_sof_dev *sdev, int dir)
+{
+ if (dir == SOF_IPC_HOST_REPLY) {
+ /*
+ * set done bit to ack dsp the msg has been
+ * processed and send reply msg to dsp
+ */
+ snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
+ CNL_DSP_REG_HIPCTDA,
+ CNL_DSP_REG_HIPCTDA_DONE,
+ CNL_DSP_REG_HIPCTDA_DONE);
+ } else {
+ /*
+ * set DONE bit - tell DSP we have received the reply msg
+ * from DSP, and processed it, don't send more reply to host
+ */
+ snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
+ CNL_DSP_REG_HIPCIDA,
+ CNL_DSP_REG_HIPCIDA_DONE,
+ CNL_DSP_REG_HIPCIDA_DONE);
+
+ /* unmask Done interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ CNL_DSP_REG_HIPCCTL,
+ CNL_DSP_REG_HIPCCTL_DONE,
+ CNL_DSP_REG_HIPCCTL_DONE);
+ }
+
+ return 0;
+}
+
+static int cnl_ipc_is_ready(struct snd_sof_dev *sdev)
+{
+ u64 busy, done;
+
+ busy = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
+ done = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
+ if ((busy & CNL_DSP_REG_HIPCIDR_BUSY) ||
+ (done & CNL_DSP_REG_HIPCIDA_DONE))
+ return 0;
+
+ return 1;
+}
+
+static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
+ struct snd_sof_ipc_msg *msg)
+{
+ u32 cmd = msg->header;
+
+ /* send the message */
+ sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
+ msg->msg_size);
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
+ cmd | CNL_DSP_REG_HIPCIDR_BUSY);
+
+ return 0;
+}
+
+/* cannonlake ops */
+struct snd_sof_dsp_ops sof_cnl_ops = {
+ /* probe and remove */
+ .probe = hda_dsp_probe,
+ .remove = hda_dsp_remove,
+
+ /* Register IO */
+ .write = sof_io_write,
+ .read = sof_io_read,
+ .write64 = sof_io_write64,
+ .read64 = sof_io_read64,
+
+ /* Block IO */
+ .block_read = sof_block_read,
+ .block_write = sof_block_write,
+
+ /* doorbell */
+ .irq_handler = hda_dsp_ipc_irq_handler,
+ .irq_thread = cnl_ipc_irq_thread,
+
+ /* mailbox */
+ .mailbox_read = sof_mailbox_read,
+ .mailbox_write = sof_mailbox_write,
+
+ /* ipc */
+ .send_msg = cnl_ipc_send_msg,
+ .get_reply = hda_dsp_ipc_get_reply,
+ .fw_ready = hda_dsp_ipc_fw_ready,
+ .is_ready = cnl_ipc_is_ready,
+ .cmd_done = cnl_ipc_cmd_done,
+
+ /* debug */
+ .debug_map = cnl_dsp_debugfs,
+ .debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs),
+ .dbg_dump = hda_dsp_dump,
+
+ /* stream callbacks */
+ .pcm_open = hda_dsp_pcm_open,
+ .pcm_close = hda_dsp_pcm_close,
+ .pcm_hw_params = hda_dsp_pcm_hw_params,
+ .pcm_trigger = hda_dsp_pcm_trigger,
+
+ /* firmware loading */
+ .load_firmware = hda_dsp_cl_load_fw,
+
+ /* pre/post fw run */
+ .pre_fw_run = hda_dsp_pre_fw_run,
+ .post_fw_run = hda_dsp_post_fw_run,
+
+ /* dsp core power up/down */
+ .core_power_up = hda_dsp_enable_core,
+ .core_power_down = hda_dsp_core_reset_power_down,
+
+ /* firmware run */
+ .run = hda_dsp_cl_boot_firmware,
+
+ /* trace callback */
+ .trace_init = hda_dsp_trace_init,
+ .trace_release = hda_dsp_trace_release,
+ .trace_trigger = hda_dsp_trace_trigger,
+
+ /* DAI drivers */
+ .drv = skl_dai,
+ .num_drv = SOF_SKL_NUM_DAIS,
+};
+EXPORT_SYMBOL(sof_cnl_ops);
diff --git a/sound/soc/sof/intel/skl.c b/sound/soc/sof/intel/skl.c
new file mode 100644
index 000000000000..f876bee744d3
--- /dev/null
+++ b/sound/soc/sof/intel/skl.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+// Rander Wang <rander.wang@intel.com>
+// Keyon Jie <yang.jie@linux.intel.com>
+//
+
+/*
+ * Hardware interface for audio DSP on Skylake and Kabylake.
+ */
+
+#include "../sof-priv.h"
+#include "hda.h"
+
+static const struct snd_sof_debugfs_map skl_dsp_debugfs[] = {
+ {"hda", HDA_DSP_HDA_BAR, 0, 0x4000},
+ {"pp", HDA_DSP_PP_BAR, 0, 0x1000},
+ {"dsp", HDA_DSP_BAR, 0, 0x10000},
+};
+
+/* skylake ops */
+struct snd_sof_dsp_ops sof_skl_ops = {
+ /* probe and remove */
+ .probe = hda_dsp_probe,
+ .remove = hda_dsp_remove,
+
+ /* Register IO */
+ .write = sof_io_write,
+ .read = sof_io_read,
+ .write64 = sof_io_write64,
+ .read64 = sof_io_read64,
+
+ /* Block IO */
+ .block_read = sof_block_read,
+ .block_write = sof_block_write,
+
+ /* doorbell */
+ .irq_handler = hda_dsp_ipc_irq_handler,
+ .irq_thread = hda_dsp_ipc_irq_thread,
+
+ /* mailbox */
+ .mailbox_read = sof_mailbox_read,
+ .mailbox_write = sof_mailbox_write,
+
+ /* ipc */
+ .send_msg = hda_dsp_ipc_send_msg,
+ .get_reply = hda_dsp_ipc_get_reply,
+ .fw_ready = hda_dsp_ipc_fw_ready,
+ .is_ready = hda_dsp_ipc_is_ready,
+ .cmd_done = hda_dsp_ipc_cmd_done,
+
+ /* debug */
+ .debug_map = skl_dsp_debugfs,
+ .debug_map_count = ARRAY_SIZE(skl_dsp_debugfs),
+ .dbg_dump = hda_dsp_dump_skl,
+
+ /* stream callbacks */
+ .pcm_open = hda_dsp_pcm_open,
+ .pcm_close = hda_dsp_pcm_close,
+ .pcm_hw_params = hda_dsp_pcm_hw_params,
+ .pcm_trigger = hda_dsp_pcm_trigger,
+
+ /* firmware loading */
+ .load_firmware = hda_dsp_cl_load_fw,
+
+ /* pre/post fw run */
+ .pre_fw_run = hda_dsp_pre_fw_run,
+ .post_fw_run = hda_dsp_post_fw_run,
+
+ /* dsp core power up/down */
+ .core_power_up = hda_dsp_enable_core,
+ .core_power_down = hda_dsp_core_reset_power_down,
+
+ /* firmware run */
+ .run = hda_dsp_cl_boot_firmware_skl,
+
+ /* trace callback */
+ .trace_init = hda_dsp_trace_init,
+ .trace_release = hda_dsp_trace_release,
+ .trace_trigger = hda_dsp_trace_trigger,
+
+ /* DAI drivers */
+ .drv = skl_dai,
+ .num_drv = SOF_SKL_NUM_DAIS,
+};
+EXPORT_SYMBOL(sof_skl_ops);
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 16/21] ASoC: SOF: Intel: Add SKL-specific code loader
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (14 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 15/21] ASoC: SOF: Intel: Add platform differentiation for SKL, APL and CNL Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 17/21] ASoC: SOF: Add ACPI device support Pierre-Louis Bossart
` (4 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
Zhu Yingjiang, sound-open-firmware
The code loader is different on SKL/KBL and we need a dedicated
loader. From APL onwards the same code loader will be used.
Signed-off-by: Zhu Yingjiang <yingjiang.zhu@linux.intel.com>
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/intel/hda-loader-skl.c | 531 +++++++++++++++++++++++++++
sound/soc/sof/intel/hda.h | 1 +
2 files changed, 532 insertions(+)
create mode 100644 sound/soc/sof/intel/hda-loader-skl.c
diff --git a/sound/soc/sof/intel/hda-loader-skl.c b/sound/soc/sof/intel/hda-loader-skl.c
new file mode 100644
index 000000000000..8437ce7201c7
--- /dev/null
+++ b/sound/soc/sof/intel/hda-loader-skl.c
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+// Zhu Yingjiang <yingjiang.zhu@linux.intel.com>
+//
+
+#include <linux/firmware.h>
+#include <sound/hdaudio_ext.h>
+#include <sound/sof.h>
+#include "../ops.h"
+#include "hda.h"
+
+#define HDA_SKL_WAIT_TIMEOUT 500 /* 500 msec */
+#define HDA_SKL_CLDMA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
+
+/* Stream Reset */
+#define HDA_CL_SD_CTL_SRST_SHIFT 0
+#define HDA_CL_SD_CTL_SRST(x) (((x) & 0x1) << \
+ HDA_CL_SD_CTL_SRST_SHIFT)
+
+/* Stream Run */
+#define HDA_CL_SD_CTL_RUN_SHIFT 1
+#define HDA_CL_SD_CTL_RUN(x) (((x) & 0x1) << \
+ HDA_CL_SD_CTL_RUN_SHIFT)
+
+/* Interrupt On Completion Enable */
+#define HDA_CL_SD_CTL_IOCE_SHIFT 2
+#define HDA_CL_SD_CTL_IOCE(x) (((x) & 0x1) << \
+ HDA_CL_SD_CTL_IOCE_SHIFT)
+
+/* FIFO Error Interrupt Enable */
+#define HDA_CL_SD_CTL_FEIE_SHIFT 3
+#define HDA_CL_SD_CTL_FEIE(x) (((x) & 0x1) << \
+ HDA_CL_SD_CTL_FEIE_SHIFT)
+
+/* Descriptor Error Interrupt Enable */
+#define HDA_CL_SD_CTL_DEIE_SHIFT 4
+#define HDA_CL_SD_CTL_DEIE(x) (((x) & 0x1) << \
+ HDA_CL_SD_CTL_DEIE_SHIFT)
+
+/* FIFO Limit Change */
+#define HDA_CL_SD_CTL_FIFOLC_SHIFT 5
+#define HDA_CL_SD_CTL_FIFOLC(x) (((x) & 0x1) << \
+ HDA_CL_SD_CTL_FIFOLC_SHIFT)
+
+/* Stripe Control */
+#define HDA_CL_SD_CTL_STRIPE_SHIFT 16
+#define HDA_CL_SD_CTL_STRIPE(x) (((x) & 0x3) << \
+ HDA_CL_SD_CTL_STRIPE_SHIFT)
+
+/* Traffic Priority */
+#define HDA_CL_SD_CTL_TP_SHIFT 18
+#define HDA_CL_SD_CTL_TP(x) (((x) & 0x1) << \
+ HDA_CL_SD_CTL_TP_SHIFT)
+
+/* Bidirectional Direction Control */
+#define HDA_CL_SD_CTL_DIR_SHIFT 19
+#define HDA_CL_SD_CTL_DIR(x) (((x) & 0x1) << \
+ HDA_CL_SD_CTL_DIR_SHIFT)
+
+/* Stream Number */
+#define HDA_CL_SD_CTL_STRM_SHIFT 20
+#define HDA_CL_SD_CTL_STRM(x) (((x) & 0xf) << \
+ HDA_CL_SD_CTL_STRM_SHIFT)
+
+#define HDA_CL_SD_CTL_INT(x) \
+ (HDA_CL_SD_CTL_IOCE(x) | \
+ HDA_CL_SD_CTL_FEIE(x) | \
+ HDA_CL_SD_CTL_DEIE(x))
+
+#define HDA_CL_SD_CTL_INT_MASK \
+ (HDA_CL_SD_CTL_IOCE(1) | \
+ HDA_CL_SD_CTL_FEIE(1) | \
+ HDA_CL_SD_CTL_DEIE(1))
+
+#define DMA_ADDRESS_128_BITS_ALIGNMENT 7
+#define BDL_ALIGN(x) ((x) >> DMA_ADDRESS_128_BITS_ALIGNMENT)
+
+/* Buffer Descriptor List Lower Base Address */
+#define HDA_CL_SD_BDLPLBA_SHIFT 7
+#define HDA_CL_SD_BDLPLBA_MASK GENMASK(HDA_CL_SD_BDLPLBA_SHIFT + 24,\
+ HDA_CL_SD_BDLPLBA_SHIFT)
+#define HDA_CL_SD_BDLPLBA(x) \
+ ((BDL_ALIGN(lower_32_bits(x)) << HDA_CL_SD_BDLPLBA_SHIFT) & \
+ HDA_CL_SD_BDLPLBA_MASK)
+
+/* Buffer Descriptor List Upper Base Address */
+#define HDA_CL_SD_BDLPUBA_SHIFT 0
+#define HDA_CL_SD_BDLPUBA_MASK GENMASK(HDA_CL_SD_BDLPUBA_SHIFT + 31,\
+ HDA_CL_SD_BDLPUBA_SHIFT)
+#define HDA_CL_SD_BDLPUBA(x) \
+ ((upper_32_bits(x) << HDA_CL_SD_BDLPUBA_SHIFT) & \
+ HDA_CL_SD_BDLPUBA_MASK)
+
+/* Software Position in Buffer Enable */
+#define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT 0
+#define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK \
+ BIT(HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT)
+
+#define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE(x) \
+ (((x) << HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) & \
+ HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK)
+
+static int cl_skl_cldma_setup_bdle(struct snd_sof_dev *sdev,
+ struct snd_dma_buffer *dmab_data,
+ __le32 **bdlp, int size, int with_ioc)
+{
+ __le32 *bdl = *bdlp;
+ int frags = 0;
+
+ while (size > 0) {
+ phys_addr_t addr = virt_to_phys(dmab_data->area +
+ (frags * size));
+
+ bdl[0] = cpu_to_le32(lower_32_bits(addr));
+ bdl[1] = cpu_to_le32(upper_32_bits(addr));
+
+ bdl[2] = cpu_to_le32(size);
+
+ size -= size;
+ bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
+
+ bdl += 4;
+ frags++;
+ }
+
+ return frags;
+}
+
+static void cl_skl_cldma_stream_run(struct snd_sof_dev *sdev, bool enable)
+{
+ unsigned char val;
+ int timeout;
+ int sd_offset = SOF_HDA_ADSP_LOADER_BASE;
+ u32 run = enable ? 0x1 : 0;
+
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+ HDA_CL_SD_CTL_RUN(1), HDA_CL_SD_CTL_RUN(run));
+
+ udelay(3);
+ timeout = 300;
+ do {
+ /* waiting for hardware to report the stream Run bit set */
+ val = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL)
+ & HDA_CL_SD_CTL_RUN(1);
+ if (enable && val)
+ break;
+ else if (!enable && !val)
+ break;
+ udelay(3);
+ } while (--timeout);
+
+ if (timeout == 0)
+ dev_err(sdev->dev, "error: failed to set Run bit=%d enable=%d\n",
+ val, enable);
+}
+
+static void cl_skl_cldma_stream_clear(struct snd_sof_dev *sdev)
+{
+ int sd_offset = SOF_HDA_ADSP_LOADER_BASE;
+
+ /* make sure Run bit is cleared before setting stream register */
+ cl_skl_cldma_stream_run(sdev, 0);
+
+ /* Disable the Interrupt On Completion, FIFO Error Interrupt,
+ * Descriptor Error Interrupt and set the cldma stream number to 0.
+ */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+ HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(0));
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+ HDA_CL_SD_CTL_STRM(0xf), HDA_CL_SD_CTL_STRM(0));
+
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+ HDA_CL_SD_BDLPLBA(0));
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
+
+ /* Set the Cyclic Buffer Length to 0. */
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, 0);
+ /* Set the Last Valid Index. */
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, 0);
+}
+
+static void cl_skl_cldma_setup_spb(struct snd_sof_dev *sdev,
+ unsigned int size, bool enable)
+{
+ int sd_offset = SOF_DSP_REG_CL_SPBFIFO;
+
+ if (enable)
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ sd_offset +
+ SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
+ HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
+ HDA_CL_SPBFIFO_SPBFCCTL_SPIBE(1));
+
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB, size);
+}
+
+static void cl_skl_cldma_set_intr(struct snd_sof_dev *sdev, bool enable)
+{
+ u32 val = enable ? HDA_DSP_ADSPIC_CL_DMA : 0;
+
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
+ HDA_DSP_ADSPIC_CL_DMA, val);
+}
+
+static void cl_skl_cldma_cleanup_spb(struct snd_sof_dev *sdev)
+{
+ int sd_offset = SOF_DSP_REG_CL_SPBFIFO;
+
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ sd_offset +
+ SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
+ HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
+ HDA_CL_SPBFIFO_SPBFCCTL_SPIBE(0));
+
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB, 0);
+}
+
+static void cl_skl_cldma_setup_controller(struct snd_sof_dev *sdev,
+ struct snd_dma_buffer *dmab_bdl,
+ unsigned int max_size, u32 count)
+{
+ int sd_offset = SOF_HDA_ADSP_LOADER_BASE;
+ /* Clear the stream first and then set it. */
+ cl_skl_cldma_stream_clear(sdev);
+
+ /* setting the stream register */
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+ HDA_CL_SD_BDLPLBA(dmab_bdl->addr));
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+ HDA_CL_SD_BDLPUBA(dmab_bdl->addr));
+
+ /* Set the Cyclic Buffer Length. */
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL, max_size);
+ /* Set the Last Valid Index. */
+ snd_sof_dsp_write(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI, count - 1);
+
+ /* Set the Interrupt On Completion, FIFO Error Interrupt,
+ * Descriptor Error Interrupt and the cldma stream number.
+ */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+ HDA_CL_SD_CTL_INT_MASK, HDA_CL_SD_CTL_INT(1));
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
+ sd_offset + SOF_HDA_ADSP_REG_CL_SD_CTL,
+ HDA_CL_SD_CTL_STRM(0xf),
+ HDA_CL_SD_CTL_STRM(1));
+}
+
+static int cl_stream_prepare_skl(struct snd_sof_dev *sdev)
+{
+ struct pci_dev *pci = sdev->pci;
+ int frags = 0;
+ int ret = 0;
+ __le32 *bdl;
+ unsigned int bufsize = HDA_SKL_CLDMA_MAX_BUFFER_SIZE;
+
+ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, bufsize,
+ &sdev->dmab);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to alloc fw buffer: %x\n",
+ ret);
+ return ret;
+ }
+
+ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, bufsize,
+ &sdev->dmab_bdl);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: failed to alloc blde: %x\n", ret);
+ snd_dma_free_pages(&sdev->dmab);
+ return ret;
+ }
+
+ bdl = (__le32 *)sdev->dmab_bdl.area;
+ frags = cl_skl_cldma_setup_bdle(sdev, &sdev->dmab, &bdl, bufsize, 1);
+ cl_skl_cldma_setup_controller(sdev, &sdev->dmab_bdl, bufsize, frags);
+
+ return ret;
+}
+
+static void cl_cleanup_skl(struct snd_sof_dev *sdev)
+{
+ cl_skl_cldma_cleanup_spb(sdev);
+ cl_skl_cldma_stream_clear(sdev);
+ snd_dma_free_pages(&sdev->dmab);
+ snd_dma_free_pages(&sdev->dmab_bdl);
+ sdev->dmab.area = NULL;
+}
+
+static int cl_dsp_init_skl(struct snd_sof_dev *sdev)
+{
+ const struct sof_intel_dsp_desc *chip = sdev->hda->desc;
+ int ret;
+
+ /* check if the core is already enabled, if yes, reset and make it run,
+ * if not, powerdown and enable it again.
+ */
+ if (hda_dsp_core_is_enabled(sdev, HDA_DSP_CORE_MASK(0))) {
+
+ /* if enabled, reset it, and run the core. */
+ ret = hda_dsp_core_stall_reset(sdev, HDA_DSP_CORE_MASK(0));
+ if (ret < 0)
+ goto err;
+
+ ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0));
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dsp core start failed %d\n",
+ ret);
+ goto err;
+ }
+ } else {
+ /* if not enabled, power down it first and then powerup and run
+ * the core.
+ */
+ ret = hda_dsp_core_reset_power_down(sdev, HDA_DSP_CORE_MASK(0));
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dsp core0 disable fail: %d\n", ret);
+ goto err;
+ }
+ ret = hda_dsp_enable_core(sdev, HDA_DSP_CORE_MASK(0));
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dsp core0 enable fail: %d\n", ret);
+ goto err;
+ }
+ }
+
+ /* prepare DMA for code loader stream */
+ ret = cl_stream_prepare_skl(sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: dma prepare fw loading err: %x\n",
+ ret);
+ return ret;
+ }
+
+ /* enable the interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
+ HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
+
+ /* enable IPC DONE interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
+ HDA_DSP_REG_HIPCCTL_DONE,
+ HDA_DSP_REG_HIPCCTL_DONE);
+
+ /* enable IPC BUSY interrupt */
+ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
+ HDA_DSP_REG_HIPCCTL_BUSY,
+ HDA_DSP_REG_HIPCCTL_BUSY);
+
+ /* polling the ROM init status information. */
+ ret = snd_sof_dsp_register_poll(sdev, HDA_DSP_BAR,
+ HDA_ADSP_FW_STATUS_SKL,
+ HDA_DSP_ROM_STS_MASK, HDA_DSP_ROM_INIT,
+ HDA_DSP_INIT_TIMEOUT);
+ if (ret < 0)
+ goto err;
+
+ return ret;
+
+err:
+ hda_dsp_dump_skl(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
+ cl_cleanup_skl(sdev);
+ hda_dsp_core_reset_power_down(sdev, HDA_DSP_CORE_MASK(0));
+ return ret;
+}
+
+static void cl_skl_cldma_fill_buffer(struct snd_sof_dev *sdev,
+ unsigned int bufsize,
+ unsigned int copysize,
+ const void *curr_pos,
+ bool intr_enable, bool trigger)
+{
+ /* 1. copy the image into the buffer with the maximum buffer size. */
+ unsigned int size = (bufsize == copysize) ? bufsize : copysize;
+
+ memcpy(sdev->dmab.area, curr_pos, size);
+
+ /* 2. Set the interrupt. */
+ if (intr_enable)
+ cl_skl_cldma_set_intr(sdev, true);
+
+ /* 3. Set the SPB. */
+ cl_skl_cldma_setup_spb(sdev, size, trigger);
+
+ /* 4. Trigger the code loading stream. */
+ if (trigger)
+ cl_skl_cldma_stream_run(sdev, true);
+}
+
+static int
+cl_skl_cldma_copy_to_buf(struct snd_sof_dev *sdev, const void *bin,
+ u32 total_size, u32 bufsize)
+{
+ int ret = 0;
+ unsigned int bytes_left = total_size;
+ const void *curr_pos = bin;
+
+ if (total_size <= 0)
+ return -EINVAL;
+
+ while (bytes_left > 0) {
+
+ if (bytes_left > bufsize) {
+
+ dev_dbg(sdev->dev, "cldma copy 0x%x bytes\n",
+ bufsize);
+
+ cl_skl_cldma_fill_buffer(sdev, bufsize, bufsize,
+ curr_pos, true, true);
+
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: fw failed to load. 0x%x bytes remaining\n",
+ bytes_left);
+ cl_skl_cldma_stream_run(sdev, false);
+ return ret;
+ }
+
+ bytes_left -= bufsize;
+ curr_pos += bufsize;
+ } else {
+
+ dev_dbg(sdev->dev, "cldma copy 0x%x bytes\n",
+ bytes_left);
+
+ cl_skl_cldma_set_intr(sdev, false);
+ cl_skl_cldma_fill_buffer(sdev, bufsize, bytes_left,
+ curr_pos, false, false);
+ return 0;
+ }
+ }
+
+ return bytes_left;
+}
+
+static int cl_copy_fw_skl(struct snd_sof_dev *sdev)
+{
+ struct snd_sof_pdata *plat_data = dev_get_platdata(sdev->dev);
+ const struct firmware *fw = plat_data->fw;
+ unsigned int bufsize = HDA_SKL_CLDMA_MAX_BUFFER_SIZE;
+ int ret = 0;
+
+ dev_dbg(sdev->dev, "firmware size: 0x%zx buffer size 0x%x\n", fw->size,
+ bufsize);
+
+ ret = cl_skl_cldma_copy_to_buf(sdev, fw->data, fw->size, bufsize);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: fw copy failed %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_sof_dsp_register_poll(sdev, HDA_DSP_BAR,
+ HDA_ADSP_FW_STATUS_SKL,
+ HDA_DSP_ROM_STS_MASK,
+ HDA_DSP_ROM_FW_FW_LOADED,
+ HDA_DSP_BASEFW_TIMEOUT);
+ if (ret < 0)
+ dev_err(sdev->dev, "error: firmware transfer timeout!");
+
+ cl_skl_cldma_stream_run(sdev, false);
+ cl_cleanup_skl(sdev);
+
+ return ret;
+}
+
+int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev)
+{
+ int ret;
+
+ ret = cl_dsp_init_skl(sdev);
+
+ /* retry enabling core and ROM load. seemed to help */
+ if (ret < 0) {
+ ret = cl_dsp_init_skl(sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: Error code=0x%x: FW status=0x%x\n",
+ snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_ADSP_ERROR_CODE_SKL),
+ snd_sof_dsp_read(sdev, HDA_DSP_BAR,
+ HDA_ADSP_FW_STATUS_SKL));
+ dev_err(sdev->dev, "error: Core En/ROM load fail:%d\n", ret);
+ goto irq_err;
+ }
+ }
+
+ dev_dbg(sdev->dev, "ROM init successful\n");
+
+ /* init for booting wait */
+ init_waitqueue_head(&sdev->boot_wait);
+ sdev->boot_complete = false;
+
+ /* at this point DSP ROM has been initialized and should be ready for
+ * code loading and firmware boot
+ */
+ ret = cl_copy_fw_skl(sdev);
+ if (ret < 0) {
+ dev_err(sdev->dev, "error: load firmware failed : %d\n", ret);
+ goto irq_err;
+ }
+
+ dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
+
+ return ret;
+
+irq_err:
+ hda_dsp_dump_skl(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
+
+ /* power down DSP */
+ hda_dsp_core_reset_power_down(sdev, HDA_DSP_CORE_MASK(0));
+ cl_cleanup_skl(sdev);
+
+ dev_err(sdev->dev, "error: load fw failed err: %d\n", ret);
+ return ret;
+}
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 1d1b8a843ecc..4a1bbc948b9f 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -59,6 +59,7 @@
#define SOF_HDA_PP_CAP_ID 0x3
#define SOF_HDA_REG_PP_PPCH 0x10
#define SOF_HDA_REG_PP_PPCTL 0x04
+#define SOF_HDA_REG_PP_PPSTS 0x08
#define SOF_HDA_PPCTL_PIE BIT(31)
#define SOF_HDA_PPCTL_GPROCEN BIT(30)
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 17/21] ASoC: SOF: Add ACPI device support
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (15 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 16/21] ASoC: SOF: Intel: Add SKL-specific code loader Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 18/21] ASoC: SOF: Add PCI " Pierre-Louis Bossart
` (3 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pierre-Louis Bossart,
liam.r.girdwood, vkoul, broonie, Alan Cox, sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add support ACPI based SOF DSP devices.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/sof-acpi-dev.c | 269 +++++++++++++++++++++++++++++++++++
1 file changed, 269 insertions(+)
create mode 100644 sound/soc/sof/sof-acpi-dev.c
diff --git a/sound/soc/sof/sof-acpi-dev.c b/sound/soc/sof/sof-acpi-dev.c
new file mode 100644
index 000000000000..52de8ac8ede0
--- /dev/null
+++ b/sound/soc/sof/sof-acpi-dev.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+//
+
+#include <asm/iosf_mbi.h>
+#include <linux/acpi.h>
+#include <linux/firmware.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <sound/soc-acpi.h>
+#include <sound/soc-acpi-intel-match.h>
+#include <sound/sof.h>
+
+#include "ops.h"
+
+/* platform specific devices */
+#include "intel/shim.h"
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HASWELL)
+static struct sof_dev_desc sof_acpi_haswell_desc = {
+ .machines = snd_soc_acpi_intel_haswell_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = 1,
+ .resindex_imr_base = -1,
+ .irqindex_host_ipc = 0,
+ .nocodec_fw_filename = "intel/sof-hsw.ri",
+ .nocodec_tplg_filename = "intel/sof-hsw-nocodec.tplg"
+};
+#endif
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BROADWELL)
+static struct sof_dev_desc sof_acpi_broadwell_desc = {
+ .machines = snd_soc_acpi_intel_broadwell_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = 1,
+ .resindex_imr_base = -1,
+ .irqindex_host_ipc = 0,
+ .nocodec_fw_filename = "intel/sof-bdw.ri",
+ .nocodec_tplg_filename = "intel/sof-bdw-nocodec.tplg"
+};
+#endif
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
+
+/* BYTCR uses different IRQ index */
+static struct sof_dev_desc sof_acpi_baytrailcr_desc = {
+ .machines = snd_soc_acpi_intel_baytrail_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = 1,
+ .resindex_imr_base = 2,
+ .irqindex_host_ipc = 0,
+ .nocodec_fw_filename = "intel/sof-byt.ri",
+ .nocodec_tplg_filename = "intel/sof-byt-nocodec.tplg"
+};
+
+static struct sof_dev_desc sof_acpi_baytrail_desc = {
+ .machines = snd_soc_acpi_intel_baytrail_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = 1,
+ .resindex_imr_base = 2,
+ .irqindex_host_ipc = 5,
+ .nocodec_fw_filename = "intel/sof-byt.ri",
+ .nocodec_tplg_filename = "intel/sof-byt-nocodec.tplg"
+};
+
+static int is_byt_cr(struct device *dev)
+{
+ u32 bios_status;
+ int status;
+
+ if (!IS_ENABLED(CONFIG_IOSF_MBI) || !iosf_mbi_available()) {
+ dev_info(dev, "IOSF_MBI not enabled - can't determine CPU variant\n");
+ return -EIO;
+ }
+
+ status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */
+ MBI_REG_READ, /* 0x10 */
+ 0x006, /* BIOS_CONFIG */
+ &bios_status);
+
+ if (status) {
+ dev_err(dev, "error: could not read PUNIT BIOS_CONFIG\n");
+ return -EIO;
+ }
+
+ /* bits 26:27 mirror PMIC options */
+ bios_status = (bios_status >> 26) & 3;
+
+ if (bios_status == 1 || bios_status == 3) {
+ dev_info(dev, "BYT-CR detected\n");
+ return 1;
+ }
+
+ dev_info(dev, "BYT-CR not detected\n");
+ return 0;
+}
+
+static struct sof_dev_desc sof_acpi_cherrytrail_desc = {
+ .machines = snd_soc_acpi_intel_cherrytrail_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = 1,
+ .resindex_imr_base = 2,
+ .irqindex_host_ipc = 5,
+ .nocodec_fw_filename = "intel/sof-cht.ri",
+ .nocodec_tplg_filename = "intel/sof-cht-nocodec.tplg"
+};
+
+#endif
+
+static const struct dev_pm_ops sof_acpi_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(snd_sof_suspend, snd_sof_resume)
+ SET_RUNTIME_PM_OPS(snd_sof_runtime_suspend, snd_sof_runtime_resume,
+ NULL)
+ .suspend_late = snd_sof_suspend_late,
+};
+
+static const struct sof_ops_table acpi_mach_ops[] = {
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HASWELL)
+ {&sof_acpi_haswell_desc, &sof_hsw_ops},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BROADWELL)
+ {&sof_acpi_broadwell_desc, &sof_bdw_ops},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
+ {&sof_acpi_baytrail_desc, &sof_byt_ops},
+ {&sof_acpi_baytrailcr_desc, &sof_byt_ops},
+ {&sof_acpi_cherrytrail_desc, &sof_cht_ops},
+#endif
+};
+
+static int sof_acpi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct sof_dev_desc *desc;
+ struct snd_soc_acpi_mach *mach;
+ struct snd_sof_pdata *sof_pdata;
+ struct sof_platform_priv *priv;
+ struct snd_sof_dsp_ops *ops;
+ int ret = 0;
+
+ dev_dbg(&pdev->dev, "ACPI DSP detected");
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ sof_pdata = devm_kzalloc(dev, sizeof(*sof_pdata), GFP_KERNEL);
+ if (!sof_pdata)
+ return -ENOMEM;
+
+ desc = (const struct sof_dev_desc *)device_get_match_data(dev);
+ if (!desc)
+ return -ENODEV;
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
+ if (desc == &sof_acpi_baytrail_desc && is_byt_cr(dev))
+ desc = &sof_acpi_baytrailcr_desc;
+#endif
+
+ /* get ops for platform */
+ ops = sof_get_ops(desc, acpi_mach_ops, ARRAY_SIZE(acpi_mach_ops));
+ if (!ops) {
+ dev_err(dev, "error: no matching ACPI descriptor ops\n");
+ return -ENODEV;
+ }
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_FORCE_NOCODEC_MODE)
+ /* force nocodec mode */
+ dev_warn(dev, "Force to use nocodec mode\n");
+ mach = devm_kzalloc(dev, sizeof(*mach), GFP_KERNEL);
+ if (!mach)
+ return -ENOMEM;
+ ret = sof_nocodec_setup(dev, sof_pdata, mach, desc, ops);
+ if (ret < 0)
+ return ret;
+#else
+ /* find machine */
+ mach = snd_soc_acpi_find_machine(desc->machines);
+ if (!mach) {
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC)
+ /* fallback to nocodec mode */
+ dev_warn(dev, "No matching ASoC machine driver found - using nocodec\n");
+ mach = devm_kzalloc(dev, sizeof(*mach), GFP_KERNEL);
+ ret = sof_nocodec_setup(dev, sof_pdata, mach, desc, ops);
+ if (ret < 0)
+ return ret;
+#else
+ dev_err(dev, "error: no matching ASoC machine driver found - aborting probe\n");
+ return -ENODEV;
+#endif
+ }
+#endif
+
+ mach->pdata = ops;
+ sof_pdata->machine = mach;
+ sof_pdata->desc = desc;
+ priv->sof_pdata = sof_pdata;
+ sof_pdata->dev = &pdev->dev;
+ sof_pdata->type = SOF_DEVICE_APCI;
+ sof_pdata->platform = "sof-audio";
+ dev_set_drvdata(&pdev->dev, priv);
+
+ /* register sof-audio platform driver */
+ ret = sof_create_platform_device(priv);
+ if (ret) {
+ dev_err(dev, "error: failed to create platform device!\n");
+ return ret;
+ }
+
+ /* allow runtime_pm */
+ pm_runtime_set_autosuspend_delay(dev, SND_SOF_SUSPEND_DELAY);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_allow(dev);
+
+ return ret;
+}
+
+static void sof_acpi_shutdown(struct platform_device *pdev)
+{
+ snd_sof_shutdown(&pdev->dev);
+}
+
+static int sof_acpi_remove(struct platform_device *pdev)
+{
+ struct sof_platform_priv *priv = dev_get_drvdata(&pdev->dev);
+ struct snd_sof_pdata *sof_pdata = priv->sof_pdata;
+
+ if (!IS_ERR(priv->pdev_pcm))
+ platform_device_unregister(priv->pdev_pcm);
+ release_firmware(sof_pdata->fw);
+
+ return 0;
+}
+
+static const struct acpi_device_id sof_acpi_match[] = {
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HASWELL)
+ { "INT33C8", (unsigned long)&sof_acpi_haswell_desc },
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BROADWELL)
+ { "INT3438", (unsigned long)&sof_acpi_broadwell_desc },
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
+ { "80860F28", (unsigned long)&sof_acpi_baytrail_desc },
+ { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc },
+#endif
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, sof_acpi_match);
+
+/* acpi_driver definition */
+static struct platform_driver snd_sof_acpi_driver = {
+ .probe = sof_acpi_probe,
+ .remove = sof_acpi_remove,
+ .shutdown = sof_acpi_shutdown,
+ .driver = {
+ .name = "sof-audio-acpi",
+ .pm = &sof_acpi_pm,
+ .acpi_match_table = ACPI_PTR(sof_acpi_match),
+ },
+};
+module_platform_driver(snd_sof_acpi_driver);
+
+MODULE_LICENSE("Dual BSD/GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 18/21] ASoC: SOF: Add PCI device support
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (16 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 17/21] ASoC: SOF: Add ACPI device support Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 19/21] ALSA: HDA: export process_unsol_events() Pierre-Louis Bossart
` (2 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pierre-Louis Bossart,
liam.r.girdwood, vkoul, broonie, Alan Cox, sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Add support for PCI based DSP devices.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/sof/sof-pci-dev.c | 361 ++++++++++++++++++++++++++++++++++++
1 file changed, 361 insertions(+)
create mode 100644 sound/soc/sof/sof-pci-dev.c
diff --git a/sound/soc/sof/sof-pci-dev.c b/sound/soc/sof/sof-pci-dev.c
new file mode 100644
index 000000000000..449ff9cbc793
--- /dev/null
+++ b/sound/soc/sof/sof-pci-dev.c
@@ -0,0 +1,361 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+//
+// This file is provided under a dual BSD/GPLv2 license. When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2018 Intel Corporation. All rights reserved.
+//
+// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+//
+
+#include <linux/firmware.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <sound/soc-acpi.h>
+#include <sound/soc-acpi-intel-match.h>
+#include <sound/sof.h>
+#include "ops.h"
+
+/* platform specific devices */
+#include "intel/shim.h"
+#include "intel/hda.h"
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_APOLLOLAKE)
+static struct sof_dev_desc bxt_desc = {
+ .machines = snd_soc_acpi_intel_bxt_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = -1,
+ .resindex_imr_base = -1,
+ .irqindex_host_ipc = -1,
+ .resindex_dma_base = -1,
+ .nocodec_fw_filename = "intel/sof-apl.ri",
+ .nocodec_tplg_filename = "intel/sof-apl-nocodec.tplg"
+};
+#endif
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_GEMINILAKE)
+static struct sof_dev_desc glk_desc = {
+ .machines = snd_soc_acpi_intel_glk_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = -1,
+ .resindex_imr_base = -1,
+ .irqindex_host_ipc = -1,
+ .resindex_dma_base = -1,
+ .nocodec_fw_filename = "intel/sof-glk.ri",
+ .nocodec_tplg_filename = "intel/sof-glk-nocodec.tplg"
+};
+#endif
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
+static struct snd_soc_acpi_mach sof_byt_machines[] = {
+ {
+ .id = "INT343A",
+ .drv_name = "edison",
+ .sof_fw_filename = "intel/sof-byt.ri",
+ .sof_tplg_filename = "intel/sof-byt.tplg",
+ .asoc_plat_name = "baytrail-pcm-audio",
+ },
+ {}
+};
+
+static const struct sof_dev_desc byt_desc = {
+ .machines = sof_byt_machines,
+ .resindex_lpe_base = 3, /* IRAM, but subtract IRAM offset */
+ .resindex_pcicfg_base = -1,
+ .resindex_imr_base = 0,
+ .irqindex_host_ipc = -1,
+ .resindex_dma_base = -1,
+ .nocodec_fw_filename = "intel/sof-byt.ri",
+ .nocodec_tplg_filename = "intel/sof-byt.tplg"
+};
+#endif
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_CANNONLAKE)
+static const struct sof_dev_desc cnl_desc = {
+ .machines = snd_soc_acpi_intel_cnl_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = -1,
+ .resindex_imr_base = -1,
+ .irqindex_host_ipc = -1,
+ .resindex_dma_base = -1,
+ .nocodec_fw_filename = "intel/sof-cnl.ri",
+ .nocodec_tplg_filename = "intel/sof-cnl.tplg"
+};
+#endif
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_SKYLAKE)
+static struct sof_dev_desc skl_desc = {
+ .machines = snd_soc_acpi_intel_skl_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = -1,
+ .resindex_imr_base = -1,
+ .irqindex_host_ipc = -1,
+ .resindex_dma_base = -1,
+ .nocodec_fw_filename = "intel/sof-skl.ri",
+ .nocodec_tplg_filename = "intel/sof-skl-nocodec.tplg"
+};
+#endif
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_KABYLAKE)
+static struct sof_dev_desc kbl_desc = {
+ .machines = snd_soc_acpi_intel_kbl_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = -1,
+ .resindex_imr_base = -1,
+ .irqindex_host_ipc = -1,
+ .resindex_dma_base = -1,
+ .nocodec_fw_filename = "intel/sof-kbl.ri",
+ .nocodec_tplg_filename = "intel/sof-kbl-nocodec.tplg"
+};
+#endif
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_ICELAKE)
+static const struct sof_dev_desc icl_desc = {
+ .machines = snd_soc_acpi_intel_icl_machines,
+ .resindex_lpe_base = 0,
+ .resindex_pcicfg_base = -1,
+ .resindex_imr_base = -1,
+ .irqindex_host_ipc = -1,
+ .resindex_dma_base = -1,
+ .nocodec_fw_filename = "intel/sof-icl.ri",
+ .nocodec_tplg_filename = "intel/sof-icl-nocodec.tplg"
+};
+#endif
+
+static const struct dev_pm_ops sof_pci_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(snd_sof_suspend, snd_sof_resume)
+ SET_RUNTIME_PM_OPS(snd_sof_runtime_suspend, snd_sof_runtime_resume,
+ NULL)
+ .suspend_late = snd_sof_suspend_late,
+ .prepare = snd_sof_prepare,
+
+};
+
+static const struct sof_ops_table pci_mach_ops[] = {
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_APOLLOLAKE)
+ {&bxt_desc, &sof_apl_ops},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_GEMINILAKE)
+ {&glk_desc, &sof_apl_ops},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
+ {&byt_desc, &sof_byt_ops},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_CANNONLAKE)
+ {&cnl_desc, &sof_cnl_ops},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_SKYLAKE)
+ {&skl_desc, &sof_skl_ops},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_KABYLAKE)
+ {&kbl_desc, &sof_skl_ops},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_ICELAKE)
+ {&icl_desc, &sof_cnl_ops},
+#endif
+};
+
+static int sof_pci_probe(struct pci_dev *pci,
+ const struct pci_device_id *pci_id)
+{
+ struct device *dev = &pci->dev;
+ const struct sof_dev_desc *desc =
+ (const struct sof_dev_desc *)pci_id->driver_data;
+ struct snd_soc_acpi_mach *mach;
+ struct snd_sof_pdata *sof_pdata;
+ struct sof_platform_priv *priv;
+ struct snd_sof_dsp_ops *ops;
+ int ret = 0;
+
+ dev_dbg(&pci->dev, "PCI DSP detected");
+
+ /* get ops for platform */
+ ops = sof_get_ops(desc, pci_mach_ops, ARRAY_SIZE(pci_mach_ops));
+ if (!ops) {
+ dev_err(dev, "error: no matching PCI descriptor ops\n");
+ return -ENODEV;
+ }
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ pci_set_drvdata(pci, priv);
+
+ sof_pdata = devm_kzalloc(dev, sizeof(*sof_pdata), GFP_KERNEL);
+ if (!sof_pdata)
+ return -ENOMEM;
+
+ ret = pcim_enable_device(pci);
+ if (ret < 0)
+ return ret;
+
+ ret = pci_request_regions(pci, "Audio DSP");
+ if (ret < 0)
+ return ret;
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_FORCE_NOCODEC_MODE)
+ /* force nocodec mode */
+ dev_warn(dev, "Force to use nocodec mode\n");
+ mach = devm_kzalloc(dev, sizeof(*mach), GFP_KERNEL);
+ if (!mach) {
+ ret = -ENOMEM;
+ goto release_regions;
+ }
+ ret = sof_nocodec_setup(dev, sof_pdata, mach, desc, ops);
+ if (ret < 0)
+ goto release_regions;
+#else
+ /* find machine */
+ mach = snd_soc_acpi_find_machine(desc->machines);
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
+ if (!mach) {
+ dev_warn(dev, "No matching ASoC machine driver found - falling back to HDA codec\n");
+ mach = snd_soc_acpi_intel_hda_machines;
+ mach->sof_fw_filename = desc->nocodec_fw_filename;
+
+ /*
+ * TODO: we need to find a way to check if codecs are actually
+ * present
+ */
+ }
+#endif /* CONFIG_SND_SOC_SOF_HDA */
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC)
+ if (!mach) {
+ /* fallback to nocodec mode */
+ dev_warn(dev, "No matching ASoC machine driver found - using nocodec\n");
+ mach = devm_kzalloc(dev, sizeof(*mach), GFP_KERNEL);
+ if (!mach) {
+ ret = -ENOMEM;
+ goto release_regions;
+ }
+ ret = sof_nocodec_setup(dev, sof_pdata, mach, desc, ops);
+ if (ret < 0)
+ goto release_regions;
+ }
+#endif /* CONFIG_SND_SOC_SOF_NOCODEC */
+
+#endif /* CONFIG_SND_SOC_SOF_FORCE_NOCODEC_MODE */
+
+ if (!mach) {
+ dev_err(dev, "error: no matching ASoC machine driver found - aborting probe\n");
+ ret = -ENODEV;
+ goto release_regions;
+ }
+
+ mach->pdata = ops;
+
+ sof_pdata->id = pci_id->device;
+ sof_pdata->name = pci_name(pci);
+ sof_pdata->machine = mach;
+ sof_pdata->desc = (struct sof_dev_desc *)pci_id->driver_data;
+ priv->sof_pdata = sof_pdata;
+ sof_pdata->dev = &pci->dev;
+ sof_pdata->type = SOF_DEVICE_PCI;
+ sof_pdata->platform = "sof-audio";
+
+ /* register sof-audio platform driver */
+ ret = sof_create_platform_device(priv);
+ if (ret) {
+ dev_err(dev, "error: failed to create platform device!\n");
+ goto release_regions;
+ }
+
+ /* allow runtime_pm */
+ pm_runtime_set_autosuspend_delay(dev, SND_SOF_SUSPEND_DELAY);
+ pm_runtime_use_autosuspend(dev);
+
+ /*
+ * runtime pm for pci device is "forbidden" by default.
+ * so call pm_runtime_allow() to enable it.
+ */
+ pm_runtime_allow(dev);
+
+ /* follow recommendation in pci-driver.c to decrement usage counter */
+ pm_runtime_put_noidle(dev);
+
+ return ret;
+
+release_regions:
+ pci_release_regions(pci);
+
+ return ret;
+}
+
+static void sof_pci_shutdown(struct pci_dev *pci)
+{
+ snd_sof_shutdown(&pci->dev);
+}
+
+static void sof_pci_remove(struct pci_dev *pci)
+{
+ struct sof_platform_priv *priv = pci_get_drvdata(pci);
+ struct snd_sof_pdata *sof_pdata = priv->sof_pdata;
+
+ /* unregister sof-audio platform driver */
+ if (!IS_ERR(priv->pdev_pcm))
+ platform_device_unregister(priv->pdev_pcm);
+
+ /* release firmware */
+ release_firmware(sof_pdata->fw);
+
+ /* follow recommendation in pci-driver.c to increment usage counter */
+ pm_runtime_get_noresume(&pci->dev);
+
+ /* release pci regions and disable device */
+ pci_release_regions(pci);
+}
+
+/* PCI IDs */
+static const struct pci_device_id sof_pci_ids[] = {
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_APOLLOLAKE)
+ /* BXT-P & Apollolake */
+ { PCI_DEVICE(0x8086, 0x5a98),
+ .driver_data = (unsigned long)&bxt_desc},
+ { PCI_DEVICE(0x8086, 0x1a98),
+ .driver_data = (unsigned long)&bxt_desc},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_GEMINILAKE)
+ { PCI_DEVICE(0x8086, 0x3198),
+ .driver_data = (unsigned long)&glk_desc},
+#endif
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
+ { PCI_DEVICE(0x8086, 0x119a),
+ .driver_data = (unsigned long)&byt_desc},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_CANNONLAKE)
+ { PCI_DEVICE(0x8086, 0x9dc8),
+ .driver_data = (unsigned long)&cnl_desc},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_KABYLAKE)
+ { PCI_DEVICE(0x8086, 0x9d71),
+ .driver_data = (unsigned long)&kbl_desc},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_SKYLAKE)
+ { PCI_DEVICE(0x8086, 0x9d70),
+ .driver_data = (unsigned long)&skl_desc},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_ICELAKE)
+ { PCI_DEVICE(0x8086, 0x34C8),
+ .driver_data = (unsigned long)&icl_desc},
+#endif
+ { 0, }
+};
+MODULE_DEVICE_TABLE(pci, sof_pci_ids);
+
+/* pci_driver definition */
+static struct pci_driver snd_sof_pci_driver = {
+ .name = "sof-audio-pci",
+ .id_table = sof_pci_ids,
+ .probe = sof_pci_probe,
+ .remove = sof_pci_remove,
+ .shutdown = sof_pci_shutdown,
+ .driver = {
+ .pm = &sof_pci_pm,
+ },
+};
+module_pci_driver(snd_sof_pci_driver);
+
+MODULE_LICENSE("Dual BSD/GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 19/21] ALSA: HDA: export process_unsol_events()
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (17 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 18/21] ASoC: SOF: Add PCI " Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 20/21] ASoC: Intel: Kconfig: expose common option between SST and SOF drivers Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 21/21] ASoC: SOF: Add Build support for SOF core and Intel drivers Pierre-Louis Bossart
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Keyon Jie,
Pierre-Louis Bossart, liam.r.girdwood, vkoul, broonie, Alan Cox,
sound-open-firmware
From: Keyon Jie <yang.jie@linux.intel.com>
The SOF implementation does not rely on the hdac_bus library, however
for HDMI and HDaudio codec support it does need to deal with
unsolicited events. Instead of re-inventing the wheel, export this
symbol to reuse this part of the library directly.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
include/sound/hdaudio.h | 1 +
sound/hda/hdac_bus.c | 7 +++----
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h
index cd1773d0e08f..2ee9eccf8d54 100644
--- a/include/sound/hdaudio.h
+++ b/include/sound/hdaudio.h
@@ -389,6 +389,7 @@ void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex);
int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec);
void snd_hdac_bus_remove_device(struct hdac_bus *bus,
struct hdac_device *codec);
+void snd_hdac_bus_process_unsol_events(struct work_struct *work);
static inline void snd_hdac_codec_link_up(struct hdac_device *codec)
{
diff --git a/sound/hda/hdac_bus.c b/sound/hda/hdac_bus.c
index 714a51721a31..012305177f68 100644
--- a/sound/hda/hdac_bus.c
+++ b/sound/hda/hdac_bus.c
@@ -9,8 +9,6 @@
#include <sound/hdaudio.h>
#include "trace.h"
-static void process_unsol_events(struct work_struct *work);
-
static const struct hdac_bus_ops default_ops = {
.command = snd_hdac_bus_send_cmd,
.get_response = snd_hdac_bus_get_response,
@@ -37,7 +35,7 @@ int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
bus->io_ops = io_ops;
INIT_LIST_HEAD(&bus->stream_list);
INIT_LIST_HEAD(&bus->codec_list);
- INIT_WORK(&bus->unsol_work, process_unsol_events);
+ INIT_WORK(&bus->unsol_work, snd_hdac_bus_process_unsol_events);
spin_lock_init(&bus->reg_lock);
mutex_init(&bus->cmd_mutex);
bus->irq = -1;
@@ -148,7 +146,7 @@ EXPORT_SYMBOL_GPL(snd_hdac_bus_queue_event);
/*
* process queued unsolicited events
*/
-static void process_unsol_events(struct work_struct *work)
+void snd_hdac_bus_process_unsol_events(struct work_struct *work)
{
struct hdac_bus *bus = container_of(work, struct hdac_bus, unsol_work);
struct hdac_device *codec;
@@ -171,6 +169,7 @@ static void process_unsol_events(struct work_struct *work)
drv->unsol_event(codec, res);
}
}
+EXPORT_SYMBOL_GPL(snd_hdac_bus_process_unsol_events);
/**
* snd_hdac_bus_add_device - Add a codec to bus
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 20/21] ASoC: Intel: Kconfig: expose common option between SST and SOF drivers
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (18 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 19/21] ALSA: HDA: export process_unsol_events() Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 21/21] ASoC: SOF: Add Build support for SOF core and Intel drivers Pierre-Louis Bossart
20 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pierre-Louis Bossart,
liam.r.girdwood, vkoul, broonie, Alan Cox, sound-open-firmware
Both drivers rely on the same module, expose it for both configurations
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/intel/Kconfig | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/sound/soc/intel/Kconfig b/sound/soc/intel/Kconfig
index 18e717703685..508d77e09196 100644
--- a/sound/soc/intel/Kconfig
+++ b/sound/soc/intel/Kconfig
@@ -137,13 +137,18 @@ config SND_SOC_INTEL_SKYLAKE_COMMON
endif ## SND_SOC_INTEL_SKYLAKE
+endif ## SND_SOC_INTEL_SST_TOPLEVEL
+
+if SND_SOC_INTEL_SST_TOPLEVEL || SND_SOC_SOF_INTEL
+
config SND_SOC_ACPI_INTEL_MATCH
tristate
select SND_SOC_ACPI if ACPI
# this option controls the compilation of ACPI matching tables and
# helpers and is not meant to be selected by the user.
-endif ## SND_SOC_INTEL_SST_TOPLEVEL
+endif ## SND_SOC_INTEL_SST_TOPLEVEL || SND_SOC_SOF_INTEL
+
# ASoC codec drivers
source "sound/soc/intel/boards/Kconfig"
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 21/21] ASoC: SOF: Add Build support for SOF core and Intel drivers
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
` (19 preceding siblings ...)
2018-12-11 21:30 ` [PATCH 20/21] ASoC: Intel: Kconfig: expose common option between SST and SOF drivers Pierre-Louis Bossart
@ 2018-12-11 21:30 ` Pierre-Louis Bossart
2018-12-12 11:50 ` Takashi Iwai
20 siblings, 1 reply; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-11 21:30 UTC (permalink / raw)
To: alsa-devel
Cc: Daniel Baluta, andriy.shevchenko, tiwai, Pierre-Louis Bossart,
liam.r.girdwood, vkoul, broonie, Alan Cox, sound-open-firmware
From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Build SOF core and Intel-specific drivers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
---
sound/soc/Kconfig | 1 +
sound/soc/Makefile | 1 +
sound/soc/sof/Kconfig | 82 +++++++++++++++++++++
sound/soc/sof/Makefile | 17 +++++
sound/soc/sof/intel/Kconfig | 136 +++++++++++++++++++++++++++++++++++
sound/soc/sof/intel/Makefile | 17 +++++
6 files changed, 254 insertions(+)
create mode 100644 sound/soc/sof/Kconfig
create mode 100644 sound/soc/sof/Makefile
create mode 100644 sound/soc/sof/intel/Kconfig
create mode 100644 sound/soc/sof/intel/Makefile
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 1cf11cf51e1d..32eab7d21aaa 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -65,6 +65,7 @@ source "sound/soc/rockchip/Kconfig"
source "sound/soc/samsung/Kconfig"
source "sound/soc/sh/Kconfig"
source "sound/soc/sirf/Kconfig"
+source "sound/soc/sof/Kconfig"
source "sound/soc/spear/Kconfig"
source "sound/soc/sti/Kconfig"
source "sound/soc/stm/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 62a5f87c3cfc..cb336e803d5a 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_SND_SOC) += rockchip/
obj-$(CONFIG_SND_SOC) += samsung/
obj-$(CONFIG_SND_SOC) += sh/
obj-$(CONFIG_SND_SOC) += sirf/
+obj-$(CONFIG_SND_SOC) += sof/
obj-$(CONFIG_SND_SOC) += spear/
obj-$(CONFIG_SND_SOC) += sti/
obj-$(CONFIG_SND_SOC) += stm/
diff --git a/sound/soc/sof/Kconfig b/sound/soc/sof/Kconfig
new file mode 100644
index 000000000000..1742df4e2536
--- /dev/null
+++ b/sound/soc/sof/Kconfig
@@ -0,0 +1,82 @@
+config SND_SOC_SOF_PCI
+ tristate
+
+config SND_SOC_SOF_ACPI
+ tristate
+
+config SND_SOC_SOF
+ tristate "Sound Open Firmware Support"
+ select SND_SOC_TOPOLOGY
+ help
+ This adds support for Sound Open Firmware (SOF). SOF is a free and
+ generic open source audio DSP firmware for multiple devices.
+ Say Y if you have such a device that is supported by SOF.
+ If unsure select "N".
+
+config SND_SOC_SOF_NOCODEC
+ tristate "SOF nocodec mode Support"
+ depends on SND_SOC_SOF
+ help
+ This adds support for a dummy/nocodec machine driver fallback
+ option if no known codec is detected. This is typically only
+ enabled for developers or devices where the sound card is
+ controlled externally
+ Say Y if you need this nocodec fallback option
+ If unsure select "N".
+
+config SND_SOC_SOF_DEBUG
+ bool "SOF debugging features"
+ depends on SND_SOC_SOF
+ help
+ This option can be used to enable or disable individual SOF firmware
+ and driver debugging options.
+ Say Y if you are debugging SOF FW or drivers.
+ If unsure select "N".
+
+config SND_SOC_SOF_FORCE_NOCODEC_MODE
+ bool "SOF force nocodec Mode"
+ depends on SND_SOC_SOF_NOCODEC
+ depends on SND_SOC_SOF_DEBUG
+ help
+ This forces SOF to use dummy/nocodec as machine driver, even
+ though there is a codec detected on the real platform. This is
+ typically only enabled for developers for debug purposes, before
+ codec/machine driver is ready, or to exclude the impact of those
+ drivers
+ Say Y if you need this force nocodec mode option
+ If unsure select "N".
+
+config SND_SOC_SOF_DEBUG_XRUN_STOP
+ bool "SOF stop on XRUN"
+ depends on SND_SOC_SOF_DEBUG
+ help
+ This option forces PCMs to stop on any XRUN event. This is useful to
+ preserve any trace data ond pipeline status prior to the XRUN.
+ Say Y if you are debugging SOF FW pipeline XRUNs.
+ If unsure select "N".
+
+config SND_SOC_SOF_DEBUG_VERBOSE_IPC
+ bool "SOF verbose IPC logs"
+ depends on SND_SOC_SOF_DEBUG
+ help
+ This option enables more verbose IPC logs, with command types in
+ human-readable form instead of just 32-bit hex dumps. This is useful
+ if you are trying to debug IPC with the DSP firmware.
+ If unsure select "N".
+
+config SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION
+ bool "SOF force to use IPC for position update on SKL+"
+ depends on SND_SOC_SOF_DEBUG
+ default n
+ help
+ This option force to handle stream position update IPCs and run pcm
+ elapse to inform ALSA about that, on platforms (e.g. Intel SKL+) that
+ with other approach (e.g. HDAC DPIB/posbuf) to elapse PCM.
+ On platforms (e.g. Intel SKL-) where position update IPC is the only
+ one choice, this setting won't impact anything.
+ if you are trying to debug pointer update with position IPCs or where
+ DPIB/posbuf is not ready, select "Y".
+ If unsure select "N".
+
+source "sound/soc/sof/intel/Kconfig"
+source "sound/soc/sof/xtensa/Kconfig"
diff --git a/sound/soc/sof/Makefile b/sound/soc/sof/Makefile
new file mode 100644
index 000000000000..2831e6257cb8
--- /dev/null
+++ b/sound/soc/sof/Makefile
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+
+snd-sof-objs := core.o ops.o loader.o ipc.o pcm.o pm.o debug.o topology.o\
+ control.o trace.o utils.o
+
+snd-sof-pci-objs := sof-pci-dev.o
+snd-sof-acpi-objs := sof-acpi-dev.o
+snd-sof-nocodec-objs := nocodec.o
+
+obj-$(CONFIG_SND_SOC_SOF) += snd-sof.o
+obj-$(CONFIG_SND_SOC_SOF_NOCODEC) += snd-sof-nocodec.o
+
+obj-$(CONFIG_SND_SOC_SOF_ACPI) += sof-acpi-dev.o
+obj-$(CONFIG_SND_SOC_SOF_PCI) += sof-pci-dev.o
+
+obj-$(CONFIG_SND_SOC_SOF_INTEL) += intel/
+obj-$(CONFIG_SND_SOC_SOF_XTENSA) += xtensa/
diff --git a/sound/soc/sof/intel/Kconfig b/sound/soc/sof/intel/Kconfig
new file mode 100644
index 000000000000..23b7c5915aac
--- /dev/null
+++ b/sound/soc/sof/intel/Kconfig
@@ -0,0 +1,136 @@
+config SND_SOC_SOF_INTEL
+ tristate "SOF support for Intel audio DSPs"
+ depends on SND_SOC_SOF
+ depends on SND_DMA_SGBUF
+ select SND_SOC_INTEL_MACH
+ select SND_SOC_SOF_XTENSA
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+if SND_SOC_SOF_INTEL
+
+config SND_SOC_SOF_BAYTRAIL
+ tristate "SOF support for Baytrail, Braswell and Cherrytrail"
+ select SND_SOC_SOF_ACPI
+ select SND_SOC_ACPI_INTEL_MATCH
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms
+ using the Baytrail, Braswell or Cherrytrail processors.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+config SND_SOC_SOF_HASWELL
+ tristate "SOF support for Haswell"
+ select SND_SOC_SOF_ACPI
+ select SND_SOC_ACPI_INTEL_MATCH
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms
+ using the Haswell processors.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+config SND_SOC_SOF_BROADWELL
+ tristate "SOF support for Broadwell"
+ depends on SND_SOC_SOF_INTEL
+ select SND_SOC_SOF_ACPI
+ select SND_SOC_ACPI_INTEL_MATCH
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms
+ using the Broadwell processors.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+config SND_SOC_SOF_APOLLOLAKE
+ tristate "SOF support for Apollolake"
+ select SND_SOC_SOF_HDA_COMMON
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms
+ using the Apollolake processors.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+config SND_SOC_SOF_GEMINILAKE
+ tristate "SOF support for GeminiLake"
+ select SND_SOC_SOF_HDA_COMMON
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms
+ using the Geminilake processors.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+config SND_SOC_SOF_CANNONLAKE
+ tristate "SOF support for Cannonlake"
+ select SND_SOC_SOF_HDA_COMMON
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms
+ using the Cannonlake processors.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+config SND_SOC_SOF_KABYLAKE
+ tristate "SOF support for Kabylake"
+ select SND_SOC_SOF_HDA_COMMON
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms
+ using the Kabylake processors.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+config SND_SOC_SOF_SKYLAKE
+ tristate "SOF support for Skylake"
+ select SND_SOC_SOF_HDA_COMMON
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms
+ using the Skylake processors.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+config SND_SOC_SOF_ICELAKE
+ tristate "SOF support for Icelake"
+ select SND_SOC_SOF_HDA_COMMON
+ help
+ This adds support for Sound Open Firmware for Intel(R) platforms
+ using the Icelake processors.
+ Say Y if you have such a device.
+ If unsure select "N".
+
+config SND_SOC_SOF_HDA_COMMON
+ tristate
+ select SND_SOC_SOF_PCI
+ select SND_SOC_ACPI_INTEL_MATCH
+ select SND_SOC_SOF_HDA_LINK_BASELINE
+
+if SND_SOC_SOF_HDA_COMMON
+
+config SND_SOC_SOF_HDA_LINK
+ bool "SOF support for HDA Links(HDA/HDMI)"
+ help
+ This adds support for HDA links(HDA/HDMI) with Sound Open Firmware
+ for Intel(R) platforms.
+ Say Y if you want to enble HDA links with SOF.
+ If unsure select "N".
+
+if SND_SOC_SOF_HDA_LINK
+config SND_SOC_SOF_HDA_AUDIO_CODEC
+ bool "SOF support for HDAudio codecs"
+ help
+ This adds support for HDAudio codecs with Sound Open Firmware
+ for Intel(R) platforms.
+ Say Y if you want to enble HDAudio codecs with SOF.
+ If unsure select "N".
+endif ## SND_SOC_SOF_HDA_LINK
+
+endif ## SND_SOC_SOF_HDA_COMMON
+
+config SND_SOC_SOF_HDA_LINK_BASELINE
+ tristate
+ select SND_SOC_SOF_HDA if SND_SOC_SOF_HDA_LINK
+
+config SND_SOC_SOF_HDA
+ tristate
+ select SND_HDA_EXT_CORE if SND_SOC_SOF_HDA_LINK
+ select SND_SOC_HDAC_HDA if SND_SOC_SOF_HDA_AUDIO_CODEC
+
+endif ## SND_SOC_SOF_INTEL
diff --git a/sound/soc/sof/intel/Makefile b/sound/soc/sof/intel/Makefile
new file mode 100644
index 000000000000..78f5fb3d3571
--- /dev/null
+++ b/sound/soc/sof/intel/Makefile
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+
+snd-sof-intel-byt-objs := byt.o
+snd-sof-intel-hsw-objs := hsw.o
+snd-sof-intel-bdw-objs := bdw.o
+snd-sof-intel-hda-common-objs := hda.o hda-loader.o hda-stream.o hda-trace.o \
+ hda-dsp.o hda-ipc.o hda-ctrl.o hda-pcm.o \
+ hda-dai.o hda-bus.o hda-loader-skl.o \
+ skl.o apl.o cnl.o
+
+snd-sof-intel-hda-objs := hda-codec.o
+
+obj-$(CONFIG_SND_SOC_SOF_BAYTRAIL) += snd-sof-intel-byt.o
+obj-$(CONFIG_SND_SOC_SOF_HASWELL) += snd-sof-intel-hsw.o
+obj-$(CONFIG_SND_SOC_SOF_BROADWELL) += snd-sof-intel-bdw.o
+obj-$(CONFIG_SND_SOC_SOF_HDA_COMMON) += snd-sof-intel-hda-common.o
+obj-$(CONFIG_SND_SOC_SOF_HDA) += snd-sof-intel-hda.o
--
2.17.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 21/21] ASoC: SOF: Add Build support for SOF core and Intel drivers
2018-12-11 21:30 ` [PATCH 21/21] ASoC: SOF: Add Build support for SOF core and Intel drivers Pierre-Louis Bossart
@ 2018-12-12 11:50 ` Takashi Iwai
2018-12-12 14:51 ` Pierre-Louis Bossart
0 siblings, 1 reply; 37+ messages in thread
From: Takashi Iwai @ 2018-12-12 11:50 UTC (permalink / raw)
To: Pierre-Louis Bossart
Cc: alsa-devel, andriy.shevchenko, Daniel Baluta, liam.r.girdwood,
vkoul, broonie, Alan Cox, sound-open-firmware
On Tue, 11 Dec 2018 22:30:29 +0100,
Pierre-Louis Bossart wrote:
>
> --- /dev/null
> +++ b/sound/soc/sof/Kconfig
> @@ -0,0 +1,82 @@
> +config SND_SOC_SOF_PCI
> + tristate
> +
> +config SND_SOC_SOF_ACPI
> + tristate
> +
> +config SND_SOC_SOF
> + tristate "Sound Open Firmware Support"
> + select SND_SOC_TOPOLOGY
> + help
> + This adds support for Sound Open Firmware (SOF). SOF is a free and
> + generic open source audio DSP firmware for multiple devices.
> + Say Y if you have such a device that is supported by SOF.
> + If unsure select "N".
You can put
if SND_SOC_SOF
at this point. This will reduce lots of "depends on SND_SOC_SOF"
lines.
> +config SND_SOC_SOF_NOCODEC
> + tristate "SOF nocodec mode Support"
> + depends on SND_SOC_SOF
....
> +source "sound/soc/sof/intel/Kconfig"
> +source "sound/soc/sof/xtensa/Kconfig"
... the endif for SND_SOC_SOF can be put here, then both Kconfigs are
covered by SND_SOC_SOF condition.
OTOH, the usage of if-block below is an overkill.
> --- /dev/null
> +++ b/sound/soc/sof/intel/Kconfig
....
> +if SND_SOC_SOF_HDA_COMMON
> +
> +config SND_SOC_SOF_HDA_LINK
> + bool "SOF support for HDA Links(HDA/HDMI)"
> + help
> + This adds support for HDA links(HDA/HDMI) with Sound Open Firmware
> + for Intel(R) platforms.
> + Say Y if you want to enble HDA links with SOF.
> + If unsure select "N".
> +
> +if SND_SOC_SOF_HDA_LINK
> +config SND_SOC_SOF_HDA_AUDIO_CODEC
> + bool "SOF support for HDAudio codecs"
> + help
> + This adds support for HDAudio codecs with Sound Open Firmware
> + for Intel(R) platforms.
> + Say Y if you want to enble HDAudio codecs with SOF.
> + If unsure select "N".
> +endif ## SND_SOC_SOF_HDA_LINK
> +
> +endif ## SND_SOC_SOF_HDA_COMMON
For single items, just use depends on. It's easier to read.
thanks,
Takashi
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 21/21] ASoC: SOF: Add Build support for SOF core and Intel drivers
2018-12-12 11:50 ` Takashi Iwai
@ 2018-12-12 14:51 ` Pierre-Louis Bossart
0 siblings, 0 replies; 37+ messages in thread
From: Pierre-Louis Bossart @ 2018-12-12 14:51 UTC (permalink / raw)
To: Takashi Iwai
Cc: alsa-devel, andriy.shevchenko, Daniel Baluta, liam.r.girdwood,
vkoul, broonie, Alan Cox, sound-open-firmware
On 12/12/18 5:50 AM, Takashi Iwai wrote:
> On Tue, 11 Dec 2018 22:30:29 +0100,
> Pierre-Louis Bossart wrote:
>> --- /dev/null
>> +++ b/sound/soc/sof/Kconfig
>> @@ -0,0 +1,82 @@
>> +config SND_SOC_SOF_PCI
>> + tristate
>> +
>> +config SND_SOC_SOF_ACPI
>> + tristate
>> +
>> +config SND_SOC_SOF
>> + tristate "Sound Open Firmware Support"
>> + select SND_SOC_TOPOLOGY
>> + help
>> + This adds support for Sound Open Firmware (SOF). SOF is a free and
>> + generic open source audio DSP firmware for multiple devices.
>> + Say Y if you have such a device that is supported by SOF.
>> + If unsure select "N".
> You can put
> if SND_SOC_SOF
> at this point. This will reduce lots of "depends on SND_SOC_SOF"
> lines.
Yes. I tend to use 'ifs' and others 'depends on', will align.
>
>> +config SND_SOC_SOF_NOCODEC
>> + tristate "SOF nocodec mode Support"
>> + depends on SND_SOC_SOF
> ....
>> +source "sound/soc/sof/intel/Kconfig"
>> +source "sound/soc/sof/xtensa/Kconfig"
> ... the endif for SND_SOC_SOF can be put here, then both Kconfigs are
> covered by SND_SOC_SOF condition.
>
>
> OTOH, the usage of if-block below is an overkill.
>
>> --- /dev/null
>> +++ b/sound/soc/sof/intel/Kconfig
> ....
>> +if SND_SOC_SOF_HDA_COMMON
>> +
>> +config SND_SOC_SOF_HDA_LINK
>> + bool "SOF support for HDA Links(HDA/HDMI)"
>> + help
>> + This adds support for HDA links(HDA/HDMI) with Sound Open Firmware
>> + for Intel(R) platforms.
>> + Say Y if you want to enble HDA links with SOF.
>> + If unsure select "N".
>> +
>> +if SND_SOC_SOF_HDA_LINK
>> +config SND_SOC_SOF_HDA_AUDIO_CODEC
>> + bool "SOF support for HDAudio codecs"
>> + help
>> + This adds support for HDAudio codecs with Sound Open Firmware
>> + for Intel(R) platforms.
>> + Say Y if you want to enble HDAudio codecs with SOF.
>> + If unsure select "N".
>> +endif ## SND_SOC_SOF_HDA_LINK
>> +
>> +endif ## SND_SOC_SOF_HDA_COMMON
> For single items, just use depends on. It's easier to read.
Agree, we could remove the nested one. I tend to use 'ifs' when there
are two or more configs, here it's not really needed.
^ permalink raw reply [flat|nested] 37+ messages in thread