All of lore.kernel.org
 help / color / mirror / Atom feed
From: Akhil P Oommen <quic_akhilpo@quicinc.com>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
	<linux-arm-msm@vger.kernel.org>, <andersson@kernel.org>,
	<agross@kernel.org>, <krzysztof.kozlowski@linaro.org>
Cc: <marijn.suijten@somainline.org>, Rob Clark <robdclark@gmail.com>,
	"Abhinav Kumar" <quic_abhinavk@quicinc.com>,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
	Daniel Vetter <daniel@ffwll.ch>, Chia-I Wu <olvaffe@gmail.com>,
	Douglas Anderson <dianders@chromium.org>,
	<dri-devel@lists.freedesktop.org>,
	<freedreno@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/7] drm/msm/a6xx: Add support for A640 speed binning
Date: Tue, 13 Dec 2022 12:36:59 +0530	[thread overview]
Message-ID: <3c017429-15c6-11d0-9aef-c718a39d87aa@quicinc.com> (raw)
In-Reply-To: <20221213002423.259039-4-konrad.dybcio@linaro.org>

On 12/13/2022 5:54 AM, Konrad Dybcio wrote:
> Add support for matching QFPROM fuse values to get the correct speed bin
> on A640 (SM8150) GPUs.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 36c8fb699b56..2c1630f0c04c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1877,6 +1877,16 @@ static u32 a619_get_speed_bin(u32 fuse)
>  	return UINT_MAX;
>  }
>  
> +static u32 a640_get_speed_bin(u32 fuse)
> +{
> +	if (fuse == 0)
> +		return 0;
> +	else if (fuse == 1)
> +		return 1;
> +
> +	return UINT_MAX;
> +}
> +
>  static u32 adreno_7c3_get_speed_bin(u32 fuse)
>  {
>  	if (fuse == 0)
> @@ -1902,6 +1912,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
>  	if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
>  		val = adreno_7c3_get_speed_bin(fuse);
>  
> +	if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
> +		val = a640_get_speed_bin(fuse);
> +
>  	if (val == UINT_MAX) {
>  		DRM_DEV_ERROR(dev,
>  			"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",

Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>


-Akhil.

WARNING: multiple messages have this Message-ID (diff)
From: Akhil P Oommen <quic_akhilpo@quicinc.com>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
	<linux-arm-msm@vger.kernel.org>,  <andersson@kernel.org>,
	<agross@kernel.org>, <krzysztof.kozlowski@linaro.org>
Cc: freedreno@lists.freedesktop.org,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	dri-devel@lists.freedesktop.org,
	Douglas Anderson <dianders@chromium.org>,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	marijn.suijten@somainline.org, Sean Paul <sean@poorly.run>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/7] drm/msm/a6xx: Add support for A640 speed binning
Date: Tue, 13 Dec 2022 12:36:59 +0530	[thread overview]
Message-ID: <3c017429-15c6-11d0-9aef-c718a39d87aa@quicinc.com> (raw)
In-Reply-To: <20221213002423.259039-4-konrad.dybcio@linaro.org>

On 12/13/2022 5:54 AM, Konrad Dybcio wrote:
> Add support for matching QFPROM fuse values to get the correct speed bin
> on A640 (SM8150) GPUs.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 36c8fb699b56..2c1630f0c04c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1877,6 +1877,16 @@ static u32 a619_get_speed_bin(u32 fuse)
>  	return UINT_MAX;
>  }
>  
> +static u32 a640_get_speed_bin(u32 fuse)
> +{
> +	if (fuse == 0)
> +		return 0;
> +	else if (fuse == 1)
> +		return 1;
> +
> +	return UINT_MAX;
> +}
> +
>  static u32 adreno_7c3_get_speed_bin(u32 fuse)
>  {
>  	if (fuse == 0)
> @@ -1902,6 +1912,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
>  	if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
>  		val = adreno_7c3_get_speed_bin(fuse);
>  
> +	if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
> +		val = a640_get_speed_bin(fuse);
> +
>  	if (val == UINT_MAX) {
>  		DRM_DEV_ERROR(dev,
>  			"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",

Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>


-Akhil.

  reply	other threads:[~2022-12-13  7:07 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-13  0:24 [PATCH 0/7] SM8[12]50 GPU speedbin Konrad Dybcio
2022-12-13  0:24 ` [PATCH 1/7] dt-bindings: nvmem: Add compatible for SM8150 Konrad Dybcio
2022-12-13 13:16   ` Krzysztof Kozlowski
2023-01-03 11:58   ` Srinivas Kandagatla
2022-12-13  0:24 ` [PATCH 2/7] dt-bindings: nvmem: Add compatible for SM8250 Konrad Dybcio
2022-12-13 13:16   ` Krzysztof Kozlowski
2023-01-03 11:58   ` Srinivas Kandagatla
2022-12-13  0:24 ` [PATCH 3/7] drm/msm/a6xx: Add support for A640 speed binning Konrad Dybcio
2022-12-13  0:24   ` Konrad Dybcio
2022-12-13  7:06   ` Akhil P Oommen [this message]
2022-12-13  7:06     ` Akhil P Oommen
2022-12-13  0:24 ` [PATCH 4/7] drm/msm/a6xx: Add support for A650 " Konrad Dybcio
2022-12-13  0:24   ` Konrad Dybcio
2022-12-13 15:23   ` Doug Anderson
2022-12-13 15:23     ` Doug Anderson
2022-12-13 15:34     ` Konrad Dybcio
2022-12-13 15:34       ` Konrad Dybcio
2022-12-13  0:24 ` [PATCH 5/7] arm64: dts: qcom: sm8150: Don't start Adreno in headless mode Konrad Dybcio
2022-12-15 21:24   ` Marijn Suijten
2022-12-13  0:24 ` [PATCH 6/7] arm64: dts: qcom: sm8150: Add GPU speedbin support Konrad Dybcio
2022-12-15 21:25   ` Marijn Suijten
2022-12-15 22:37   ` Marijn Suijten
2022-12-13  0:24 ` [PATCH 7/7] arm64: dts: qcom: sm8250: " Konrad Dybcio
2022-12-15 22:36   ` Marijn Suijten

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=3c017429-15c6-11d0-9aef-c718a39d87aa@quicinc.com \
    --to=quic_akhilpo@quicinc.com \
    --cc=agross@kernel.org \
    --cc=airlied@gmail.com \
    --cc=andersson@kernel.org \
    --cc=daniel@ffwll.ch \
    --cc=dianders@chromium.org \
    --cc=dmitry.baryshkov@linaro.org \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=freedreno@lists.freedesktop.org \
    --cc=konrad.dybcio@linaro.org \
    --cc=krzysztof.kozlowski@linaro.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=marijn.suijten@somainline.org \
    --cc=olvaffe@gmail.com \
    --cc=quic_abhinavk@quicinc.com \
    --cc=robdclark@gmail.com \
    --cc=sean@poorly.run \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.