* Re: [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU
2017-02-22 5:12 [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU Aneesh Kumar K.V
@ 2017-02-22 6:16 ` Balbir Singh
2017-02-22 6:23 ` Aneesh Kumar K.V
2017-02-22 6:24 ` Balbir Singh
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Balbir Singh @ 2017-02-22 6:16 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
On Wed, Feb 22, 2017 at 10:42:02AM +0530, Aneesh Kumar K.V wrote:
> We will set LPCR with correct value for radix during int. This make sure we
> start with a sanitized value of LPCR. In case of kexec, cpus can have LPCR
> value based on the previous translation mode we were running.
>
> Fixes: fe036a0605d60 ("powerpc/64/kexec: Fix MMU cleanup on radix")
> Cc: stable@vger.kernel.org # v4.9+
> Acked-by: Michael Neuling <mikey@neuling.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/kernel/cpu_setup_power.S | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
> index 917188615bf5..7fe8c79e6937 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -101,6 +101,8 @@ _GLOBAL(__setup_cpu_power9)
> mfspr r3,SPRN_LPCR
> LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
> or r3, r3, r4
> + LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
> + andc r3, r3, r4
> bl __init_LPCR
> bl __init_HFSCR
> bl __init_tlb_power9
> @@ -122,6 +124,8 @@ _GLOBAL(__restore_cpu_power9)
> mfspr r3,SPRN_LPCR
> LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
> or r3, r3, r4
> + LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
> + andc r3, r3, r4
> bl __init_LPCR
> bl __init_HFSCR
> bl __init_tlb_power9
What about LPCR_GTSE and other bits?
Balbir Singh.
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU
2017-02-22 6:16 ` Balbir Singh
@ 2017-02-22 6:23 ` Aneesh Kumar K.V
0 siblings, 0 replies; 7+ messages in thread
From: Aneesh Kumar K.V @ 2017-02-22 6:23 UTC (permalink / raw)
To: Balbir Singh; +Cc: benh, paulus, mpe, linuxppc-dev
On Wednesday 22 February 2017 11:46 AM, Balbir Singh wrote:
> On Wed, Feb 22, 2017 at 10:42:02AM +0530, Aneesh Kumar K.V wrote:
>> We will set LPCR with correct value for radix during int. This make sure we
>> start with a sanitized value of LPCR. In case of kexec, cpus can have LPCR
>> value based on the previous translation mode we were running.
>>
>> Fixes: fe036a0605d60 ("powerpc/64/kexec: Fix MMU cleanup on radix")
>> Cc: stable@vger.kernel.org # v4.9+
>> Acked-by: Michael Neuling <mikey@neuling.org>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> arch/powerpc/kernel/cpu_setup_power.S | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
>> index 917188615bf5..7fe8c79e6937 100644
>> --- a/arch/powerpc/kernel/cpu_setup_power.S
>> +++ b/arch/powerpc/kernel/cpu_setup_power.S
>> @@ -101,6 +101,8 @@ _GLOBAL(__setup_cpu_power9)
>> mfspr r3,SPRN_LPCR
>> LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
>> or r3, r3, r4
>> + LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
>> + andc r3, r3, r4
>> bl __init_LPCR
>> bl __init_HFSCR
>> bl __init_tlb_power9
>> @@ -122,6 +124,8 @@ _GLOBAL(__restore_cpu_power9)
>> mfspr r3,SPRN_LPCR
>> LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
>> or r3, r3, r4
>> + LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
>> + andc r3, r3, r4
>> bl __init_LPCR
>> bl __init_HFSCR
>> bl __init_tlb_power9
> What about LPCR_GTSE and other bits?
>
>
That is set by the hypervisor for guest. We don't set that and expect to
inherit that from
a previous run for baremetal. Also setting that in the context of LPID 0
shouldn't have
any impact.
-aneesh
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU
2017-02-22 5:12 [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU Aneesh Kumar K.V
2017-02-22 6:16 ` Balbir Singh
@ 2017-02-22 6:24 ` Balbir Singh
2017-02-22 6:40 ` Aneesh Kumar K.V
2017-02-22 21:28 ` Michael Ellerman
2017-02-27 10:11 ` Michael Ellerman
3 siblings, 1 reply; 7+ messages in thread
From: Balbir Singh @ 2017-02-22 6:24 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
On Wed, Feb 22, 2017 at 10:42:02AM +0530, Aneesh Kumar K.V wrote:
> We will set LPCR with correct value for radix during int. This make sure we
> start with a sanitized value of LPCR. In case of kexec, cpus can have LPCR
> value based on the previous translation mode we were running.
>
> Fixes: fe036a0605d60 ("powerpc/64/kexec: Fix MMU cleanup on radix")
> Cc: stable@vger.kernel.org # v4.9+
> Acked-by: Michael Neuling <mikey@neuling.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/kernel/cpu_setup_power.S | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
> index 917188615bf5..7fe8c79e6937 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -101,6 +101,8 @@ _GLOBAL(__setup_cpu_power9)
> mfspr r3,SPRN_LPCR
> LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
> or r3, r3, r4
> + LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
> + andc r3, r3, r4
> bl __init_LPCR
> bl __init_HFSCR
> bl __init_tlb_power9
> @@ -122,6 +124,8 @@ _GLOBAL(__restore_cpu_power9)
> mfspr r3,SPRN_LPCR
> LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
> or r3, r3, r4
> + LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
> + andc r3, r3, r4
> bl __init_LPCR
> bl __init_HFSCR
> bl __init_tlb_power9
My previous comment mentions GTSE, but really we should be clearing
LPCR to 0 and setting it to sane values in __init_LPCR
Balbir
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU
2017-02-22 6:24 ` Balbir Singh
@ 2017-02-22 6:40 ` Aneesh Kumar K.V
0 siblings, 0 replies; 7+ messages in thread
From: Aneesh Kumar K.V @ 2017-02-22 6:40 UTC (permalink / raw)
To: Balbir Singh; +Cc: benh, paulus, mpe, linuxppc-dev
On Wednesday 22 February 2017 11:54 AM, Balbir Singh wrote:
> On Wed, Feb 22, 2017 at 10:42:02AM +0530, Aneesh Kumar K.V wrote:
>> We will set LPCR with correct value for radix during int. This make sure we
>> start with a sanitized value of LPCR. In case of kexec, cpus can have LPCR
>> value based on the previous translation mode we were running.
>>
>> Fixes: fe036a0605d60 ("powerpc/64/kexec: Fix MMU cleanup on radix")
>> Cc: stable@vger.kernel.org # v4.9+
>> Acked-by: Michael Neuling <mikey@neuling.org>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> arch/powerpc/kernel/cpu_setup_power.S | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
>> index 917188615bf5..7fe8c79e6937 100644
>> --- a/arch/powerpc/kernel/cpu_setup_power.S
>> +++ b/arch/powerpc/kernel/cpu_setup_power.S
>> @@ -101,6 +101,8 @@ _GLOBAL(__setup_cpu_power9)
>> mfspr r3,SPRN_LPCR
>> LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
>> or r3, r3, r4
>> + LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
>> + andc r3, r3, r4
>> bl __init_LPCR
>> bl __init_HFSCR
>> bl __init_tlb_power9
>> @@ -122,6 +124,8 @@ _GLOBAL(__restore_cpu_power9)
>> mfspr r3,SPRN_LPCR
>> LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
>> or r3, r3, r4
>> + LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
>> + andc r3, r3, r4
>> bl __init_LPCR
>> bl __init_HFSCR
>> bl __init_tlb_power9
> My previous comment mentions GTSE, but really we should be clearing
> LPCR to 0 and setting it to sane values in __init_LPCR
>
>
IIUC we do want to inherit values from firmware/skiboot. Hence the
explicit usage of mfspr/or. What we want to clear here are values we
updated/changed
based on translation mode.
-aneesh
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU
2017-02-22 5:12 [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU Aneesh Kumar K.V
2017-02-22 6:16 ` Balbir Singh
2017-02-22 6:24 ` Balbir Singh
@ 2017-02-22 21:28 ` Michael Ellerman
2017-02-27 10:11 ` Michael Ellerman
3 siblings, 0 replies; 7+ messages in thread
From: Michael Ellerman @ 2017-02-22 21:28 UTC (permalink / raw)
To: Aneesh Kumar K.V, benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
> We will set LPCR with correct value for radix during int. This make sure we
> start with a sanitized value of LPCR. In case of kexec, cpus can have LPCR
> value based on the previous translation mode we were running.
>
> Fixes: fe036a0605d60 ("powerpc/64/kexec: Fix MMU cleanup on radix")
> Cc: stable@vger.kernel.org # v4.9+
> Acked-by: Michael Neuling <mikey@neuling.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
I can merge this, but the proper fix is to set a sensible value on the
kexec down path.
That way you can kexec into an older kernel, which doesn't have this
fix. For this specific case maybe that's not really an issue, because
this is Power9 only and there aren't any old kernels that are expected
to work.
cheers
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU
2017-02-22 5:12 [PATCH] powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU Aneesh Kumar K.V
` (2 preceding siblings ...)
2017-02-22 21:28 ` Michael Ellerman
@ 2017-02-27 10:11 ` Michael Ellerman
3 siblings, 0 replies; 7+ messages in thread
From: Michael Ellerman @ 2017-02-27 10:11 UTC (permalink / raw)
To: Aneesh Kumar K.V, benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
On Wed, 2017-02-22 at 05:12:02 UTC, "Aneesh Kumar K.V" wrote:
> We will set LPCR with correct value for radix during int. This make sure we
> start with a sanitized value of LPCR. In case of kexec, cpus can have LPCR
> value based on the previous translation mode we were running.
>
> Fixes: fe036a0605d60 ("powerpc/64/kexec: Fix MMU cleanup on radix")
> Cc: stable@vger.kernel.org # v4.9+
> Acked-by: Michael Neuling <mikey@neuling.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/fda2d27db6eae5c2468f9e4657539b
cheers
^ permalink raw reply [flat|nested] 7+ messages in thread