From: Atish Patra <atish.patra@wdc.com>
To: Christoph Hellwig <hch@lst.de>
Cc: "tglx@linutronix.de" <tglx@linutronix.de>,
"palmer@sifive.com" <palmer@sifive.com>,
"jason@lakedaemon.net" <jason@lakedaemon.net>,
"marc.zyngier@arm.com" <marc.zyngier@arm.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"anup@brainfault.org" <anup@brainfault.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"shorne@gmail.com" <shorne@gmail.com>
Subject: Re: [PATCH 7/9] irqchip: add a RISC-V PLIC driver
Date: Wed, 1 Aug 2018 18:02:52 -0700 [thread overview]
Message-ID: <41a996bf-b591-db0c-718e-524743f348fd@wdc.com> (raw)
In-Reply-To: <20180801141858.GA28203@lst.de>
On 8/1/18 7:14 AM, Christoph Hellwig wrote:
> I've pushed out an update to the riscv-irq-simple.2 branch to better
> handle with sparse contexid maps, please retry with that.
>
I see you have changed the driver file name from irq-riscv-plic to
irq-riscv-sifive along with default Y for SIFIVE_PLIC. I guess it was
done because PLIC register spec is SIFIVE specific rather than RISC-V.
But can we keep the new kconfig option "SIFIVE_PLIC" enabled in
driver/irqchip/Kconfig or arch/riscv/Kconfig for now to avoid breakage
without linux_defconfig update.
With the config enabled, Qemu virt machine booting has no issues with
riscv-irq-simple.2 branch. I am still looking at the crash from the
hardware.
Regards,
Atish
WARNING: multiple messages have this Message-ID (diff)
From: atish.patra@wdc.com (Atish Patra)
To: linux-riscv@lists.infradead.org
Subject: [PATCH 7/9] irqchip: add a RISC-V PLIC driver
Date: Wed, 1 Aug 2018 18:02:52 -0700 [thread overview]
Message-ID: <41a996bf-b591-db0c-718e-524743f348fd@wdc.com> (raw)
In-Reply-To: <20180801141858.GA28203@lst.de>
On 8/1/18 7:14 AM, Christoph Hellwig wrote:
> I've pushed out an update to the riscv-irq-simple.2 branch to better
> handle with sparse contexid maps, please retry with that.
>
I see you have changed the driver file name from irq-riscv-plic to
irq-riscv-sifive along with default Y for SIFIVE_PLIC. I guess it was
done because PLIC register spec is SIFIVE specific rather than RISC-V.
But can we keep the new kconfig option "SIFIVE_PLIC" enabled in
driver/irqchip/Kconfig or arch/riscv/Kconfig for now to avoid breakage
without linux_defconfig update.
With the config enabled, Qemu virt machine booting has no issues with
riscv-irq-simple.2 branch. I am still looking at the crash from the
hardware.
Regards,
Atish
next prev parent reply other threads:[~2018-08-02 1:02 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-26 14:37 RFC: simplified RISC-V interrupt and clocksource handling Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 1/9] RISC-V: remove timer leftovers Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 2/9] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 3/9] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 4/9] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 5/9] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-08-02 9:48 ` Thomas Gleixner
2018-08-02 9:48 ` Thomas Gleixner
2018-08-02 9:59 ` Christoph Hellwig
2018-08-02 9:59 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 6/9] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 7/9] irqchip: add a RISC-V PLIC driver Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-28 0:04 ` Atish Patra
2018-07-28 0:04 ` Atish Patra
2018-07-30 15:51 ` Anup Patel
2018-07-30 15:51 ` Anup Patel
2018-07-31 3:21 ` Atish Patra
2018-07-31 3:21 ` Atish Patra
2018-07-31 3:21 ` Atish Patra
2018-07-31 16:57 ` Christoph Hellwig
2018-07-31 16:57 ` Christoph Hellwig
2018-08-01 0:38 ` Atish Patra
2018-08-01 0:38 ` Atish Patra
2018-08-01 0:38 ` Atish Patra
2018-08-01 7:14 ` Christoph Hellwig
2018-08-01 7:14 ` Christoph Hellwig
2018-08-01 12:16 ` Christoph Hellwig
2018-08-01 12:16 ` Christoph Hellwig
2018-08-02 1:09 ` Atish Patra
2018-08-02 1:09 ` Atish Patra
2018-08-02 9:53 ` Christoph Hellwig
2018-08-02 9:53 ` Christoph Hellwig
2018-08-01 14:18 ` Christoph Hellwig
2018-08-01 14:18 ` Christoph Hellwig
2018-08-02 1:02 ` Atish Patra [this message]
2018-08-02 1:02 ` Atish Patra
2018-08-02 9:50 ` Christoph Hellwig
2018-08-02 9:50 ` Christoph Hellwig
2018-07-31 16:37 ` Christoph Hellwig
2018-07-31 16:37 ` Christoph Hellwig
2018-08-02 10:04 ` Thomas Gleixner
2018-08-02 10:04 ` Thomas Gleixner
2018-08-02 11:51 ` Christoph Hellwig
2018-08-02 11:51 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 8/9] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-08-02 7:24 ` Nikolay Borisov
2018-08-02 7:24 ` Nikolay Borisov
2018-08-02 9:52 ` Christoph Hellwig
2018-08-02 9:52 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 9/9] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 18:51 ` Atish Patra
2018-07-26 18:51 ` Atish Patra
2018-07-27 14:41 ` Christoph Hellwig
2018-07-27 14:41 ` Christoph Hellwig
2018-07-27 17:44 ` Atish Patra
2018-07-27 17:44 ` Atish Patra
2018-07-28 21:12 ` kbuild test robot
2018-07-28 21:12 ` kbuild test robot
2018-07-28 21:16 ` kbuild test robot
2018-07-28 21:16 ` kbuild test robot
2018-07-26 23:38 ` RFC: simplified RISC-V interrupt and clocksource handling Atish Patra
2018-07-26 23:38 ` Atish Patra
2018-07-27 14:44 ` Christoph Hellwig
2018-07-27 14:44 ` Christoph Hellwig
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=41a996bf-b591-db0c-718e-524743f348fd@wdc.com \
--to=atish.patra@wdc.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=devicetree@vger.kernel.org \
--cc=hch@lst.de \
--cc=jason@lakedaemon.net \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=palmer@sifive.com \
--cc=robh+dt@kernel.org \
--cc=shorne@gmail.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.