* [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions
@ 2020-12-01 13:28 Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 1/3] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA Philippe Mathieu-Daudé
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 13:28 UTC (permalink / raw)
To: Huacai Chen, qemu-devel, Jiaxun Yang
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Add some MIPS3 and R6 definitions to ease code review.
Philippe Mathieu-Daudé (3):
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
target/mips: Replace CP0_Config0 magic values by proper definitions
target/mips: Explicit Release 6 MMU types
target/mips/cpu.h | 11 +++++++++--
target/mips/internal.h | 9 +++++----
target/mips/translate_init.c.inc | 14 ++++++++------
3 files changed, 22 insertions(+), 12 deletions(-)
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
2020-12-01 13:28 [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Philippe Mathieu-Daudé
@ 2020-12-01 13:28 ` Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 2/3] target/mips: Replace CP0_Config0 magic values by proper definitions Philippe Mathieu-Daudé
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 13:28 UTC (permalink / raw)
To: Huacai Chen, qemu-devel, Jiaxun Yang
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 23f8c6f96cd..05291cee4db 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -828,7 +828,7 @@ struct CPUMIPSState {
#define CP0EBase_WG 11
target_ulong CP0_CMGCRBase;
/*
- * CP0 Register 16
+ * CP0 Register 16 (after Release 1)
*/
int32_t CP0_Config0;
#define CP0C0_M 31
@@ -837,13 +837,20 @@ struct CPUMIPSState {
#define CP0C0_MDU 20
#define CP0C0_MM 18
#define CP0C0_BM 16
-#define CP0C0_Impl 16 /* 24..16 */
#define CP0C0_BE 15
#define CP0C0_AT 13 /* 14..13 */
#define CP0C0_AR 10 /* 12..10 */
#define CP0C0_MT 7 /* 9..7 */
#define CP0C0_VI 3
#define CP0C0_K0 0 /* 2..0 */
+/*
+ * CP0 Register 16 (before Release 1)
+ */
+#define CP0C0_Impl 16 /* 24..16 */
+#define CP0C0_IC 9 /* 11..9 */
+#define CP0C0_DC 6 /* 8..6 */
+#define CP0C0_IB 5
+#define CP0C0_DB 4
int32_t CP0_Config1;
#define CP0C1_M 31
#define CP0C1_MMU 25 /* 30..25 */
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] target/mips: Replace CP0_Config0 magic values by proper definitions
2020-12-01 13:28 [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 1/3] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA Philippe Mathieu-Daudé
@ 2020-12-01 13:28 ` Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 3/3] target/mips: Explicit Release 6 MMU types Philippe Mathieu-Daudé
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 13:28 UTC (permalink / raw)
To: Huacai Chen, qemu-devel, Jiaxun Yang
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate_init.c.inc | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index ea85d5c6a79..4206d8f0859 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -495,7 +495,8 @@ const mips_def_t mips_defs[] =
.name = "R4000",
.CP0_PRid = 0x00000400,
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
- .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
+ .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
+ (2 << CP0C0_K0),
/* Note: Config1 is only used internally, the R4000 has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
@@ -516,7 +517,8 @@ const mips_def_t mips_defs[] =
.name = "VR5432",
.CP0_PRid = 0x00005400,
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
- .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
+ .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
+ (2 << CP0C0_K0),
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
.CP0_LLAddr_shift = 4,
@@ -766,8 +768,8 @@ const mips_def_t mips_defs[] =
.name = "Loongson-2E",
.CP0_PRid = 0x6302,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
- .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
- (0x1<<5) | (0x1<<4) | (0x1<<1),
+ .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
+ (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
/* Note: Config1 is only used internally,
Loongson-2E has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
@@ -786,8 +788,8 @@ const mips_def_t mips_defs[] =
.name = "Loongson-2F",
.CP0_PRid = 0x6303,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
- .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
- (0x1<<5) | (0x1<<4) | (0x1<<1),
+ .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
+ (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
/* Note: Config1 is only used internally,
Loongson-2F has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] target/mips: Explicit Release 6 MMU types
2020-12-01 13:28 [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 1/3] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 2/3] target/mips: Replace CP0_Config0 magic values by proper definitions Philippe Mathieu-Daudé
@ 2020-12-01 13:28 ` Philippe Mathieu-Daudé
2020-12-01 16:30 ` [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Richard Henderson
2020-12-07 22:31 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-01 13:28 UTC (permalink / raw)
To: Huacai Chen, qemu-devel, Jiaxun Yang
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno
As of Release 6, MMU type 4 is assigned to "Dual Variable-Page-Size
and Fixed-Page-Size TLBs" and type 2 to "Block Address Translation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index dd8a7809b64..d290c1afe30 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -15,10 +15,11 @@
* CP0C0_MT field.
*/
enum mips_mmu_types {
- MMU_TYPE_NONE,
- MMU_TYPE_R4000,
- MMU_TYPE_RESERVED,
- MMU_TYPE_FMT,
+ MMU_TYPE_NONE = 0,
+ MMU_TYPE_R4000 = 1, /* Standard TLB */
+ MMU_TYPE_BAT = 2, /* Block Address Translation */
+ MMU_TYPE_FMT = 3, /* Fixed Mapping */
+ MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */
MMU_TYPE_R3000,
MMU_TYPE_R6000,
MMU_TYPE_R8000
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions
2020-12-01 13:28 [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2020-12-01 13:28 ` [PATCH 3/3] target/mips: Explicit Release 6 MMU types Philippe Mathieu-Daudé
@ 2020-12-01 16:30 ` Richard Henderson
2020-12-07 22:31 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2020-12-01 16:30 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Huacai Chen, qemu-devel, Jiaxun Yang
Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/1/20 7:28 AM, Philippe Mathieu-Daudé wrote:
> Add some MIPS3 and R6 definitions to ease code review.
>
> Philippe Mathieu-Daudé (3):
> target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
> target/mips: Replace CP0_Config0 magic values by proper definitions
> target/mips: Explicit Release 6 MMU types
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions
2020-12-01 13:28 [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2020-12-01 16:30 ` [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Richard Henderson
@ 2020-12-07 22:31 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-07 22:31 UTC (permalink / raw)
To: qemu-devel, Jiaxun Yang
Cc: Aleksandar Rikalo, Richard Henderson, Aurelien Jarno
On 12/1/20 2:28 PM, Philippe Mathieu-Daudé wrote:
> Add some MIPS3 and R6 definitions to ease code review.
>
> Philippe Mathieu-Daudé (3):
> target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
> target/mips: Replace CP0_Config0 magic values by proper definitions
> target/mips: Explicit Release 6 MMU types
>
> target/mips/cpu.h | 11 +++++++++--
> target/mips/internal.h | 9 +++++----
> target/mips/translate_init.c.inc | 14 ++++++++------
> 3 files changed, 22 insertions(+), 12 deletions(-)
Thanks, applied to mips-next.
^ permalink raw reply [flat|nested] 6+ messages in thread
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2020-12-01 13:28 [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 1/3] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 2/3] target/mips: Replace CP0_Config0 magic values by proper definitions Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 3/3] target/mips: Explicit Release 6 MMU types Philippe Mathieu-Daudé
2020-12-01 16:30 ` [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Richard Henderson
2020-12-07 22:31 ` Philippe Mathieu-Daudé
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