From: "Heiko Stübner" <heiko@sntech.de> To: Rob Herring <robh@kernel.org> Cc: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, krzk+dt@kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size Date: Wed, 25 May 2022 17:14:31 +0200 [thread overview] Message-ID: <4376261.8F6SAcFxjW@diego> (raw) In-Reply-To: <20220518002529.GA1928329-robh@kernel.org> Am Mittwoch, 18. Mai 2022, 02:25:29 CEST schrieb Rob Herring: > On Wed, May 11, 2022 at 11:41:30PM +0200, Heiko Stuebner wrote: > > The Zicbom operates on a block-size defined for the cpu-core, > > which does not necessarily match other cache-sizes used. > > > > So add the necessary property for the system to know the core's > > block-size. > > > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index d632ac76532e..b179bfd155a3 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -63,6 +63,13 @@ properties: > > - riscv,sv48 > > - riscv,none > > > > + riscv,cbom-block-size: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > Any value 0-2^32 is valid? funnily enough there really seems to be _no_ constraints defined in the spec [0] regarding the actual cache-block size. It essentially only states "The capacity and organization of a cache and the size of a cache block are both implementation-specific" and later in software-discovery: "The initial set of CMO extensions requires the following information to be discovered by software: - The size of the cache block for management and prefetch instructions - The size of the cache block for zero instructions" [0] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf > > > + description: > > + Blocksize in bytes for the Zicbom cache operations. The block > > + size is a property of the core itself and does not necessarily > > + match other software defined cache sizes. > > What about hardware defined cache sizes? I'm scratching my head as to > what a 'software defined cache size' is. > > > + > > riscv,isa: > > description: > > Identifies the specific RISC-V instruction set architecture >
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de> To: Rob Herring <robh@kernel.org> Cc: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, krzk+dt@kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size Date: Wed, 25 May 2022 17:14:31 +0200 [thread overview] Message-ID: <4376261.8F6SAcFxjW@diego> (raw) In-Reply-To: <20220518002529.GA1928329-robh@kernel.org> Am Mittwoch, 18. Mai 2022, 02:25:29 CEST schrieb Rob Herring: > On Wed, May 11, 2022 at 11:41:30PM +0200, Heiko Stuebner wrote: > > The Zicbom operates on a block-size defined for the cpu-core, > > which does not necessarily match other cache-sizes used. > > > > So add the necessary property for the system to know the core's > > block-size. > > > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index d632ac76532e..b179bfd155a3 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -63,6 +63,13 @@ properties: > > - riscv,sv48 > > - riscv,none > > > > + riscv,cbom-block-size: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > Any value 0-2^32 is valid? funnily enough there really seems to be _no_ constraints defined in the spec [0] regarding the actual cache-block size. It essentially only states "The capacity and organization of a cache and the size of a cache block are both implementation-specific" and later in software-discovery: "The initial set of CMO extensions requires the following information to be discovered by software: - The size of the cache block for management and prefetch instructions - The size of the cache block for zero instructions" [0] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf > > > + description: > > + Blocksize in bytes for the Zicbom cache operations. The block > > + size is a property of the core itself and does not necessarily > > + match other software defined cache sizes. > > What about hardware defined cache sizes? I'm scratching my head as to > what a 'software defined cache size' is. > > > + > > riscv,isa: > > description: > > Identifies the specific RISC-V instruction set architecture > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-05-25 15:15 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-11 21:41 [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner 2022-05-11 21:41 ` Heiko Stuebner 2022-05-11 21:41 ` [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size Heiko Stuebner 2022-05-11 21:41 ` Heiko Stuebner 2022-05-12 4:18 ` Anup Patel 2022-05-12 4:18 ` Anup Patel 2022-05-13 10:28 ` Christoph Müllner 2022-05-13 10:28 ` Christoph Müllner 2022-05-18 0:25 ` Rob Herring 2022-05-18 0:25 ` Rob Herring 2022-05-18 8:22 ` Philipp Tomsich 2022-05-18 8:22 ` Philipp Tomsich 2022-05-18 9:02 ` Heiko Stübner 2022-05-18 9:02 ` Heiko Stübner 2022-05-18 9:10 ` Anup Patel 2022-05-18 9:10 ` Anup Patel 2022-05-18 9:20 ` Philipp Tomsich 2022-05-18 9:20 ` Philipp Tomsich 2022-05-25 15:14 ` Heiko Stübner [this message] 2022-05-25 15:14 ` Heiko Stübner 2022-05-11 21:41 ` [PATCH v2 2/3] riscv: Implement Zicbom-based cache management operations Heiko Stuebner 2022-05-11 21:41 ` Heiko Stuebner 2022-05-12 4:19 ` Anup Patel 2022-05-12 4:19 ` Anup Patel 2022-05-13 13:38 ` Guo Ren 2022-05-13 13:38 ` Guo Ren 2022-05-16 6:00 ` Christoph Hellwig 2022-05-16 6:00 ` Christoph Hellwig 2022-05-11 21:41 ` [PATCH v2 3/3] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner 2022-05-11 21:41 ` Heiko Stuebner 2022-05-12 4:40 ` Anup Patel 2022-05-12 4:40 ` Anup Patel 2022-05-13 13:37 ` Guo Ren 2022-05-13 13:37 ` Guo Ren
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